Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
otbn_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
otbn_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
otbn_req_during_lc_esc	2	0	2	100.00	100	1	1	0
otbn_req_during_otp_idle	2	0	2	100.00	100	1	1	2
otbn_req_during_sram_0_req	2	0	2	100.00	100	1	1	2
otbn_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable otbn_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13152

1

T3

16

T4

8

T5

2

auto[1]

1034

1

T6

34

T7

6

T115

2

---

Summary for Variable otbn_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13248

1

T3

15

T4

8

T5

2

auto[1]

938

1

T3

1

T6

41

T7

4

---

Summary for Variable otbn_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for otbn_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

14153

1

T3

16

T4

8

T5

2

lc_esc_on

33

1

T103

1

T71

1

T373

1

---

Summary for Variable otbn_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2794

1

T3

5

T10

2

T6

7

auto[1]

11392

1

T3

11

T4

8

T5

2

---

Summary for Variable otbn_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13215

1

T3

16

T4

8

T5

2

auto[1]

971

1

T6

43

T7

2

T25

4

---

Summary for Variable otbn_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13844

1

T3

16

T4

8

T5

2

auto[1]

342

1

T6

34

T25

1

T115

2