Group : tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg
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Group : tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
sram_1_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
sram_1_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
sram_1_req_during_lc_esc 2 0 2 100.00 100 1 1 0
sram_1_req_during_otbn_req 2 0 2 100.00 100 1 1 2
sram_1_req_during_otp_idle 2 0 2 100.00 100 1 1 2
sram_1_req_during_sram_0_req 2 0 2 100.00 100 1 1 2


Summary for Variable sram_1_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13031 1 T3 14 T4 8 T5 2
auto[1] 665 1 T6 41 T7 1 T66 8



Summary for Variable sram_1_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13030 1 T3 14 T4 8 T5 2
auto[1] 666 1 T6 29 T7 5 T115 2



Summary for Variable sram_1_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for sram_1_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 13675 1 T3 14 T4 8 T5 2
lc_esc_on 21 1 T114 1 T249 1 T95 1



Summary for Variable sram_1_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13089 1 T3 14 T4 8 T5 2
auto[1] 607 1 T6 30 T7 2 T25 1



Summary for Variable sram_1_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2083 1 T3 2 T6 14 T7 8
auto[1] 11613 1 T3 12 T4 8 T5 2



Summary for Variable sram_1_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13516 1 T3 14 T4 8 T5 2
auto[1] 180 1 T114 1 T249 1 T95 1

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