SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 44541 | 1 | T4 | 61 | T112 | 40 | T14 | 648 | ||||
access_err | 66779 | 1 | T3 | 182 | T10 | 46 | T6 | 534 | ||||
write_blank_err | 503 | 1 | T3 | 3 | T6 | 1 | T7 | 5 | ||||
ecc_uncorr_err | 69361 | 1 | T3 | 436 | T4 | 305 | T6 | 173 | ||||
ecc_corr_err | 1188 | 1 | T3 | 1 | T4 | 6 | T112 | 5 | ||||
no_err | 94919 | 1 | T3 | 231 | T4 | 4 | T5 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 808 | 1 | T6 | 6 | T7 | 7 | T12 | 17 | ||||
secret2 | 23899 | 1 | T3 | 43 | T5 | 5 | T10 | 11 | ||||
secret1 | 29390 | 1 | T3 | 475 | T10 | 11 | T6 | 129 | ||||
secret0 | 41411 | 1 | T3 | 21 | T4 | 62 | T10 | 12 | ||||
hw_cfg1 | 31953 | 1 | T3 | 33 | T4 | 60 | T10 | 5 | ||||
hw_cfg0 | 26077 | 1 | T3 | 43 | T4 | 2 | T5 | 2 | ||||
rot_creator_auth_state | 25880 | 1 | T3 | 35 | T4 | 61 | T10 | 10 | ||||
rot_creator_auth_codesign | 22150 | 1 | T3 | 34 | T4 | 69 | T10 | 9 | ||||
owner_sw_cfg | 22136 | 1 | T3 | 58 | T4 | 63 | T10 | 12 | ||||
creator_sw_cfg | 23794 | 1 | T3 | 60 | T4 | 59 | T5 | 2 | ||||
vendor_test | 29793 | 1 | T3 | 51 | T5 | 2 | T10 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 3368 | 1 | T14 | 86 | T71 | 270 | T177 | 9 | ||||
fsm_err | secret1 | 2685 | 1 | T14 | 562 | T114 | 132 | T126 | 225 | ||||
fsm_err | secret0 | 4172 | 1 | T141 | 20 | T71 | 228 | T217 | 504 | ||||
fsm_err | hw_cfg1 | 4699 | 1 | T103 | 118 | T95 | 255 | T324 | 114 | ||||
fsm_err | hw_cfg0 | 5212 | 1 | T249 | 101 | T96 | 246 | T230 | 100 | ||||
fsm_err | rot_creator_auth_state | 2073 | 1 | T117 | 2 | T144 | 66 | T197 | 10 | ||||
fsm_err | rot_creator_auth_codesign | 2595 | 1 | T325 | 118 | T237 | 374 | T326 | 568 | ||||
fsm_err | owner_sw_cfg | 3709 | 1 | T4 | 61 | T141 | 20 | T68 | 388 | ||||
fsm_err | creator_sw_cfg | 4484 | 1 | T112 | 22 | T150 | 301 | T141 | 31 | ||||
fsm_err | vendor_test | 11544 | 1 | T112 | 18 | T119 | 446 | T248 | 3 | ||||
access_err | life_cycle | 808 | 1 | T6 | 6 | T7 | 7 | T12 | 17 | ||||
access_err | secret2 | 11619 | 1 | T3 | 33 | T10 | 5 | T6 | 135 | ||||
access_err | secret1 | 6657 | 1 | T10 | 11 | T25 | 23 | T66 | 2 | ||||
access_err | secret0 | 5082 | 1 | T10 | 12 | T6 | 1 | T13 | 2 | ||||
access_err | hw_cfg1 | 1368 | 1 | T3 | 2 | T10 | 2 | T6 | 3 | ||||
access_err | hw_cfg0 | 2548 | 1 | T37 | 11 | T97 | 2 | T110 | 5 | ||||
access_err | rot_creator_auth_state | 6287 | 1 | T3 | 20 | T10 | 6 | T6 | 67 | ||||
access_err | rot_creator_auth_codesign | 8503 | 1 | T3 | 23 | T10 | 1 | T6 | 77 | ||||
access_err | owner_sw_cfg | 7433 | 1 | T3 | 31 | T6 | 80 | T7 | 36 | ||||
access_err | creator_sw_cfg | 8695 | 1 | T3 | 38 | T10 | 7 | T6 | 87 | ||||
access_err | vendor_test | 7779 | 1 | T3 | 35 | T10 | 2 | T6 | 78 | ||||
write_blank_err | secret2 | 10 | 1 | T97 | 1 | T327 | 1 | T228 | 1 | ||||
write_blank_err | secret1 | 24 | 1 | T3 | 1 | T191 | 1 | T328 | 1 | ||||
write_blank_err | secret0 | 63 | 1 | T6 | 1 | T7 | 1 | T14 | 1 | ||||
write_blank_err | hw_cfg1 | 63 | 1 | T3 | 1 | T66 | 1 | T67 | 1 | ||||
write_blank_err | hw_cfg0 | 21 | 1 | T329 | 1 | T257 | 2 | T330 | 1 | ||||
write_blank_err | rot_creator_auth_state | 182 | 1 | T12 | 1 | T14 | 1 | T146 | 1 | ||||
write_blank_err | rot_creator_auth_codesign | 70 | 1 | T7 | 4 | T146 | 1 | T67 | 2 | ||||
write_blank_err | owner_sw_cfg | 20 | 1 | T146 | 1 | T67 | 1 | T68 | 1 | ||||
write_blank_err | creator_sw_cfg | 24 | 1 | T240 | 1 | T331 | 5 | T332 | 1 | ||||
write_blank_err | vendor_test | 26 | 1 | T3 | 1 | T12 | 1 | T68 | 2 | ||||
ecc_uncorr_err | secret2 | 3431 | 1 | T112 | 25 | T97 | 429 | T234 | 24 | ||||
ecc_uncorr_err | secret1 | 10585 | 1 | T3 | 436 | T112 | 18 | T113 | 23 | ||||
ecc_uncorr_err | secret0 | 23093 | 1 | T4 | 62 | T6 | 173 | T112 | 21 | ||||
ecc_uncorr_err | hw_cfg1 | 14609 | 1 | T4 | 60 | T33 | 4 | T140 | 3 | ||||
ecc_uncorr_err | hw_cfg0 | 5429 | 1 | T112 | 23 | T113 | 29 | T33 | 4 | ||||
ecc_uncorr_err | rot_creator_auth_state | 8036 | 1 | T4 | 61 | T113 | 30 | T12 | 369 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 1743 | 1 | T4 | 64 | T172 | 24 | T141 | 59 | ||||
ecc_uncorr_err | owner_sw_cfg | 919 | 1 | T112 | 31 | T113 | 25 | T141 | 26 | ||||
ecc_uncorr_err | creator_sw_cfg | 1516 | 1 | T4 | 58 | T112 | 15 | T113 | 49 | ||||
ecc_corr_err | secret2 | 83 | 1 | T140 | 2 | T27 | 2 | T79 | 1 | ||||
ecc_corr_err | secret1 | 105 | 1 | T112 | 1 | T236 | 2 | T120 | 11 | ||||
ecc_corr_err | secret0 | 148 | 1 | T112 | 2 | T33 | 1 | T140 | 2 | ||||
ecc_corr_err | hw_cfg1 | 213 | 1 | T3 | 1 | T33 | 1 | T66 | 6 | ||||
ecc_corr_err | hw_cfg0 | 171 | 1 | T329 | 1 | T257 | 1 | T120 | 3 | ||||
ecc_corr_err | rot_creator_auth_state | 106 | 1 | T146 | 4 | T140 | 1 | T120 | 1 | ||||
ecc_corr_err | rot_creator_auth_codesign | 122 | 1 | T4 | 5 | T112 | 2 | T94 | 1 | ||||
ecc_corr_err | owner_sw_cfg | 117 | 1 | T4 | 1 | T113 | 2 | T33 | 1 | ||||
ecc_corr_err | creator_sw_cfg | 123 | 1 | T140 | 2 | T141 | 1 | T27 | 1 | ||||
no_err | secret2 | 5388 | 1 | T3 | 10 | T5 | 5 | T10 | 6 | ||||
no_err | secret1 | 9334 | 1 | T3 | 38 | T6 | 129 | T112 | 10 | ||||
no_err | secret0 | 8853 | 1 | T3 | 21 | T6 | 114 | T13 | 1 | ||||
no_err | hw_cfg1 | 11001 | 1 | T3 | 29 | T10 | 3 | T6 | 108 | ||||
no_err | hw_cfg0 | 12696 | 1 | T3 | 43 | T4 | 2 | T5 | 2 | ||||
no_err | rot_creator_auth_state | 9196 | 1 | T3 | 15 | T10 | 4 | T6 | 38 | ||||
no_err | rot_creator_auth_codesign | 9117 | 1 | T3 | 11 | T10 | 8 | T6 | 89 | ||||
no_err | owner_sw_cfg | 9938 | 1 | T3 | 27 | T4 | 1 | T10 | 12 | ||||
no_err | creator_sw_cfg | 8952 | 1 | T3 | 22 | T4 | 1 | T5 | 2 | ||||
no_err | vendor_test | 10444 | 1 | T3 | 15 | T5 | 2 | T10 | 7 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |