Group : tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
otbn_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
otbn_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
otbn_req_during_lc_esc 2 0 2 100.00 100 1 1 0
otbn_req_during_otp_idle 2 0 2 100.00 100 1 1 2
otbn_req_during_sram_0_req 2 0 2 100.00 100 1 1 2
otbn_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable otbn_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11643 1 T1 2 T2 233 T3 16
auto[1] 853 1 T2 23 T10 10 T94 1



Summary for Variable otbn_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11652 1 T1 2 T2 231 T3 16
auto[1] 844 1 T2 25 T10 6 T94 3



Summary for Variable otbn_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for otbn_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 12465 1 T1 2 T2 256 T3 16
lc_esc_on 31 1 T35 1 T335 1 T65 1



Summary for Variable otbn_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2285 1 T1 1 T2 52 T5 1
auto[1] 10211 1 T1 1 T2 204 T3 16



Summary for Variable otbn_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11666 1 T1 2 T2 225 T3 16
auto[1] 830 1 T2 31 T10 7 T94 2



Summary for Variable otbn_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12145 1 T1 2 T2 236 T3 16
auto[1] 351 1 T2 20 T10 6 T94 1

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