Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	50947	1			T1	37		T2	219		T146	600
access_err	62753	1			T2	1125		T3	53		T5	171
write_blank_err	380	1			T2	8		T5	4		T6	1
ecc_uncorr_err	66988	1			T2	1050		T5	309		T6	245
ecc_corr_err	1623	1			T102	4		T60	4		T128	2
no_err	91551	1			T2	1239		T3	77		T5	276

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	663	1			T2	6		T5	2		T6	8
secret2	22440	1			T2	220		T3	9		T5	51
secret1	30306	1			T2	197		T3	9		T5	342
secret0	37296	1			T2	503		T3	14		T5	43
hw_cfg1	31906	1			T2	643		T3	19		T5	32
hw_cfg0	26734	1			T2	277		T3	5		T5	40
rot_creator_auth_state	24919	1			T2	229		T3	10		T5	51
rot_creator_auth_codesign	23958	1			T2	454		T3	20		T5	54
owner_sw_cfg	19819	1			T2	234		T3	16		T5	65
creator_sw_cfg	21775	1			T2	629		T3	12		T5	34
vendor_test	34426	1			T1	37		T2	249		T3	16

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2273	1			T153	169		T253	232		T334	163
fsm_err	secret1	4274	1			T15	70		T134	287		T261	37
fsm_err	secret0	3534	1			T199	593		T281	126		T335	64
fsm_err	hw_cfg1	2147	1			T262	285		T136	59		T336	129
fsm_err	hw_cfg0	6812	1			T92	80		T142	213		T246	404
fsm_err	rot_creator_auth_state	4523	1			T146	600		T248	45		T337	486
fsm_err	rot_creator_auth_codesign	4875	1			T2	219		T250	159		T242	212
fsm_err	owner_sw_cfg	2171	1			T12	34		T338	220		T339	5
fsm_err	creator_sw_cfg	3300	1			T340	36		T121	229		T341	53
fsm_err	vendor_test	17038	1			T1	37		T60	7		T59	188
access_err	life_cycle	663	1			T2	6		T5	2		T6	8
access_err	secret2	10853	1			T2	136		T3	6		T5	29
access_err	secret1	6207	1			T2	119		T5	10		T9	66
access_err	secret0	4495	1			T2	120		T3	9		T5	24
access_err	hw_cfg1	1254	1			T2	30		T3	3		T5	3
access_err	hw_cfg0	2333	1			T2	60		T3	1		T5	2
access_err	rot_creator_auth_state	6019	1			T2	94		T5	16		T9	41
access_err	rot_creator_auth_codesign	8275	1			T2	163		T3	13		T5	19
access_err	owner_sw_cfg	7198	1			T2	123		T3	11		T5	39
access_err	creator_sw_cfg	8063	1			T2	159		T3	4		T5	14
access_err	vendor_test	7393	1			T2	115		T3	6		T5	13
write_blank_err	secret2	10	1			T342	2		T122	1		T298	1
write_blank_err	secret1	22	1			T5	1		T129	1		T343	2
write_blank_err	secret0	53	1			T2	1		T128	1		T12	1
write_blank_err	hw_cfg1	63	1			T2	2		T128	1		T15	1
write_blank_err	hw_cfg0	16	1			T128	1		T12	1		T13	1
write_blank_err	rot_creator_auth_state	111	1			T2	3		T128	1		T12	1
write_blank_err	rot_creator_auth_codesign	43	1			T5	3		T6	1		T216	1
write_blank_err	owner_sw_cfg	25	1			T203	2		T129	1		T122	1
write_blank_err	creator_sw_cfg	17	1			T2	2		T203	1		T129	1
write_blank_err	vendor_test	20	1			T12	2		T122	2		T344	1
ecc_uncorr_err	secret2	4008	1			T158	29		T166	47		T342	482
ecc_uncorr_err	secret1	10412	1			T5	309		T158	103		T210	17
ecc_uncorr_err	secret0	20444	1			T2	270		T12	395		T157	260
ecc_uncorr_err	hw_cfg1	17147	1			T2	444		T15	144		T157	73
ecc_uncorr_err	hw_cfg0	5362	1			T128	564		T13	246		T157	133
ecc_uncorr_err	rot_creator_auth_state	5820	1			T89	57		T15	574		T157	63
ecc_uncorr_err	rot_creator_auth_codesign	1446	1			T6	245		T158	20		T210	9
ecc_uncorr_err	owner_sw_cfg	815	1			T89	53		T157	63		T210	24
ecc_uncorr_err	creator_sw_cfg	1534	1			T2	336		T158	27		T159	41
ecc_corr_err	secret2	108	1			T59	1		T157	3		T158	1
ecc_corr_err	secret1	84	1			T59	1		T157	2		T159	1
ecc_corr_err	secret0	183	1			T128	1		T158	2		T159	3
ecc_corr_err	hw_cfg1	338	1			T60	1		T128	1		T59	1
ecc_corr_err	hw_cfg0	295	1			T12	1		T63	3		T111	12
ecc_corr_err	rot_creator_auth_state	149	1			T102	1		T59	3		T157	1
ecc_corr_err	rot_creator_auth_codesign	165	1			T89	4		T157	1		T159	1
ecc_corr_err	owner_sw_cfg	164	1			T102	3		T60	3		T157	1
ecc_corr_err	creator_sw_cfg	137	1			T59	2		T157	2		T158	5
no_err	secret2	5188	1			T2	84		T3	3		T5	22
no_err	secret1	9307	1			T2	78		T3	9		T5	22
no_err	secret0	8587	1			T2	112		T3	5		T5	19
no_err	hw_cfg1	10957	1			T2	167		T3	16		T5	29
no_err	hw_cfg0	11916	1			T2	217		T3	4		T5	38
no_err	rot_creator_auth_state	8297	1			T2	132		T3	10		T5	35
no_err	rot_creator_auth_codesign	9154	1			T2	72		T3	7		T5	32
no_err	owner_sw_cfg	9446	1			T2	111		T3	5		T5	26
no_err	creator_sw_cfg	8724	1			T2	132		T3	8		T5	20
no_err	vendor_test	9975	1			T2	134		T3	10		T5	33

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded