Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
creator_sw_cfg_lock	2	0	2	100.00	100	1	1	2
hw_cfg0_lock	2	0	2	100.00	100	1	1	2
hw_cfg1_lock	2	0	2	100.00	100	1	1	2
lc_esc	2	0	2	100.00	100	1	1	2
owner_sw_cfg_lock	2	0	2	100.00	100	1	1	2
rot_creator_auth_codesign_lock	2	0	2	100.00	100	1	1	2
rot_creator_auth_state_lock	2	0	2	100.00	100	1	1	2
secret0_lock	2	0	2	100.00	100	1	1	2
secret1_lock	2	0	2	100.00	100	1	1	2
secret2_lock	2	0	2	100.00	100	1	1	2
vendor_test_lock	2	0	2	100.00	100	1	1	2

Summary for Variable creator_sw_cfg_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for creator_sw_cfg_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7688

1

T1

5

T2

83

T3

8

auto[1]

4606

1

T2

78

T3

5

T5

7

---

Summary for Variable hw_cfg0_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_cfg0_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7427

1

T1

5

T2

64

T3

4

auto[1]

4867

1

T2

97

T3

9

T4

1

---

Summary for Variable hw_cfg1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_cfg1_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7509

1

T1

5

T2

68

T3

2

auto[1]

4785

1

T2

93

T3

11

T4

1

---

Summary for Variable lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12249

1

T1

5

T2

161

T3

13

auto[1]

45

1

T206

1

T207

1

T208

1

---

Summary for Variable owner_sw_cfg_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for owner_sw_cfg_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9252

1

T1

5

T2

93

T3

2

auto[1]

3042

1

T2

68

T3

11

T5

7

---

Summary for Variable rot_creator_auth_codesign_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rot_creator_auth_codesign_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7614

1

T1

5

T2

82

T3

2

auto[1]

4680

1

T2

79

T3

11

T5

7

---

Summary for Variable rot_creator_auth_state_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rot_creator_auth_state_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10311

1

T1

5

T2

142

T3

13

auto[1]

1983

1

T2

19

T9

18

T93

8

---

Summary for Variable secret0_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret0_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7463

1

T1

5

T2

69

T3

6

auto[1]

4831

1

T2

92

T3

7

T4

1

---

Summary for Variable secret1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret1_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7406

1

T1

5

T2

63

T3

12

auto[1]

4888

1

T2

98

T3

1

T4

1

---

Summary for Variable secret2_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret2_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8641

1

T1

5

T2

106

T3

4

auto[1]

3653

1

T2

55

T3

9

T4

1

---

Summary for Variable vendor_test_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for vendor_test_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7655

1

T1

5

T2

80

T3

6

auto[1]

4639

1

T2

81

T3

7

T5

7