Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

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Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
secret1_lock	2	0	2	100.00	100	1	1	2
sram_index	4	0	4	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sram_req_lock_cross	8	0	8	100.00	100	1	1	0

Summary for Variable secret1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret1_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1282

1

T105

4

T97

9

T12

4

auto[1]

786

1

T97

5

T98

30

T106

3

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Summary for Variable sram_index

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for sram_index

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_key[0x0]	82	1			T97	3		T98	1		T35	6
sram_key[0x1]	634	1			T105	2		T97	5		T12	2
sram_key[0x2]	614	1			T97	4		T12	1		T157	10
sram_key[0x3]	738	1			T105	2		T97	2		T12	1

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Summary for Cross sram_req_lock_cross

Samples crossed: sram_index secret1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for sram_req_lock_cross

Bins

sram_index	secret1_lock	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_key[0x0]	auto[0]	55	1			T97	2		T98	1		T35	6
sram_key[0x0]	auto[1]	27	1			T97	1		T236	6		T405	1
sram_key[0x1]	auto[0]	406	1			T105	2		T97	3		T12	2
sram_key[0x1]	auto[1]	228	1			T97	2		T98	10		T106	1
sram_key[0x2]	auto[0]	381	1			T97	3		T12	1		T157	10
sram_key[0x2]	auto[1]	233	1			T97	1		T98	11		T106	1
sram_key[0x3]	auto[0]	440	1			T105	2		T97	1		T12	1
sram_key[0x3]	auto[1]	298	1			T97	1		T98	9		T106	1