Group : tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg
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Group : tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 0 14 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
lc_esc_during_flash_addr_req 2 0 2 100.00 100 1 1 2
lc_esc_during_flash_data_req 2 0 2 100.00 100 1 1 2
lc_esc_during_lc_otp_prog_req 2 0 2 100.00 100 1 1 2
lc_esc_during_otbn_req 2 0 2 100.00 100 1 1 2
lc_esc_during_otp_idle 2 0 2 100.00 100 1 1 2
lc_esc_during_sram_0_req 2 0 2 100.00 100 1 1 2
lc_esc_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable lc_esc_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 347 1 T3 2 T4 2 T10 2
auto[1] 39 1 T6 2 T95 1 T349 1



Summary for Variable lc_esc_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 342 1 T3 2 T4 2 T10 2
auto[1] 44 1 T7 2 T156 2 T96 1



Summary for Variable lc_esc_during_lc_otp_prog_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_lc_otp_prog_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 345 1 T4 2 T10 1 T6 2
auto[1] 41 1 T3 2 T10 1 T93 2



Summary for Variable lc_esc_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 335 1 T3 2 T4 2 T10 2
auto[1] 51 1 T7 1 T143 1 T392 1



Summary for Variable lc_esc_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33 1 T3 1 T7 1 T93 1
auto[1] 353 1 T3 1 T4 2 T10 2



Summary for Variable lc_esc_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 343 1 T3 2 T4 1 T10 2
auto[1] 43 1 T4 1 T142 2 T115 1



Summary for Variable lc_esc_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 340 1 T3 2 T4 1 T10 2
auto[1] 46 1 T4 1 T142 2 T115 1

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