SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 53430 | 1 | T1 | 73 | T4 | 309 | T100 | 64 | ||||
access_err | 64533 | 1 | T1 | 1 | T3 | 11 | T4 | 96 | ||||
write_blank_err | 381 | 1 | T4 | 2 | T6 | 2 | T7 | 1 | ||||
ecc_uncorr_err | 65361 | 1 | T4 | 121 | T100 | 206 | T101 | 337 | ||||
ecc_corr_err | 1437 | 1 | T8 | 8 | T4 | 1 | T100 | 9 | ||||
no_err | 95141 | 1 | T1 | 17 | T2 | 33 | T3 | 47 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 754 | 1 | T4 | 9 | T6 | 7 | T7 | 5 | ||||
secret2 | 25463 | 1 | T2 | 1 | T8 | 6 | T4 | 159 | ||||
secret1 | 31804 | 1 | T1 | 3 | T2 | 2 | T3 | 7 | ||||
secret0 | 35918 | 1 | T1 | 2 | T2 | 2 | T3 | 11 | ||||
hw_cfg1 | 33918 | 1 | T2 | 2 | T3 | 7 | T8 | 3 | ||||
hw_cfg0 | 27535 | 1 | T1 | 3 | T2 | 6 | T3 | 7 | ||||
rot_creator_auth_state | 21981 | 1 | T1 | 5 | T2 | 2 | T3 | 5 | ||||
rot_creator_auth_codesign | 22955 | 1 | T1 | 1 | T2 | 4 | T3 | 7 | ||||
owner_sw_cfg | 24205 | 1 | T2 | 3 | T3 | 5 | T8 | 2 | ||||
creator_sw_cfg | 24327 | 1 | T1 | 4 | T2 | 10 | T3 | 7 | ||||
vendor_test | 31423 | 1 | T1 | 73 | T2 | 1 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 2802 | 1 | T247 | 34 | T343 | 125 | T344 | 5 | ||||
fsm_err | secret1 | 4344 | 1 | T141 | 446 | T18 | 59 | T158 | 19 | ||||
fsm_err | secret0 | 4099 | 1 | T345 | 183 | T157 | 61 | T346 | 256 | ||||
fsm_err | hw_cfg1 | 3361 | 1 | T6 | 182 | T261 | 638 | T259 | 40 | ||||
fsm_err | hw_cfg0 | 6648 | 1 | T265 | 32 | T95 | 18 | T142 | 520 | ||||
fsm_err | rot_creator_auth_state | 3784 | 1 | T156 | 112 | T347 | 232 | T348 | 137 | ||||
fsm_err | rot_creator_auth_codesign | 3990 | 1 | T100 | 18 | T101 | 44 | T160 | 54 | ||||
fsm_err | owner_sw_cfg | 5792 | 1 | T4 | 309 | T96 | 75 | T349 | 286 | ||||
fsm_err | creator_sw_cfg | 5020 | 1 | T100 | 46 | T7 | 33 | T160 | 52 | ||||
fsm_err | vendor_test | 13590 | 1 | T1 | 73 | T27 | 149 | T52 | 29 | ||||
access_err | life_cycle | 754 | 1 | T4 | 9 | T6 | 7 | T7 | 5 | ||||
access_err | secret2 | 11765 | 1 | T4 | 26 | T12 | 20 | T100 | 5 | ||||
access_err | secret1 | 5965 | 1 | T12 | 33 | T27 | 52 | T36 | 7 | ||||
access_err | secret0 | 4865 | 1 | T3 | 1 | T12 | 30 | T27 | 22 | ||||
access_err | hw_cfg1 | 1366 | 1 | T3 | 1 | T4 | 1 | T12 | 3 | ||||
access_err | hw_cfg0 | 2306 | 1 | T5 | 1 | T12 | 16 | T27 | 8 | ||||
access_err | rot_creator_auth_state | 6237 | 1 | T1 | 1 | T3 | 3 | T4 | 6 | ||||
access_err | rot_creator_auth_codesign | 8304 | 1 | T3 | 1 | T4 | 12 | T12 | 32 | ||||
access_err | owner_sw_cfg | 7014 | 1 | T3 | 1 | T4 | 13 | T12 | 36 | ||||
access_err | creator_sw_cfg | 8540 | 1 | T3 | 3 | T4 | 5 | T5 | 1 | ||||
access_err | vendor_test | 7417 | 1 | T3 | 1 | T4 | 24 | T12 | 27 | ||||
write_blank_err | secret2 | 17 | 1 | T4 | 1 | T162 | 2 | T18 | 1 | ||||
write_blank_err | secret1 | 31 | 1 | T18 | 1 | T241 | 1 | T350 | 1 | ||||
write_blank_err | secret0 | 48 | 1 | T6 | 1 | T7 | 1 | T14 | 1 | ||||
write_blank_err | hw_cfg1 | 64 | 1 | T4 | 1 | T91 | 1 | T17 | 2 | ||||
write_blank_err | hw_cfg0 | 14 | 1 | T162 | 1 | T344 | 1 | T351 | 1 | ||||
write_blank_err | rot_creator_auth_state | 99 | 1 | T162 | 1 | T18 | 1 | T241 | 1 | ||||
write_blank_err | rot_creator_auth_codesign | 45 | 1 | T162 | 1 | T115 | 1 | T352 | 1 | ||||
write_blank_err | owner_sw_cfg | 21 | 1 | T91 | 1 | T18 | 3 | T115 | 2 | ||||
write_blank_err | creator_sw_cfg | 14 | 1 | T6 | 1 | T143 | 1 | T351 | 1 | ||||
write_blank_err | vendor_test | 28 | 1 | T162 | 1 | T18 | 2 | T241 | 2 | ||||
ecc_uncorr_err | secret2 | 5618 | 1 | T4 | 121 | T100 | 31 | T101 | 32 | ||||
ecc_uncorr_err | secret1 | 11896 | 1 | T100 | 42 | T101 | 44 | T160 | 47 | ||||
ecc_uncorr_err | secret0 | 17592 | 1 | T100 | 47 | T101 | 49 | T6 | 146 | ||||
ecc_uncorr_err | hw_cfg1 | 17703 | 1 | T100 | 45 | T101 | 95 | T160 | 50 | ||||
ecc_uncorr_err | hw_cfg0 | 5776 | 1 | T160 | 151 | T161 | 31 | T158 | 42 | ||||
ecc_uncorr_err | rot_creator_auth_state | 2678 | 1 | T101 | 35 | T161 | 33 | T190 | 11 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 1080 | 1 | T101 | 46 | T158 | 19 | T353 | 7 | ||||
ecc_uncorr_err | owner_sw_cfg | 1642 | 1 | T100 | 41 | T354 | 26 | T355 | 34 | ||||
ecc_uncorr_err | creator_sw_cfg | 1376 | 1 | T101 | 36 | T157 | 74 | T356 | 54 | ||||
ecc_corr_err | secret2 | 62 | 1 | T101 | 1 | T72 | 2 | T162 | 1 | ||||
ecc_corr_err | secret1 | 122 | 1 | T100 | 4 | T27 | 2 | T101 | 1 | ||||
ecc_corr_err | secret0 | 178 | 1 | T8 | 2 | T100 | 1 | T27 | 14 | ||||
ecc_corr_err | hw_cfg1 | 280 | 1 | T8 | 1 | T4 | 1 | T27 | 19 | ||||
ecc_corr_err | hw_cfg0 | 237 | 1 | T8 | 2 | T27 | 18 | T101 | 1 | ||||
ecc_corr_err | rot_creator_auth_state | 174 | 1 | T8 | 3 | T100 | 3 | T27 | 8 | ||||
ecc_corr_err | rot_creator_auth_codesign | 103 | 1 | T100 | 1 | T27 | 4 | T101 | 1 | ||||
ecc_corr_err | owner_sw_cfg | 168 | 1 | T101 | 10 | T52 | 1 | T72 | 3 | ||||
ecc_corr_err | creator_sw_cfg | 113 | 1 | T27 | 8 | T52 | 2 | T103 | 1 | ||||
no_err | secret2 | 5199 | 1 | T2 | 1 | T8 | 6 | T4 | 11 | ||||
no_err | secret1 | 9446 | 1 | T1 | 3 | T2 | 2 | T3 | 7 | ||||
no_err | secret0 | 9136 | 1 | T1 | 2 | T2 | 2 | T3 | 10 | ||||
no_err | hw_cfg1 | 11144 | 1 | T2 | 2 | T3 | 6 | T8 | 2 | ||||
no_err | hw_cfg0 | 12554 | 1 | T1 | 3 | T2 | 6 | T3 | 7 | ||||
no_err | rot_creator_auth_state | 9009 | 1 | T1 | 4 | T2 | 2 | T3 | 2 | ||||
no_err | rot_creator_auth_codesign | 9433 | 1 | T1 | 1 | T2 | 4 | T3 | 6 | ||||
no_err | owner_sw_cfg | 9568 | 1 | T2 | 3 | T3 | 4 | T8 | 2 | ||||
no_err | creator_sw_cfg | 9264 | 1 | T1 | 4 | T2 | 10 | T3 | 4 | ||||
no_err | vendor_test | 10388 | 1 | T2 | 1 | T3 | 1 | T8 | 2 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |