Group : tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
flash_data_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
flash_data_req_during_lc_esc 2 0 2 100.00 100 1 1 0
flash_data_req_during_otbn_req 2 0 2 100.00 100 1 1 2
flash_data_req_during_otp_idle 2 0 2 100.00 100 1 1 2
flash_data_req_during_sram_0_req 2 0 2 100.00 100 1 1 2
flash_data_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable flash_data_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_flash_addr_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 12559 1 T1 8 T3 20 T4 2
auto[1] 865 1 T8 11 T50 18 T34 1



Summary for Variable flash_data_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for flash_data_req_during_lc_esc

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
lc_esc_off 13381 1 T1 8 T3 20 T4 2
lc_esc_on 43 1 T198 1 T64 1 T65 1



Summary for Variable flash_data_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_otbn_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 12440 1 T1 8 T3 20 T4 2
auto[1] 984 1 T8 8 T50 15 T34 1



Summary for Variable flash_data_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_otp_idle

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1911 1 T8 18 T14 2 T6 8
auto[1] 11513 1 T1 8 T3 20 T4 2



Summary for Variable flash_data_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_sram_0_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 11256 1 T1 4 T3 20 T4 2
auto[1] 2168 1 T1 4 T8 11 T100 6



Summary for Variable flash_data_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_sram_1_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 12941 1 T1 8 T3 20 T4 2
auto[1] 483 1 T8 1 T50 7 T64 2