Group : tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
sram_0_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
sram_0_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
sram_0_req_during_lc_esc 2 0 2 100.00 100 1 1 0
sram_0_req_during_otbn_req 2 0 2 100.00 100 1 1 2
sram_0_req_during_otp_idle 2 0 2 100.00 100 1 1 2
sram_0_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable sram_0_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12486 1 T1 8 T3 20 T4 2
auto[1] 900 1 T8 9 T50 23 T64 4



Summary for Variable sram_0_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12456 1 T1 8 T3 20 T4 2
auto[1] 930 1 T8 9 T50 17 T34 1



Summary for Variable sram_0_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for sram_0_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 13345 1 T1 8 T3 20 T4 2
lc_esc_on 41 1 T144 1 T65 1 T237 1



Summary for Variable sram_0_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12434 1 T1 8 T3 20 T4 2
auto[1] 952 1 T8 4 T50 18 T34 1



Summary for Variable sram_0_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1976 1 T8 19 T14 1 T6 7
auto[1] 11410 1 T1 8 T3 20 T4 2



Summary for Variable sram_0_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11486 1 T1 8 T3 20 T4 2
auto[1] 1900 1 T8 52 T50 9 T94 6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%