Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_csr_rd_after_alert_cg_wrap::csr_rd_after_alert_cg

Group : otp_ctrl_env_pkg::otp_ctrl_csr_rd_after_alert_cg_wrap::csr_rd_after_alert_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

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Summary for Group otp_ctrl_env_pkg::otp_ctrl_csr_rd_after_alert_cg_wrap::csr_rd_after_alert_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group otp_ctrl_env_pkg::otp_ctrl_csr_rd_after_alert_cg_wrap::csr_rd_after_alert_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
read_csr_after_alert_issued	6	0	6	100.00	100	1	1	0

Summary for Variable read_csr_after_alert_issued

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for read_csr_after_alert_issued

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
error_code	1396306	1			T3	936		T5	5798		T4	5434
status	411551	1			T3	71		T5	472		T4	451
direct_access_rdata	54532	1			T3	29		T5	189		T4	186
secret_digests	14580	1			T5	12		T4	6		T8	174
hw_digests	9720	1			T5	8		T4	4		T8	116
unbuffered_digests	24300	1			T5	20		T4	10		T8	290