Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
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Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv



Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 0 5 100.00
Crosses 6 0 6 100.00


Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
dai_access_cmd 3 0 3 100.00 100 1 1 0
lc_creator_seed_sw_rw_en 2 0 2 100.00 100 1 1 2


Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
dai_access_secret2 6 0 6 100.00 100 1 1 0


Summary for Variable dai_access_cmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for dai_access_cmd

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
dai_digest 2284 1 T1 1 T3 2 T7 1
dai_wr 4154 1 T1 3 T2 6 T3 5
dai_rd 7016 1 T2 7 T3 23 T5 1



Summary for Variable lc_creator_seed_sw_rw_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_creator_seed_sw_rw_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6100 1 T1 3 T3 19 T5 2
auto[1] 7354 1 T1 1 T2 13 T3 11



Summary for Cross dai_access_secret2

Samples crossed: lc_creator_seed_sw_rw_en dai_access_cmd
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 0 6 100.00


Automatically Generated Cross Bins for dai_access_secret2

Bins
lc_creator_seed_sw_rw_endai_access_cmdCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] dai_digest 1250 1 T8 10 T14 1 T104 1
auto[0] dai_wr 1557 1 T1 3 T3 4 T5 1
auto[0] dai_rd 3293 1 T3 15 T5 1 T8 29
auto[1] dai_digest 1034 1 T1 1 T3 2 T7 1
auto[1] dai_wr 2597 1 T2 6 T3 1 T7 6
auto[1] dai_rd 3723 1 T2 7 T3 8 T7 10

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