Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	50782	1			T3	72		T8	851		T100	74
access_err	61169	1			T1	30		T3	229		T5	6
write_blank_err	459	1			T5	1		T4	13		T6	2
ecc_uncorr_err	56621	1			T5	446		T4	418		T100	633
ecc_corr_err	1516	1			T3	86		T4	1		T100	6
no_err	90361	1			T1	69		T3	183		T5	38

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	671	1			T5	2		T4	4		T6	4
secret2	25678	1			T1	8		T3	68		T5	2
secret1	26374	1			T1	9		T3	50		T4	425
secret0	33325	1			T1	3		T3	44		T5	454
hw_cfg1	32336	1			T1	10		T3	22		T4	8
hw_cfg0	23518	1			T1	11		T3	34		T5	2
rot_creator_auth_state	22627	1			T1	4		T3	69		T5	4
rot_creator_auth_codesign	20724	1			T1	13		T3	29		T5	9
owner_sw_cfg	20676	1			T1	7		T3	58		T5	7
creator_sw_cfg	22179	1			T1	18		T3	43		T5	6
vendor_test	32800	1			T1	16		T3	153		T5	5

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	5441	1			T8	210		T6	1		T144	264
fsm_err	secret1	2833	1			T65	451		T313	198		T116	61
fsm_err	secret0	3467	1			T6	462		T137	28		T281	264
fsm_err	hw_cfg1	3709	1			T319	3		T135	80		T254	411
fsm_err	hw_cfg0	5875	1			T8	142		T64	253		T237	42
fsm_err	rot_creator_auth_state	3585	1			T64	544		T157	29		T280	146
fsm_err	rot_creator_auth_codesign	3016	1			T100	74		T159	52		T123	42
fsm_err	owner_sw_cfg	3890	1			T8	499		T157	23		T65	113
fsm_err	creator_sw_cfg	3540	1			T314	182		T168	8		T320	307
fsm_err	vendor_test	15426	1			T3	72		T104	119		T107	31
access_err	life_cycle	671	1			T5	2		T4	4		T6	4
access_err	secret2	10631	1			T1	7		T3	44		T5	2
access_err	secret1	5828	1			T3	41		T4	1		T8	44
access_err	secret0	4494	1			T1	3		T3	36		T8	80
access_err	hw_cfg1	1282	1			T1	1		T3	5		T4	1
access_err	hw_cfg0	2247	1			T1	3		T3	4		T8	30
access_err	rot_creator_auth_state	6284	1			T1	1		T3	39		T4	1
access_err	rot_creator_auth_codesign	7891	1			T1	2		T3	9		T4	4
access_err	owner_sw_cfg	6565	1			T1	3		T3	14		T4	13
access_err	creator_sw_cfg	7761	1			T1	6		T3	7		T5	2
access_err	vendor_test	7515	1			T1	4		T3	30		T4	9
write_blank_err	secret2	11	1			T64	1		T18	1		T321	1
write_blank_err	secret1	23	1			T4	1		T64	1		T15	1
write_blank_err	secret0	47	1			T5	1		T6	1		T12	1
write_blank_err	hw_cfg1	56	1			T4	1		T64	1		T13	1
write_blank_err	hw_cfg0	13	1			T6	1		T322	1		T323	1
write_blank_err	rot_creator_auth_state	154	1			T12	2		T217	4		T218	8
write_blank_err	rot_creator_auth_codesign	73	1			T4	5		T12	1		T217	1
write_blank_err	owner_sw_cfg	35	1			T4	2		T324	1		T123	2
write_blank_err	creator_sw_cfg	15	1			T4	2		T325	1		T326	1
write_blank_err	vendor_test	32	1			T4	2		T322	3		T134	3
ecc_uncorr_err	secret2	4418	1			T64	371		T327	35		T18	486
ecc_uncorr_err	secret1	8596	1			T4	418		T100	139		T64	666
ecc_uncorr_err	secret0	16517	1			T5	446		T6	635		T12	470
ecc_uncorr_err	hw_cfg1	16555	1			T100	76		T64	641		T157	31
ecc_uncorr_err	hw_cfg0	3030	1			T100	52		T6	303		T157	88
ecc_uncorr_err	rot_creator_auth_state	3972	1			T100	76		T157	22		T158	13
ecc_uncorr_err	rot_creator_auth_codesign	849	1			T100	135		T159	154		T203	3
ecc_uncorr_err	owner_sw_cfg	679	1			T100	80		T158	15		T159	56
ecc_uncorr_err	creator_sw_cfg	2005	1			T100	75		T203	10		T199	104
ecc_corr_err	secret2	102	1			T3	15		T157	1		T69	1
ecc_corr_err	secret1	121	1			T3	1		T33	2		T157	1
ecc_corr_err	secret0	132	1			T3	1		T100	3		T157	4
ecc_corr_err	hw_cfg1	328	1			T3	9		T4	1		T100	2
ecc_corr_err	hw_cfg0	275	1			T3	21		T33	1		T157	9
ecc_corr_err	rot_creator_auth_state	127	1			T3	4		T328	3		T69	2
ecc_corr_err	rot_creator_auth_codesign	110	1			T3	6		T33	1		T69	4
ecc_corr_err	owner_sw_cfg	138	1			T3	17		T100	1		T157	3
ecc_corr_err	creator_sw_cfg	183	1			T3	12		T33	3		T157	1
no_err	secret2	5075	1			T1	1		T3	9		T8	83
no_err	secret1	8973	1			T1	9		T3	8		T4	5
no_err	secret0	8668	1			T3	7		T5	7		T4	6
no_err	hw_cfg1	10406	1			T1	9		T3	8		T4	5
no_err	hw_cfg0	12078	1			T1	8		T3	9		T5	2
no_err	rot_creator_auth_state	8505	1			T1	3		T3	26		T5	4
no_err	rot_creator_auth_codesign	8785	1			T1	11		T3	14		T5	9
no_err	owner_sw_cfg	9369	1			T1	4		T3	27		T5	7
no_err	creator_sw_cfg	8675	1			T1	12		T3	24		T5	4
no_err	vendor_test	9827	1			T1	12		T3	51		T5	5

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded