Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
sram_1_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
sram_1_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
sram_1_req_during_lc_esc	2	0	2	100.00	100	1	1	0
sram_1_req_during_otbn_req	2	0	2	100.00	100	1	1	2
sram_1_req_during_otp_idle	2	0	2	100.00	100	1	1	2
sram_1_req_during_sram_0_req	2	0	2	100.00	100	1	1	2

Summary for Variable sram_1_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12473

1

T2

35

T3

4

T4

144

auto[1]

817

1

T2

3

T6

13

T11

8

---

Summary for Variable sram_1_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12336

1

T2

36

T3

4

T4

144

auto[1]

954

1

T2

2

T6

13

T11

9

---

Summary for Variable sram_1_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sram_1_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

13254

1

T2

38

T3

4

T4

144

lc_esc_on

36

1

T12

1

T33

1

T132

1

---

Summary for Variable sram_1_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12475

1

T2

37

T3

4

T4

144

auto[1]

815

1

T2

1

T6

10

T11

7

---

Summary for Variable sram_1_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1857

1

T2

1

T3

2

T4

36

auto[1]

11433

1

T2

37

T3

2

T4

108

---

Summary for Variable sram_1_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13110

1

T2

38

T3

4

T4

144

auto[1]

180

1

T12

1

T132

1

T257

1