Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	56572	1			T2	503		T4	546		T6	205
access_err	62228	1			T2	398		T4	646		T7	66
write_blank_err	448	1			T2	1		T4	4		T12	1
ecc_uncorr_err	69724	1			T2	138		T4	766		T12	363
ecc_corr_err	1206	1			T89	32		T94	8		T34	5
no_err	90208	1			T2	552		T3	3		T4	732

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	777	1			T2	4		T4	9		T12	2
secret2	25391	1			T2	313		T4	171		T7	20
secret1	28606	1			T2	75		T3	2		T4	115
secret0	35341	1			T2	108		T4	272		T7	15
hw_cfg1	36545	1			T2	63		T4	105		T7	11
hw_cfg0	29127	1			T2	72		T4	769		T7	15
rot_creator_auth_state	24605	1			T2	71		T4	121		T7	15
rot_creator_auth_codesign	23168	1			T2	91		T4	164		T7	15
owner_sw_cfg	20036	1			T2	128		T4	132		T7	13
creator_sw_cfg	22103	1			T2	559		T3	1		T4	135
vendor_test	34687	1			T2	108		T4	701		T7	14

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	4426	1			T2	56		T13	184		T149	211
fsm_err	secret1	4863	1			T33	95		T137	59		T138	45
fsm_err	secret0	3862	1			T334	1		T249	226		T195	127
fsm_err	hw_cfg1	3434	1			T132	10		T257	321		T161	111
fsm_err	hw_cfg0	7056	1			T12	131		T133	23		T335	39
fsm_err	rot_creator_auth_state	3899	1			T150	25		T252	151		T200	68
fsm_err	rot_creator_auth_codesign	4489	1			T162	34		T161	56		T150	33
fsm_err	owner_sw_cfg	2628	1			T33	129		T200	56		T129	14
fsm_err	creator_sw_cfg	4540	1			T2	447		T6	205		T336	357
fsm_err	vendor_test	17375	1			T4	546		T34	46		T68	50
access_err	life_cycle	777	1			T2	4		T4	9		T12	2
access_err	secret2	10976	1			T2	112		T4	124		T7	16
access_err	secret1	5849	1			T4	57		T7	9		T9	52
access_err	secret0	4597	1			T2	1		T4	65		T7	11
access_err	hw_cfg1	1233	1			T2	2		T4	10		T9	5
access_err	hw_cfg0	2155	1			T4	30		T9	11		T24	1
access_err	rot_creator_auth_state	5842	1			T2	47		T4	32		T7	2
access_err	rot_creator_auth_codesign	8010	1			T2	33		T4	80		T7	8
access_err	owner_sw_cfg	7092	1			T2	76		T4	85		T7	7
access_err	creator_sw_cfg	8120	1			T2	54		T4	89		T7	9
access_err	vendor_test	7577	1			T2	69		T4	65		T7	4
write_blank_err	secret2	15	1			T2	1		T33	1		T122	1
write_blank_err	secret1	23	1			T155	1		T251	1		T252	1
write_blank_err	secret0	56	1			T4	1		T14	1		T156	1
write_blank_err	hw_cfg1	78	1			T12	1		T154	1		T156	1
write_blank_err	hw_cfg0	19	1			T4	1		T99	1		T274	1
write_blank_err	rot_creator_auth_state	146	1			T4	1		T154	2		T156	2
write_blank_err	rot_creator_auth_codesign	38	1			T337	2		T338	1		T20	2
write_blank_err	owner_sw_cfg	26	1			T4	1		T156	1		T33	1
write_blank_err	creator_sw_cfg	15	1			T156	1		T33	1		T99	1
write_blank_err	vendor_test	32	1			T154	1		T337	1		T122	3
ecc_uncorr_err	secret2	4943	1			T2	138		T157	2		T33	182
ecc_uncorr_err	secret1	8861	1			T155	148		T150	41		T251	441
ecc_uncorr_err	secret0	18013	1			T4	136		T14	513		T156	339
ecc_uncorr_err	hw_cfg1	20818	1			T12	363		T154	454		T157	7
ecc_uncorr_err	hw_cfg0	7314	1			T4	630		T157	3		T99	252
ecc_uncorr_err	rot_creator_auth_state	6097	1			T99	433		T272	2		T150	72
ecc_uncorr_err	rot_creator_auth_codesign	1532	1			T94	21		T162	59		T161	60
ecc_uncorr_err	owner_sw_cfg	1033	1			T157	7		T332	32		T151	66
ecc_uncorr_err	creator_sw_cfg	1113	1			T157	10		T272	5		T150	38
ecc_corr_err	secret2	79	1			T89	1		T67	1		T113	5
ecc_corr_err	secret1	87	1			T89	4		T68	2		T113	2
ecc_corr_err	secret0	143	1			T89	8		T94	2		T67	4
ecc_corr_err	hw_cfg1	236	1			T89	7		T34	1		T156	4
ecc_corr_err	hw_cfg0	211	1			T89	4		T34	3		T157	2
ecc_corr_err	rot_creator_auth_state	113	1			T94	1		T34	1		T194	1
ecc_corr_err	rot_creator_auth_codesign	108	1			T89	7		T157	3		T67	2
ecc_corr_err	owner_sw_cfg	113	1			T89	1		T94	3		T156	4
ecc_corr_err	creator_sw_cfg	116	1			T94	2		T68	1		T67	2
no_err	secret2	4952	1			T2	6		T4	47		T7	4
no_err	secret1	8923	1			T2	75		T3	2		T4	58
no_err	secret0	8670	1			T2	107		T4	70		T7	4
no_err	hw_cfg1	10746	1			T2	61		T4	95		T7	11
no_err	hw_cfg0	12372	1			T2	72		T4	108		T7	15
no_err	rot_creator_auth_state	8508	1			T2	24		T4	88		T7	13
no_err	rot_creator_auth_codesign	8991	1			T2	58		T4	84		T7	7
no_err	owner_sw_cfg	9144	1			T2	52		T4	46		T7	6
no_err	creator_sw_cfg	8199	1			T2	58		T3	1		T4	46
no_err	vendor_test	9703	1			T2	39		T4	90		T7	10

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded