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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.06 93.89 96.77 96.17 91.65 97.24 96.33 93.35


Total test records in report: 1321
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T1262 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.458218973 May 26 01:18:32 PM PDT 24 May 26 01:18:34 PM PDT 24 42365607 ps
T1263 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.803274324 May 26 01:18:34 PM PDT 24 May 26 01:18:39 PM PDT 24 207567570 ps
T266 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.359910649 May 26 01:19:01 PM PDT 24 May 26 01:19:33 PM PDT 24 19032671880 ps
T1264 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.239285353 May 26 01:18:58 PM PDT 24 May 26 01:19:01 PM PDT 24 44877473 ps
T299 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2655596602 May 26 01:18:22 PM PDT 24 May 26 01:18:27 PM PDT 24 80682976 ps
T1265 /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.1625991191 May 26 01:19:01 PM PDT 24 May 26 01:19:04 PM PDT 24 137250140 ps
T1266 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.3805404527 May 26 01:18:42 PM PDT 24 May 26 01:18:44 PM PDT 24 85975925 ps
T1267 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.24909759 May 26 01:18:28 PM PDT 24 May 26 01:18:34 PM PDT 24 226768383 ps
T1268 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1382262475 May 26 01:19:00 PM PDT 24 May 26 01:19:05 PM PDT 24 804072315 ps
T1269 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.1902011058 May 26 01:19:01 PM PDT 24 May 26 01:19:04 PM PDT 24 45424251 ps
T1270 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3632265982 May 26 01:18:42 PM PDT 24 May 26 01:18:50 PM PDT 24 2853465655 ps
T1271 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.2015279549 May 26 01:18:31 PM PDT 24 May 26 01:18:34 PM PDT 24 82539719 ps
T339 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3401264545 May 26 01:18:52 PM PDT 24 May 26 01:19:04 PM PDT 24 2752294744 ps
T1272 /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.4061092740 May 26 01:19:00 PM PDT 24 May 26 01:19:03 PM PDT 24 36499841 ps
T1273 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.3910126774 May 26 01:18:25 PM PDT 24 May 26 01:18:29 PM PDT 24 329629820 ps
T1274 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.1341226751 May 26 01:18:24 PM PDT 24 May 26 01:18:25 PM PDT 24 82340258 ps
T1275 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.823882879 May 26 01:18:49 PM PDT 24 May 26 01:19:01 PM PDT 24 2356744976 ps
T345 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3517144598 May 26 01:18:41 PM PDT 24 May 26 01:18:59 PM PDT 24 2587154886 ps
T1276 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3042150206 May 26 01:18:26 PM PDT 24 May 26 01:18:29 PM PDT 24 115457596 ps
T1277 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2282313160 May 26 01:18:50 PM PDT 24 May 26 01:18:53 PM PDT 24 135821954 ps
T1278 /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3148410565 May 26 01:18:45 PM PDT 24 May 26 01:18:48 PM PDT 24 55315098 ps
T1279 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1016044823 May 26 01:18:31 PM PDT 24 May 26 01:18:34 PM PDT 24 207955623 ps
T1280 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3055774634 May 26 01:18:44 PM PDT 24 May 26 01:18:49 PM PDT 24 200848350 ps
T1281 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2084979351 May 26 01:18:53 PM PDT 24 May 26 01:19:00 PM PDT 24 174919572 ps
T1282 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3783020798 May 26 01:18:31 PM PDT 24 May 26 01:18:37 PM PDT 24 1096448371 ps
T269 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.174017517 May 26 01:18:45 PM PDT 24 May 26 01:18:57 PM PDT 24 1097934691 ps
T1283 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3474360694 May 26 01:18:28 PM PDT 24 May 26 01:18:30 PM PDT 24 131368946 ps
T1284 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.1323967860 May 26 01:18:51 PM PDT 24 May 26 01:18:53 PM PDT 24 133625852 ps
T1285 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.4230411207 May 26 01:18:49 PM PDT 24 May 26 01:18:52 PM PDT 24 676017989 ps
T1286 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.3121973702 May 26 01:18:26 PM PDT 24 May 26 01:18:27 PM PDT 24 56305888 ps
T1287 /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.2698868253 May 26 01:18:49 PM PDT 24 May 26 01:18:52 PM PDT 24 67112588 ps
T1288 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.607042883 May 26 01:18:42 PM PDT 24 May 26 01:18:44 PM PDT 24 82850201 ps
T1289 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.3650003241 May 26 01:18:49 PM PDT 24 May 26 01:18:55 PM PDT 24 65696260 ps
T1290 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2237402111 May 26 01:19:03 PM PDT 24 May 26 01:19:05 PM PDT 24 77371978 ps
T1291 /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.328431576 May 26 01:18:59 PM PDT 24 May 26 01:19:01 PM PDT 24 70083071 ps
T297 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3994881099 May 26 01:18:33 PM PDT 24 May 26 01:18:40 PM PDT 24 191201067 ps
T340 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.1283219244 May 26 01:18:53 PM PDT 24 May 26 01:19:04 PM PDT 24 746098827 ps
T1292 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.1843697417 May 26 01:18:51 PM PDT 24 May 26 01:18:54 PM PDT 24 73974378 ps
T298 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2343805145 May 26 01:18:45 PM PDT 24 May 26 01:18:47 PM PDT 24 141302497 ps
T1293 /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.469417989 May 26 01:18:59 PM PDT 24 May 26 01:19:02 PM PDT 24 118104310 ps
T1294 /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.3648871167 May 26 01:18:51 PM PDT 24 May 26 01:18:53 PM PDT 24 73563518 ps
T1295 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.1997163168 May 26 01:18:56 PM PDT 24 May 26 01:18:58 PM PDT 24 91063495 ps
T1296 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.139384946 May 26 01:19:00 PM PDT 24 May 26 01:19:03 PM PDT 24 147303241 ps
T303 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1490885909 May 26 01:18:55 PM PDT 24 May 26 01:18:57 PM PDT 24 135795598 ps
T1297 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.849289077 May 26 01:18:31 PM PDT 24 May 26 01:18:33 PM PDT 24 95055976 ps
T348 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1048124019 May 26 01:18:56 PM PDT 24 May 26 01:19:10 PM PDT 24 10523594838 ps
T1298 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.2715326856 May 26 01:18:32 PM PDT 24 May 26 01:18:36 PM PDT 24 63206064 ps
T304 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2510983552 May 26 01:18:28 PM PDT 24 May 26 01:18:32 PM PDT 24 668581984 ps
T1299 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3858616801 May 26 01:18:29 PM PDT 24 May 26 01:18:31 PM PDT 24 124588650 ps
T1300 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3700596984 May 26 01:18:48 PM PDT 24 May 26 01:18:51 PM PDT 24 616061046 ps
T1301 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.2642675345 May 26 01:19:01 PM PDT 24 May 26 01:19:05 PM PDT 24 205911887 ps
T1302 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.4285472838 May 26 01:18:49 PM PDT 24 May 26 01:18:51 PM PDT 24 599702612 ps
T1303 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1376913006 May 26 01:18:40 PM PDT 24 May 26 01:18:42 PM PDT 24 137690336 ps
T1304 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1853132834 May 26 01:18:56 PM PDT 24 May 26 01:18:58 PM PDT 24 71723763 ps
T1305 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.809333897 May 26 01:19:01 PM PDT 24 May 26 01:19:04 PM PDT 24 148392380 ps
T1306 /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.1502409152 May 26 01:18:35 PM PDT 24 May 26 01:18:37 PM PDT 24 565927496 ps
T1307 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3586257274 May 26 01:18:43 PM PDT 24 May 26 01:18:50 PM PDT 24 161292766 ps
T1308 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.3980152952 May 26 01:18:41 PM PDT 24 May 26 01:18:45 PM PDT 24 240907101 ps
T1309 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.3761065910 May 26 01:18:52 PM PDT 24 May 26 01:18:55 PM PDT 24 130953596 ps
T1310 /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.2638655399 May 26 01:19:03 PM PDT 24 May 26 01:19:05 PM PDT 24 146496423 ps
T1311 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.265268336 May 26 01:18:54 PM PDT 24 May 26 01:18:56 PM PDT 24 148931599 ps
T1312 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2741326484 May 26 01:18:49 PM PDT 24 May 26 01:18:55 PM PDT 24 305399565 ps
T1313 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.3503899032 May 26 01:18:50 PM PDT 24 May 26 01:19:11 PM PDT 24 3564973139 ps
T1314 /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1216539265 May 26 01:18:51 PM PDT 24 May 26 01:18:54 PM PDT 24 646198798 ps
T1315 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1153863686 May 26 01:18:50 PM PDT 24 May 26 01:18:54 PM PDT 24 99021292 ps
T1316 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.4105198950 May 26 01:19:01 PM PDT 24 May 26 01:19:04 PM PDT 24 147108520 ps
T1317 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.326301145 May 26 01:19:00 PM PDT 24 May 26 01:19:03 PM PDT 24 39138842 ps
T1318 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.294985707 May 26 01:18:38 PM PDT 24 May 26 01:18:41 PM PDT 24 130911833 ps
T1319 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3783716157 May 26 01:18:42 PM PDT 24 May 26 01:18:47 PM PDT 24 118733689 ps
T1320 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2682562292 May 26 01:18:41 PM PDT 24 May 26 01:18:43 PM PDT 24 76420360 ps
T1321 /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.1120581671 May 26 01:18:41 PM PDT 24 May 26 01:18:44 PM PDT 24 581290696 ps

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.1640394319
Short name T4
Test name
Test status
Simulation time 51280899553 ps
CPU time 287.68 seconds
Started May 26 01:28:50 PM PDT 24
Finished May 26 01:33:39 PM PDT 24
Peak memory 262820 kb
Host smart-c1134366-9dae-4629-b5d0-deac2ab7abf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640394319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all
.1640394319
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.388390377
Short name T2
Test name
Test status
Simulation time 47670887782 ps
CPU time 775.38 seconds
Started May 26 01:31:22 PM PDT 24
Finished May 26 01:44:18 PM PDT 24
Peak memory 295508 kb
Host smart-64b1a266-3054-4825-992b-33825e816d63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388390377 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.388390377
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.4275679091
Short name T99
Test name
Test status
Simulation time 115053250208 ps
CPU time 324.7 seconds
Started May 26 01:25:28 PM PDT 24
Finished May 26 01:30:55 PM PDT 24
Peak memory 283688 kb
Host smart-94f5eb11-41f7-4ccc-a76a-b0761024f62e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275679091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.
4275679091
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.1233651466
Short name T159
Test name
Test status
Simulation time 546884844 ps
CPU time 3.94 seconds
Started May 26 01:32:23 PM PDT 24
Finished May 26 01:32:27 PM PDT 24
Peak memory 242064 kb
Host smart-cf01ea88-c2b7-4939-9adf-736df5f79b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233651466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.1233651466
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.2702621916
Short name T18
Test name
Test status
Simulation time 165157915196 ps
CPU time 458.43 seconds
Started May 26 01:25:02 PM PDT 24
Finished May 26 01:32:41 PM PDT 24
Peak memory 266156 kb
Host smart-a9ac2807-0d17-409c-8a98-b29695c32ee6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702621916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.2702621916
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.2965303586
Short name T34
Test name
Test status
Simulation time 1735047323 ps
CPU time 13.81 seconds
Started May 26 01:30:12 PM PDT 24
Finished May 26 01:30:27 PM PDT 24
Peak memory 242276 kb
Host smart-93417f78-02ce-40b4-8fe4-6d9b78d2507c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965303586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.2965303586
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.114767576
Short name T161
Test name
Test status
Simulation time 1880665053 ps
CPU time 46.53 seconds
Started May 26 01:24:37 PM PDT 24
Finished May 26 01:25:24 PM PDT 24
Peak memory 257016 kb
Host smart-b0ebe417-9b36-462f-9b50-d88769e2421c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114767576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.114767576
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.799558396
Short name T122
Test name
Test status
Simulation time 86541419437 ps
CPU time 320.51 seconds
Started May 26 01:27:25 PM PDT 24
Finished May 26 01:32:46 PM PDT 24
Peak memory 260572 kb
Host smart-78d311b0-496a-456f-bb6b-4c737ee53751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799558396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all.
799558396
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.2831881194
Short name T37
Test name
Test status
Simulation time 114309671 ps
CPU time 3.99 seconds
Started May 26 01:30:54 PM PDT 24
Finished May 26 01:30:59 PM PDT 24
Peak memory 242164 kb
Host smart-ebe47830-1eda-4dac-b119-33bb535c3b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831881194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.2831881194
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3412073037
Short name T263
Test name
Test status
Simulation time 1861859961 ps
CPU time 17.54 seconds
Started May 26 01:18:42 PM PDT 24
Finished May 26 01:19:01 PM PDT 24
Peak memory 243920 kb
Host smart-ec77f36e-556b-49d5-a604-9b92859bfb8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412073037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.3412073037
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.12163824
Short name T277
Test name
Test status
Simulation time 97230926829 ps
CPU time 1677.57 seconds
Started May 26 01:26:24 PM PDT 24
Finished May 26 01:54:22 PM PDT 24
Peak memory 308356 kb
Host smart-99ed0dba-defe-4c12-81ad-20b1cd96c921
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12163824 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.12163824
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.2672389446
Short name T367
Test name
Test status
Simulation time 99732100761 ps
CPU time 258.87 seconds
Started May 26 01:26:49 PM PDT 24
Finished May 26 01:31:09 PM PDT 24
Peak memory 258424 kb
Host smart-593d3ca3-c34d-48e9-886a-367454412735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672389446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.2672389446
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.644946662
Short name T328
Test name
Test status
Simulation time 302398766313 ps
CPU time 1206.31 seconds
Started May 26 01:30:53 PM PDT 24
Finished May 26 01:51:00 PM PDT 24
Peak memory 343156 kb
Host smart-bf3fb00e-b85a-4a04-9802-cb23ee847c2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644946662 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.644946662
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.70401524
Short name T23
Test name
Test status
Simulation time 283265258 ps
CPU time 5.01 seconds
Started May 26 01:31:10 PM PDT 24
Finished May 26 01:31:16 PM PDT 24
Peak memory 242116 kb
Host smart-756a41c9-246d-4717-8305-265fb75c4907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70401524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.70401524
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.2728016395
Short name T228
Test name
Test status
Simulation time 4686249843 ps
CPU time 45.03 seconds
Started May 26 01:24:31 PM PDT 24
Finished May 26 01:25:17 PM PDT 24
Peak memory 257116 kb
Host smart-83ffa1b2-ce36-4cb0-b793-4c2138f6b063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728016395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.2728016395
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.3656426172
Short name T6
Test name
Test status
Simulation time 215138385582 ps
CPU time 1707.36 seconds
Started May 26 01:29:41 PM PDT 24
Finished May 26 01:58:09 PM PDT 24
Peak memory 376112 kb
Host smart-4c417e27-d1eb-4b32-bf05-2eec62e7ef8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656426172 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.3656426172
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.164181817
Short name T31
Test name
Test status
Simulation time 197042612 ps
CPU time 4.65 seconds
Started May 26 01:27:13 PM PDT 24
Finished May 26 01:27:18 PM PDT 24
Peak memory 242400 kb
Host smart-3d509aed-f609-41d8-80b1-e5b110b661ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164181817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.164181817
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.1043891568
Short name T177
Test name
Test status
Simulation time 120379259 ps
CPU time 4.04 seconds
Started May 26 01:32:04 PM PDT 24
Finished May 26 01:32:09 PM PDT 24
Peak memory 242036 kb
Host smart-8a9a33ec-e615-4833-8cd0-345f2ebf38e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043891568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.1043891568
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.344633833
Short name T12
Test name
Test status
Simulation time 297441164406 ps
CPU time 995.58 seconds
Started May 26 01:25:13 PM PDT 24
Finished May 26 01:41:49 PM PDT 24
Peak memory 274708 kb
Host smart-0bad4362-2151-493c-aed9-18ba2ddad688
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344633833 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.344633833
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.318723710
Short name T407
Test name
Test status
Simulation time 68357555 ps
CPU time 1.95 seconds
Started May 26 01:25:55 PM PDT 24
Finished May 26 01:25:59 PM PDT 24
Peak memory 240476 kb
Host smart-a88af6df-3d5c-42e1-8760-c70c79f9a9d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318723710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.318723710
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.4192165969
Short name T48
Test name
Test status
Simulation time 163826021 ps
CPU time 4.65 seconds
Started May 26 01:30:36 PM PDT 24
Finished May 26 01:30:41 PM PDT 24
Peak memory 242344 kb
Host smart-f82d2a33-e2a8-4faa-af61-acff638f85d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192165969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.4192165969
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.2554605747
Short name T58
Test name
Test status
Simulation time 148870202 ps
CPU time 5.11 seconds
Started May 26 01:32:46 PM PDT 24
Finished May 26 01:32:52 PM PDT 24
Peak memory 242084 kb
Host smart-0b6ba61d-d972-482c-a7ea-e19a5beaf806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554605747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.2554605747
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.2413815647
Short name T444
Test name
Test status
Simulation time 167941214 ps
CPU time 4.5 seconds
Started May 26 01:33:27 PM PDT 24
Finished May 26 01:33:33 PM PDT 24
Peak memory 242268 kb
Host smart-d3b5817f-6447-4e13-a0cb-f80a118ac2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413815647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.2413815647
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.1293042585
Short name T46
Test name
Test status
Simulation time 4015310546 ps
CPU time 27.84 seconds
Started May 26 01:30:12 PM PDT 24
Finished May 26 01:30:41 PM PDT 24
Peak memory 242220 kb
Host smart-46a5ed2e-6b07-4f9f-873e-778092f25f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293042585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.1293042585
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.2830626642
Short name T64
Test name
Test status
Simulation time 1591229102 ps
CPU time 4.4 seconds
Started May 26 01:24:36 PM PDT 24
Finished May 26 01:24:41 PM PDT 24
Peak memory 242120 kb
Host smart-e48f17bf-33ba-42c0-beb0-1a5abadfb2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830626642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.2830626642
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.1987688807
Short name T71
Test name
Test status
Simulation time 570809101 ps
CPU time 4.1 seconds
Started May 26 01:25:59 PM PDT 24
Finished May 26 01:26:05 PM PDT 24
Peak memory 242376 kb
Host smart-1c54a049-2085-4a95-8b79-5af590a5dfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987688807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.1987688807
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.1825024488
Short name T484
Test name
Test status
Simulation time 970083887 ps
CPU time 16.04 seconds
Started May 26 01:31:11 PM PDT 24
Finished May 26 01:31:28 PM PDT 24
Peak memory 241984 kb
Host smart-25c3c14d-c6f9-430d-9e18-d50a40cda685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825024488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.1825024488
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.514724335
Short name T28
Test name
Test status
Simulation time 154348388 ps
CPU time 3.81 seconds
Started May 26 01:33:18 PM PDT 24
Finished May 26 01:33:22 PM PDT 24
Peak memory 242024 kb
Host smart-60462b89-d323-459e-bd1b-bee829ff6aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514724335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.514724335
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.1149275221
Short name T378
Test name
Test status
Simulation time 14879401606 ps
CPU time 206.61 seconds
Started May 26 01:28:44 PM PDT 24
Finished May 26 01:32:12 PM PDT 24
Peak memory 263456 kb
Host smart-e127805b-6acc-4942-a8a8-fec1d2d17aa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149275221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.1149275221
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.2374251257
Short name T36
Test name
Test status
Simulation time 382211354 ps
CPU time 5.07 seconds
Started May 26 01:33:03 PM PDT 24
Finished May 26 01:33:09 PM PDT 24
Peak memory 241952 kb
Host smart-9557e6b1-7377-4f9b-898a-f86056120002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374251257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.2374251257
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.1106535167
Short name T148
Test name
Test status
Simulation time 34368949257 ps
CPU time 319.16 seconds
Started May 26 01:27:05 PM PDT 24
Finished May 26 01:32:26 PM PDT 24
Peak memory 282140 kb
Host smart-52fce25d-dd2f-416f-8901-6a42bd546614
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106535167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all
.1106535167
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.3033380264
Short name T30
Test name
Test status
Simulation time 396874526 ps
CPU time 4.92 seconds
Started May 26 01:31:18 PM PDT 24
Finished May 26 01:31:24 PM PDT 24
Peak memory 241912 kb
Host smart-eb1d7ffd-75a9-4ca8-9b91-7b93ac9424c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033380264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.3033380264
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.932526492
Short name T211
Test name
Test status
Simulation time 1613405985 ps
CPU time 4.06 seconds
Started May 26 01:31:46 PM PDT 24
Finished May 26 01:31:50 PM PDT 24
Peak memory 242152 kb
Host smart-b7603068-3869-427d-b7fd-da253dc44f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932526492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.932526492
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.3470364101
Short name T131
Test name
Test status
Simulation time 261459217 ps
CPU time 15.21 seconds
Started May 26 01:26:06 PM PDT 24
Finished May 26 01:26:22 PM PDT 24
Peak memory 241940 kb
Host smart-afc50f9d-52f8-4643-9ce4-27ab36647057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470364101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.3470364101
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.836420127
Short name T20
Test name
Test status
Simulation time 171908290900 ps
CPU time 1542.47 seconds
Started May 26 01:30:45 PM PDT 24
Finished May 26 01:56:29 PM PDT 24
Peak memory 264804 kb
Host smart-ba735a3e-07e9-4a84-82ad-e3b596df301c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836420127 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.836420127
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.2587504303
Short name T69
Test name
Test status
Simulation time 334723164 ps
CPU time 9.63 seconds
Started May 26 01:25:40 PM PDT 24
Finished May 26 01:25:50 PM PDT 24
Peak memory 248684 kb
Host smart-edb65dc9-81e8-492b-952d-87c3cc8f09e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587504303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.2587504303
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.233259705
Short name T78
Test name
Test status
Simulation time 1895924516 ps
CPU time 5.18 seconds
Started May 26 01:32:57 PM PDT 24
Finished May 26 01:33:03 PM PDT 24
Peak memory 242192 kb
Host smart-7cd1cfa7-2e4d-43c0-8ff5-c541786c38dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233259705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.233259705
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.2814614356
Short name T350
Test name
Test status
Simulation time 4147054625 ps
CPU time 12.31 seconds
Started May 26 01:27:07 PM PDT 24
Finished May 26 01:27:20 PM PDT 24
Peak memory 242728 kb
Host smart-864dfef1-173d-4421-9fac-2da5da6e68ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2814614356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.2814614356
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.1207232076
Short name T130
Test name
Test status
Simulation time 11299834257 ps
CPU time 28.27 seconds
Started May 26 01:32:21 PM PDT 24
Finished May 26 01:32:50 PM PDT 24
Peak memory 242104 kb
Host smart-6255956b-3c94-44ed-b6b8-366b4c290a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207232076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.1207232076
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.4087597483
Short name T246
Test name
Test status
Simulation time 2213222456 ps
CPU time 4.49 seconds
Started May 26 01:33:09 PM PDT 24
Finished May 26 01:33:14 PM PDT 24
Peak memory 242308 kb
Host smart-8e5f53b4-ef97-4b15-b68a-ceaa83026517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087597483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.4087597483
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.2184215703
Short name T136
Test name
Test status
Simulation time 18597803860 ps
CPU time 244.53 seconds
Started May 26 01:30:19 PM PDT 24
Finished May 26 01:34:25 PM PDT 24
Peak memory 249804 kb
Host smart-8b7d116e-1fcb-4c0c-9a2d-ff42a6d4a7ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184215703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all
.2184215703
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.447235269
Short name T61
Test name
Test status
Simulation time 107332230 ps
CPU time 3.26 seconds
Started May 26 01:31:41 PM PDT 24
Finished May 26 01:31:45 PM PDT 24
Peak memory 241932 kb
Host smart-67c6d96e-62b9-4b3d-ac16-1b36e53ff20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447235269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.447235269
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.4282217263
Short name T295
Test name
Test status
Simulation time 38546053 ps
CPU time 1.68 seconds
Started May 26 01:19:01 PM PDT 24
Finished May 26 01:19:04 PM PDT 24
Peak memory 239940 kb
Host smart-694d38b3-563e-4fd7-b721-db3423b4b94e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282217263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.4282217263
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.1591411893
Short name T26
Test name
Test status
Simulation time 757201212 ps
CPU time 21.28 seconds
Started May 26 01:25:57 PM PDT 24
Finished May 26 01:26:20 PM PDT 24
Peak memory 248736 kb
Host smart-322a1f52-c561-4315-ba0b-96404c203001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591411893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.1591411893
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.2598325160
Short name T40
Test name
Test status
Simulation time 1272374800 ps
CPU time 19.55 seconds
Started May 26 01:25:12 PM PDT 24
Finished May 26 01:25:32 PM PDT 24
Peak memory 242432 kb
Host smart-d7cca4b8-7ca0-4d1b-a91f-c650ef4d77b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598325160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.2598325160
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.2046523838
Short name T52
Test name
Test status
Simulation time 184819504 ps
CPU time 4.9 seconds
Started May 26 01:32:16 PM PDT 24
Finished May 26 01:32:21 PM PDT 24
Peak memory 242176 kb
Host smart-7b81748e-56ff-4208-9b8e-f1dd6f00afe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046523838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.2046523838
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.621379649
Short name T359
Test name
Test status
Simulation time 884319039 ps
CPU time 7.88 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:25 PM PDT 24
Peak memory 242224 kb
Host smart-85e28bae-3078-4f1b-bcf5-11420391a742
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621379649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.621379649
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.4293888240
Short name T53
Test name
Test status
Simulation time 3017010600 ps
CPU time 21.33 seconds
Started May 26 01:25:49 PM PDT 24
Finished May 26 01:26:11 PM PDT 24
Peak memory 242028 kb
Host smart-2b9f6f7c-041d-48b3-b38a-f4a9482bfd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293888240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.4293888240
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1453565171
Short name T268
Test name
Test status
Simulation time 4105993775 ps
CPU time 24.3 seconds
Started May 26 01:18:24 PM PDT 24
Finished May 26 01:18:49 PM PDT 24
Peak memory 243736 kb
Host smart-470357b8-a16e-4bc9-a5d4-e1a3f661755d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453565171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.1453565171
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.3420309303
Short name T142
Test name
Test status
Simulation time 925074167 ps
CPU time 19.09 seconds
Started May 26 01:24:39 PM PDT 24
Finished May 26 01:24:59 PM PDT 24
Peak memory 242676 kb
Host smart-f92c6ac8-f72d-45c9-aab0-2ad825f8c2ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420309303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
3420309303
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.220391835
Short name T861
Test name
Test status
Simulation time 240876655 ps
CPU time 8.87 seconds
Started May 26 01:31:44 PM PDT 24
Finished May 26 01:31:54 PM PDT 24
Peak memory 242028 kb
Host smart-7c66fed9-76ed-43bc-9986-0c7efcf632cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220391835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.220391835
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.2840788514
Short name T324
Test name
Test status
Simulation time 656497311 ps
CPU time 4.94 seconds
Started May 26 01:32:55 PM PDT 24
Finished May 26 01:33:01 PM PDT 24
Peak memory 241996 kb
Host smart-e5cea9d3-f12e-4b37-811a-675b0734818e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840788514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.2840788514
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.705542241
Short name T1
Test name
Test status
Simulation time 99267807 ps
CPU time 3.87 seconds
Started May 26 01:33:03 PM PDT 24
Finished May 26 01:33:08 PM PDT 24
Peak memory 241844 kb
Host smart-378cac39-89c4-4736-bd21-17cb51d9b669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705542241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.705542241
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.604701723
Short name T114
Test name
Test status
Simulation time 817892451 ps
CPU time 13.58 seconds
Started May 26 01:33:12 PM PDT 24
Finished May 26 01:33:26 PM PDT 24
Peak memory 241992 kb
Host smart-20df3e37-e1f2-4e2a-abab-92e432e6580b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604701723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.604701723
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.156660061
Short name T244
Test name
Test status
Simulation time 1116512009 ps
CPU time 8.25 seconds
Started May 26 01:26:59 PM PDT 24
Finished May 26 01:27:08 PM PDT 24
Peak memory 241940 kb
Host smart-0fded9a8-af77-4b54-adcc-931e7a6dd926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156660061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.156660061
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.1302845237
Short name T180
Test name
Test status
Simulation time 163453050 ps
CPU time 4.27 seconds
Started May 26 01:31:45 PM PDT 24
Finished May 26 01:31:50 PM PDT 24
Peak memory 242120 kb
Host smart-52a8a919-017b-4e61-a5c7-517740d8c830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302845237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.1302845237
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.2999278163
Short name T56
Test name
Test status
Simulation time 20751519588 ps
CPU time 53.91 seconds
Started May 26 01:27:37 PM PDT 24
Finished May 26 01:28:32 PM PDT 24
Peak memory 248864 kb
Host smart-76617d09-5e5a-4aeb-a7ae-8d6a7f43f26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999278163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.2999278163
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.3051330102
Short name T356
Test name
Test status
Simulation time 522470578 ps
CPU time 8.64 seconds
Started May 26 01:24:29 PM PDT 24
Finished May 26 01:24:39 PM PDT 24
Peak memory 242356 kb
Host smart-3050833a-c6aa-4a05-9998-1032c684e3b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3051330102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.3051330102
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.2475759116
Short name T253
Test name
Test status
Simulation time 254220106628 ps
CPU time 1113.03 seconds
Started May 26 01:27:40 PM PDT 24
Finished May 26 01:46:14 PM PDT 24
Peak memory 263160 kb
Host smart-8f4b2b22-3ae7-4569-b20a-a0945f1ee337
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475759116 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.2475759116
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.2148952543
Short name T384
Test name
Test status
Simulation time 105670496098 ps
CPU time 1787.91 seconds
Started May 26 01:31:10 PM PDT 24
Finished May 26 02:00:59 PM PDT 24
Peak memory 342572 kb
Host smart-3c085741-da26-4d79-859a-ea35cbc3789e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148952543 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.2148952543
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.345729359
Short name T98
Test name
Test status
Simulation time 19860191036 ps
CPU time 116.85 seconds
Started May 26 01:30:02 PM PDT 24
Finished May 26 01:32:00 PM PDT 24
Peak memory 257104 kb
Host smart-ef2883d4-8222-4055-91e0-6c9cadfb8a0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345729359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.
345729359
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.2843779516
Short name T83
Test name
Test status
Simulation time 18258134283 ps
CPU time 29.86 seconds
Started May 26 01:25:40 PM PDT 24
Finished May 26 01:26:10 PM PDT 24
Peak memory 242556 kb
Host smart-823e247f-a164-4c8e-8f7c-b7c1c44fd1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843779516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.2843779516
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1337319437
Short name T267
Test name
Test status
Simulation time 3022986274 ps
CPU time 18.43 seconds
Started May 26 01:18:43 PM PDT 24
Finished May 26 01:19:02 PM PDT 24
Peak memory 244932 kb
Host smart-6c436d7c-de75-4bc7-b1b0-dff289d3da96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337319437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in
tg_err.1337319437
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.2461471474
Short name T112
Test name
Test status
Simulation time 608011830 ps
CPU time 5.12 seconds
Started May 26 01:31:43 PM PDT 24
Finished May 26 01:31:49 PM PDT 24
Peak memory 242056 kb
Host smart-3c29e646-157a-4d98-9bd9-42c912ca5554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461471474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.2461471474
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.1786098842
Short name T226
Test name
Test status
Simulation time 1557026342 ps
CPU time 4.55 seconds
Started May 26 01:32:00 PM PDT 24
Finished May 26 01:32:05 PM PDT 24
Peak memory 242120 kb
Host smart-95c5107f-6199-41e8-afd8-588739bb01bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786098842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.1786098842
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.1990288136
Short name T21
Test name
Test status
Simulation time 1942483102 ps
CPU time 6.1 seconds
Started May 26 01:32:08 PM PDT 24
Finished May 26 01:32:15 PM PDT 24
Peak memory 242012 kb
Host smart-fdd8e923-ffca-43ee-81b5-230dfd3b23cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990288136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.1990288136
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.1821324273
Short name T354
Test name
Test status
Simulation time 1458688251 ps
CPU time 11.69 seconds
Started May 26 01:25:58 PM PDT 24
Finished May 26 01:26:11 PM PDT 24
Peak memory 242012 kb
Host smart-83b1249f-bebb-4dd1-b003-01f0245abfa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1821324273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.1821324273
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3120472810
Short name T341
Test name
Test status
Simulation time 4781717012 ps
CPU time 23.6 seconds
Started May 26 01:18:26 PM PDT 24
Finished May 26 01:18:50 PM PDT 24
Peak memory 243976 kb
Host smart-72aeca9e-2e49-4431-8288-fbec6e8329c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120472810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.3120472810
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.1283219244
Short name T340
Test name
Test status
Simulation time 746098827 ps
CPU time 10.35 seconds
Started May 26 01:18:53 PM PDT 24
Finished May 26 01:19:04 PM PDT 24
Peak memory 243724 kb
Host smart-2840477a-4dc5-49be-b144-09a327efc558
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283219244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.1283219244
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.701944812
Short name T292
Test name
Test status
Simulation time 93527253 ps
CPU time 4.69 seconds
Started May 26 01:18:28 PM PDT 24
Finished May 26 01:18:34 PM PDT 24
Peak memory 237332 kb
Host smart-9e3b1945-ab2d-4dd4-a2c0-33f15b6df533
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701944812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alias
ing.701944812
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.179031237
Short name T254
Test name
Test status
Simulation time 38786742597 ps
CPU time 171.45 seconds
Started May 26 01:30:19 PM PDT 24
Finished May 26 01:33:12 PM PDT 24
Peak memory 257088 kb
Host smart-d55ceefb-84f5-4c78-a03a-ccaf0cc0d6d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179031237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.
179031237
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.3515206535
Short name T153
Test name
Test status
Simulation time 50304627 ps
CPU time 1.75 seconds
Started May 26 01:24:29 PM PDT 24
Finished May 26 01:24:31 PM PDT 24
Peak memory 240672 kb
Host smart-c129b5cf-2e2d-42b6-be9e-588489cd1137
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3515206535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.3515206535
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.2993018132
Short name T231
Test name
Test status
Simulation time 5899437729 ps
CPU time 111.89 seconds
Started May 26 01:24:45 PM PDT 24
Finished May 26 01:26:38 PM PDT 24
Peak memory 244512 kb
Host smart-79c8148b-b835-4b68-9a90-b0b976ebeb7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993018132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.
2993018132
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.2684664027
Short name T1130
Test name
Test status
Simulation time 461166893 ps
CPU time 3.92 seconds
Started May 26 01:28:06 PM PDT 24
Finished May 26 01:28:11 PM PDT 24
Peak memory 242136 kb
Host smart-6613331b-b14d-4695-b331-72bf2ec16bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684664027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.2684664027
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.1809097558
Short name T129
Test name
Test status
Simulation time 6753266549 ps
CPU time 84.27 seconds
Started May 26 01:24:37 PM PDT 24
Finished May 26 01:26:02 PM PDT 24
Peak memory 260800 kb
Host smart-2b2cc09a-2b05-4787-b145-439cc58611c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809097558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
1809097558
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.2275935568
Short name T358
Test name
Test status
Simulation time 495715941 ps
CPU time 11.2 seconds
Started May 26 01:27:38 PM PDT 24
Finished May 26 01:27:50 PM PDT 24
Peak memory 248592 kb
Host smart-77561bb0-c2d1-46f4-9bda-f06fbed943f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2275935568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.2275935568
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.3204144815
Short name T245
Test name
Test status
Simulation time 18563747790 ps
CPU time 216.85 seconds
Started May 26 01:29:11 PM PDT 24
Finished May 26 01:32:49 PM PDT 24
Peak memory 248720 kb
Host smart-0245a6a3-1ce1-4af8-82cf-aaeab82d7794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204144815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.3204144815
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.359910649
Short name T266
Test name
Test status
Simulation time 19032671880 ps
CPU time 29.8 seconds
Started May 26 01:19:01 PM PDT 24
Finished May 26 01:19:33 PM PDT 24
Peak memory 238676 kb
Host smart-01663c62-7425-46af-8f8a-2ec3f9f944a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359910649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_in
tg_err.359910649
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.3316416627
Short name T234
Test name
Test status
Simulation time 10353747312 ps
CPU time 188.25 seconds
Started May 26 01:24:54 PM PDT 24
Finished May 26 01:28:03 PM PDT 24
Peak memory 279528 kb
Host smart-5ae07876-e838-4d9c-9319-b1bd25c1ddfc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316416627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.3316416627
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.3832754341
Short name T516
Test name
Test status
Simulation time 3263608127 ps
CPU time 41.97 seconds
Started May 26 01:30:28 PM PDT 24
Finished May 26 01:31:11 PM PDT 24
Peak memory 242484 kb
Host smart-99d1cc97-bde1-41c7-846d-4bfc8a3f6bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832754341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.3832754341
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.54653043
Short name T85
Test name
Test status
Simulation time 542535382 ps
CPU time 5.26 seconds
Started May 26 01:33:45 PM PDT 24
Finished May 26 01:33:51 PM PDT 24
Peak memory 242144 kb
Host smart-786de976-a4ab-4444-a2fe-5adc8589825f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54653043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.54653043
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.3347559190
Short name T519
Test name
Test status
Simulation time 16759416911 ps
CPU time 109.41 seconds
Started May 26 01:28:17 PM PDT 24
Finished May 26 01:30:08 PM PDT 24
Peak memory 248932 kb
Host smart-7e1c3192-093e-41e0-a87a-8b296a5f92b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347559190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all
.3347559190
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.4120253006
Short name T86
Test name
Test status
Simulation time 296571244 ps
CPU time 4.88 seconds
Started May 26 01:31:57 PM PDT 24
Finished May 26 01:32:03 PM PDT 24
Peak memory 242352 kb
Host smart-cdb2e0d0-e788-4af4-a63e-e24e7ed26562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120253006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.4120253006
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.2100471014
Short name T476
Test name
Test status
Simulation time 1049634092 ps
CPU time 24.11 seconds
Started May 26 01:26:38 PM PDT 24
Finished May 26 01:27:03 PM PDT 24
Peak memory 241836 kb
Host smart-2aaf9650-0f66-4298-8a53-269b769f4082
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2100471014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.2100471014
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3222071621
Short name T1215
Test name
Test status
Simulation time 316863147 ps
CPU time 6.08 seconds
Started May 26 01:18:28 PM PDT 24
Finished May 26 01:18:35 PM PDT 24
Peak memory 237720 kb
Host smart-782fb280-36c2-4f97-a5b3-d2014c8c9dae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222071621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.3222071621
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1571526505
Short name T1232
Test name
Test status
Simulation time 497389345 ps
CPU time 9.84 seconds
Started May 26 01:18:27 PM PDT 24
Finished May 26 01:18:38 PM PDT 24
Peak memory 238536 kb
Host smart-b00111ad-e1c9-4f77-aeb9-12b1486e3a2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571526505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.1571526505
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.4134522811
Short name T1221
Test name
Test status
Simulation time 119917980 ps
CPU time 1.89 seconds
Started May 26 01:18:23 PM PDT 24
Finished May 26 01:18:25 PM PDT 24
Peak memory 237356 kb
Host smart-9756252e-36ca-4d3c-9ad0-92c35ba33e66
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134522811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r
eset.4134522811
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3042150206
Short name T1276
Test name
Test status
Simulation time 115457596 ps
CPU time 2.77 seconds
Started May 26 01:18:26 PM PDT 24
Finished May 26 01:18:29 PM PDT 24
Peak memory 246028 kb
Host smart-321463ef-3d93-40d3-b9dc-cd06d96866b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042150206 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.3042150206
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.398236403
Short name T316
Test name
Test status
Simulation time 73615766 ps
CPU time 1.64 seconds
Started May 26 01:18:27 PM PDT 24
Finished May 26 01:18:29 PM PDT 24
Peak memory 239948 kb
Host smart-0c9eaf26-72c8-4e34-893f-3e1a970138d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398236403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.398236403
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.3437432279
Short name T1238
Test name
Test status
Simulation time 42589308 ps
CPU time 1.44 seconds
Started May 26 01:18:28 PM PDT 24
Finished May 26 01:18:31 PM PDT 24
Peak memory 229328 kb
Host smart-f68f2bf6-e8d7-46f6-82a7-39b0c856d8c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437432279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.3437432279
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3474360694
Short name T1283
Test name
Test status
Simulation time 131368946 ps
CPU time 1.43 seconds
Started May 26 01:18:28 PM PDT 24
Finished May 26 01:18:30 PM PDT 24
Peak memory 228840 kb
Host smart-4074e270-e8aa-4d20-9677-ea6eedee582d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474360694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.3474360694
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3858616801
Short name T1299
Test name
Test status
Simulation time 124588650 ps
CPU time 1.34 seconds
Started May 26 01:18:29 PM PDT 24
Finished May 26 01:18:31 PM PDT 24
Peak memory 229340 kb
Host smart-1c542aaf-a653-4f10-945b-cdc1ecef8174
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858616801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.3858616801
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.2498757339
Short name T1231
Test name
Test status
Simulation time 136264818 ps
CPU time 3.34 seconds
Started May 26 01:18:27 PM PDT 24
Finished May 26 01:18:31 PM PDT 24
Peak memory 238764 kb
Host smart-81847645-6943-46b1-9f32-a43e30356fab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498757339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.2498757339
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2325491622
Short name T1252
Test name
Test status
Simulation time 61203927 ps
CPU time 3.36 seconds
Started May 26 01:18:24 PM PDT 24
Finished May 26 01:18:28 PM PDT 24
Peak memory 246396 kb
Host smart-4d6b0889-73f2-4389-8d35-b42f8fb47995
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325491622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.2325491622
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2655596602
Short name T299
Test name
Test status
Simulation time 80682976 ps
CPU time 3.97 seconds
Started May 26 01:18:22 PM PDT 24
Finished May 26 01:18:27 PM PDT 24
Peak memory 237416 kb
Host smart-2e7476db-8c26-4aa1-8fef-546a5007e4b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655596602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_
bash.2655596602
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1974234758
Short name T293
Test name
Test status
Simulation time 130994736 ps
CPU time 2.07 seconds
Started May 26 01:18:29 PM PDT 24
Finished May 26 01:18:32 PM PDT 24
Peak memory 238648 kb
Host smart-71b479a1-9f7c-48e9-b7e8-ce1453ef8800
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974234758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.1974234758
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3695272667
Short name T1241
Test name
Test status
Simulation time 424865473 ps
CPU time 2.81 seconds
Started May 26 01:18:25 PM PDT 24
Finished May 26 01:18:29 PM PDT 24
Peak memory 246928 kb
Host smart-50874a19-4226-42dc-b0c5-9679c9baea71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695272667 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.3695272667
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2510983552
Short name T304
Test name
Test status
Simulation time 668581984 ps
CPU time 1.85 seconds
Started May 26 01:18:28 PM PDT 24
Finished May 26 01:18:32 PM PDT 24
Peak memory 238656 kb
Host smart-c627c6b0-dfc9-4269-bbd4-d839b3342277
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510983552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.2510983552
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.3466840319
Short name T1195
Test name
Test status
Simulation time 560183164 ps
CPU time 1.79 seconds
Started May 26 01:18:24 PM PDT 24
Finished May 26 01:18:27 PM PDT 24
Peak memory 229224 kb
Host smart-db063a40-c2de-4764-90d0-dfdf32becd04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466840319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.3466840319
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.166889942
Short name T1216
Test name
Test status
Simulation time 64454248 ps
CPU time 1.37 seconds
Started May 26 01:18:28 PM PDT 24
Finished May 26 01:18:30 PM PDT 24
Peak memory 230536 kb
Host smart-9575d3f5-f4a3-4b4a-890d-206599dd0486
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166889942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl
_mem_partial_access.166889942
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2996311451
Short name T1228
Test name
Test status
Simulation time 62899405 ps
CPU time 1.36 seconds
Started May 26 01:18:29 PM PDT 24
Finished May 26 01:18:32 PM PDT 24
Peak memory 229528 kb
Host smart-d7dac185-5c75-4b50-9a43-4966fccecabc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996311451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.2996311451
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.3910126774
Short name T1273
Test name
Test status
Simulation time 329629820 ps
CPU time 3.09 seconds
Started May 26 01:18:25 PM PDT 24
Finished May 26 01:18:29 PM PDT 24
Peak memory 238628 kb
Host smart-e6841598-7fbc-45cd-a8da-6d1cb22d960d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910126774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.3910126774
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.4229627928
Short name T1203
Test name
Test status
Simulation time 753500605 ps
CPU time 6.9 seconds
Started May 26 01:18:24 PM PDT 24
Finished May 26 01:18:32 PM PDT 24
Peak memory 246616 kb
Host smart-23c8e7bd-733b-4dae-ab17-05931192ea86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229627928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.4229627928
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.546261510
Short name T1192
Test name
Test status
Simulation time 1690479042 ps
CPU time 3.9 seconds
Started May 26 01:18:49 PM PDT 24
Finished May 26 01:18:54 PM PDT 24
Peak memory 246968 kb
Host smart-729d551f-726a-4eb4-92ea-3d0dada456dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546261510 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.546261510
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.2812990695
Short name T1256
Test name
Test status
Simulation time 44952715 ps
CPU time 1.56 seconds
Started May 26 01:18:56 PM PDT 24
Finished May 26 01:18:58 PM PDT 24
Peak memory 238696 kb
Host smart-9ad027d4-e804-4438-af19-a65471825443
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812990695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.2812990695
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.341026249
Short name T1230
Test name
Test status
Simulation time 107935627 ps
CPU time 1.51 seconds
Started May 26 01:18:53 PM PDT 24
Finished May 26 01:18:55 PM PDT 24
Peak memory 229400 kb
Host smart-67b0f745-9e0a-40d3-b095-309d2bf16045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341026249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.341026249
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1838226674
Short name T320
Test name
Test status
Simulation time 1024853049 ps
CPU time 2.98 seconds
Started May 26 01:18:50 PM PDT 24
Finished May 26 01:18:54 PM PDT 24
Peak memory 237680 kb
Host smart-c863f865-308e-487a-ac0c-911feabf2b00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838226674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.1838226674
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.146253497
Short name T1253
Test name
Test status
Simulation time 88790476 ps
CPU time 5.54 seconds
Started May 26 01:18:50 PM PDT 24
Finished May 26 01:18:57 PM PDT 24
Peak memory 246336 kb
Host smart-b8e024d7-8794-4a19-9fc0-980019f5d196
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146253497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.146253497
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.823882879
Short name T1275
Test name
Test status
Simulation time 2356744976 ps
CPU time 10.65 seconds
Started May 26 01:18:49 PM PDT 24
Finished May 26 01:19:01 PM PDT 24
Peak memory 243932 kb
Host smart-4fd29e5f-5364-4d49-bd0f-9eda6387e529
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823882879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_in
tg_err.823882879
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.2832603514
Short name T1204
Test name
Test status
Simulation time 114288156 ps
CPU time 2.82 seconds
Started May 26 01:19:02 PM PDT 24
Finished May 26 01:19:06 PM PDT 24
Peak memory 246356 kb
Host smart-f8e310c7-4542-466c-90bc-dc439fea31ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832603514 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.2832603514
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1490885909
Short name T303
Test name
Test status
Simulation time 135795598 ps
CPU time 1.5 seconds
Started May 26 01:18:55 PM PDT 24
Finished May 26 01:18:57 PM PDT 24
Peak memory 239588 kb
Host smart-0b98a571-d279-4aaf-aeb4-aacfc8d94304
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490885909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.1490885909
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2705756427
Short name T1196
Test name
Test status
Simulation time 136530734 ps
CPU time 1.49 seconds
Started May 26 01:18:49 PM PDT 24
Finished May 26 01:18:51 PM PDT 24
Peak memory 229332 kb
Host smart-6bf43c17-7f47-4d52-a91b-b0f76cc22306
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705756427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.2705756427
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1160729450
Short name T1227
Test name
Test status
Simulation time 229392702 ps
CPU time 2.4 seconds
Started May 26 01:18:55 PM PDT 24
Finished May 26 01:18:58 PM PDT 24
Peak memory 237552 kb
Host smart-d1b6168e-27ff-40dc-adbb-a40d6f6f3bd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160729450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.1160729450
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2084979351
Short name T1281
Test name
Test status
Simulation time 174919572 ps
CPU time 6.49 seconds
Started May 26 01:18:53 PM PDT 24
Finished May 26 01:19:00 PM PDT 24
Peak memory 246528 kb
Host smart-103bc631-caf5-48f4-acf2-f3cf10a60a25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084979351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.2084979351
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.540744746
Short name T342
Test name
Test status
Simulation time 1607494390 ps
CPU time 18.15 seconds
Started May 26 01:18:56 PM PDT 24
Finished May 26 01:19:15 PM PDT 24
Peak memory 238664 kb
Host smart-db075c14-a9d0-491b-8252-5d228b073777
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540744746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_in
tg_err.540744746
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1853132834
Short name T1304
Test name
Test status
Simulation time 71723763 ps
CPU time 1.92 seconds
Started May 26 01:18:56 PM PDT 24
Finished May 26 01:18:58 PM PDT 24
Peak memory 244640 kb
Host smart-11159a50-1e68-41bb-a30b-9f899cb50ae8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853132834 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.1853132834
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.265268336
Short name T1311
Test name
Test status
Simulation time 148931599 ps
CPU time 1.64 seconds
Started May 26 01:18:54 PM PDT 24
Finished May 26 01:18:56 PM PDT 24
Peak memory 239880 kb
Host smart-dce2e97d-51cf-4fc8-999c-c67bb5bde585
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265268336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.265268336
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.1323967860
Short name T1284
Test name
Test status
Simulation time 133625852 ps
CPU time 1.43 seconds
Started May 26 01:18:51 PM PDT 24
Finished May 26 01:18:53 PM PDT 24
Peak memory 229548 kb
Host smart-c0005e4d-d98a-4136-afa0-167e284ecb7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323967860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.1323967860
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.3850274113
Short name T265
Test name
Test status
Simulation time 103071877 ps
CPU time 2.16 seconds
Started May 26 01:18:52 PM PDT 24
Finished May 26 01:18:55 PM PDT 24
Peak memory 237564 kb
Host smart-fb043c14-b879-42e0-ade2-a7cdaf5b64ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850274113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.3850274113
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2741326484
Short name T1312
Test name
Test status
Simulation time 305399565 ps
CPU time 5.3 seconds
Started May 26 01:18:49 PM PDT 24
Finished May 26 01:18:55 PM PDT 24
Peak memory 246968 kb
Host smart-36032c41-1f12-4a97-842e-3bfb9a498ba9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741326484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.2741326484
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2091813377
Short name T262
Test name
Test status
Simulation time 10194510073 ps
CPU time 20.71 seconds
Started May 26 01:18:49 PM PDT 24
Finished May 26 01:19:10 PM PDT 24
Peak memory 244256 kb
Host smart-992e8ba7-6515-4628-8875-c7172b26bb6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091813377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.2091813377
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1836014986
Short name T1243
Test name
Test status
Simulation time 104304012 ps
CPU time 2.89 seconds
Started May 26 01:19:02 PM PDT 24
Finished May 26 01:19:06 PM PDT 24
Peak memory 246820 kb
Host smart-2d915eb4-fdbc-4c4c-8d34-15cae5bb0990
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836014986 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.1836014986
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.3827528302
Short name T302
Test name
Test status
Simulation time 39931523 ps
CPU time 1.5 seconds
Started May 26 01:18:48 PM PDT 24
Finished May 26 01:18:51 PM PDT 24
Peak memory 239424 kb
Host smart-27f4c997-cb51-4831-8892-6ef683a7044a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827528302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.3827528302
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.3648871167
Short name T1294
Test name
Test status
Simulation time 73563518 ps
CPU time 1.47 seconds
Started May 26 01:18:51 PM PDT 24
Finished May 26 01:18:53 PM PDT 24
Peak memory 229588 kb
Host smart-53c7f442-360e-4917-b762-007859cdcbfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648871167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.3648871167
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3062422630
Short name T1239
Test name
Test status
Simulation time 47584800 ps
CPU time 1.93 seconds
Started May 26 01:18:53 PM PDT 24
Finished May 26 01:18:56 PM PDT 24
Peak memory 238680 kb
Host smart-f136d031-fd9f-4d46-97f4-f41a70a79848
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062422630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.3062422630
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.4002997168
Short name T1251
Test name
Test status
Simulation time 53768492 ps
CPU time 2.94 seconds
Started May 26 01:18:53 PM PDT 24
Finished May 26 01:18:56 PM PDT 24
Peak memory 246428 kb
Host smart-68bba0fe-02a3-43c4-b5f5-8f50db445991
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002997168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.4002997168
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.2185265792
Short name T264
Test name
Test status
Simulation time 1893838043 ps
CPU time 21.65 seconds
Started May 26 01:18:53 PM PDT 24
Finished May 26 01:19:16 PM PDT 24
Peak memory 243364 kb
Host smart-28796fd9-1ca1-420b-b6ad-862abe2d6ac6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185265792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.2185265792
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1153863686
Short name T1315
Test name
Test status
Simulation time 99021292 ps
CPU time 3.31 seconds
Started May 26 01:18:50 PM PDT 24
Finished May 26 01:18:54 PM PDT 24
Peak memory 246876 kb
Host smart-94482c84-5ea0-4121-81fa-b52511409f1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153863686 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.1153863686
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3322322903
Short name T294
Test name
Test status
Simulation time 41499615 ps
CPU time 1.61 seconds
Started May 26 01:18:55 PM PDT 24
Finished May 26 01:18:57 PM PDT 24
Peak memory 239316 kb
Host smart-6e943c6a-a9ce-409f-a905-74f11036c66d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322322903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.3322322903
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.22517678
Short name T1188
Test name
Test status
Simulation time 59293550 ps
CPU time 1.54 seconds
Started May 26 01:18:52 PM PDT 24
Finished May 26 01:18:54 PM PDT 24
Peak memory 229220 kb
Host smart-fd357a0c-23c9-4558-92cb-50ae861af908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22517678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.22517678
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1216539265
Short name T1314
Test name
Test status
Simulation time 646198798 ps
CPU time 2.14 seconds
Started May 26 01:18:51 PM PDT 24
Finished May 26 01:18:54 PM PDT 24
Peak memory 238648 kb
Host smart-cde4e7af-fbb0-4fa6-913e-12cfa5836f67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216539265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.1216539265
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.691065126
Short name T1250
Test name
Test status
Simulation time 721829748 ps
CPU time 6.98 seconds
Started May 26 01:18:50 PM PDT 24
Finished May 26 01:18:58 PM PDT 24
Peak memory 247152 kb
Host smart-0cda5ed7-188a-4139-a55c-be5e2cb1460b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691065126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.691065126
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3401264545
Short name T339
Test name
Test status
Simulation time 2752294744 ps
CPU time 11.14 seconds
Started May 26 01:18:52 PM PDT 24
Finished May 26 01:19:04 PM PDT 24
Peak memory 238712 kb
Host smart-82c6489c-49bc-4dfa-a8dc-c5cd88e44da9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401264545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.3401264545
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1387663841
Short name T1226
Test name
Test status
Simulation time 103167903 ps
CPU time 4.06 seconds
Started May 26 01:18:50 PM PDT 24
Finished May 26 01:18:55 PM PDT 24
Peak memory 246872 kb
Host smart-b6f0ad93-f566-419f-a40c-c6a699c2b5ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387663841 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.1387663841
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3700596984
Short name T1300
Test name
Test status
Simulation time 616061046 ps
CPU time 1.91 seconds
Started May 26 01:18:48 PM PDT 24
Finished May 26 01:18:51 PM PDT 24
Peak memory 239820 kb
Host smart-3afc9b62-9f91-4b35-970d-ae830f2109df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700596984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.3700596984
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.1997163168
Short name T1295
Test name
Test status
Simulation time 91063495 ps
CPU time 1.38 seconds
Started May 26 01:18:56 PM PDT 24
Finished May 26 01:18:58 PM PDT 24
Peak memory 230540 kb
Host smart-0a559e9c-d2fc-475b-9b3e-ec330e68c1a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997163168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.1997163168
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.1843697417
Short name T1292
Test name
Test status
Simulation time 73974378 ps
CPU time 2.39 seconds
Started May 26 01:18:51 PM PDT 24
Finished May 26 01:18:54 PM PDT 24
Peak memory 238604 kb
Host smart-32d51811-15a9-40ed-b49a-75cbe4d86679
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843697417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_
ctrl_same_csr_outstanding.1843697417
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.519661546
Short name T1197
Test name
Test status
Simulation time 118138366 ps
CPU time 3.51 seconds
Started May 26 01:18:54 PM PDT 24
Finished May 26 01:18:58 PM PDT 24
Peak memory 238788 kb
Host smart-5237b9b2-0510-4d1f-bdcf-bf6b403a88cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519661546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.519661546
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3691280830
Short name T347
Test name
Test status
Simulation time 2899806144 ps
CPU time 10.42 seconds
Started May 26 01:18:50 PM PDT 24
Finished May 26 01:19:01 PM PDT 24
Peak memory 238720 kb
Host smart-e5c36dfc-e21a-45dd-af32-5eb2cf838f77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691280830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i
ntg_err.3691280830
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2282313160
Short name T1277
Test name
Test status
Simulation time 135821954 ps
CPU time 2.25 seconds
Started May 26 01:18:50 PM PDT 24
Finished May 26 01:18:53 PM PDT 24
Peak memory 245668 kb
Host smart-cffdb5a4-f462-422c-9bdb-554a287ad1e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282313160 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.2282313160
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.4230411207
Short name T1285
Test name
Test status
Simulation time 676017989 ps
CPU time 2.41 seconds
Started May 26 01:18:49 PM PDT 24
Finished May 26 01:18:52 PM PDT 24
Peak memory 239820 kb
Host smart-3ffaec38-6d0a-4900-9ad3-4a031a0f2b9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230411207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.4230411207
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.3761065910
Short name T1309
Test name
Test status
Simulation time 130953596 ps
CPU time 1.47 seconds
Started May 26 01:18:52 PM PDT 24
Finished May 26 01:18:55 PM PDT 24
Peak memory 229640 kb
Host smart-cc7502a6-3cd2-4eec-9fbb-eb5264b7cec4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761065910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.3761065910
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.972637091
Short name T314
Test name
Test status
Simulation time 70657702 ps
CPU time 2.29 seconds
Started May 26 01:18:51 PM PDT 24
Finished May 26 01:18:54 PM PDT 24
Peak memory 238632 kb
Host smart-76ec50a8-b38e-4771-be16-0cfa8891196b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972637091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_c
trl_same_csr_outstanding.972637091
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.3650003241
Short name T1289
Test name
Test status
Simulation time 65696260 ps
CPU time 4.61 seconds
Started May 26 01:18:49 PM PDT 24
Finished May 26 01:18:55 PM PDT 24
Peak memory 238736 kb
Host smart-c4c83adb-6816-437c-9538-be8b98f0f58e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650003241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.3650003241
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.3503899032
Short name T1313
Test name
Test status
Simulation time 3564973139 ps
CPU time 20.01 seconds
Started May 26 01:18:50 PM PDT 24
Finished May 26 01:19:11 PM PDT 24
Peak memory 244708 kb
Host smart-f7b385a4-3ac6-46fd-8f7f-6b95f61cada6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503899032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.3503899032
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.153034669
Short name T1236
Test name
Test status
Simulation time 240262875 ps
CPU time 2.43 seconds
Started May 26 01:18:56 PM PDT 24
Finished May 26 01:19:00 PM PDT 24
Peak memory 246844 kb
Host smart-78de63d4-fb54-46e5-bacf-e910256af2fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153034669 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.153034669
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2857064209
Short name T315
Test name
Test status
Simulation time 91706018 ps
CPU time 1.71 seconds
Started May 26 01:18:54 PM PDT 24
Finished May 26 01:18:57 PM PDT 24
Peak memory 239636 kb
Host smart-56e19195-0e7d-47ad-87a0-dd2fd4d6e9c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857064209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.2857064209
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.4285472838
Short name T1302
Test name
Test status
Simulation time 599702612 ps
CPU time 1.89 seconds
Started May 26 01:18:49 PM PDT 24
Finished May 26 01:18:51 PM PDT 24
Peak memory 229600 kb
Host smart-a776065c-c241-40c7-a6ef-57cb5c656587
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285472838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.4285472838
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.3543150950
Short name T319
Test name
Test status
Simulation time 494184088 ps
CPU time 3.51 seconds
Started May 26 01:18:52 PM PDT 24
Finished May 26 01:18:56 PM PDT 24
Peak memory 238744 kb
Host smart-cfbca72c-144d-4b82-9513-38ee8b053054
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543150950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.3543150950
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.587791318
Short name T1206
Test name
Test status
Simulation time 751146017 ps
CPU time 3.67 seconds
Started May 26 01:18:53 PM PDT 24
Finished May 26 01:18:58 PM PDT 24
Peak memory 245540 kb
Host smart-38b52a01-62cb-49cf-8797-5e832a6c70a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587791318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.587791318
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.2642675345
Short name T1301
Test name
Test status
Simulation time 205911887 ps
CPU time 2.94 seconds
Started May 26 01:19:01 PM PDT 24
Finished May 26 01:19:05 PM PDT 24
Peak memory 246776 kb
Host smart-78594d18-b0f2-4e8b-8aa8-a5cfb9eb73ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642675345 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.2642675345
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.3036342024
Short name T1211
Test name
Test status
Simulation time 593206258 ps
CPU time 1.39 seconds
Started May 26 01:18:52 PM PDT 24
Finished May 26 01:18:54 PM PDT 24
Peak memory 230532 kb
Host smart-9c044bf7-b918-42cc-ae95-e0daede081aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036342024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.3036342024
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1964176565
Short name T322
Test name
Test status
Simulation time 392647428 ps
CPU time 3.39 seconds
Started May 26 01:19:02 PM PDT 24
Finished May 26 01:19:06 PM PDT 24
Peak memory 237584 kb
Host smart-5775f403-0d71-4617-a309-a8f2c38a17bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964176565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.1964176565
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2632049350
Short name T1191
Test name
Test status
Simulation time 793186152 ps
CPU time 7.42 seconds
Started May 26 01:19:02 PM PDT 24
Finished May 26 01:19:11 PM PDT 24
Peak memory 246628 kb
Host smart-9f86fabf-d7b7-4414-8fa7-116ad1a8bf2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632049350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.2632049350
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1470475840
Short name T1220
Test name
Test status
Simulation time 266044675 ps
CPU time 2.23 seconds
Started May 26 01:19:06 PM PDT 24
Finished May 26 01:19:09 PM PDT 24
Peak memory 244304 kb
Host smart-63571b2c-9bd6-4d41-9b39-88ef43d9a6bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470475840 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.1470475840
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1970004492
Short name T296
Test name
Test status
Simulation time 141946224 ps
CPU time 1.51 seconds
Started May 26 01:18:58 PM PDT 24
Finished May 26 01:19:01 PM PDT 24
Peak memory 238648 kb
Host smart-9864efe8-5089-4823-8351-e95c687cb625
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970004492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.1970004492
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3807218855
Short name T1258
Test name
Test status
Simulation time 40105600 ps
CPU time 1.47 seconds
Started May 26 01:18:59 PM PDT 24
Finished May 26 01:19:02 PM PDT 24
Peak memory 230536 kb
Host smart-cdbe8fb7-a35d-4338-b229-64bf91eccd15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807218855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.3807218855
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.469417989
Short name T1293
Test name
Test status
Simulation time 118104310 ps
CPU time 2.44 seconds
Started May 26 01:18:59 PM PDT 24
Finished May 26 01:19:02 PM PDT 24
Peak memory 238692 kb
Host smart-be18f194-6424-4c9a-b93d-d8c4760a8b89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469417989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_c
trl_same_csr_outstanding.469417989
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1382262475
Short name T1268
Test name
Test status
Simulation time 804072315 ps
CPU time 3.67 seconds
Started May 26 01:19:00 PM PDT 24
Finished May 26 01:19:05 PM PDT 24
Peak memory 246620 kb
Host smart-994f0498-375b-478d-9abe-aa55a743dcd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382262475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.1382262475
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1048124019
Short name T348
Test name
Test status
Simulation time 10523594838 ps
CPU time 13.55 seconds
Started May 26 01:18:56 PM PDT 24
Finished May 26 01:19:10 PM PDT 24
Peak memory 238780 kb
Host smart-b115c7ec-dbd9-45be-a480-53bf15ce321b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048124019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.1048124019
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3994881099
Short name T297
Test name
Test status
Simulation time 191201067 ps
CPU time 5.82 seconds
Started May 26 01:18:33 PM PDT 24
Finished May 26 01:18:40 PM PDT 24
Peak memory 237332 kb
Host smart-08a6ddb6-b094-42c7-81aa-b62b06bc6401
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994881099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.3994881099
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3783020798
Short name T1282
Test name
Test status
Simulation time 1096448371 ps
CPU time 5.45 seconds
Started May 26 01:18:31 PM PDT 24
Finished May 26 01:18:37 PM PDT 24
Peak memory 238664 kb
Host smart-fd45a9ee-dda8-4dc7-a6c9-84c66a6c9a3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783020798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.3783020798
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.294985707
Short name T1318
Test name
Test status
Simulation time 130911833 ps
CPU time 1.97 seconds
Started May 26 01:18:38 PM PDT 24
Finished May 26 01:18:41 PM PDT 24
Peak memory 237444 kb
Host smart-7ef12b8f-1b79-426a-bf7a-f9355cc41f69
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294985707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_re
set.294985707
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.2015279549
Short name T1271
Test name
Test status
Simulation time 82539719 ps
CPU time 2.12 seconds
Started May 26 01:18:31 PM PDT 24
Finished May 26 01:18:34 PM PDT 24
Peak memory 244828 kb
Host smart-5c810b52-8836-46c1-87d3-206f6f221834
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015279549 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.2015279549
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.695689871
Short name T291
Test name
Test status
Simulation time 72431336 ps
CPU time 1.6 seconds
Started May 26 01:18:32 PM PDT 24
Finished May 26 01:18:34 PM PDT 24
Peak memory 239868 kb
Host smart-01d7b497-dcae-439b-87b7-104d7d3375a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695689871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.695689871
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.1341226751
Short name T1274
Test name
Test status
Simulation time 82340258 ps
CPU time 1.46 seconds
Started May 26 01:18:24 PM PDT 24
Finished May 26 01:18:25 PM PDT 24
Peak memory 229712 kb
Host smart-ddba7568-18cd-4071-bb55-6c41c895206c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341226751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.1341226751
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.3121973702
Short name T1286
Test name
Test status
Simulation time 56305888 ps
CPU time 1.35 seconds
Started May 26 01:18:26 PM PDT 24
Finished May 26 01:18:27 PM PDT 24
Peak memory 228820 kb
Host smart-da5436a0-a49f-464b-b578-d333586318a4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121973702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.3121973702
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.4135746354
Short name T1235
Test name
Test status
Simulation time 130079769 ps
CPU time 1.52 seconds
Started May 26 01:18:23 PM PDT 24
Finished May 26 01:18:25 PM PDT 24
Peak memory 230380 kb
Host smart-1ce66571-ab91-459f-a661-789f3a78d346
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135746354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.4135746354
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1016044823
Short name T1279
Test name
Test status
Simulation time 207955623 ps
CPU time 3.21 seconds
Started May 26 01:18:31 PM PDT 24
Finished May 26 01:18:34 PM PDT 24
Peak memory 237580 kb
Host smart-fd8aec6b-1d5e-4120-9ed7-d2bceb3f93cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016044823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.1016044823
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.24909759
Short name T1267
Test name
Test status
Simulation time 226768383 ps
CPU time 4.62 seconds
Started May 26 01:18:28 PM PDT 24
Finished May 26 01:18:34 PM PDT 24
Peak memory 246744 kb
Host smart-f6a31c5b-d1c0-424e-b14f-97a922b41aee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24909759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.24909759
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.3941522564
Short name T346
Test name
Test status
Simulation time 10439563685 ps
CPU time 15.03 seconds
Started May 26 01:18:28 PM PDT 24
Finished May 26 01:18:44 PM PDT 24
Peak memory 244360 kb
Host smart-93e836a3-5966-46ad-9c4b-4dfd13ffe7da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941522564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.3941522564
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.326301145
Short name T1317
Test name
Test status
Simulation time 39138842 ps
CPU time 1.46 seconds
Started May 26 01:19:00 PM PDT 24
Finished May 26 01:19:03 PM PDT 24
Peak memory 229676 kb
Host smart-303fff89-41bc-4abf-b8aa-26ce608ca137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326301145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.326301145
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2165236948
Short name T1214
Test name
Test status
Simulation time 90743905 ps
CPU time 1.48 seconds
Started May 26 01:19:02 PM PDT 24
Finished May 26 01:19:05 PM PDT 24
Peak memory 229204 kb
Host smart-c42b1590-d134-424a-989c-06e197d9cef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165236948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.2165236948
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.3064722563
Short name T1202
Test name
Test status
Simulation time 144079342 ps
CPU time 1.66 seconds
Started May 26 01:19:01 PM PDT 24
Finished May 26 01:19:04 PM PDT 24
Peak memory 229584 kb
Host smart-dd1abc90-25e9-4149-a169-2be009f3a552
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064722563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.3064722563
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.1723998649
Short name T1190
Test name
Test status
Simulation time 56361615 ps
CPU time 1.61 seconds
Started May 26 01:18:59 PM PDT 24
Finished May 26 01:19:01 PM PDT 24
Peak memory 229284 kb
Host smart-99a48ad9-dd44-4a06-b760-9fef1ab0d3f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723998649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.1723998649
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2237402111
Short name T1290
Test name
Test status
Simulation time 77371978 ps
CPU time 1.45 seconds
Started May 26 01:19:03 PM PDT 24
Finished May 26 01:19:05 PM PDT 24
Peak memory 230540 kb
Host smart-d38eb514-4309-46fd-b12f-2b3519e37876
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237402111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.2237402111
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.1803979552
Short name T1194
Test name
Test status
Simulation time 65990377 ps
CPU time 1.44 seconds
Started May 26 01:19:02 PM PDT 24
Finished May 26 01:19:05 PM PDT 24
Peak memory 229680 kb
Host smart-afa496d7-2856-4530-a1d0-f76b970f8b3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803979552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.1803979552
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.2471642979
Short name T1210
Test name
Test status
Simulation time 47952502 ps
CPU time 1.51 seconds
Started May 26 01:19:06 PM PDT 24
Finished May 26 01:19:08 PM PDT 24
Peak memory 229304 kb
Host smart-05b79f62-a5a5-43d6-94fb-3ac422154bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471642979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.2471642979
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.4105198950
Short name T1316
Test name
Test status
Simulation time 147108520 ps
CPU time 1.46 seconds
Started May 26 01:19:01 PM PDT 24
Finished May 26 01:19:04 PM PDT 24
Peak memory 229484 kb
Host smart-23921b8c-e8bd-4cca-9196-bf6faa24d689
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105198950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.4105198950
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.239285353
Short name T1264
Test name
Test status
Simulation time 44877473 ps
CPU time 1.56 seconds
Started May 26 01:18:58 PM PDT 24
Finished May 26 01:19:01 PM PDT 24
Peak memory 229156 kb
Host smart-b4a84e5b-66c3-4d4b-b0c8-ad214c2a604f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239285353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.239285353
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.809333897
Short name T1305
Test name
Test status
Simulation time 148392380 ps
CPU time 1.54 seconds
Started May 26 01:19:01 PM PDT 24
Finished May 26 01:19:04 PM PDT 24
Peak memory 229272 kb
Host smart-942488be-f338-4c3f-867f-cb82948b9cb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809333897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.809333897
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2028656970
Short name T1257
Test name
Test status
Simulation time 247525210 ps
CPU time 4.56 seconds
Started May 26 01:18:39 PM PDT 24
Finished May 26 01:18:44 PM PDT 24
Peak memory 237440 kb
Host smart-5a359c4a-8433-45cf-81fe-4228860334f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028656970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.2028656970
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.803274324
Short name T1263
Test name
Test status
Simulation time 207567570 ps
CPU time 4.86 seconds
Started May 26 01:18:34 PM PDT 24
Finished May 26 01:18:39 PM PDT 24
Peak memory 237276 kb
Host smart-40fe39d2-02b7-4a3d-b163-fbbf615cde7b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803274324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_b
ash.803274324
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3391201509
Short name T300
Test name
Test status
Simulation time 200422864 ps
CPU time 2.35 seconds
Started May 26 01:18:32 PM PDT 24
Finished May 26 01:18:35 PM PDT 24
Peak memory 237728 kb
Host smart-c7dea0b3-9f12-4267-81c5-7a5fb2ca27be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391201509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.3391201509
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1944847474
Short name T1222
Test name
Test status
Simulation time 127986721 ps
CPU time 2.39 seconds
Started May 26 01:18:42 PM PDT 24
Finished May 26 01:18:45 PM PDT 24
Peak memory 238748 kb
Host smart-4dc2c1a3-7d70-4a55-b18b-583a0ad91ed6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944847474 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.1944847474
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.458218973
Short name T1262
Test name
Test status
Simulation time 42365607 ps
CPU time 1.63 seconds
Started May 26 01:18:32 PM PDT 24
Finished May 26 01:18:34 PM PDT 24
Peak memory 238736 kb
Host smart-d73b20f1-97b2-4757-9a36-f5a3412eed49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458218973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.458218973
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.1502409152
Short name T1306
Test name
Test status
Simulation time 565927496 ps
CPU time 1.75 seconds
Started May 26 01:18:35 PM PDT 24
Finished May 26 01:18:37 PM PDT 24
Peak memory 229708 kb
Host smart-f3f54faf-c740-4388-aabc-9166d11937bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502409152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.1502409152
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.849289077
Short name T1297
Test name
Test status
Simulation time 95055976 ps
CPU time 1.48 seconds
Started May 26 01:18:31 PM PDT 24
Finished May 26 01:18:33 PM PDT 24
Peak memory 229240 kb
Host smart-2af1dd4e-63f0-4445-9e3b-9463a2ff7d55
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849289077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl
_mem_partial_access.849289077
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.1189536501
Short name T1259
Test name
Test status
Simulation time 38423431 ps
CPU time 1.42 seconds
Started May 26 01:18:32 PM PDT 24
Finished May 26 01:18:34 PM PDT 24
Peak memory 230444 kb
Host smart-dd3cb918-ed0d-4ec3-805e-0e06057a9994
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189536501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.1189536501
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2682562292
Short name T1320
Test name
Test status
Simulation time 76420360 ps
CPU time 2.18 seconds
Started May 26 01:18:41 PM PDT 24
Finished May 26 01:18:43 PM PDT 24
Peak memory 238572 kb
Host smart-167416ab-2c6b-4cc1-9d0b-143f87e6fe14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682562292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.2682562292
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.2715326856
Short name T1298
Test name
Test status
Simulation time 63206064 ps
CPU time 3.35 seconds
Started May 26 01:18:32 PM PDT 24
Finished May 26 01:18:36 PM PDT 24
Peak memory 246408 kb
Host smart-befe5408-c77a-4bcf-b1ca-403334db0ba3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715326856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.2715326856
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.3468880594
Short name T1260
Test name
Test status
Simulation time 2372886876 ps
CPU time 19.61 seconds
Started May 26 01:18:31 PM PDT 24
Finished May 26 01:18:52 PM PDT 24
Peak memory 238716 kb
Host smart-bb676f09-c796-44b9-bd76-226fbbaaff52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468880594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.3468880594
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.1625991191
Short name T1265
Test name
Test status
Simulation time 137250140 ps
CPU time 1.43 seconds
Started May 26 01:19:01 PM PDT 24
Finished May 26 01:19:04 PM PDT 24
Peak memory 229496 kb
Host smart-fb04386f-a7a2-46f5-b16c-7417845453de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625991191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.1625991191
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.1463678312
Short name T1207
Test name
Test status
Simulation time 55157353 ps
CPU time 1.49 seconds
Started May 26 01:19:00 PM PDT 24
Finished May 26 01:19:02 PM PDT 24
Peak memory 230600 kb
Host smart-667f052d-2a75-4ef7-bc65-1f05593952c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463678312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.1463678312
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.328431576
Short name T1291
Test name
Test status
Simulation time 70083071 ps
CPU time 1.45 seconds
Started May 26 01:18:59 PM PDT 24
Finished May 26 01:19:01 PM PDT 24
Peak memory 229156 kb
Host smart-6f9cc9f5-e185-4efe-b6bf-be36a652d3a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328431576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.328431576
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.1902011058
Short name T1269
Test name
Test status
Simulation time 45424251 ps
CPU time 1.48 seconds
Started May 26 01:19:01 PM PDT 24
Finished May 26 01:19:04 PM PDT 24
Peak memory 229372 kb
Host smart-d1502acc-e066-4956-aa19-325ceccb05f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902011058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.1902011058
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.2638655399
Short name T1310
Test name
Test status
Simulation time 146496423 ps
CPU time 1.54 seconds
Started May 26 01:19:03 PM PDT 24
Finished May 26 01:19:05 PM PDT 24
Peak memory 229320 kb
Host smart-4682eca1-a218-493a-bf9f-3c11fab42522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638655399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.2638655399
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3476545449
Short name T1255
Test name
Test status
Simulation time 42315276 ps
CPU time 1.56 seconds
Started May 26 01:19:02 PM PDT 24
Finished May 26 01:19:05 PM PDT 24
Peak memory 230496 kb
Host smart-31f1d844-014f-476b-a9b3-9da00e8cd59f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476545449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3476545449
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.4061092740
Short name T1272
Test name
Test status
Simulation time 36499841 ps
CPU time 1.53 seconds
Started May 26 01:19:00 PM PDT 24
Finished May 26 01:19:03 PM PDT 24
Peak memory 230560 kb
Host smart-f3edecd7-42a6-4f6e-a54b-28bfcd1a8237
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061092740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.4061092740
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.2758131764
Short name T1212
Test name
Test status
Simulation time 144056330 ps
CPU time 1.52 seconds
Started May 26 01:19:01 PM PDT 24
Finished May 26 01:19:04 PM PDT 24
Peak memory 229228 kb
Host smart-a6405338-1ed0-4055-a39b-4f48759bd940
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758131764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.2758131764
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.2470504
Short name T1223
Test name
Test status
Simulation time 139180587 ps
CPU time 1.64 seconds
Started May 26 01:18:58 PM PDT 24
Finished May 26 01:19:01 PM PDT 24
Peak memory 230484 kb
Host smart-ab4dc3e7-c585-464b-9fe2-f4e79a40cbe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.2470504
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.1854660149
Short name T1219
Test name
Test status
Simulation time 100307539 ps
CPU time 1.43 seconds
Started May 26 01:19:02 PM PDT 24
Finished May 26 01:19:05 PM PDT 24
Peak memory 229264 kb
Host smart-333c5123-0547-44e0-83bf-c7fcf3a1d8c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854660149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.1854660149
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3783716157
Short name T1319
Test name
Test status
Simulation time 118733689 ps
CPU time 3.86 seconds
Started May 26 01:18:42 PM PDT 24
Finished May 26 01:18:47 PM PDT 24
Peak memory 238668 kb
Host smart-7a8697ed-6e45-442c-9799-86c38e448268
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783716157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.3783716157
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.632243506
Short name T1254
Test name
Test status
Simulation time 156213856 ps
CPU time 3.72 seconds
Started May 26 01:18:41 PM PDT 24
Finished May 26 01:18:46 PM PDT 24
Peak memory 237576 kb
Host smart-06f22a7d-d024-43e1-93da-8c1c11220659
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632243506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_b
ash.632243506
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1001563031
Short name T1247
Test name
Test status
Simulation time 135176871 ps
CPU time 2.04 seconds
Started May 26 01:18:42 PM PDT 24
Finished May 26 01:18:45 PM PDT 24
Peak memory 238696 kb
Host smart-26c6267e-4f0e-4bb0-815b-b9362e144424
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001563031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.1001563031
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3156678185
Short name T1225
Test name
Test status
Simulation time 1600755846 ps
CPU time 3.92 seconds
Started May 26 01:18:44 PM PDT 24
Finished May 26 01:18:49 PM PDT 24
Peak memory 246908 kb
Host smart-2b8304d1-a8ce-4c82-a810-e31c27b78193
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156678185 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.3156678185
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3254433105
Short name T1199
Test name
Test status
Simulation time 44587378 ps
CPU time 1.63 seconds
Started May 26 01:18:40 PM PDT 24
Finished May 26 01:18:43 PM PDT 24
Peak memory 238700 kb
Host smart-be4da0c0-a8da-4940-8f98-2ff16bcfe855
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254433105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.3254433105
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1376913006
Short name T1303
Test name
Test status
Simulation time 137690336 ps
CPU time 1.57 seconds
Started May 26 01:18:40 PM PDT 24
Finished May 26 01:18:42 PM PDT 24
Peak memory 230464 kb
Host smart-e6650bb3-0741-45a4-945a-d2c71091351c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376913006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.1376913006
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.607042883
Short name T1288
Test name
Test status
Simulation time 82850201 ps
CPU time 1.4 seconds
Started May 26 01:18:42 PM PDT 24
Finished May 26 01:18:44 PM PDT 24
Peak memory 230260 kb
Host smart-80427631-0435-40f3-b043-ac838b4f3589
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607042883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl
_mem_partial_access.607042883
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.1010159095
Short name T1200
Test name
Test status
Simulation time 147049049 ps
CPU time 1.42 seconds
Started May 26 01:18:41 PM PDT 24
Finished May 26 01:18:43 PM PDT 24
Peak memory 229440 kb
Host smart-9d8fe01a-08b1-4ed7-985c-227c3c5376bb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010159095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.1010159095
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.3980152952
Short name T1308
Test name
Test status
Simulation time 240907101 ps
CPU time 3.49 seconds
Started May 26 01:18:41 PM PDT 24
Finished May 26 01:18:45 PM PDT 24
Peak memory 238616 kb
Host smart-f285a49b-d416-40e7-a73f-7be8a607b1c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980152952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.3980152952
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3632265982
Short name T1270
Test name
Test status
Simulation time 2853465655 ps
CPU time 6.68 seconds
Started May 26 01:18:42 PM PDT 24
Finished May 26 01:18:50 PM PDT 24
Peak memory 238976 kb
Host smart-a58737b5-769f-44da-8299-45989b7c05eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632265982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.3632265982
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1511319779
Short name T343
Test name
Test status
Simulation time 1297947572 ps
CPU time 11.9 seconds
Started May 26 01:18:40 PM PDT 24
Finished May 26 01:18:52 PM PDT 24
Peak memory 243624 kb
Host smart-d725d535-8a75-4f94-838e-ae4af226a762
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511319779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in
tg_err.1511319779
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2159529153
Short name T1234
Test name
Test status
Simulation time 598760095 ps
CPU time 2.19 seconds
Started May 26 01:19:02 PM PDT 24
Finished May 26 01:19:05 PM PDT 24
Peak memory 229180 kb
Host smart-ac01c8f1-1389-4668-8572-a1c7a3c4a425
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159529153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.2159529153
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.139384946
Short name T1296
Test name
Test status
Simulation time 147303241 ps
CPU time 1.57 seconds
Started May 26 01:19:00 PM PDT 24
Finished May 26 01:19:03 PM PDT 24
Peak memory 229384 kb
Host smart-41ae252f-8f2c-401d-86f5-d4b1348402c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139384946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.139384946
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.1734251348
Short name T1224
Test name
Test status
Simulation time 40554094 ps
CPU time 1.36 seconds
Started May 26 01:18:56 PM PDT 24
Finished May 26 01:18:58 PM PDT 24
Peak memory 229484 kb
Host smart-213cf6fe-b266-404e-9890-4bc8c91a3d9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734251348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.1734251348
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.475037292
Short name T1233
Test name
Test status
Simulation time 68404442 ps
CPU time 1.34 seconds
Started May 26 01:18:58 PM PDT 24
Finished May 26 01:19:00 PM PDT 24
Peak memory 230488 kb
Host smart-d8c1379b-ecee-491c-8b33-894adccb1ab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475037292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.475037292
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.2965211526
Short name T1240
Test name
Test status
Simulation time 76846086 ps
CPU time 1.51 seconds
Started May 26 01:19:06 PM PDT 24
Finished May 26 01:19:08 PM PDT 24
Peak memory 230500 kb
Host smart-b755d940-5a88-4235-ae83-b0955906aaad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965211526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.2965211526
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.2733917308
Short name T1201
Test name
Test status
Simulation time 566069545 ps
CPU time 2.26 seconds
Started May 26 01:19:01 PM PDT 24
Finished May 26 01:19:04 PM PDT 24
Peak memory 229176 kb
Host smart-842b806b-c50d-467a-8d01-22f2fe1fdaa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733917308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.2733917308
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.1156705913
Short name T1208
Test name
Test status
Simulation time 583062220 ps
CPU time 1.89 seconds
Started May 26 01:18:59 PM PDT 24
Finished May 26 01:19:02 PM PDT 24
Peak memory 229436 kb
Host smart-c2f22a38-c5a0-4a0e-bae6-0eb712a5dee4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156705913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.1156705913
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.2803630405
Short name T1213
Test name
Test status
Simulation time 74634804 ps
CPU time 1.47 seconds
Started May 26 01:19:01 PM PDT 24
Finished May 26 01:19:04 PM PDT 24
Peak memory 230496 kb
Host smart-43acc481-5636-4710-9ce4-62650e315a66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803630405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.2803630405
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.251775711
Short name T1198
Test name
Test status
Simulation time 73730268 ps
CPU time 1.43 seconds
Started May 26 01:18:58 PM PDT 24
Finished May 26 01:19:01 PM PDT 24
Peak memory 229384 kb
Host smart-f77c34bd-b76a-4002-896c-c9a567dce309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251775711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.251775711
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3999257533
Short name T1246
Test name
Test status
Simulation time 529468251 ps
CPU time 1.71 seconds
Started May 26 01:19:01 PM PDT 24
Finished May 26 01:19:04 PM PDT 24
Peak memory 230544 kb
Host smart-c89e960c-0d4e-40e1-9b26-acc78ec8be29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999257533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3999257533
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.807540369
Short name T1209
Test name
Test status
Simulation time 250851164 ps
CPU time 2.32 seconds
Started May 26 01:18:41 PM PDT 24
Finished May 26 01:18:44 PM PDT 24
Peak memory 238608 kb
Host smart-451b6dc8-d136-4fff-a842-75988d64c1a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807540369 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.807540369
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3938120211
Short name T1244
Test name
Test status
Simulation time 157952170 ps
CPU time 1.58 seconds
Started May 26 01:18:41 PM PDT 24
Finished May 26 01:18:44 PM PDT 24
Peak memory 239788 kb
Host smart-e900f7a8-a4ac-4e9e-a1d6-fa9fc9912676
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938120211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.3938120211
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3415199811
Short name T1189
Test name
Test status
Simulation time 534110728 ps
CPU time 1.63 seconds
Started May 26 01:18:45 PM PDT 24
Finished May 26 01:18:47 PM PDT 24
Peak memory 229824 kb
Host smart-6e943d07-64b1-41d2-98cd-552c27cb1fa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415199811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.3415199811
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1782726827
Short name T321
Test name
Test status
Simulation time 673671254 ps
CPU time 2.61 seconds
Started May 26 01:18:46 PM PDT 24
Finished May 26 01:18:49 PM PDT 24
Peak memory 238928 kb
Host smart-1656c122-7a70-4223-b9b7-c99a7ceb1ddd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782726827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.1782726827
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3586257274
Short name T1307
Test name
Test status
Simulation time 161292766 ps
CPU time 6.04 seconds
Started May 26 01:18:43 PM PDT 24
Finished May 26 01:18:50 PM PDT 24
Peak memory 238920 kb
Host smart-a8937a80-cc5c-4476-bb7a-b2ba236e15f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586257274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.3586257274
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3517144598
Short name T345
Test name
Test status
Simulation time 2587154886 ps
CPU time 17.09 seconds
Started May 26 01:18:41 PM PDT 24
Finished May 26 01:18:59 PM PDT 24
Peak memory 244328 kb
Host smart-d9b31eb4-bffb-4bad-a7cf-c65325ff1942
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517144598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.3517144598
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1542656017
Short name T1193
Test name
Test status
Simulation time 132287322 ps
CPU time 2.77 seconds
Started May 26 01:18:46 PM PDT 24
Finished May 26 01:18:49 PM PDT 24
Peak memory 244584 kb
Host smart-cefa4d16-3824-41fa-96a3-de695628b46a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542656017 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.1542656017
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2343805145
Short name T298
Test name
Test status
Simulation time 141302497 ps
CPU time 1.59 seconds
Started May 26 01:18:45 PM PDT 24
Finished May 26 01:18:47 PM PDT 24
Peak memory 239316 kb
Host smart-31e28f46-1461-4c77-9140-908bfe8b4462
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343805145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.2343805145
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.630571490
Short name T1249
Test name
Test status
Simulation time 115831405 ps
CPU time 1.38 seconds
Started May 26 01:18:43 PM PDT 24
Finished May 26 01:18:45 PM PDT 24
Peak memory 230592 kb
Host smart-0b0bf8ac-742c-4a73-bef5-0708785af522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630571490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.630571490
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3148410565
Short name T1278
Test name
Test status
Simulation time 55315098 ps
CPU time 2.42 seconds
Started May 26 01:18:45 PM PDT 24
Finished May 26 01:18:48 PM PDT 24
Peak memory 237836 kb
Host smart-ff594b7f-1042-49ba-95d7-093c29fc591e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148410565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.3148410565
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.3248395263
Short name T1245
Test name
Test status
Simulation time 97451006 ps
CPU time 3.17 seconds
Started May 26 01:18:41 PM PDT 24
Finished May 26 01:18:44 PM PDT 24
Peak memory 238760 kb
Host smart-943e3a94-f00f-4fec-b1b5-7790baeaa083
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248395263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.3248395263
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2722443897
Short name T344
Test name
Test status
Simulation time 10258773372 ps
CPU time 13.54 seconds
Started May 26 01:18:50 PM PDT 24
Finished May 26 01:19:05 PM PDT 24
Peak memory 244360 kb
Host smart-e672ea8d-0b62-49e4-9ca5-d7922b197303
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722443897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.2722443897
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1713250499
Short name T1242
Test name
Test status
Simulation time 198505078 ps
CPU time 3.37 seconds
Started May 26 01:18:40 PM PDT 24
Finished May 26 01:18:45 PM PDT 24
Peak memory 246936 kb
Host smart-1e304a41-a2d8-4c3f-8954-d3ba2c5e1c74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713250499 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.1713250499
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.712263298
Short name T318
Test name
Test status
Simulation time 692440513 ps
CPU time 2.64 seconds
Started May 26 01:18:42 PM PDT 24
Finished May 26 01:18:46 PM PDT 24
Peak memory 238496 kb
Host smart-55dbf458-f34e-42e5-850e-815534c60deb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712263298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.712263298
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.1120581671
Short name T1321
Test name
Test status
Simulation time 581290696 ps
CPU time 1.53 seconds
Started May 26 01:18:41 PM PDT 24
Finished May 26 01:18:44 PM PDT 24
Peak memory 230488 kb
Host smart-8b3ec39e-54b7-43d6-a616-04fecdb96b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120581671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.1120581671
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.2895943654
Short name T317
Test name
Test status
Simulation time 192967857 ps
CPU time 3.15 seconds
Started May 26 01:18:41 PM PDT 24
Finished May 26 01:18:45 PM PDT 24
Peak memory 238560 kb
Host smart-b64b41c5-268b-4f2e-ad2d-14f1d9f136b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895943654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c
trl_same_csr_outstanding.2895943654
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3055774634
Short name T1280
Test name
Test status
Simulation time 200848350 ps
CPU time 3.92 seconds
Started May 26 01:18:44 PM PDT 24
Finished May 26 01:18:49 PM PDT 24
Peak memory 246196 kb
Host smart-addaa187-a13c-4b2d-ac1a-0806f8bd7595
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055774634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3055774634
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.226895067
Short name T1248
Test name
Test status
Simulation time 67415855 ps
CPU time 2.08 seconds
Started May 26 01:18:45 PM PDT 24
Finished May 26 01:18:48 PM PDT 24
Peak memory 244572 kb
Host smart-0cdd732c-0435-40fa-bd88-f4791f1f555c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226895067 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.226895067
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2301455520
Short name T1229
Test name
Test status
Simulation time 44928210 ps
CPU time 1.57 seconds
Started May 26 01:18:42 PM PDT 24
Finished May 26 01:18:44 PM PDT 24
Peak memory 240036 kb
Host smart-56d06dcd-3e37-4e7e-9596-386716304b0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301455520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.2301455520
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.3202549997
Short name T1261
Test name
Test status
Simulation time 45798066 ps
CPU time 1.33 seconds
Started May 26 01:18:42 PM PDT 24
Finished May 26 01:18:44 PM PDT 24
Peak memory 230568 kb
Host smart-e18af8da-24a9-46f5-a392-8b934f00dcde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202549997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.3202549997
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.44852395
Short name T1237
Test name
Test status
Simulation time 165880172 ps
CPU time 1.84 seconds
Started May 26 01:18:44 PM PDT 24
Finished May 26 01:18:47 PM PDT 24
Peak memory 238604 kb
Host smart-beb2b09e-0923-44fb-82e0-b9c4cb3fdbed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44852395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctr
l_same_csr_outstanding.44852395
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.1199858070
Short name T1205
Test name
Test status
Simulation time 161319582 ps
CPU time 5.64 seconds
Started May 26 01:18:44 PM PDT 24
Finished May 26 01:18:51 PM PDT 24
Peak memory 245716 kb
Host smart-cb16002b-45aa-4839-bd1c-cf30bdaba2e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199858070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.1199858070
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.4081428983
Short name T1217
Test name
Test status
Simulation time 245316867 ps
CPU time 3.78 seconds
Started May 26 01:18:55 PM PDT 24
Finished May 26 01:18:59 PM PDT 24
Peak memory 246764 kb
Host smart-f1ebd467-c61c-431d-829c-83c729114306
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081428983 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.4081428983
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1933553131
Short name T301
Test name
Test status
Simulation time 94475380 ps
CPU time 1.77 seconds
Started May 26 01:18:42 PM PDT 24
Finished May 26 01:18:45 PM PDT 24
Peak memory 240144 kb
Host smart-3ff9b79b-bbcb-4648-979a-a2d4d9fd9be9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933553131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.1933553131
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.3805404527
Short name T1266
Test name
Test status
Simulation time 85975925 ps
CPU time 1.54 seconds
Started May 26 01:18:42 PM PDT 24
Finished May 26 01:18:44 PM PDT 24
Peak memory 229568 kb
Host smart-0ffa2dda-86c2-4ef3-8c71-c04b8f726495
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805404527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.3805404527
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.2698868253
Short name T1287
Test name
Test status
Simulation time 67112588 ps
CPU time 2.35 seconds
Started May 26 01:18:49 PM PDT 24
Finished May 26 01:18:52 PM PDT 24
Peak memory 238644 kb
Host smart-ebb2d6b7-572d-4eb3-9839-39f5677463bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698868253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.2698868253
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.687843735
Short name T1218
Test name
Test status
Simulation time 142013514 ps
CPU time 4.1 seconds
Started May 26 01:18:41 PM PDT 24
Finished May 26 01:18:46 PM PDT 24
Peak memory 246432 kb
Host smart-2d3426ec-cdc3-40bb-9926-62c3c7312790
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687843735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.687843735
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.174017517
Short name T269
Test name
Test status
Simulation time 1097934691 ps
CPU time 11.62 seconds
Started May 26 01:18:45 PM PDT 24
Finished May 26 01:18:57 PM PDT 24
Peak memory 238584 kb
Host smart-9003d373-21b6-46d7-b375-c37bc1e388b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174017517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_int
g_err.174017517
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.4041131645
Short name T600
Test name
Test status
Simulation time 111649990 ps
CPU time 2.03 seconds
Started May 26 01:24:39 PM PDT 24
Finished May 26 01:24:42 PM PDT 24
Peak memory 240496 kb
Host smart-53790a22-eba1-4821-85ea-fb2a3396734b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041131645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.4041131645
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.2534513661
Short name T101
Test name
Test status
Simulation time 1453171641 ps
CPU time 18.05 seconds
Started May 26 01:24:29 PM PDT 24
Finished May 26 01:24:48 PM PDT 24
Peak memory 242052 kb
Host smart-bf4fc489-f7a2-4b17-b4a2-ee6971d32ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534513661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.2534513661
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.1391106805
Short name T68
Test name
Test status
Simulation time 1355632208 ps
CPU time 9.49 seconds
Started May 26 01:24:30 PM PDT 24
Finished May 26 01:24:40 PM PDT 24
Peak memory 241976 kb
Host smart-5888b963-9568-4b84-8704-bbbb798bf571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391106805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.1391106805
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.1372433878
Short name T1148
Test name
Test status
Simulation time 405217657 ps
CPU time 12.23 seconds
Started May 26 01:24:30 PM PDT 24
Finished May 26 01:24:43 PM PDT 24
Peak memory 241916 kb
Host smart-9ed9c1ee-2170-4fde-84a9-ef05ead9528e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372433878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.1372433878
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.3078895865
Short name T448
Test name
Test status
Simulation time 10077783238 ps
CPU time 19.03 seconds
Started May 26 01:24:29 PM PDT 24
Finished May 26 01:24:49 PM PDT 24
Peak memory 248792 kb
Host smart-29def2eb-0e2f-43f9-b19d-8fc62a273251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078895865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.3078895865
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.2909066463
Short name T816
Test name
Test status
Simulation time 110331837 ps
CPU time 3.8 seconds
Started May 26 01:24:32 PM PDT 24
Finished May 26 01:24:36 PM PDT 24
Peak memory 241944 kb
Host smart-59290d23-e534-4d5c-a6f5-5a17f87aca77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909066463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.2909066463
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.443212343
Short name T782
Test name
Test status
Simulation time 7531755907 ps
CPU time 18.53 seconds
Started May 26 01:24:31 PM PDT 24
Finished May 26 01:24:50 PM PDT 24
Peak memory 241576 kb
Host smart-8340d868-360c-410a-a92d-2c2c7636914e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443212343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.443212343
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.2145545969
Short name T1180
Test name
Test status
Simulation time 825943627 ps
CPU time 19.21 seconds
Started May 26 01:24:39 PM PDT 24
Finished May 26 01:24:59 PM PDT 24
Peak memory 242196 kb
Host smart-f2d4cf30-0db1-4430-9abe-e97487ce3e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145545969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.2145545969
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.2454600249
Short name T708
Test name
Test status
Simulation time 2954196507 ps
CPU time 9.66 seconds
Started May 26 01:24:31 PM PDT 24
Finished May 26 01:24:41 PM PDT 24
Peak memory 242292 kb
Host smart-6a90854f-b092-482c-b30b-5f801bcdfca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454600249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.2454600249
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.198561893
Short name T710
Test name
Test status
Simulation time 551642460 ps
CPU time 15.02 seconds
Started May 26 01:24:29 PM PDT 24
Finished May 26 01:24:45 PM PDT 24
Peak memory 241992 kb
Host smart-cb3f2c99-2adf-4e3e-ab1d-243585767e95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=198561893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.198561893
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.2024078406
Short name T1120
Test name
Test status
Simulation time 616986638 ps
CPU time 22.29 seconds
Started May 26 01:24:31 PM PDT 24
Finished May 26 01:24:54 PM PDT 24
Peak memory 241332 kb
Host smart-6fe5b607-5042-4532-bd49-2edf1204d0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024078406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.2024078406
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.43212006
Short name T17
Test name
Test status
Simulation time 165695413400 ps
CPU time 224.94 seconds
Started May 26 01:24:36 PM PDT 24
Finished May 26 01:28:21 PM PDT 24
Peak memory 274252 kb
Host smart-1481471c-5dff-43a4-bd33-40fc2faeb847
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43212006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.43212006
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.257838019
Short name T645
Test name
Test status
Simulation time 728624498 ps
CPU time 12.32 seconds
Started May 26 01:24:29 PM PDT 24
Finished May 26 01:24:43 PM PDT 24
Peak memory 241924 kb
Host smart-179416f5-f5ba-4249-b2f9-c15f7c5b9606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257838019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.257838019
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.3749820783
Short name T808
Test name
Test status
Simulation time 467287587629 ps
CPU time 848.84 seconds
Started May 26 01:24:37 PM PDT 24
Finished May 26 01:38:47 PM PDT 24
Peak memory 285612 kb
Host smart-02d185d0-e4d8-4772-99d0-2972c33f2ce3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749820783 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.3749820783
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.286958880
Short name T232
Test name
Test status
Simulation time 1495946604 ps
CPU time 37.34 seconds
Started May 26 01:24:39 PM PDT 24
Finished May 26 01:25:17 PM PDT 24
Peak memory 242396 kb
Host smart-05b48fc4-ea0f-4538-ae9d-45395d6e37c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286958880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.286958880
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.2524207024
Short name T775
Test name
Test status
Simulation time 434284830 ps
CPU time 4.6 seconds
Started May 26 01:24:39 PM PDT 24
Finished May 26 01:24:44 PM PDT 24
Peak memory 240324 kb
Host smart-ee8b416e-5e29-4224-8815-fcc8a3f33921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524207024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.2524207024
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.1284932533
Short name T998
Test name
Test status
Simulation time 6994454024 ps
CPU time 37.14 seconds
Started May 26 01:24:37 PM PDT 24
Finished May 26 01:25:15 PM PDT 24
Peak memory 248784 kb
Host smart-e056059a-36f6-471c-b7da-efb2dfaab86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284932533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.1284932533
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.4238563198
Short name T106
Test name
Test status
Simulation time 2413707523 ps
CPU time 16.88 seconds
Started May 26 01:24:38 PM PDT 24
Finished May 26 01:24:55 PM PDT 24
Peak memory 248956 kb
Host smart-923298f7-c623-422a-a4a2-a32646716599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238563198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.4238563198
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.2669104208
Short name T870
Test name
Test status
Simulation time 854883515 ps
CPU time 28.57 seconds
Started May 26 01:24:41 PM PDT 24
Finished May 26 01:25:10 PM PDT 24
Peak memory 242180 kb
Host smart-525c579e-482a-4e0a-8bc9-f16a09f81ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669104208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.2669104208
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.3326886286
Short name T449
Test name
Test status
Simulation time 183469356 ps
CPU time 3.98 seconds
Started May 26 01:24:39 PM PDT 24
Finished May 26 01:24:43 PM PDT 24
Peak memory 241816 kb
Host smart-8a4e2aa6-8eba-4843-a844-1c4777c45602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326886286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.3326886286
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.1035170903
Short name T868
Test name
Test status
Simulation time 893138658 ps
CPU time 6.91 seconds
Started May 26 01:24:37 PM PDT 24
Finished May 26 01:24:45 PM PDT 24
Peak memory 242428 kb
Host smart-f170207e-3182-44e8-a8b3-79124c0453e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035170903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.1035170903
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.85862212
Short name T137
Test name
Test status
Simulation time 147654595 ps
CPU time 5.97 seconds
Started May 26 01:24:37 PM PDT 24
Finished May 26 01:24:44 PM PDT 24
Peak memory 241964 kb
Host smart-ee3138ea-3ae6-4b8c-8431-7320f0f48e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85862212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.85862212
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.837191819
Short name T543
Test name
Test status
Simulation time 1587529446 ps
CPU time 14.95 seconds
Started May 26 01:24:41 PM PDT 24
Finished May 26 01:24:56 PM PDT 24
Peak memory 241904 kb
Host smart-5c3cb7c6-d70a-488a-a75b-0206cdb8e1b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=837191819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.837191819
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.2343291211
Short name T829
Test name
Test status
Simulation time 235418643 ps
CPU time 9.01 seconds
Started May 26 01:24:41 PM PDT 24
Finished May 26 01:24:51 PM PDT 24
Peak memory 242024 kb
Host smart-aa58fd57-cfc6-40e8-83a0-3ae4c88373d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2343291211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.2343291211
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.72312020
Short name T235
Test name
Test status
Simulation time 172965888463 ps
CPU time 351.47 seconds
Started May 26 01:24:37 PM PDT 24
Finished May 26 01:30:29 PM PDT 24
Peak memory 280152 kb
Host smart-23825185-3d9e-4cb6-aa04-377252b4d44f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72312020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.72312020
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.3239032145
Short name T951
Test name
Test status
Simulation time 373995749 ps
CPU time 8.48 seconds
Started May 26 01:24:37 PM PDT 24
Finished May 26 01:24:46 PM PDT 24
Peak memory 242236 kb
Host smart-c9747d07-65fe-4354-b113-de448e21eec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239032145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.3239032145
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.2057076896
Short name T999
Test name
Test status
Simulation time 44955202081 ps
CPU time 781.83 seconds
Started May 26 01:24:38 PM PDT 24
Finished May 26 01:37:41 PM PDT 24
Peak memory 375700 kb
Host smart-cad39d3f-c831-4148-9755-9d7bbb8398bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057076896 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.2057076896
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.2553009151
Short name T567
Test name
Test status
Simulation time 1335115689 ps
CPU time 22.47 seconds
Started May 26 01:24:38 PM PDT 24
Finished May 26 01:25:01 PM PDT 24
Peak memory 242248 kb
Host smart-741361f0-7867-4810-8df0-26df0bbcfe3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553009151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.2553009151
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.3252953912
Short name T290
Test name
Test status
Simulation time 270173546 ps
CPU time 1.91 seconds
Started May 26 01:25:42 PM PDT 24
Finished May 26 01:25:44 PM PDT 24
Peak memory 240524 kb
Host smart-30f2306e-7650-4f80-950e-1c9d19413e87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252953912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.3252953912
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.99979205
Short name T1057
Test name
Test status
Simulation time 512287797 ps
CPU time 16.74 seconds
Started May 26 01:25:40 PM PDT 24
Finished May 26 01:25:58 PM PDT 24
Peak memory 242156 kb
Host smart-f421b2a2-fbb6-4fa9-a05a-ca23d88c38e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99979205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.99979205
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.4080162711
Short name T981
Test name
Test status
Simulation time 8837055010 ps
CPU time 55.14 seconds
Started May 26 01:25:41 PM PDT 24
Finished May 26 01:26:37 PM PDT 24
Peak memory 242952 kb
Host smart-07681a1c-4369-4d29-a1b4-bc099bb3b225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080162711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.4080162711
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.3131139795
Short name T242
Test name
Test status
Simulation time 173684141 ps
CPU time 3.96 seconds
Started May 26 01:25:29 PM PDT 24
Finished May 26 01:25:35 PM PDT 24
Peak memory 241928 kb
Host smart-32b7af0a-f140-4a58-a809-c75d504fadfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131139795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.3131139795
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.664408481
Short name T915
Test name
Test status
Simulation time 1549230795 ps
CPU time 39.4 seconds
Started May 26 01:25:42 PM PDT 24
Finished May 26 01:26:22 PM PDT 24
Peak memory 256964 kb
Host smart-29feff49-e51a-40c3-8963-b1fc65bedf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664408481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.664408481
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.251485608
Short name T990
Test name
Test status
Simulation time 127297325 ps
CPU time 4.29 seconds
Started May 26 01:25:42 PM PDT 24
Finished May 26 01:25:47 PM PDT 24
Peak memory 241940 kb
Host smart-1dc01c61-c748-4597-912b-c1e5d6ab4bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251485608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.251485608
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.2434237655
Short name T882
Test name
Test status
Simulation time 537351796 ps
CPU time 8.18 seconds
Started May 26 01:25:43 PM PDT 24
Finished May 26 01:25:52 PM PDT 24
Peak memory 242404 kb
Host smart-b08de059-0517-482a-954b-6fe45b891979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434237655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.2434237655
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.3170994292
Short name T104
Test name
Test status
Simulation time 1229410265 ps
CPU time 16 seconds
Started May 26 01:25:40 PM PDT 24
Finished May 26 01:25:57 PM PDT 24
Peak memory 241884 kb
Host smart-128ec49b-a49c-48f3-ae84-f85d115790fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170994292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.3170994292
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.1679899308
Short name T986
Test name
Test status
Simulation time 228762473 ps
CPU time 3.42 seconds
Started May 26 01:25:41 PM PDT 24
Finished May 26 01:25:45 PM PDT 24
Peak memory 242380 kb
Host smart-effc9244-1db3-4f36-820b-7406fffd72c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679899308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.1679899308
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.1436856734
Short name T1169
Test name
Test status
Simulation time 2213553864 ps
CPU time 13.46 seconds
Started May 26 01:25:31 PM PDT 24
Finished May 26 01:25:46 PM PDT 24
Peak memory 241984 kb
Host smart-5a68f71f-bc25-4aaa-9e7d-ed0feec162d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436856734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.1436856734
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.2440601936
Short name T1115
Test name
Test status
Simulation time 7206926521 ps
CPU time 36.13 seconds
Started May 26 01:25:40 PM PDT 24
Finished May 26 01:26:17 PM PDT 24
Peak memory 241736 kb
Host smart-2c2cc7a7-381a-4f21-bdb6-6562e906f5d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440601936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all
.2440601936
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.1619232943
Short name T584
Test name
Test status
Simulation time 76582237900 ps
CPU time 619.77 seconds
Started May 26 01:25:40 PM PDT 24
Finished May 26 01:36:01 PM PDT 24
Peak memory 262128 kb
Host smart-9b8c2ee8-7454-4b12-b4ec-2ba61a5bde88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619232943 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.1619232943
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.3225302638
Short name T678
Test name
Test status
Simulation time 2887963245 ps
CPU time 7.99 seconds
Started May 26 01:25:40 PM PDT 24
Finished May 26 01:25:49 PM PDT 24
Peak memory 242060 kb
Host smart-0c81ffc9-ff65-4bea-84a1-e022534f6704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225302638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.3225302638
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.3707744689
Short name T811
Test name
Test status
Simulation time 91146054 ps
CPU time 2.78 seconds
Started May 26 01:31:47 PM PDT 24
Finished May 26 01:31:50 PM PDT 24
Peak memory 242120 kb
Host smart-b2b73f3a-e27a-4f92-9d32-0e71b00343bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707744689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.3707744689
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.1744758606
Short name T396
Test name
Test status
Simulation time 846320187 ps
CPU time 13.2 seconds
Started May 26 01:31:47 PM PDT 24
Finished May 26 01:32:00 PM PDT 24
Peak memory 242320 kb
Host smart-13f81c57-6725-4a13-bf06-66186231cc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744758606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.1744758606
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.2491293476
Short name T509
Test name
Test status
Simulation time 1494015266 ps
CPU time 5.2 seconds
Started May 26 01:31:45 PM PDT 24
Finished May 26 01:31:51 PM PDT 24
Peak memory 242276 kb
Host smart-5e24d720-bafd-4da4-b44f-0fec94cc9665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491293476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.2491293476
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.789793708
Short name T995
Test name
Test status
Simulation time 293260703 ps
CPU time 6.31 seconds
Started May 26 01:31:47 PM PDT 24
Finished May 26 01:31:54 PM PDT 24
Peak memory 242036 kb
Host smart-0211c0cc-49d3-4518-bdd0-e2bc189661f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789793708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.789793708
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.1614971003
Short name T835
Test name
Test status
Simulation time 165644073 ps
CPU time 4.28 seconds
Started May 26 01:31:43 PM PDT 24
Finished May 26 01:31:48 PM PDT 24
Peak memory 242348 kb
Host smart-e2c69ee6-3ae3-4f75-916a-ed88390264e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614971003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.1614971003
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.4084260839
Short name T313
Test name
Test status
Simulation time 4488159739 ps
CPU time 21.74 seconds
Started May 26 01:31:43 PM PDT 24
Finished May 26 01:32:05 PM PDT 24
Peak memory 242116 kb
Host smart-dd950ae9-f5fe-4703-9153-da8419006ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084260839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.4084260839
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.659293308
Short name T733
Test name
Test status
Simulation time 271805506 ps
CPU time 8.48 seconds
Started May 26 01:31:55 PM PDT 24
Finished May 26 01:32:04 PM PDT 24
Peak memory 242060 kb
Host smart-4772e313-f027-478b-a57e-93722a71fdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659293308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.659293308
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.3076983141
Short name T5
Test name
Test status
Simulation time 192660394 ps
CPU time 3.46 seconds
Started May 26 01:31:56 PM PDT 24
Finished May 26 01:32:00 PM PDT 24
Peak memory 242024 kb
Host smart-ead5680e-d799-4789-af26-e5b0ed5f61a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076983141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.3076983141
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.3463490149
Short name T711
Test name
Test status
Simulation time 190467059 ps
CPU time 5.69 seconds
Started May 26 01:31:58 PM PDT 24
Finished May 26 01:32:05 PM PDT 24
Peak memory 241876 kb
Host smart-c345e6b5-e0cb-45e6-bce2-ae7db04bc3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463490149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.3463490149
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.3407114129
Short name T812
Test name
Test status
Simulation time 2252606354 ps
CPU time 5.26 seconds
Started May 26 01:31:57 PM PDT 24
Finished May 26 01:32:03 PM PDT 24
Peak memory 242084 kb
Host smart-21d3fafa-8572-4087-9642-10ef7b87fcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407114129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.3407114129
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.1323778089
Short name T705
Test name
Test status
Simulation time 391359730 ps
CPU time 6.35 seconds
Started May 26 01:31:58 PM PDT 24
Finished May 26 01:32:05 PM PDT 24
Peak memory 242000 kb
Host smart-3f3f67c0-c9e9-4486-a0f3-7480c245a0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323778089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.1323778089
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.3111371
Short name T544
Test name
Test status
Simulation time 575676487 ps
CPU time 14.8 seconds
Started May 26 01:31:57 PM PDT 24
Finished May 26 01:32:13 PM PDT 24
Peak memory 242344 kb
Host smart-2bf67b73-075d-444a-af89-6f9d250eda48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3111371
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.3594020917
Short name T90
Test name
Test status
Simulation time 168082763 ps
CPU time 3.86 seconds
Started May 26 01:31:56 PM PDT 24
Finished May 26 01:32:01 PM PDT 24
Peak memory 242064 kb
Host smart-410195bc-f927-43cf-aa3d-b2f2eee7b071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594020917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.3594020917
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.1140151599
Short name T196
Test name
Test status
Simulation time 442658473 ps
CPU time 14.48 seconds
Started May 26 01:31:56 PM PDT 24
Finished May 26 01:32:12 PM PDT 24
Peak memory 242436 kb
Host smart-a67f7646-7845-4f1a-b8c9-c33b3bab71b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140151599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.1140151599
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.2239853915
Short name T1025
Test name
Test status
Simulation time 49274465 ps
CPU time 1.79 seconds
Started May 26 01:25:51 PM PDT 24
Finished May 26 01:25:53 PM PDT 24
Peak memory 240528 kb
Host smart-55740644-513a-4299-a5db-ee59aecfd554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239853915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.2239853915
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.1403322041
Short name T128
Test name
Test status
Simulation time 604607434 ps
CPU time 21.56 seconds
Started May 26 01:25:41 PM PDT 24
Finished May 26 01:26:03 PM PDT 24
Peak memory 241996 kb
Host smart-4705da7b-1cfd-4dc5-9373-d1475a874ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403322041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.1403322041
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.1548078277
Short name T1058
Test name
Test status
Simulation time 3601265025 ps
CPU time 17.12 seconds
Started May 26 01:25:43 PM PDT 24
Finished May 26 01:26:00 PM PDT 24
Peak memory 241968 kb
Host smart-8d047fa9-c675-4ede-bfb2-e1a95f8bc8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548078277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.1548078277
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.3508997133
Short name T752
Test name
Test status
Simulation time 262354901 ps
CPU time 3.24 seconds
Started May 26 01:25:41 PM PDT 24
Finished May 26 01:25:45 PM PDT 24
Peak memory 241988 kb
Host smart-745a75b7-3d8a-48f0-8cd1-b42b7a8651d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508997133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.3508997133
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.1055695951
Short name T202
Test name
Test status
Simulation time 213961099 ps
CPU time 5.15 seconds
Started May 26 01:25:42 PM PDT 24
Finished May 26 01:25:48 PM PDT 24
Peak memory 242208 kb
Host smart-3acef5c1-7340-45d6-98a5-28c9015c1dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055695951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.1055695951
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.640082296
Short name T173
Test name
Test status
Simulation time 883911537 ps
CPU time 13.95 seconds
Started May 26 01:25:40 PM PDT 24
Finished May 26 01:25:55 PM PDT 24
Peak memory 242248 kb
Host smart-b2cd7c52-6f5b-490e-a45f-a8f68d1fa2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640082296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.640082296
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.2960276485
Short name T488
Test name
Test status
Simulation time 747408032 ps
CPU time 16.8 seconds
Started May 26 01:25:41 PM PDT 24
Finished May 26 01:25:58 PM PDT 24
Peak memory 242336 kb
Host smart-baca8ac4-a18f-434a-ad89-372567fc7e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960276485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.2960276485
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.1009882108
Short name T561
Test name
Test status
Simulation time 3019646769 ps
CPU time 21.66 seconds
Started May 26 01:25:43 PM PDT 24
Finished May 26 01:26:05 PM PDT 24
Peak memory 248744 kb
Host smart-83a1cd18-cb95-4570-ad61-a9501c4659d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1009882108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.1009882108
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.764978433
Short name T170
Test name
Test status
Simulation time 563275078 ps
CPU time 8.15 seconds
Started May 26 01:25:41 PM PDT 24
Finished May 26 01:25:50 PM PDT 24
Peak memory 241996 kb
Host smart-c2def66d-9826-4075-921b-68c23027a949
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=764978433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.764978433
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.1721574828
Short name T880
Test name
Test status
Simulation time 448815393 ps
CPU time 10.23 seconds
Started May 26 01:25:40 PM PDT 24
Finished May 26 01:25:51 PM PDT 24
Peak memory 241996 kb
Host smart-985e1a6a-119f-469b-9a44-933287d4fb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721574828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.1721574828
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.3311666499
Short name T814
Test name
Test status
Simulation time 5273882634 ps
CPU time 107.08 seconds
Started May 26 01:25:52 PM PDT 24
Finished May 26 01:27:39 PM PDT 24
Peak memory 257056 kb
Host smart-6100f6c1-4202-4c73-8b16-72c09b794f4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311666499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.3311666499
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.2119313702
Short name T810
Test name
Test status
Simulation time 334075412 ps
CPU time 3.34 seconds
Started May 26 01:25:42 PM PDT 24
Finished May 26 01:25:46 PM PDT 24
Peak memory 246700 kb
Host smart-8e63c27a-9837-4d7b-bd4d-ac34b489fd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119313702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.2119313702
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.2053595079
Short name T427
Test name
Test status
Simulation time 265637788 ps
CPU time 4.64 seconds
Started May 26 01:31:55 PM PDT 24
Finished May 26 01:32:01 PM PDT 24
Peak memory 242352 kb
Host smart-8f8a0fc1-7d15-4d96-a128-191cda9edf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053595079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.2053595079
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.3493532022
Short name T847
Test name
Test status
Simulation time 829285804 ps
CPU time 20.18 seconds
Started May 26 01:31:56 PM PDT 24
Finished May 26 01:32:18 PM PDT 24
Peak memory 242044 kb
Host smart-833a2512-a10e-48fc-9c3d-291ac6901739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493532022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.3493532022
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.3222878241
Short name T891
Test name
Test status
Simulation time 109472839 ps
CPU time 3.04 seconds
Started May 26 01:31:57 PM PDT 24
Finished May 26 01:32:01 PM PDT 24
Peak memory 242152 kb
Host smart-dbecb8dd-c976-495f-80e9-ca5101490e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222878241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3222878241
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.4128886591
Short name T924
Test name
Test status
Simulation time 11029953497 ps
CPU time 22.77 seconds
Started May 26 01:31:57 PM PDT 24
Finished May 26 01:32:20 PM PDT 24
Peak memory 242408 kb
Host smart-e0d8693f-af8d-41da-bd67-e167f306f7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128886591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.4128886591
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.1091011523
Short name T412
Test name
Test status
Simulation time 1981345856 ps
CPU time 5.08 seconds
Started May 26 01:31:57 PM PDT 24
Finished May 26 01:32:03 PM PDT 24
Peak memory 241980 kb
Host smart-07f47ebe-c3c6-4ed4-939c-864aa8c3e584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091011523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.1091011523
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.6594519
Short name T139
Test name
Test status
Simulation time 1403711322 ps
CPU time 10.41 seconds
Started May 26 01:31:56 PM PDT 24
Finished May 26 01:32:07 PM PDT 24
Peak memory 241944 kb
Host smart-ad8c539a-014e-4707-8b45-28bffc442da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6594519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.6594519
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.3029238429
Short name T212
Test name
Test status
Simulation time 168219974 ps
CPU time 4.47 seconds
Started May 26 01:31:55 PM PDT 24
Finished May 26 01:32:00 PM PDT 24
Peak memory 242008 kb
Host smart-3c0383fa-796c-4949-b91f-d1a111d5fd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029238429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.3029238429
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.2098701720
Short name T249
Test name
Test status
Simulation time 613088804 ps
CPU time 9.31 seconds
Started May 26 01:31:56 PM PDT 24
Finished May 26 01:32:06 PM PDT 24
Peak memory 241832 kb
Host smart-7d3fd179-0f63-4f73-a20a-02be1cdbab5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098701720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.2098701720
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.1621163952
Short name T1042
Test name
Test status
Simulation time 258523969 ps
CPU time 4.04 seconds
Started May 26 01:31:57 PM PDT 24
Finished May 26 01:32:02 PM PDT 24
Peak memory 242400 kb
Host smart-0d000116-5a9f-41d8-a8ba-e4bcc5318a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621163952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.1621163952
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.1631677147
Short name T333
Test name
Test status
Simulation time 241533962 ps
CPU time 11.19 seconds
Started May 26 01:31:58 PM PDT 24
Finished May 26 01:32:10 PM PDT 24
Peak memory 242308 kb
Host smart-abeab00f-a9eb-4121-a466-edd153740d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631677147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.1631677147
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.897372419
Short name T772
Test name
Test status
Simulation time 421890736 ps
CPU time 3.24 seconds
Started May 26 01:31:58 PM PDT 24
Finished May 26 01:32:02 PM PDT 24
Peak memory 242088 kb
Host smart-fe86871a-87f2-44c2-b9bb-f60a5c976411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897372419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.897372419
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.2445728487
Short name T1061
Test name
Test status
Simulation time 749300916 ps
CPU time 5.81 seconds
Started May 26 01:31:57 PM PDT 24
Finished May 26 01:32:03 PM PDT 24
Peak memory 242276 kb
Host smart-92389af4-6f07-4748-a2b1-0554651f6345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445728487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.2445728487
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.2498317779
Short name T610
Test name
Test status
Simulation time 244230270 ps
CPU time 4.76 seconds
Started May 26 01:32:00 PM PDT 24
Finished May 26 01:32:05 PM PDT 24
Peak memory 241932 kb
Host smart-ab65e510-fcba-4a5a-ab18-d82fe8b8aae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498317779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.2498317779
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.2589391606
Short name T635
Test name
Test status
Simulation time 141820703 ps
CPU time 3.94 seconds
Started May 26 01:32:05 PM PDT 24
Finished May 26 01:32:10 PM PDT 24
Peak memory 242168 kb
Host smart-db5fd2e2-561b-4f8d-995c-ce668d397bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589391606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.2589391606
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.2860497363
Short name T917
Test name
Test status
Simulation time 550118196 ps
CPU time 14.54 seconds
Started May 26 01:32:04 PM PDT 24
Finished May 26 01:32:20 PM PDT 24
Peak memory 248816 kb
Host smart-4899a8a2-4695-4994-8eb3-b2166f57118c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860497363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.2860497363
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.3222150827
Short name T178
Test name
Test status
Simulation time 1708827992 ps
CPU time 4.75 seconds
Started May 26 01:32:07 PM PDT 24
Finished May 26 01:32:13 PM PDT 24
Peak memory 242268 kb
Host smart-33bfd23b-f925-401e-8710-bf6b556f7263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222150827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.3222150827
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.2830247866
Short name T247
Test name
Test status
Simulation time 13589290953 ps
CPU time 37.34 seconds
Started May 26 01:32:08 PM PDT 24
Finished May 26 01:32:47 PM PDT 24
Peak memory 242100 kb
Host smart-e8ce270c-105a-4741-98a5-d0fbf85ac5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830247866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.2830247866
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.3892421770
Short name T822
Test name
Test status
Simulation time 290955945 ps
CPU time 4.64 seconds
Started May 26 01:32:07 PM PDT 24
Finished May 26 01:32:12 PM PDT 24
Peak memory 242128 kb
Host smart-fc0b2f73-8d67-4cec-b27b-74e293b02af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892421770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.3892421770
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.378991151
Short name T198
Test name
Test status
Simulation time 281327743 ps
CPU time 7.78 seconds
Started May 26 01:32:03 PM PDT 24
Finished May 26 01:32:12 PM PDT 24
Peak memory 242432 kb
Host smart-8e21b665-fba7-4cd3-9fa3-9da0d6c007e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378991151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.378991151
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.1184521436
Short name T395
Test name
Test status
Simulation time 1663135304 ps
CPU time 14.01 seconds
Started May 26 01:25:50 PM PDT 24
Finished May 26 01:26:04 PM PDT 24
Peak memory 242096 kb
Host smart-66f2bd90-3c3e-4bd1-8c9c-623f589eeb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184521436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.1184521436
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.4057606878
Short name T755
Test name
Test status
Simulation time 4276074957 ps
CPU time 17 seconds
Started May 26 01:25:51 PM PDT 24
Finished May 26 01:26:09 PM PDT 24
Peak memory 242784 kb
Host smart-b154763f-6746-4c6e-b797-51a4556905f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057606878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.4057606878
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.220757199
Short name T65
Test name
Test status
Simulation time 165334399 ps
CPU time 4.39 seconds
Started May 26 01:25:52 PM PDT 24
Finished May 26 01:25:57 PM PDT 24
Peak memory 242008 kb
Host smart-65ec894d-785b-48f1-81a8-dda5c4a3902f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220757199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.220757199
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.2095958040
Short name T151
Test name
Test status
Simulation time 18831734261 ps
CPU time 65.82 seconds
Started May 26 01:25:52 PM PDT 24
Finished May 26 01:26:58 PM PDT 24
Peak memory 248912 kb
Host smart-4e2342b6-2d9c-48ea-966a-d8c0381f1c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095958040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.2095958040
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.1009967266
Short name T719
Test name
Test status
Simulation time 993791225 ps
CPU time 9.18 seconds
Started May 26 01:25:50 PM PDT 24
Finished May 26 01:25:59 PM PDT 24
Peak memory 242008 kb
Host smart-6d387fab-9d30-4f20-9474-ed3d87cc0c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009967266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.1009967266
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.2227110792
Short name T928
Test name
Test status
Simulation time 308979224 ps
CPU time 4.62 seconds
Started May 26 01:25:50 PM PDT 24
Finished May 26 01:25:56 PM PDT 24
Peak memory 241980 kb
Host smart-22f9dcdb-e79f-4e09-8e58-d4eb396a8b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227110792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.2227110792
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.1208518341
Short name T875
Test name
Test status
Simulation time 1042606355 ps
CPU time 31.89 seconds
Started May 26 01:25:55 PM PDT 24
Finished May 26 01:26:28 PM PDT 24
Peak memory 241816 kb
Host smart-7dbb14a9-4e96-46b5-85f4-86a3b1d79e5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1208518341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.1208518341
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.1820402236
Short name T695
Test name
Test status
Simulation time 151702608 ps
CPU time 5.09 seconds
Started May 26 01:25:49 PM PDT 24
Finished May 26 01:25:54 PM PDT 24
Peak memory 248776 kb
Host smart-6d65734d-4220-4c34-866c-adff1de3fca5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1820402236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.1820402236
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.1138464775
Short name T487
Test name
Test status
Simulation time 331490059 ps
CPU time 3.14 seconds
Started May 26 01:25:51 PM PDT 24
Finished May 26 01:25:55 PM PDT 24
Peak memory 242220 kb
Host smart-6866306b-19c0-44b8-9ca1-087f51a75e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138464775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.1138464775
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.2875978341
Short name T813
Test name
Test status
Simulation time 16165529708 ps
CPU time 90.14 seconds
Started May 26 01:25:53 PM PDT 24
Finished May 26 01:27:24 PM PDT 24
Peak memory 256956 kb
Host smart-618a3ded-9ce1-47b6-bd86-05c718401a66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875978341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all
.2875978341
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.3311031792
Short name T33
Test name
Test status
Simulation time 91607637083 ps
CPU time 1774.12 seconds
Started May 26 01:25:51 PM PDT 24
Finished May 26 01:55:25 PM PDT 24
Peak memory 281356 kb
Host smart-305c2b6e-8e9a-4b68-b31b-21b224777c2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311031792 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.3311031792
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.1988891915
Short name T596
Test name
Test status
Simulation time 2695754075 ps
CPU time 24.97 seconds
Started May 26 01:25:56 PM PDT 24
Finished May 26 01:26:22 PM PDT 24
Peak memory 241920 kb
Host smart-e0eea5d8-b36a-4028-97a0-aece7b0920d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988891915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.1988891915
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.2573071387
Short name T381
Test name
Test status
Simulation time 121636629 ps
CPU time 5.26 seconds
Started May 26 01:32:06 PM PDT 24
Finished May 26 01:32:12 PM PDT 24
Peak memory 242076 kb
Host smart-4069cc17-668e-4a66-bc1b-12e9dc4bc2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573071387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.2573071387
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.407475018
Short name T885
Test name
Test status
Simulation time 291498318 ps
CPU time 4.88 seconds
Started May 26 01:32:06 PM PDT 24
Finished May 26 01:32:12 PM PDT 24
Peak memory 242332 kb
Host smart-401180eb-ad2d-4f78-96e4-57b91809befa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407475018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.407475018
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.864298708
Short name T147
Test name
Test status
Simulation time 205650041 ps
CPU time 10.46 seconds
Started May 26 01:32:06 PM PDT 24
Finished May 26 01:32:17 PM PDT 24
Peak memory 242036 kb
Host smart-e3a95174-7f2b-4856-b3f3-33089cbbb8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864298708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.864298708
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.209284585
Short name T946
Test name
Test status
Simulation time 554165267 ps
CPU time 5.49 seconds
Started May 26 01:32:08 PM PDT 24
Finished May 26 01:32:15 PM PDT 24
Peak memory 242252 kb
Host smart-fa822532-17ca-4241-a252-429ec6bda18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209284585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.209284585
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.1314251481
Short name T672
Test name
Test status
Simulation time 932764866 ps
CPU time 22.01 seconds
Started May 26 01:32:03 PM PDT 24
Finished May 26 01:32:26 PM PDT 24
Peak memory 241908 kb
Host smart-0cdc6d31-93ca-43dc-b29a-37f645c6ce8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314251481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.1314251481
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.1310608981
Short name T869
Test name
Test status
Simulation time 158044376 ps
CPU time 4.56 seconds
Started May 26 01:32:03 PM PDT 24
Finished May 26 01:32:09 PM PDT 24
Peak memory 242172 kb
Host smart-fe245a8b-be0a-4bb6-ad8b-dbc0c483a962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310608981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.1310608981
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.46886835
Short name T439
Test name
Test status
Simulation time 271631096 ps
CPU time 16.18 seconds
Started May 26 01:32:03 PM PDT 24
Finished May 26 01:32:20 PM PDT 24
Peak memory 241984 kb
Host smart-16246edd-e12e-4880-8b70-68acfbc9660a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46886835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.46886835
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.1540880578
Short name T1067
Test name
Test status
Simulation time 190091966 ps
CPU time 3.45 seconds
Started May 26 01:32:04 PM PDT 24
Finished May 26 01:32:08 PM PDT 24
Peak memory 242100 kb
Host smart-9b7905cb-7dfe-42e6-a248-865932c47098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540880578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.1540880578
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.531126027
Short name T913
Test name
Test status
Simulation time 875321432 ps
CPU time 11.19 seconds
Started May 26 01:32:04 PM PDT 24
Finished May 26 01:32:17 PM PDT 24
Peak memory 242008 kb
Host smart-13ca3ff1-9a75-4622-82d7-7f86d893d594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531126027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.531126027
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.466370494
Short name T664
Test name
Test status
Simulation time 651380016 ps
CPU time 5.33 seconds
Started May 26 01:32:06 PM PDT 24
Finished May 26 01:32:12 PM PDT 24
Peak memory 242160 kb
Host smart-c8713d94-a4a6-4acf-91fb-da227e8a735b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466370494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.466370494
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.1996103255
Short name T464
Test name
Test status
Simulation time 398791394 ps
CPU time 8.31 seconds
Started May 26 01:32:05 PM PDT 24
Finished May 26 01:32:15 PM PDT 24
Peak memory 241908 kb
Host smart-d4385d7f-65cf-460a-8515-979b9107b110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996103255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.1996103255
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.1025596411
Short name T636
Test name
Test status
Simulation time 616803889 ps
CPU time 4.27 seconds
Started May 26 01:32:08 PM PDT 24
Finished May 26 01:32:14 PM PDT 24
Peak memory 242032 kb
Host smart-24e5fcd5-4e85-4e69-89e2-048fd638afcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025596411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.1025596411
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.2480086346
Short name T260
Test name
Test status
Simulation time 506279661 ps
CPU time 10.09 seconds
Started May 26 01:32:05 PM PDT 24
Finished May 26 01:32:17 PM PDT 24
Peak memory 242024 kb
Host smart-92830cb0-2422-4921-b8ba-5a029bb3d9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480086346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.2480086346
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.3576065928
Short name T826
Test name
Test status
Simulation time 1943627110 ps
CPU time 4.49 seconds
Started May 26 01:32:06 PM PDT 24
Finished May 26 01:32:12 PM PDT 24
Peak memory 242432 kb
Host smart-4499f3c0-9a2b-42e5-bafd-c15defd3e269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576065928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.3576065928
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.3179770664
Short name T727
Test name
Test status
Simulation time 2993572090 ps
CPU time 11.89 seconds
Started May 26 01:32:04 PM PDT 24
Finished May 26 01:32:17 PM PDT 24
Peak memory 242120 kb
Host smart-1b909813-70fc-486b-b6c5-270971296015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179770664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.3179770664
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.421874496
Short name T628
Test name
Test status
Simulation time 2718939377 ps
CPU time 21.21 seconds
Started May 26 01:32:05 PM PDT 24
Finished May 26 01:32:27 PM PDT 24
Peak memory 242320 kb
Host smart-45e8ac12-8114-4f17-9a3e-5e85800d5737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421874496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.421874496
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.682931337
Short name T518
Test name
Test status
Simulation time 480444837 ps
CPU time 4.4 seconds
Started May 26 01:32:04 PM PDT 24
Finished May 26 01:32:10 PM PDT 24
Peak memory 242260 kb
Host smart-946d0a39-c68d-47bc-a41c-873e85ad8e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682931337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.682931337
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.3953383037
Short name T256
Test name
Test status
Simulation time 311456639 ps
CPU time 7.62 seconds
Started May 26 01:32:12 PM PDT 24
Finished May 26 01:32:21 PM PDT 24
Peak memory 242292 kb
Host smart-d39561fd-d643-4b02-a6d5-bb345d3cac02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953383037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.3953383037
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.3609272102
Short name T612
Test name
Test status
Simulation time 913460611 ps
CPU time 2.19 seconds
Started May 26 01:25:57 PM PDT 24
Finished May 26 01:26:01 PM PDT 24
Peak memory 240616 kb
Host smart-f5e8fa55-b1b8-419e-8763-ecef132a6389
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609272102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.3609272102
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.3526169173
Short name T671
Test name
Test status
Simulation time 633649296 ps
CPU time 11.64 seconds
Started May 26 01:25:57 PM PDT 24
Finished May 26 01:26:11 PM PDT 24
Peak memory 242524 kb
Host smart-3f38ca86-5db2-4c16-8675-268194e49e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526169173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.3526169173
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.845110507
Short name T1068
Test name
Test status
Simulation time 1177545745 ps
CPU time 21.46 seconds
Started May 26 01:25:52 PM PDT 24
Finished May 26 01:26:14 PM PDT 24
Peak memory 242496 kb
Host smart-e1107299-9a74-4e42-8a0b-1d2412e9af4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845110507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.845110507
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.3838741800
Short name T871
Test name
Test status
Simulation time 230691708 ps
CPU time 8.12 seconds
Started May 26 01:25:50 PM PDT 24
Finished May 26 01:25:58 PM PDT 24
Peak memory 242256 kb
Host smart-dcaf48ad-dba5-4392-a1eb-8e26166cabe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838741800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.3838741800
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.1742637111
Short name T611
Test name
Test status
Simulation time 138932464 ps
CPU time 4.41 seconds
Started May 26 01:25:49 PM PDT 24
Finished May 26 01:25:54 PM PDT 24
Peak memory 242440 kb
Host smart-92489b56-aaf1-4800-be9d-7dc99731cb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742637111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.1742637111
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.1078202320
Short name T722
Test name
Test status
Simulation time 1247036787 ps
CPU time 39.6 seconds
Started May 26 01:25:57 PM PDT 24
Finished May 26 01:26:39 PM PDT 24
Peak memory 245692 kb
Host smart-f6bf176a-08f2-4b45-bc50-aa306853755b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078202320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.1078202320
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.1103554544
Short name T1005
Test name
Test status
Simulation time 357718325 ps
CPU time 13.3 seconds
Started May 26 01:25:57 PM PDT 24
Finished May 26 01:26:12 PM PDT 24
Peak memory 242272 kb
Host smart-b100dffe-1cb7-4e41-9bb8-22358a2cd39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103554544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.1103554544
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.1784033019
Short name T1092
Test name
Test status
Simulation time 315729543 ps
CPU time 5.09 seconds
Started May 26 01:25:51 PM PDT 24
Finished May 26 01:25:57 PM PDT 24
Peak memory 242320 kb
Host smart-537b156b-59fc-4361-a478-5108015e3291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784033019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.1784033019
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.3171504664
Short name T742
Test name
Test status
Simulation time 466948119 ps
CPU time 12.82 seconds
Started May 26 01:25:52 PM PDT 24
Finished May 26 01:26:06 PM PDT 24
Peak memory 248648 kb
Host smart-70d53366-8ac8-47d1-b421-370317a57c89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3171504664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.3171504664
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.3712403126
Short name T351
Test name
Test status
Simulation time 226122433 ps
CPU time 4.1 seconds
Started May 26 01:25:59 PM PDT 24
Finished May 26 01:26:05 PM PDT 24
Peak memory 242340 kb
Host smart-8c28d9da-23ff-4c4f-9083-b8ebfbdcb292
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3712403126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.3712403126
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.19047863
Short name T391
Test name
Test status
Simulation time 476178033 ps
CPU time 6.49 seconds
Started May 26 01:25:54 PM PDT 24
Finished May 26 01:26:01 PM PDT 24
Peak memory 242068 kb
Host smart-48b7f941-e9f4-4601-a4c9-3d2048c390f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19047863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.19047863
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.852314243
Short name T1079
Test name
Test status
Simulation time 6803525726 ps
CPU time 126.9 seconds
Started May 26 01:25:59 PM PDT 24
Finished May 26 01:28:08 PM PDT 24
Peak memory 246380 kb
Host smart-f6e74d36-d408-407a-bcbb-79a3262dd070
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852314243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.
852314243
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.3832799924
Short name T97
Test name
Test status
Simulation time 1669898517 ps
CPU time 20.5 seconds
Started May 26 01:25:58 PM PDT 24
Finished May 26 01:26:21 PM PDT 24
Peak memory 248768 kb
Host smart-d6f51613-49f4-4b55-86eb-ebb500ab3cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832799924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.3832799924
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.3675700578
Short name T74
Test name
Test status
Simulation time 402823377 ps
CPU time 4.03 seconds
Started May 26 01:32:15 PM PDT 24
Finished May 26 01:32:20 PM PDT 24
Peak memory 242076 kb
Host smart-410665eb-160b-4986-93c4-0c8ae3890d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675700578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.3675700578
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.2196685927
Short name T522
Test name
Test status
Simulation time 241279872 ps
CPU time 6.82 seconds
Started May 26 01:32:14 PM PDT 24
Finished May 26 01:32:22 PM PDT 24
Peak memory 242268 kb
Host smart-f6c59aef-b86e-471b-8ab7-39c7dc56a19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196685927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.2196685927
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.1831429459
Short name T1154
Test name
Test status
Simulation time 495757004 ps
CPU time 4.83 seconds
Started May 26 01:32:11 PM PDT 24
Finished May 26 01:32:18 PM PDT 24
Peak memory 242272 kb
Host smart-e9887629-63e2-450f-9400-667cc29f5e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831429459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.1831429459
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.3196223121
Short name T1126
Test name
Test status
Simulation time 222107019 ps
CPU time 13.22 seconds
Started May 26 01:32:12 PM PDT 24
Finished May 26 01:32:26 PM PDT 24
Peak memory 241988 kb
Host smart-7045cbc3-86fc-4979-8aea-6293fe9d5faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196223121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.3196223121
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.3640475091
Short name T804
Test name
Test status
Simulation time 176141634 ps
CPU time 5.58 seconds
Started May 26 01:32:11 PM PDT 24
Finished May 26 01:32:18 PM PDT 24
Peak memory 242100 kb
Host smart-d17b05aa-0218-4999-9c4a-6f9a7f58f689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640475091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.3640475091
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.2719857651
Short name T510
Test name
Test status
Simulation time 1331844948 ps
CPU time 28.8 seconds
Started May 26 01:32:14 PM PDT 24
Finished May 26 01:32:43 PM PDT 24
Peak memory 242048 kb
Host smart-31022964-810b-44c6-8941-b7c2e25244c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719857651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.2719857651
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.2710028728
Short name T557
Test name
Test status
Simulation time 155957266 ps
CPU time 3.9 seconds
Started May 26 01:32:15 PM PDT 24
Finished May 26 01:32:20 PM PDT 24
Peak memory 242060 kb
Host smart-15a04f32-6154-451d-80bb-27bf47b3578e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710028728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.2710028728
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.3171241959
Short name T398
Test name
Test status
Simulation time 155250305 ps
CPU time 2.7 seconds
Started May 26 01:32:14 PM PDT 24
Finished May 26 01:32:17 PM PDT 24
Peak memory 242240 kb
Host smart-9f10e622-09e2-444c-89b4-f5cf9129d309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171241959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.3171241959
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.2715411902
Short name T538
Test name
Test status
Simulation time 453979256 ps
CPU time 12.87 seconds
Started May 26 01:32:12 PM PDT 24
Finished May 26 01:32:26 PM PDT 24
Peak memory 242072 kb
Host smart-50f4834f-4d5e-4f35-b423-72acb180170b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715411902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.2715411902
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.2379577255
Short name T431
Test name
Test status
Simulation time 150944796 ps
CPU time 4.25 seconds
Started May 26 01:32:13 PM PDT 24
Finished May 26 01:32:18 PM PDT 24
Peak memory 242048 kb
Host smart-59489037-4c3d-4077-b496-e68813f3afce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379577255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.2379577255
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.2410025707
Short name T568
Test name
Test status
Simulation time 1338493213 ps
CPU time 13.22 seconds
Started May 26 01:32:12 PM PDT 24
Finished May 26 01:32:27 PM PDT 24
Peak memory 241936 kb
Host smart-60d88587-d5ee-41df-83f1-7622b718216f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410025707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.2410025707
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.2141080734
Short name T1113
Test name
Test status
Simulation time 545500071 ps
CPU time 5.25 seconds
Started May 26 01:32:14 PM PDT 24
Finished May 26 01:32:20 PM PDT 24
Peak memory 242360 kb
Host smart-cbc727f1-065a-43ec-ac9d-e29b377b6b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141080734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.2141080734
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.1592016439
Short name T1027
Test name
Test status
Simulation time 818118648 ps
CPU time 26.86 seconds
Started May 26 01:32:15 PM PDT 24
Finished May 26 01:32:43 PM PDT 24
Peak memory 242052 kb
Host smart-60231049-c924-45ab-bebe-55793a3560a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592016439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.1592016439
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.719474362
Short name T506
Test name
Test status
Simulation time 264884898 ps
CPU time 3.76 seconds
Started May 26 01:32:18 PM PDT 24
Finished May 26 01:32:22 PM PDT 24
Peak memory 242324 kb
Host smart-6744717f-8f1a-467a-915b-0bb1bb15b838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719474362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.719474362
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.619665635
Short name T440
Test name
Test status
Simulation time 460160704 ps
CPU time 7.23 seconds
Started May 26 01:32:12 PM PDT 24
Finished May 26 01:32:21 PM PDT 24
Peak memory 241908 kb
Host smart-71cc97da-0469-4d17-aa74-5c4e6d0a0fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619665635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.619665635
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.3781903727
Short name T623
Test name
Test status
Simulation time 155957791 ps
CPU time 4.54 seconds
Started May 26 01:32:13 PM PDT 24
Finished May 26 01:32:18 PM PDT 24
Peak memory 242144 kb
Host smart-cc5c4295-c8cf-4910-a7c1-f4674e8683e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781903727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.3781903727
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.1002904959
Short name T1076
Test name
Test status
Simulation time 1403632015 ps
CPU time 9.95 seconds
Started May 26 01:32:14 PM PDT 24
Finished May 26 01:32:25 PM PDT 24
Peak memory 242016 kb
Host smart-32697a7e-e5b0-4593-ac92-f475158dc54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002904959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.1002904959
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.2411383867
Short name T190
Test name
Test status
Simulation time 157589439 ps
CPU time 4.44 seconds
Started May 26 01:32:21 PM PDT 24
Finished May 26 01:32:27 PM PDT 24
Peak memory 242016 kb
Host smart-3063808a-4fa2-4b5e-88ca-80951aa7776a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411383867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2411383867
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.2834520617
Short name T730
Test name
Test status
Simulation time 1776698883 ps
CPU time 5.43 seconds
Started May 26 01:32:20 PM PDT 24
Finished May 26 01:32:27 PM PDT 24
Peak memory 242188 kb
Host smart-2f49cfb5-fb9c-473a-8e9f-f8411c937d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834520617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.2834520617
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.2635753942
Short name T419
Test name
Test status
Simulation time 108850935 ps
CPU time 1.88 seconds
Started May 26 01:26:05 PM PDT 24
Finished May 26 01:26:07 PM PDT 24
Peak memory 240512 kb
Host smart-150c4beb-fe00-4935-be8f-8a55b7f47fbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635753942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.2635753942
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.3440050243
Short name T1090
Test name
Test status
Simulation time 696949654 ps
CPU time 10.87 seconds
Started May 26 01:25:59 PM PDT 24
Finished May 26 01:26:11 PM PDT 24
Peak memory 242080 kb
Host smart-9ba3daa3-778f-4d4a-8e8c-715930d0af65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440050243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.3440050243
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.878091819
Short name T794
Test name
Test status
Simulation time 4836835086 ps
CPU time 16.14 seconds
Started May 26 01:25:57 PM PDT 24
Finished May 26 01:26:15 PM PDT 24
Peak memory 242504 kb
Host smart-da85d1e2-14dc-48f8-9670-4697b938d05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878091819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.878091819
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.2108982008
Short name T688
Test name
Test status
Simulation time 1706632604 ps
CPU time 31.97 seconds
Started May 26 01:26:00 PM PDT 24
Finished May 26 01:26:34 PM PDT 24
Peak memory 245604 kb
Host smart-980fead0-f39f-4475-99d4-1fbcef82ea7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108982008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.2108982008
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.2369197443
Short name T176
Test name
Test status
Simulation time 824652245 ps
CPU time 9.84 seconds
Started May 26 01:26:00 PM PDT 24
Finished May 26 01:26:11 PM PDT 24
Peak memory 242176 kb
Host smart-9a42a957-87e0-4266-8de5-0fb00a41bb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369197443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.2369197443
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.2440240615
Short name T716
Test name
Test status
Simulation time 212296704 ps
CPU time 5.19 seconds
Started May 26 01:26:02 PM PDT 24
Finished May 26 01:26:09 PM PDT 24
Peak memory 241900 kb
Host smart-4d154adb-57cc-4a09-98ef-73fd68839a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440240615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.2440240615
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.2823299572
Short name T1051
Test name
Test status
Simulation time 504513127 ps
CPU time 13.57 seconds
Started May 26 01:25:57 PM PDT 24
Finished May 26 01:26:13 PM PDT 24
Peak memory 248680 kb
Host smart-49a9f53a-5d15-4e2d-a263-ffdd08df3028
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2823299572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.2823299572
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.196606760
Short name T633
Test name
Test status
Simulation time 1216045049 ps
CPU time 12.79 seconds
Started May 26 01:25:56 PM PDT 24
Finished May 26 01:26:11 PM PDT 24
Peak memory 242004 kb
Host smart-e401fcb9-18ed-46e9-a64d-8f1f953206ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196606760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.196606760
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.204895223
Short name T1078
Test name
Test status
Simulation time 20776943092 ps
CPU time 126.26 seconds
Started May 26 01:26:05 PM PDT 24
Finished May 26 01:28:13 PM PDT 24
Peak memory 247760 kb
Host smart-a2c4cef1-e52f-4d76-9e8a-1fef13cb7f3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204895223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.
204895223
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.32910486
Short name T330
Test name
Test status
Simulation time 1027293629270 ps
CPU time 1390.91 seconds
Started May 26 01:26:06 PM PDT 24
Finished May 26 01:49:18 PM PDT 24
Peak memory 342528 kb
Host smart-867ec84d-d6fa-4d3d-830a-fac5796d92eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32910486 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.32910486
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.2083072944
Short name T603
Test name
Test status
Simulation time 345055460 ps
CPU time 11.76 seconds
Started May 26 01:25:57 PM PDT 24
Finished May 26 01:26:11 PM PDT 24
Peak memory 241936 kb
Host smart-62e50da1-a004-4499-a1fe-e5696dfec887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083072944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.2083072944
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.2704960503
Short name T608
Test name
Test status
Simulation time 123625256 ps
CPU time 3.65 seconds
Started May 26 01:32:21 PM PDT 24
Finished May 26 01:32:25 PM PDT 24
Peak memory 242428 kb
Host smart-edf737c0-69ae-486d-9001-964879830f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704960503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.2704960503
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.2113566294
Short name T657
Test name
Test status
Simulation time 1597992900 ps
CPU time 4.88 seconds
Started May 26 01:32:22 PM PDT 24
Finished May 26 01:32:27 PM PDT 24
Peak memory 242144 kb
Host smart-d5445c4b-629f-4c67-b7d7-1ae1d37b6f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113566294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.2113566294
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.1931958492
Short name T1185
Test name
Test status
Simulation time 145364840 ps
CPU time 4.14 seconds
Started May 26 01:32:21 PM PDT 24
Finished May 26 01:32:26 PM PDT 24
Peak memory 241944 kb
Host smart-12fe6210-7d05-460a-a579-9805884046bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931958492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.1931958492
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.2176212678
Short name T840
Test name
Test status
Simulation time 470311066 ps
CPU time 5.15 seconds
Started May 26 01:32:19 PM PDT 24
Finished May 26 01:32:25 PM PDT 24
Peak memory 242308 kb
Host smart-2e73e20b-f0ab-43d3-8fb1-898ce4187a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176212678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.2176212678
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.1392648984
Short name T992
Test name
Test status
Simulation time 427236780 ps
CPU time 11.55 seconds
Started May 26 01:32:21 PM PDT 24
Finished May 26 01:32:33 PM PDT 24
Peak memory 242128 kb
Host smart-6915aad8-9652-451c-ab8c-854593d3d16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392648984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.1392648984
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.2003944830
Short name T996
Test name
Test status
Simulation time 382011141 ps
CPU time 4.4 seconds
Started May 26 01:32:29 PM PDT 24
Finished May 26 01:32:34 PM PDT 24
Peak memory 242096 kb
Host smart-45c3e592-9e5f-4c01-9f27-bc2ec0df760a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003944830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.2003944830
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.3305903707
Short name T132
Test name
Test status
Simulation time 302515754 ps
CPU time 2.86 seconds
Started May 26 01:32:20 PM PDT 24
Finished May 26 01:32:23 PM PDT 24
Peak memory 241940 kb
Host smart-f9626858-163c-4a3f-a133-7dc9403c983c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305903707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.3305903707
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.1108150442
Short name T141
Test name
Test status
Simulation time 467073168 ps
CPU time 13.9 seconds
Started May 26 01:32:20 PM PDT 24
Finished May 26 01:32:34 PM PDT 24
Peak memory 242028 kb
Host smart-e45a7a17-b461-4ac5-a6d2-303e227fe336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108150442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.1108150442
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.2223407254
Short name T1164
Test name
Test status
Simulation time 202772712 ps
CPU time 4.45 seconds
Started May 26 01:32:20 PM PDT 24
Finished May 26 01:32:25 PM PDT 24
Peak memory 242372 kb
Host smart-bd854dab-9510-4175-9fec-4d038c373772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223407254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.2223407254
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.4112164016
Short name T606
Test name
Test status
Simulation time 406552873 ps
CPU time 5.24 seconds
Started May 26 01:32:27 PM PDT 24
Finished May 26 01:32:33 PM PDT 24
Peak memory 241988 kb
Host smart-1c2d4a2e-1c23-43df-854a-b33e163c66dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112164016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.4112164016
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.312942214
Short name T545
Test name
Test status
Simulation time 291193672 ps
CPU time 3.71 seconds
Started May 26 01:32:33 PM PDT 24
Finished May 26 01:32:37 PM PDT 24
Peak memory 242016 kb
Host smart-cdad0f81-69e0-4bc4-a1fb-1352d0366bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312942214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.312942214
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.4178332929
Short name T771
Test name
Test status
Simulation time 666517319 ps
CPU time 9.41 seconds
Started May 26 01:32:30 PM PDT 24
Finished May 26 01:32:40 PM PDT 24
Peak memory 241868 kb
Host smart-49aaf7e0-fbec-4656-ac34-fc7f3d023360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178332929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.4178332929
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.3201633495
Short name T1022
Test name
Test status
Simulation time 272614809 ps
CPU time 3.47 seconds
Started May 26 01:32:28 PM PDT 24
Finished May 26 01:32:33 PM PDT 24
Peak memory 242404 kb
Host smart-878f67a7-4aaa-4979-9644-6b274001a70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201633495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.3201633495
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.2878761707
Short name T850
Test name
Test status
Simulation time 363398919 ps
CPU time 5.68 seconds
Started May 26 01:32:29 PM PDT 24
Finished May 26 01:32:36 PM PDT 24
Peak memory 242344 kb
Host smart-9b5d7836-ff1b-4cea-9149-618537bf046a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878761707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.2878761707
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.3180578845
Short name T415
Test name
Test status
Simulation time 196653109 ps
CPU time 4 seconds
Started May 26 01:32:28 PM PDT 24
Finished May 26 01:32:33 PM PDT 24
Peak memory 242384 kb
Host smart-082b7ccf-9529-46e6-a856-ee8ec5e40b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180578845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.3180578845
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.699182652
Short name T554
Test name
Test status
Simulation time 2280347039 ps
CPU time 6.95 seconds
Started May 26 01:32:28 PM PDT 24
Finished May 26 01:32:36 PM PDT 24
Peak memory 242124 kb
Host smart-c46bdb98-f60c-47e7-960a-aae8b19c5ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699182652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.699182652
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.2957315136
Short name T187
Test name
Test status
Simulation time 1848038007 ps
CPU time 4.58 seconds
Started May 26 01:32:28 PM PDT 24
Finished May 26 01:32:34 PM PDT 24
Peak memory 242284 kb
Host smart-efc43081-eb5b-42bf-820e-b517ae92cd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957315136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.2957315136
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.847965151
Short name T903
Test name
Test status
Simulation time 444099068 ps
CPU time 5.05 seconds
Started May 26 01:32:30 PM PDT 24
Finished May 26 01:32:36 PM PDT 24
Peak memory 241892 kb
Host smart-6fd77d5a-007c-45de-b5d3-dad1c7c0ac96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847965151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.847965151
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.3325484478
Short name T973
Test name
Test status
Simulation time 143445846 ps
CPU time 1.8 seconds
Started May 26 01:26:08 PM PDT 24
Finished May 26 01:26:10 PM PDT 24
Peak memory 240492 kb
Host smart-7676b9fb-3541-40e0-96ab-43be27860a86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325484478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.3325484478
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.1967247030
Short name T964
Test name
Test status
Simulation time 3362345784 ps
CPU time 29.63 seconds
Started May 26 01:26:09 PM PDT 24
Finished May 26 01:26:39 PM PDT 24
Peak memory 243156 kb
Host smart-1f030b29-923e-4746-b7d4-5cc04cb20679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967247030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.1967247030
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.2418680716
Short name T581
Test name
Test status
Simulation time 1472584087 ps
CPU time 28.26 seconds
Started May 26 01:26:05 PM PDT 24
Finished May 26 01:26:34 PM PDT 24
Peak memory 242012 kb
Host smart-6fb7ad7a-46c5-4afe-8fd7-361cb268f701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418680716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.2418680716
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.2306326892
Short name T898
Test name
Test status
Simulation time 5047480072 ps
CPU time 9.16 seconds
Started May 26 01:26:09 PM PDT 24
Finished May 26 01:26:18 PM PDT 24
Peak memory 242452 kb
Host smart-d624ad00-4c6b-4cac-b83e-c8eae5de76da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306326892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.2306326892
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.195174254
Short name T630
Test name
Test status
Simulation time 568955739 ps
CPU time 4.52 seconds
Started May 26 01:26:07 PM PDT 24
Finished May 26 01:26:12 PM PDT 24
Peak memory 242096 kb
Host smart-cfadf67f-accb-4489-ad94-c65afba0d54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195174254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.195174254
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.1106133535
Short name T152
Test name
Test status
Simulation time 1346810231 ps
CPU time 21.14 seconds
Started May 26 01:26:07 PM PDT 24
Finished May 26 01:26:29 PM PDT 24
Peak memory 242444 kb
Host smart-d7dbdc47-de14-4753-9d30-8732894e018f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106133535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.1106133535
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.2894612560
Short name T809
Test name
Test status
Simulation time 492755674 ps
CPU time 11.93 seconds
Started May 26 01:26:06 PM PDT 24
Finished May 26 01:26:19 PM PDT 24
Peak memory 241940 kb
Host smart-fd093389-7a68-483e-adee-20acf715ac6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894612560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.2894612560
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.2737172259
Short name T386
Test name
Test status
Simulation time 2082061051 ps
CPU time 6.62 seconds
Started May 26 01:26:07 PM PDT 24
Finished May 26 01:26:15 PM PDT 24
Peak memory 242004 kb
Host smart-fb005a5e-23f5-476f-a033-9125684ffcfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2737172259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.2737172259
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.3264833638
Short name T1055
Test name
Test status
Simulation time 677466009 ps
CPU time 7.9 seconds
Started May 26 01:26:08 PM PDT 24
Finished May 26 01:26:17 PM PDT 24
Peak memory 242096 kb
Host smart-8d1e5d8c-c855-4121-9f66-b16f04aceba1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3264833638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.3264833638
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.2599664197
Short name T413
Test name
Test status
Simulation time 1031355164 ps
CPU time 12.28 seconds
Started May 26 01:26:07 PM PDT 24
Finished May 26 01:26:21 PM PDT 24
Peak memory 241852 kb
Host smart-484e2ecb-0bb2-42cf-829c-a5d1ec3c95ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599664197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.2599664197
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.3023585087
Short name T940
Test name
Test status
Simulation time 44381076533 ps
CPU time 199.33 seconds
Started May 26 01:26:06 PM PDT 24
Finished May 26 01:29:26 PM PDT 24
Peak memory 257000 kb
Host smart-a9dd48e5-35e7-4ba9-b4a5-25d1d8ffa05f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023585087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all
.3023585087
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.358558763
Short name T376
Test name
Test status
Simulation time 1188028695 ps
CPU time 23.39 seconds
Started May 26 01:26:08 PM PDT 24
Finished May 26 01:26:32 PM PDT 24
Peak memory 248704 kb
Host smart-14df103f-1c07-4e15-a2fc-9b3151ee446f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358558763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.358558763
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.1286776585
Short name T1041
Test name
Test status
Simulation time 1699010234 ps
CPU time 3.38 seconds
Started May 26 01:32:29 PM PDT 24
Finished May 26 01:32:33 PM PDT 24
Peak memory 242244 kb
Host smart-32b720f1-a627-4d99-a202-1399e85f582f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286776585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.1286776585
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.751990758
Short name T761
Test name
Test status
Simulation time 197100607 ps
CPU time 11.32 seconds
Started May 26 01:32:29 PM PDT 24
Finished May 26 01:32:41 PM PDT 24
Peak memory 241924 kb
Host smart-bcf36023-bb16-42ff-9ac3-85c701ebf519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751990758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.751990758
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.1164066434
Short name T1096
Test name
Test status
Simulation time 245288316 ps
CPU time 3.51 seconds
Started May 26 01:32:27 PM PDT 24
Finished May 26 01:32:31 PM PDT 24
Peak memory 242020 kb
Host smart-31fe9df4-4022-44a0-8294-10b841b312de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164066434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.1164066434
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.335660478
Short name T553
Test name
Test status
Simulation time 1084087791 ps
CPU time 7.74 seconds
Started May 26 01:32:28 PM PDT 24
Finished May 26 01:32:36 PM PDT 24
Peak memory 242044 kb
Host smart-78f8e706-b6dd-45c0-8199-f8953bf6c6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335660478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.335660478
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.1725459240
Short name T893
Test name
Test status
Simulation time 1809264216 ps
CPU time 6.14 seconds
Started May 26 01:32:30 PM PDT 24
Finished May 26 01:32:37 PM PDT 24
Peak memory 242468 kb
Host smart-68481202-4665-4267-90e6-199e3ce4467d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725459240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.1725459240
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.3071944772
Short name T699
Test name
Test status
Simulation time 1556973486 ps
CPU time 4.22 seconds
Started May 26 01:32:27 PM PDT 24
Finished May 26 01:32:32 PM PDT 24
Peak memory 242064 kb
Host smart-090bad11-80a6-4d94-85db-69c503babf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071944772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.3071944772
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.3870549320
Short name T925
Test name
Test status
Simulation time 651904668 ps
CPU time 5.16 seconds
Started May 26 01:32:33 PM PDT 24
Finished May 26 01:32:38 PM PDT 24
Peak memory 242484 kb
Host smart-efa6b25a-c630-4bc8-b127-0a9aa6c64f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870549320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.3870549320
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.538986893
Short name T1062
Test name
Test status
Simulation time 161609624 ps
CPU time 2.99 seconds
Started May 26 01:32:39 PM PDT 24
Finished May 26 01:32:42 PM PDT 24
Peak memory 242000 kb
Host smart-d188a66a-f908-4b47-9f58-63576ee1b1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538986893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.538986893
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.3922082989
Short name T594
Test name
Test status
Simulation time 448114789 ps
CPU time 3.42 seconds
Started May 26 01:32:43 PM PDT 24
Finished May 26 01:32:47 PM PDT 24
Peak memory 241904 kb
Host smart-cbc86364-2de0-43ef-ba27-c09de8029c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922082989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.3922082989
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.2608525655
Short name T1121
Test name
Test status
Simulation time 391073818 ps
CPU time 3.11 seconds
Started May 26 01:32:39 PM PDT 24
Finished May 26 01:32:42 PM PDT 24
Peak memory 242388 kb
Host smart-f6d6b9d7-641a-442a-a988-113b58cf89df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608525655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.2608525655
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.1921380676
Short name T643
Test name
Test status
Simulation time 576189622 ps
CPU time 4.79 seconds
Started May 26 01:32:39 PM PDT 24
Finished May 26 01:32:44 PM PDT 24
Peak memory 241972 kb
Host smart-5987e56c-f44a-4796-93e3-a6d1ca9100c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921380676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.1921380676
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.4175728210
Short name T936
Test name
Test status
Simulation time 1097421228 ps
CPU time 7.74 seconds
Started May 26 01:32:38 PM PDT 24
Finished May 26 01:32:46 PM PDT 24
Peak memory 242404 kb
Host smart-9a1d8f5c-280f-4473-a8fe-d2745fe8a5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175728210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.4175728210
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.3900633470
Short name T703
Test name
Test status
Simulation time 2449077485 ps
CPU time 8.24 seconds
Started May 26 01:32:37 PM PDT 24
Finished May 26 01:32:46 PM PDT 24
Peak memory 242268 kb
Host smart-20fba89b-696e-4e20-96eb-aed2a44ea012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900633470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.3900633470
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.1571396350
Short name T1116
Test name
Test status
Simulation time 3033193424 ps
CPU time 23.66 seconds
Started May 26 01:32:38 PM PDT 24
Finished May 26 01:33:02 PM PDT 24
Peak memory 241964 kb
Host smart-6f103df2-b0b2-4b4c-ac05-a96100049fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571396350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.1571396350
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.397907228
Short name T1119
Test name
Test status
Simulation time 1662926299 ps
CPU time 5.72 seconds
Started May 26 01:32:36 PM PDT 24
Finished May 26 01:32:43 PM PDT 24
Peak memory 241904 kb
Host smart-a415ac01-8d4d-419f-9d15-238b193bb5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397907228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.397907228
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.385870980
Short name T859
Test name
Test status
Simulation time 220387796 ps
CPU time 6.19 seconds
Started May 26 01:32:41 PM PDT 24
Finished May 26 01:32:48 PM PDT 24
Peak memory 242512 kb
Host smart-6bd7b4bf-8371-4334-900f-b447491f2534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385870980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.385870980
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.3474532955
Short name T27
Test name
Test status
Simulation time 484198540 ps
CPU time 5.77 seconds
Started May 26 01:32:36 PM PDT 24
Finished May 26 01:32:42 PM PDT 24
Peak memory 241932 kb
Host smart-5dfa54fa-6fcb-4737-ad0f-16441149096b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474532955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.3474532955
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.3692525606
Short name T443
Test name
Test status
Simulation time 1424750986 ps
CPU time 8.65 seconds
Started May 26 01:32:43 PM PDT 24
Finished May 26 01:32:52 PM PDT 24
Peak memory 242320 kb
Host smart-923c36cf-4fe1-47d8-9f8e-a69da3879c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692525606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.3692525606
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.2646663171
Short name T1133
Test name
Test status
Simulation time 675419413 ps
CPU time 5.15 seconds
Started May 26 01:32:35 PM PDT 24
Finished May 26 01:32:41 PM PDT 24
Peak memory 242084 kb
Host smart-7421d2b6-c726-4f27-8d5b-fe0e7e0f6378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646663171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.2646663171
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.1549358750
Short name T502
Test name
Test status
Simulation time 535167060 ps
CPU time 4.81 seconds
Started May 26 01:32:38 PM PDT 24
Finished May 26 01:32:43 PM PDT 24
Peak memory 242344 kb
Host smart-bdf61876-1881-4729-a17f-bfbe6af9e8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549358750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.1549358750
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.3240580181
Short name T846
Test name
Test status
Simulation time 78929520 ps
CPU time 2.06 seconds
Started May 26 01:26:14 PM PDT 24
Finished May 26 01:26:17 PM PDT 24
Peak memory 240500 kb
Host smart-aca93e39-5ba9-48f8-abc9-1cc552b59bea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240580181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.3240580181
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.3720419290
Short name T1088
Test name
Test status
Simulation time 2861637667 ps
CPU time 26.3 seconds
Started May 26 01:26:16 PM PDT 24
Finished May 26 01:26:43 PM PDT 24
Peak memory 248760 kb
Host smart-8e147e00-67ae-444b-9b33-8f55acff8d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720419290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.3720419290
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.3623200320
Short name T432
Test name
Test status
Simulation time 2508089863 ps
CPU time 26.35 seconds
Started May 26 01:26:15 PM PDT 24
Finished May 26 01:26:42 PM PDT 24
Peak memory 242416 kb
Host smart-84399464-88e1-4190-a4ab-07a6b93dcaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623200320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.3623200320
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.838750966
Short name T375
Test name
Test status
Simulation time 722202428 ps
CPU time 16.43 seconds
Started May 26 01:26:14 PM PDT 24
Finished May 26 01:26:31 PM PDT 24
Peak memory 242132 kb
Host smart-1c4ae6b5-3d86-44cf-ac3f-21cea2cca7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838750966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.838750966
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.762059390
Short name T988
Test name
Test status
Simulation time 117196213 ps
CPU time 4.04 seconds
Started May 26 01:26:06 PM PDT 24
Finished May 26 01:26:11 PM PDT 24
Peak memory 242156 kb
Host smart-db5b1111-b9df-440d-85c8-c0d2430cb24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762059390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.762059390
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.4199244532
Short name T531
Test name
Test status
Simulation time 3497233533 ps
CPU time 19.79 seconds
Started May 26 01:26:15 PM PDT 24
Finished May 26 01:26:36 PM PDT 24
Peak memory 243152 kb
Host smart-c553387d-83c0-4e74-9f7f-66854f23bebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199244532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.4199244532
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.4284189411
Short name T530
Test name
Test status
Simulation time 2777356484 ps
CPU time 17.98 seconds
Started May 26 01:26:15 PM PDT 24
Finished May 26 01:26:34 PM PDT 24
Peak memory 248848 kb
Host smart-a55fa269-de34-4737-852c-62a722e9e954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284189411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.4284189411
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.3689394384
Short name T599
Test name
Test status
Simulation time 536214878 ps
CPU time 14.85 seconds
Started May 26 01:26:15 PM PDT 24
Finished May 26 01:26:30 PM PDT 24
Peak memory 242004 kb
Host smart-096ee0ee-7af7-48ed-a127-d5223e76c312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689394384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.3689394384
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.319252043
Short name T781
Test name
Test status
Simulation time 2121107083 ps
CPU time 25.86 seconds
Started May 26 01:26:14 PM PDT 24
Finished May 26 01:26:40 PM PDT 24
Peak memory 241984 kb
Host smart-15425a52-9c2d-4119-b665-6bc973e26ce4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=319252043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.319252043
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.558137387
Short name T353
Test name
Test status
Simulation time 288564471 ps
CPU time 5.85 seconds
Started May 26 01:26:15 PM PDT 24
Finished May 26 01:26:22 PM PDT 24
Peak memory 242332 kb
Host smart-309030bf-f1c6-4991-a36b-43badd0f433a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=558137387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.558137387
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.1563082027
Short name T433
Test name
Test status
Simulation time 822992263 ps
CPU time 8.7 seconds
Started May 26 01:26:05 PM PDT 24
Finished May 26 01:26:15 PM PDT 24
Peak memory 248624 kb
Host smart-e069a224-355e-4a9f-8684-c744439ed752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563082027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.1563082027
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.424620511
Short name T560
Test name
Test status
Simulation time 5696416068 ps
CPU time 53.97 seconds
Started May 26 01:26:16 PM PDT 24
Finished May 26 01:27:10 PM PDT 24
Peak memory 245092 kb
Host smart-f0cab448-d820-454e-904f-dc3bc1543a03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424620511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.
424620511
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.485794106
Short name T656
Test name
Test status
Simulation time 174652495125 ps
CPU time 1623.2 seconds
Started May 26 01:26:16 PM PDT 24
Finished May 26 01:53:20 PM PDT 24
Peak memory 535312 kb
Host smart-9cc3eb72-0290-4684-9c99-c953466d53dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485794106 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.485794106
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.3041333282
Short name T736
Test name
Test status
Simulation time 3480653982 ps
CPU time 24.31 seconds
Started May 26 01:26:20 PM PDT 24
Finished May 26 01:26:45 PM PDT 24
Peak memory 242456 kb
Host smart-a1004fc9-d044-474c-8c18-df5f08cf2f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041333282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.3041333282
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.2655468717
Short name T908
Test name
Test status
Simulation time 429503786 ps
CPU time 3.83 seconds
Started May 26 01:32:39 PM PDT 24
Finished May 26 01:32:43 PM PDT 24
Peak memory 242076 kb
Host smart-641a88bc-c93f-4aaa-a310-e8cabb9a1b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655468717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.2655468717
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.3068862394
Short name T845
Test name
Test status
Simulation time 112360870 ps
CPU time 5.12 seconds
Started May 26 01:32:36 PM PDT 24
Finished May 26 01:32:42 PM PDT 24
Peak memory 241960 kb
Host smart-7adfdd10-9968-4fbe-927c-1948c56a0b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068862394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.3068862394
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.1571522409
Short name T966
Test name
Test status
Simulation time 262035806 ps
CPU time 4.19 seconds
Started May 26 01:32:47 PM PDT 24
Finished May 26 01:32:51 PM PDT 24
Peak memory 242080 kb
Host smart-30ae7932-f958-428e-a587-03e7db3c76d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571522409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.1571522409
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.1364147356
Short name T696
Test name
Test status
Simulation time 186263717 ps
CPU time 6.13 seconds
Started May 26 01:32:46 PM PDT 24
Finished May 26 01:32:53 PM PDT 24
Peak memory 242048 kb
Host smart-30768fa6-42b8-46ea-af26-5cce11e9fcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364147356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.1364147356
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.2058202804
Short name T562
Test name
Test status
Simulation time 332499567 ps
CPU time 4.03 seconds
Started May 26 01:32:46 PM PDT 24
Finished May 26 01:32:51 PM PDT 24
Peak memory 242296 kb
Host smart-90193512-8606-4112-b8be-8a5149a3d5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058202804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.2058202804
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.357331457
Short name T216
Test name
Test status
Simulation time 102959512 ps
CPU time 4.33 seconds
Started May 26 01:32:46 PM PDT 24
Finished May 26 01:32:51 PM PDT 24
Peak memory 241904 kb
Host smart-2f9ba3f0-b304-49a2-9b0e-2b81a3467ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357331457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.357331457
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.1695364655
Short name T421
Test name
Test status
Simulation time 454048257 ps
CPU time 4.5 seconds
Started May 26 01:32:57 PM PDT 24
Finished May 26 01:33:02 PM PDT 24
Peak memory 241976 kb
Host smart-e3d3f6aa-bbe9-47a2-8f15-5679a830484e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695364655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.1695364655
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.2491131193
Short name T121
Test name
Test status
Simulation time 379511221 ps
CPU time 9.74 seconds
Started May 26 01:32:47 PM PDT 24
Finished May 26 01:32:57 PM PDT 24
Peak memory 241996 kb
Host smart-a94f9779-bc10-4ae4-9344-09597ae03d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491131193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.2491131193
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.696858107
Short name T787
Test name
Test status
Simulation time 414374560 ps
CPU time 5.79 seconds
Started May 26 01:32:45 PM PDT 24
Finished May 26 01:32:52 PM PDT 24
Peak memory 241916 kb
Host smart-b2856b05-bf1d-46a0-95ea-2435df035879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696858107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.696858107
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.3822989163
Short name T43
Test name
Test status
Simulation time 496274404 ps
CPU time 3.78 seconds
Started May 26 01:32:45 PM PDT 24
Finished May 26 01:32:49 PM PDT 24
Peak memory 242028 kb
Host smart-b1dcbd7d-6367-49ba-b071-f5e262a2c468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822989163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.3822989163
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.2645552699
Short name T309
Test name
Test status
Simulation time 1235868162 ps
CPU time 3.86 seconds
Started May 26 01:32:47 PM PDT 24
Finished May 26 01:32:51 PM PDT 24
Peak memory 242264 kb
Host smart-9e589902-75ee-4ff6-9e5b-f431cbad79e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645552699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.2645552699
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.1387634792
Short name T50
Test name
Test status
Simulation time 216052277 ps
CPU time 4.64 seconds
Started May 26 01:32:45 PM PDT 24
Finished May 26 01:32:51 PM PDT 24
Peak memory 242384 kb
Host smart-732b4646-2b4a-431a-8be3-186911f562e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387634792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.1387634792
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.2769042165
Short name T1083
Test name
Test status
Simulation time 2104803241 ps
CPU time 8.49 seconds
Started May 26 01:32:45 PM PDT 24
Finished May 26 01:32:55 PM PDT 24
Peak memory 242308 kb
Host smart-1ae54afc-dc55-487e-bb70-e52fabf689f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769042165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.2769042165
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.4067979620
Short name T972
Test name
Test status
Simulation time 391075030 ps
CPU time 11.11 seconds
Started May 26 01:32:45 PM PDT 24
Finished May 26 01:32:57 PM PDT 24
Peak memory 242568 kb
Host smart-41503a65-ac72-4d86-abdb-063b9b694708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067979620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.4067979620
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.1090556024
Short name T1155
Test name
Test status
Simulation time 2497558365 ps
CPU time 7.75 seconds
Started May 26 01:32:47 PM PDT 24
Finished May 26 01:32:55 PM PDT 24
Peak memory 242152 kb
Host smart-6c6510ba-1f8f-420b-b52e-59f8e60c2f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090556024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.1090556024
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.839641071
Short name T149
Test name
Test status
Simulation time 388005752 ps
CPU time 8.53 seconds
Started May 26 01:32:56 PM PDT 24
Finished May 26 01:33:06 PM PDT 24
Peak memory 241896 kb
Host smart-24e8b207-4b17-44d0-ba80-ad2674e6eebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839641071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.839641071
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.568737724
Short name T670
Test name
Test status
Simulation time 97361065 ps
CPU time 4.26 seconds
Started May 26 01:32:46 PM PDT 24
Finished May 26 01:32:51 PM PDT 24
Peak memory 241952 kb
Host smart-a3c924fd-bcef-45e7-9b31-2a5f7e8fa3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568737724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.568737724
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.1180985980
Short name T819
Test name
Test status
Simulation time 388642103 ps
CPU time 3.74 seconds
Started May 26 01:32:55 PM PDT 24
Finished May 26 01:33:00 PM PDT 24
Peak memory 242196 kb
Host smart-8cae50c8-cdca-4a55-a9b6-c214c66b26c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180985980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.1180985980
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.856081529
Short name T430
Test name
Test status
Simulation time 199705740 ps
CPU time 2.16 seconds
Started May 26 01:26:23 PM PDT 24
Finished May 26 01:26:26 PM PDT 24
Peak memory 240600 kb
Host smart-c5d19160-fe1f-430a-9560-8129937c9fa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856081529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.856081529
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.2581735460
Short name T35
Test name
Test status
Simulation time 1551982699 ps
CPU time 24.87 seconds
Started May 26 01:26:22 PM PDT 24
Finished May 26 01:26:48 PM PDT 24
Peak memory 242040 kb
Host smart-ff4095b0-8caf-4f37-8bbc-0ddd0b8ab6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581735460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.2581735460
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.997330031
Short name T1080
Test name
Test status
Simulation time 4781320973 ps
CPU time 24.55 seconds
Started May 26 01:26:24 PM PDT 24
Finished May 26 01:26:49 PM PDT 24
Peak memory 242368 kb
Host smart-8b1034f5-b246-4ad3-b1fa-79df1b7773e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997330031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.997330031
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.3709253925
Short name T102
Test name
Test status
Simulation time 1138601914 ps
CPU time 11.34 seconds
Started May 26 01:26:23 PM PDT 24
Finished May 26 01:26:34 PM PDT 24
Peak memory 242140 kb
Host smart-515d0127-4276-4753-a8bf-33813d25c3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709253925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.3709253925
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.2062559730
Short name T609
Test name
Test status
Simulation time 572916751 ps
CPU time 4.32 seconds
Started May 26 01:26:17 PM PDT 24
Finished May 26 01:26:21 PM PDT 24
Peak memory 242048 kb
Host smart-c4e47def-ee0a-44a3-ab7d-74c09a962791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062559730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.2062559730
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.3301798719
Short name T503
Test name
Test status
Simulation time 970874137 ps
CPU time 26.14 seconds
Started May 26 01:26:21 PM PDT 24
Finished May 26 01:26:48 PM PDT 24
Peak memory 245936 kb
Host smart-d44f64ce-0993-4ef9-83c7-2a379dda8ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301798719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.3301798719
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.3834689800
Short name T778
Test name
Test status
Simulation time 492191272 ps
CPU time 17.18 seconds
Started May 26 01:26:25 PM PDT 24
Finished May 26 01:26:42 PM PDT 24
Peak memory 241984 kb
Host smart-f4240d1a-46bf-4a0c-abbb-9c88d556d4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834689800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.3834689800
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.3897646808
Short name T939
Test name
Test status
Simulation time 971227713 ps
CPU time 8.43 seconds
Started May 26 01:26:17 PM PDT 24
Finished May 26 01:26:26 PM PDT 24
Peak memory 241928 kb
Host smart-44a387f7-9d2e-496a-ba51-b806055ef1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897646808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.3897646808
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.1079701990
Short name T493
Test name
Test status
Simulation time 7723668235 ps
CPU time 18.71 seconds
Started May 26 01:26:14 PM PDT 24
Finished May 26 01:26:34 PM PDT 24
Peak memory 241980 kb
Host smart-40bfc9af-4bcc-44c0-8e35-530bb8680c4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1079701990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.1079701990
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.3550102209
Short name T718
Test name
Test status
Simulation time 332021969 ps
CPU time 8.14 seconds
Started May 26 01:26:23 PM PDT 24
Finished May 26 01:26:32 PM PDT 24
Peak memory 248700 kb
Host smart-6915f8f1-4867-478f-961e-4d6b4aa7c00e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3550102209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.3550102209
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.3495493798
Short name T1028
Test name
Test status
Simulation time 4842754163 ps
CPU time 11.09 seconds
Started May 26 01:26:16 PM PDT 24
Finished May 26 01:26:28 PM PDT 24
Peak memory 242288 kb
Host smart-d26ccf3b-eb83-4ba6-a798-acf8e7a6d81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495493798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.3495493798
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.3740641634
Short name T1073
Test name
Test status
Simulation time 35524801919 ps
CPU time 67.22 seconds
Started May 26 01:26:23 PM PDT 24
Finished May 26 01:27:30 PM PDT 24
Peak memory 246296 kb
Host smart-72ac6cb2-d107-4107-96e9-35ad57f0727c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740641634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.3740641634
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.3627457530
Short name T749
Test name
Test status
Simulation time 1095275517 ps
CPU time 8.42 seconds
Started May 26 01:26:22 PM PDT 24
Finished May 26 01:26:31 PM PDT 24
Peak memory 242384 kb
Host smart-d2f2257e-e976-431c-8abf-d9372effec4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627457530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.3627457530
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.1101207452
Short name T615
Test name
Test status
Simulation time 103002500 ps
CPU time 3.48 seconds
Started May 26 01:32:56 PM PDT 24
Finished May 26 01:33:00 PM PDT 24
Peak memory 242064 kb
Host smart-46ffb84c-eab2-4725-acfe-d91a8e3fb451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101207452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.1101207452
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.2911745993
Short name T728
Test name
Test status
Simulation time 183509544 ps
CPU time 3.84 seconds
Started May 26 01:32:54 PM PDT 24
Finished May 26 01:32:59 PM PDT 24
Peak memory 242004 kb
Host smart-b79efd18-199a-419d-9a5e-6fa52aad1d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911745993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.2911745993
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.3274668335
Short name T188
Test name
Test status
Simulation time 227652960 ps
CPU time 3.11 seconds
Started May 26 01:32:56 PM PDT 24
Finished May 26 01:33:01 PM PDT 24
Peak memory 242384 kb
Host smart-499f575d-30db-4a08-b613-ee16d0f4682f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274668335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.3274668335
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.2819923167
Short name T788
Test name
Test status
Simulation time 157057433 ps
CPU time 5.15 seconds
Started May 26 01:32:52 PM PDT 24
Finished May 26 01:32:58 PM PDT 24
Peak memory 241984 kb
Host smart-9be91458-9e11-463a-b45e-8d7096f27a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819923167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.2819923167
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.1938421757
Short name T872
Test name
Test status
Simulation time 316188705 ps
CPU time 4.72 seconds
Started May 26 01:32:54 PM PDT 24
Finished May 26 01:33:00 PM PDT 24
Peak memory 242160 kb
Host smart-f740e1e0-362d-4bd3-9eea-79f07ef2d91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938421757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.1938421757
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.2612093184
Short name T1010
Test name
Test status
Simulation time 1175514773 ps
CPU time 23.17 seconds
Started May 26 01:32:53 PM PDT 24
Finished May 26 01:33:17 PM PDT 24
Peak memory 241952 kb
Host smart-0d2d668f-33a7-41c5-be0d-db5f5b057085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612093184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.2612093184
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.3911541237
Short name T993
Test name
Test status
Simulation time 297005840 ps
CPU time 4.74 seconds
Started May 26 01:32:55 PM PDT 24
Finished May 26 01:33:01 PM PDT 24
Peak memory 242024 kb
Host smart-a778ee3d-b98f-4c1b-bebd-e8683c360b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911541237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.3911541237
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.300706234
Short name T1181
Test name
Test status
Simulation time 102736256 ps
CPU time 3.04 seconds
Started May 26 01:32:53 PM PDT 24
Finished May 26 01:32:57 PM PDT 24
Peak memory 242060 kb
Host smart-2a5c87ce-bb81-492f-a779-a789648f443f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300706234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.300706234
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.2726612562
Short name T646
Test name
Test status
Simulation time 2228941596 ps
CPU time 5.32 seconds
Started May 26 01:32:55 PM PDT 24
Finished May 26 01:33:01 PM PDT 24
Peak memory 242236 kb
Host smart-072f2f50-c86f-46a2-99fe-e18093a8f063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726612562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.2726612562
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.3189080662
Short name T687
Test name
Test status
Simulation time 227325902 ps
CPU time 6.59 seconds
Started May 26 01:32:56 PM PDT 24
Finished May 26 01:33:03 PM PDT 24
Peak memory 241988 kb
Host smart-207b97d4-7b36-410a-85e8-a0e0993d584e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189080662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.3189080662
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.2505941500
Short name T186
Test name
Test status
Simulation time 137866814 ps
CPU time 4.18 seconds
Started May 26 01:32:58 PM PDT 24
Finished May 26 01:33:02 PM PDT 24
Peak memory 242024 kb
Host smart-7b78086d-00be-45f0-bee5-5a2de87e11cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505941500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.2505941500
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.3342822427
Short name T820
Test name
Test status
Simulation time 319282522 ps
CPU time 2.99 seconds
Started May 26 01:32:54 PM PDT 24
Finished May 26 01:32:57 PM PDT 24
Peak memory 242220 kb
Host smart-17fbff0d-b1a5-496e-b95b-906c1a55e0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342822427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.3342822427
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.3817951973
Short name T629
Test name
Test status
Simulation time 364251408 ps
CPU time 4.71 seconds
Started May 26 01:32:54 PM PDT 24
Finished May 26 01:33:00 PM PDT 24
Peak memory 242164 kb
Host smart-7ac9e11e-892d-493e-880f-903ed1451b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817951973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.3817951973
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.4243783206
Short name T1085
Test name
Test status
Simulation time 88674758 ps
CPU time 3.52 seconds
Started May 26 01:32:53 PM PDT 24
Finished May 26 01:32:57 PM PDT 24
Peak memory 241976 kb
Host smart-d5bd7022-fbb3-4874-9a02-4a2601d735d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243783206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.4243783206
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.2503546692
Short name T668
Test name
Test status
Simulation time 306334852 ps
CPU time 3.88 seconds
Started May 26 01:32:55 PM PDT 24
Finished May 26 01:33:00 PM PDT 24
Peak memory 242016 kb
Host smart-129897a6-f4b2-4ba5-b512-90ecd33e2071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503546692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.2503546692
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.2546477410
Short name T181
Test name
Test status
Simulation time 275655867 ps
CPU time 4.36 seconds
Started May 26 01:32:56 PM PDT 24
Finished May 26 01:33:01 PM PDT 24
Peak memory 241992 kb
Host smart-1cc34119-3dc1-4633-b08f-2181e9e85afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546477410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.2546477410
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.1516448
Short name T815
Test name
Test status
Simulation time 242383869 ps
CPU time 6.65 seconds
Started May 26 01:32:54 PM PDT 24
Finished May 26 01:33:01 PM PDT 24
Peak memory 241984 kb
Host smart-a3f1677a-66f2-4e1b-801b-a58ea4da533f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.1516448
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.410916592
Short name T1104
Test name
Test status
Simulation time 126214061 ps
CPU time 4.01 seconds
Started May 26 01:32:55 PM PDT 24
Finished May 26 01:33:00 PM PDT 24
Peak memory 242040 kb
Host smart-8b27f4ac-9338-49ac-8359-8954d4a841db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410916592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.410916592
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.850907655
Short name T197
Test name
Test status
Simulation time 898514479 ps
CPU time 13.79 seconds
Started May 26 01:32:55 PM PDT 24
Finished May 26 01:33:10 PM PDT 24
Peak memory 242196 kb
Host smart-df71964a-4eb2-4130-8bb6-7aad0e0e6087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850907655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.850907655
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.4137949114
Short name T1047
Test name
Test status
Simulation time 88369220 ps
CPU time 1.63 seconds
Started May 26 01:26:39 PM PDT 24
Finished May 26 01:26:41 PM PDT 24
Peak memory 240536 kb
Host smart-2a2aa3d9-8c94-410d-8f4e-ebe8872fcf65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137949114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.4137949114
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.3466460758
Short name T833
Test name
Test status
Simulation time 633755223 ps
CPU time 12.98 seconds
Started May 26 01:26:31 PM PDT 24
Finished May 26 01:26:45 PM PDT 24
Peak memory 242544 kb
Host smart-195f5f9c-9450-4bc1-8121-6158dc7d1b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466460758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.3466460758
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.3128192622
Short name T666
Test name
Test status
Simulation time 1204758378 ps
CPU time 20.32 seconds
Started May 26 01:26:32 PM PDT 24
Finished May 26 01:26:53 PM PDT 24
Peak memory 242232 kb
Host smart-4b816609-c4b1-457e-aab7-131669c4e378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128192622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.3128192622
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.2261060445
Short name T838
Test name
Test status
Simulation time 425674104 ps
CPU time 9.72 seconds
Started May 26 01:26:30 PM PDT 24
Finished May 26 01:26:41 PM PDT 24
Peak memory 242092 kb
Host smart-51036f13-6920-42f3-970d-5f9d0c0600b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261060445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.2261060445
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.2658271746
Short name T548
Test name
Test status
Simulation time 157545524 ps
CPU time 4.33 seconds
Started May 26 01:26:23 PM PDT 24
Finished May 26 01:26:28 PM PDT 24
Peak memory 242004 kb
Host smart-8ec4dabe-23a7-44f2-a8ed-5765b038ac0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658271746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.2658271746
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.2808962694
Short name T94
Test name
Test status
Simulation time 458163363 ps
CPU time 3.81 seconds
Started May 26 01:26:32 PM PDT 24
Finished May 26 01:26:37 PM PDT 24
Peak memory 242328 kb
Host smart-4d17d7c9-4ac5-4a0e-99d7-a5eba2a7156c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808962694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.2808962694
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.2161979416
Short name T1070
Test name
Test status
Simulation time 8705005375 ps
CPU time 32.86 seconds
Started May 26 01:26:32 PM PDT 24
Finished May 26 01:27:05 PM PDT 24
Peak memory 248688 kb
Host smart-8717a8cf-8d80-4e42-a862-14fe8c3900a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161979416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.2161979416
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.236748892
Short name T66
Test name
Test status
Simulation time 742595177 ps
CPU time 19.82 seconds
Started May 26 01:26:31 PM PDT 24
Finished May 26 01:26:51 PM PDT 24
Peak memory 242112 kb
Host smart-fb900e68-1237-4e90-9d89-c18a87721c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236748892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.236748892
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.1757539116
Short name T551
Test name
Test status
Simulation time 317468259 ps
CPU time 8.88 seconds
Started May 26 01:26:32 PM PDT 24
Finished May 26 01:26:41 PM PDT 24
Peak memory 248776 kb
Host smart-54b28e66-2362-401f-b002-1cd97a9c5ded
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1757539116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.1757539116
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.2936670732
Short name T452
Test name
Test status
Simulation time 176887456 ps
CPU time 5.04 seconds
Started May 26 01:26:30 PM PDT 24
Finished May 26 01:26:36 PM PDT 24
Peak memory 242072 kb
Host smart-fb72684d-5590-4be5-8313-0e381af33c75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2936670732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.2936670732
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.3970317345
Short name T451
Test name
Test status
Simulation time 428168097 ps
CPU time 6.15 seconds
Started May 26 01:26:24 PM PDT 24
Finished May 26 01:26:31 PM PDT 24
Peak memory 242096 kb
Host smart-563c33c6-a327-4430-8119-faa766130c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970317345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.3970317345
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.1663238248
Short name T932
Test name
Test status
Simulation time 38657242757 ps
CPU time 120.41 seconds
Started May 26 01:26:40 PM PDT 24
Finished May 26 01:28:41 PM PDT 24
Peak memory 248856 kb
Host smart-adfd2632-16cb-4561-af71-f59737965d5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663238248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.1663238248
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.138760136
Short name T436
Test name
Test status
Simulation time 66207229765 ps
CPU time 1272.94 seconds
Started May 26 01:26:34 PM PDT 24
Finished May 26 01:47:47 PM PDT 24
Peak memory 326500 kb
Host smart-a134489f-1ee0-490c-b85c-c9a32b097cf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138760136 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.138760136
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.878549938
Short name T1048
Test name
Test status
Simulation time 2944352411 ps
CPU time 19.17 seconds
Started May 26 01:26:32 PM PDT 24
Finished May 26 01:26:51 PM PDT 24
Peak memory 242648 kb
Host smart-57cb6908-aa4a-41ff-997a-d65350af415e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878549938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.878549938
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.1882382106
Short name T1111
Test name
Test status
Simulation time 449878387 ps
CPU time 4.32 seconds
Started May 26 01:32:54 PM PDT 24
Finished May 26 01:32:59 PM PDT 24
Peak memory 242020 kb
Host smart-bfe12c5f-df1a-4e7b-815f-08ff488faa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882382106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.1882382106
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.1017254216
Short name T1109
Test name
Test status
Simulation time 374585435 ps
CPU time 6.41 seconds
Started May 26 01:32:54 PM PDT 24
Finished May 26 01:33:02 PM PDT 24
Peak memory 241912 kb
Host smart-8bfd00e7-315d-45a6-8d2b-8706ad27b0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017254216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.1017254216
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.375027158
Short name T63
Test name
Test status
Simulation time 235743209 ps
CPU time 4.02 seconds
Started May 26 01:32:58 PM PDT 24
Finished May 26 01:33:02 PM PDT 24
Peak memory 242264 kb
Host smart-d50b7bc3-d2c1-48fd-8e32-9066d513a79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375027158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.375027158
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.2354191256
Short name T844
Test name
Test status
Simulation time 400616720 ps
CPU time 5.93 seconds
Started May 26 01:33:03 PM PDT 24
Finished May 26 01:33:10 PM PDT 24
Peak memory 242460 kb
Host smart-26e2b8ff-52a5-47b7-90f8-6b85c712b86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354191256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.2354191256
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.3024995569
Short name T1060
Test name
Test status
Simulation time 242790611 ps
CPU time 5.78 seconds
Started May 26 01:32:56 PM PDT 24
Finished May 26 01:33:03 PM PDT 24
Peak memory 242088 kb
Host smart-36f36aef-ca69-48c7-a535-8b4aeaaed67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024995569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.3024995569
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.3128979501
Short name T836
Test name
Test status
Simulation time 494267708 ps
CPU time 13.12 seconds
Started May 26 01:32:58 PM PDT 24
Finished May 26 01:33:12 PM PDT 24
Peak memory 242016 kb
Host smart-3578e752-5f1f-42cb-834a-525372f23004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128979501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.3128979501
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.641399190
Short name T860
Test name
Test status
Simulation time 95019075 ps
CPU time 3.43 seconds
Started May 26 01:32:54 PM PDT 24
Finished May 26 01:32:59 PM PDT 24
Peak memory 241988 kb
Host smart-07e5430c-4e38-4d41-b153-734c4a24e72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641399190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.641399190
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.2691040152
Short name T92
Test name
Test status
Simulation time 471424807 ps
CPU time 4.39 seconds
Started May 26 01:33:03 PM PDT 24
Finished May 26 01:33:08 PM PDT 24
Peak memory 242292 kb
Host smart-c7b52aac-e299-4373-a672-f728bd633b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691040152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.2691040152
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.148869140
Short name T41
Test name
Test status
Simulation time 1688789223 ps
CPU time 5.53 seconds
Started May 26 01:33:09 PM PDT 24
Finished May 26 01:33:15 PM PDT 24
Peak memory 242016 kb
Host smart-07535f4c-1ae9-4c99-b9b3-51b1f5650131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148869140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.148869140
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.1000612870
Short name T887
Test name
Test status
Simulation time 347176240 ps
CPU time 5.05 seconds
Started May 26 01:33:03 PM PDT 24
Finished May 26 01:33:09 PM PDT 24
Peak memory 242408 kb
Host smart-06023344-2585-4ecb-820a-bd26e97e2fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000612870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.1000612870
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.2880977981
Short name T70
Test name
Test status
Simulation time 463183076 ps
CPU time 3.21 seconds
Started May 26 01:33:02 PM PDT 24
Finished May 26 01:33:07 PM PDT 24
Peak memory 242128 kb
Host smart-137aa9ad-b80f-444e-9447-0f6e1f163bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880977981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.2880977981
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.1670678693
Short name T532
Test name
Test status
Simulation time 1677756151 ps
CPU time 4.74 seconds
Started May 26 01:33:03 PM PDT 24
Finished May 26 01:33:09 PM PDT 24
Peak memory 241984 kb
Host smart-d638684b-ea07-41ad-8e47-fe81e4d2aebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670678693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.1670678693
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.2513310841
Short name T1007
Test name
Test status
Simulation time 1881798273 ps
CPU time 5.68 seconds
Started May 26 01:33:01 PM PDT 24
Finished May 26 01:33:07 PM PDT 24
Peak memory 242056 kb
Host smart-f6825a3d-857c-4e39-9648-f7872c31a535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513310841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.2513310841
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.1302024648
Short name T387
Test name
Test status
Simulation time 638918087 ps
CPU time 7.71 seconds
Started May 26 01:33:02 PM PDT 24
Finished May 26 01:33:10 PM PDT 24
Peak memory 241888 kb
Host smart-0c571357-efe5-4961-a6b5-38da8087d97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302024648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.1302024648
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.1007397993
Short name T857
Test name
Test status
Simulation time 116776858 ps
CPU time 4.4 seconds
Started May 26 01:32:59 PM PDT 24
Finished May 26 01:33:04 PM PDT 24
Peak memory 241872 kb
Host smart-a03a0233-9ccc-4382-900e-15db20b65548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007397993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.1007397993
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.3838207667
Short name T644
Test name
Test status
Simulation time 651689041 ps
CPU time 6.32 seconds
Started May 26 01:33:03 PM PDT 24
Finished May 26 01:33:10 PM PDT 24
Peak memory 242052 kb
Host smart-5f8188c7-6e0d-42ff-a9c4-7382468ea19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838207667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.3838207667
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.3482755874
Short name T1077
Test name
Test status
Simulation time 1767551725 ps
CPU time 6.93 seconds
Started May 26 01:33:04 PM PDT 24
Finished May 26 01:33:12 PM PDT 24
Peak memory 242092 kb
Host smart-ac3bb09c-4394-41ac-a2f4-a58b2d205d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482755874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.3482755874
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.2323917130
Short name T1075
Test name
Test status
Simulation time 3357246539 ps
CPU time 13.45 seconds
Started May 26 01:33:03 PM PDT 24
Finished May 26 01:33:17 PM PDT 24
Peak memory 242032 kb
Host smart-7c07715c-c3d8-485c-b472-193609ea0960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323917130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.2323917130
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.2517265716
Short name T961
Test name
Test status
Simulation time 404088707 ps
CPU time 5.13 seconds
Started May 26 01:33:03 PM PDT 24
Finished May 26 01:33:09 PM PDT 24
Peak memory 242276 kb
Host smart-22019a73-aac4-4e11-9a24-b461e192dadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517265716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.2517265716
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.4017479219
Short name T1049
Test name
Test status
Simulation time 50611460 ps
CPU time 1.78 seconds
Started May 26 01:26:50 PM PDT 24
Finished May 26 01:26:53 PM PDT 24
Peak memory 240612 kb
Host smart-147981c0-4541-4953-8d6c-1b01b2903106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017479219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.4017479219
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.3022419247
Short name T422
Test name
Test status
Simulation time 14461381323 ps
CPU time 25.25 seconds
Started May 26 01:26:42 PM PDT 24
Finished May 26 01:27:08 PM PDT 24
Peak memory 242248 kb
Host smart-fbd87755-40a6-4ece-85ef-8d7e05893ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022419247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.3022419247
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.1304230895
Short name T1150
Test name
Test status
Simulation time 256731166 ps
CPU time 12.1 seconds
Started May 26 01:26:38 PM PDT 24
Finished May 26 01:26:51 PM PDT 24
Peak memory 242136 kb
Host smart-7f50a317-fea0-48e4-9fc8-0a948be253ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304230895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.1304230895
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.3434517079
Short name T498
Test name
Test status
Simulation time 2542416218 ps
CPU time 23.75 seconds
Started May 26 01:26:40 PM PDT 24
Finished May 26 01:27:05 PM PDT 24
Peak memory 242312 kb
Host smart-1b84b7f8-5918-41df-bc4b-32fcafb87302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434517079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.3434517079
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.895033484
Short name T1052
Test name
Test status
Simulation time 213474910 ps
CPU time 4.38 seconds
Started May 26 01:26:41 PM PDT 24
Finished May 26 01:26:46 PM PDT 24
Peak memory 242376 kb
Host smart-9124bc90-cf0d-42ea-a816-9f9f8b54bf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895033484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.895033484
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.1741040815
Short name T501
Test name
Test status
Simulation time 1537656305 ps
CPU time 19.83 seconds
Started May 26 01:26:40 PM PDT 24
Finished May 26 01:27:01 PM PDT 24
Peak memory 244856 kb
Host smart-10aa976d-c69a-4106-9bcf-bbfea1398f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741040815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.1741040815
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.455034359
Short name T1117
Test name
Test status
Simulation time 4999836905 ps
CPU time 16.23 seconds
Started May 26 01:26:40 PM PDT 24
Finished May 26 01:26:56 PM PDT 24
Peak memory 242004 kb
Host smart-13cd3b57-9dcd-478f-b89c-41c240373af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455034359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.455034359
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.3860794885
Short name T982
Test name
Test status
Simulation time 209805351 ps
CPU time 5.87 seconds
Started May 26 01:26:41 PM PDT 24
Finished May 26 01:26:47 PM PDT 24
Peak memory 242204 kb
Host smart-366306db-6c55-4761-bdd2-e06dcc81c915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860794885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.3860794885
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.3128631349
Short name T472
Test name
Test status
Simulation time 638288722 ps
CPU time 6.38 seconds
Started May 26 01:26:41 PM PDT 24
Finished May 26 01:26:48 PM PDT 24
Peak memory 242180 kb
Host smart-c419f2c3-c7e2-496d-ad80-bc36a8217dea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3128631349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.3128631349
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.4106276254
Short name T239
Test name
Test status
Simulation time 2289752559 ps
CPU time 7.3 seconds
Started May 26 01:26:40 PM PDT 24
Finished May 26 01:26:48 PM PDT 24
Peak memory 242400 kb
Host smart-acf6f341-0fe8-44d6-aa90-45eda6fbc6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106276254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.4106276254
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.3528111201
Short name T15
Test name
Test status
Simulation time 1311468751332 ps
CPU time 3735.94 seconds
Started May 26 01:26:49 PM PDT 24
Finished May 26 02:29:06 PM PDT 24
Peak memory 344040 kb
Host smart-c24efeb6-749a-4601-a9d4-b899c6eea06f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528111201 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.3528111201
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.4269646973
Short name T192
Test name
Test status
Simulation time 138855109 ps
CPU time 4.49 seconds
Started May 26 01:26:48 PM PDT 24
Finished May 26 01:26:53 PM PDT 24
Peak memory 242152 kb
Host smart-cb13018c-61d9-4238-9137-2c5cf79abc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269646973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.4269646973
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.4243768997
Short name T732
Test name
Test status
Simulation time 1632177163 ps
CPU time 5.29 seconds
Started May 26 01:33:02 PM PDT 24
Finished May 26 01:33:09 PM PDT 24
Peak memory 242168 kb
Host smart-54b13d9c-ac20-4050-ba52-1db1433a83d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243768997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.4243768997
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.2593699232
Short name T1019
Test name
Test status
Simulation time 234209442 ps
CPU time 13.64 seconds
Started May 26 01:33:10 PM PDT 24
Finished May 26 01:33:24 PM PDT 24
Peak memory 242260 kb
Host smart-6aa80883-235d-4a52-9f43-97673cf14664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593699232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.2593699232
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.3234522747
Short name T504
Test name
Test status
Simulation time 475648976 ps
CPU time 4.12 seconds
Started May 26 01:33:04 PM PDT 24
Finished May 26 01:33:09 PM PDT 24
Peak memory 242068 kb
Host smart-efb99e34-e0d3-45e8-92a4-fa69ae6a8d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234522747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.3234522747
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.1815796258
Short name T1009
Test name
Test status
Simulation time 745962822 ps
CPU time 10.77 seconds
Started May 26 01:33:09 PM PDT 24
Finished May 26 01:33:20 PM PDT 24
Peak memory 242336 kb
Host smart-69442b5b-5580-4d31-9fc1-92c905a3bf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815796258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.1815796258
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.619454240
Short name T183
Test name
Test status
Simulation time 230792866 ps
CPU time 2.84 seconds
Started May 26 01:33:06 PM PDT 24
Finished May 26 01:33:09 PM PDT 24
Peak memory 242176 kb
Host smart-361abbb0-0136-4243-aa96-3236d1d3df4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619454240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.619454240
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.3956296237
Short name T1174
Test name
Test status
Simulation time 323215634 ps
CPU time 10.04 seconds
Started May 26 01:33:02 PM PDT 24
Finished May 26 01:33:12 PM PDT 24
Peak memory 241912 kb
Host smart-399e14e1-2a77-4d7b-806c-17906c0bb1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956296237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.3956296237
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.3230342087
Short name T457
Test name
Test status
Simulation time 9983682287 ps
CPU time 19.65 seconds
Started May 26 01:33:06 PM PDT 24
Finished May 26 01:33:26 PM PDT 24
Peak memory 242244 kb
Host smart-70389811-f679-4cef-9ad6-308e3fba5d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230342087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.3230342087
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.3354850162
Short name T220
Test name
Test status
Simulation time 1987074695 ps
CPU time 6.35 seconds
Started May 26 01:33:03 PM PDT 24
Finished May 26 01:33:10 PM PDT 24
Peak memory 242128 kb
Host smart-7fa6b639-c2ae-4baf-b442-dd611b9af71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354850162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.3354850162
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.3361989177
Short name T959
Test name
Test status
Simulation time 407120610 ps
CPU time 10.08 seconds
Started May 26 01:33:03 PM PDT 24
Finished May 26 01:33:14 PM PDT 24
Peak memory 241996 kb
Host smart-d3ff57cc-1ca5-4137-8be4-96fc1c6e5b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361989177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.3361989177
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.4042675839
Short name T685
Test name
Test status
Simulation time 134004515 ps
CPU time 3.82 seconds
Started May 26 01:33:05 PM PDT 24
Finished May 26 01:33:09 PM PDT 24
Peak memory 242412 kb
Host smart-94117e08-4503-4894-8e3a-d8f9c1fc6045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042675839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.4042675839
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.1576978087
Short name T1153
Test name
Test status
Simulation time 173212986 ps
CPU time 4.98 seconds
Started May 26 01:33:12 PM PDT 24
Finished May 26 01:33:18 PM PDT 24
Peak memory 247456 kb
Host smart-9b859d5f-4a9e-4ad0-a794-74e93b0811b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576978087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.1576978087
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.4210222798
Short name T573
Test name
Test status
Simulation time 255397557 ps
CPU time 3.78 seconds
Started May 26 01:33:10 PM PDT 24
Finished May 26 01:33:16 PM PDT 24
Peak memory 242148 kb
Host smart-193f50d8-755f-4a38-9ef9-78d14f2f6cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210222798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.4210222798
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.3266933553
Short name T796
Test name
Test status
Simulation time 179948621 ps
CPU time 4.35 seconds
Started May 26 01:33:10 PM PDT 24
Finished May 26 01:33:15 PM PDT 24
Peak memory 242004 kb
Host smart-7c6025fc-417d-437b-b822-e898457386e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266933553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.3266933553
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.91571853
Short name T306
Test name
Test status
Simulation time 570717827 ps
CPU time 3.94 seconds
Started May 26 01:33:11 PM PDT 24
Finished May 26 01:33:16 PM PDT 24
Peak memory 242052 kb
Host smart-c5547587-aacf-4ae1-adae-1b13cbb32b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91571853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.91571853
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.2927441465
Short name T1122
Test name
Test status
Simulation time 997903679 ps
CPU time 28.48 seconds
Started May 26 01:33:11 PM PDT 24
Finished May 26 01:33:41 PM PDT 24
Peak memory 242076 kb
Host smart-58ac087f-8547-4eff-85db-df1a07be45c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927441465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2927441465
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.822528285
Short name T1000
Test name
Test status
Simulation time 153259815 ps
CPU time 3 seconds
Started May 26 01:33:11 PM PDT 24
Finished May 26 01:33:15 PM PDT 24
Peak memory 242204 kb
Host smart-947fe16e-4082-4439-ae16-c5f9afbbc792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822528285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.822528285
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.3901437581
Short name T442
Test name
Test status
Simulation time 6570304252 ps
CPU time 12.96 seconds
Started May 26 01:33:15 PM PDT 24
Finished May 26 01:33:29 PM PDT 24
Peak memory 242116 kb
Host smart-fe1a1b4a-010f-42da-8f96-e09cb1c2f93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901437581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.3901437581
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.3294169663
Short name T93
Test name
Test status
Simulation time 149859382 ps
CPU time 1.68 seconds
Started May 26 01:24:54 PM PDT 24
Finished May 26 01:24:56 PM PDT 24
Peak memory 240868 kb
Host smart-7d48a284-ba72-4794-8239-3fb16269ea94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294169663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.3294169663
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.832715758
Short name T1107
Test name
Test status
Simulation time 10402203371 ps
CPU time 20.77 seconds
Started May 26 01:24:39 PM PDT 24
Finished May 26 01:25:00 PM PDT 24
Peak memory 248820 kb
Host smart-1c6e5c85-dba7-4926-b7ba-1f66a70bb094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832715758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.832715758
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.4290267690
Short name T45
Test name
Test status
Simulation time 790984314 ps
CPU time 10.66 seconds
Started May 26 01:24:44 PM PDT 24
Finished May 26 01:24:55 PM PDT 24
Peak memory 242264 kb
Host smart-56077aa9-29fd-466e-8b06-7df097ec3364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290267690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.4290267690
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.386047693
Short name T390
Test name
Test status
Simulation time 1201334463 ps
CPU time 10.45 seconds
Started May 26 01:24:38 PM PDT 24
Finished May 26 01:24:49 PM PDT 24
Peak memory 242004 kb
Host smart-58b8e006-8412-4a4e-8d61-2206312aed8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386047693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.386047693
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.2401866010
Short name T1023
Test name
Test status
Simulation time 628017369 ps
CPU time 11.77 seconds
Started May 26 01:24:38 PM PDT 24
Finished May 26 01:24:51 PM PDT 24
Peak memory 248764 kb
Host smart-87e864cf-a28b-459f-b378-13792e9b56db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401866010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.2401866010
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.695085573
Short name T1139
Test name
Test status
Simulation time 149595493 ps
CPU time 5.12 seconds
Started May 26 01:24:38 PM PDT 24
Finished May 26 01:24:44 PM PDT 24
Peak memory 242396 kb
Host smart-99a1acb5-1db7-4427-8341-5747b5824ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695085573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.695085573
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.918989623
Short name T818
Test name
Test status
Simulation time 324874276 ps
CPU time 8.22 seconds
Started May 26 01:24:45 PM PDT 24
Finished May 26 01:24:54 PM PDT 24
Peak memory 241964 kb
Host smart-e0361058-e0db-4e01-855b-ad839a6b65df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918989623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.918989623
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.2707823267
Short name T1160
Test name
Test status
Simulation time 2147299762 ps
CPU time 6.65 seconds
Started May 26 01:24:48 PM PDT 24
Finished May 26 01:24:55 PM PDT 24
Peak memory 241880 kb
Host smart-598bfef6-0054-43a6-b067-07b402ca7e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707823267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.2707823267
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.1417973526
Short name T261
Test name
Test status
Simulation time 702353055 ps
CPU time 9.19 seconds
Started May 26 01:24:40 PM PDT 24
Finished May 26 01:24:50 PM PDT 24
Peak memory 241956 kb
Host smart-9dce80c0-98d6-422a-b772-4b35d865f7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417973526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.1417973526
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.525450157
Short name T453
Test name
Test status
Simulation time 1300737889 ps
CPU time 10.09 seconds
Started May 26 01:24:36 PM PDT 24
Finished May 26 01:24:46 PM PDT 24
Peak memory 242000 kb
Host smart-ebaad625-ec77-44f4-8683-3f41d7d2585c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=525450157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.525450157
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.4044523019
Short name T355
Test name
Test status
Simulation time 517171206 ps
CPU time 5.8 seconds
Started May 26 01:24:45 PM PDT 24
Finished May 26 01:24:52 PM PDT 24
Peak memory 242320 kb
Host smart-5bf0717d-fe2e-4d2a-82d7-b62f1c06e8d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4044523019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.4044523019
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.3530504313
Short name T1176
Test name
Test status
Simulation time 500130952 ps
CPU time 4.83 seconds
Started May 26 01:24:40 PM PDT 24
Finished May 26 01:24:46 PM PDT 24
Peak memory 241956 kb
Host smart-fc407c68-62d5-4c13-8d12-0d32663f2e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530504313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.3530504313
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.1411650007
Short name T791
Test name
Test status
Simulation time 94944870846 ps
CPU time 1414.82 seconds
Started May 26 01:24:45 PM PDT 24
Finished May 26 01:48:20 PM PDT 24
Peak memory 307236 kb
Host smart-6cd0a2b3-5235-4e66-99b5-1e9212534a3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411650007 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.1411650007
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.412568910
Short name T899
Test name
Test status
Simulation time 5121367769 ps
CPU time 40.2 seconds
Started May 26 01:24:49 PM PDT 24
Finished May 26 01:25:29 PM PDT 24
Peak memory 242692 kb
Host smart-81fd447d-14c2-41bb-9b24-dc229a3e9bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412568910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.412568910
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.1087947764
Short name T843
Test name
Test status
Simulation time 76264691 ps
CPU time 2.28 seconds
Started May 26 01:26:57 PM PDT 24
Finished May 26 01:27:00 PM PDT 24
Peak memory 240604 kb
Host smart-27923ae4-29da-4807-9ea5-979428e57858
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087947764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.1087947764
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.2883406447
Short name T39
Test name
Test status
Simulation time 916511378 ps
CPU time 15.07 seconds
Started May 26 01:26:47 PM PDT 24
Finished May 26 01:27:03 PM PDT 24
Peak memory 241912 kb
Host smart-446956d6-8ab6-413c-88e7-fc3083077403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883406447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.2883406447
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.2805528887
Short name T662
Test name
Test status
Simulation time 562824051 ps
CPU time 19.63 seconds
Started May 26 01:26:47 PM PDT 24
Finished May 26 01:27:07 PM PDT 24
Peak memory 242024 kb
Host smart-ddfadee4-0bec-49f6-86bc-3e212ed2aad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805528887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.2805528887
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.3905027276
Short name T96
Test name
Test status
Simulation time 11764103812 ps
CPU time 44.94 seconds
Started May 26 01:26:47 PM PDT 24
Finished May 26 01:27:33 PM PDT 24
Peak memory 243448 kb
Host smart-45271882-ffc1-4b0e-b864-f1131c733907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905027276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.3905027276
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.3174118556
Short name T445
Test name
Test status
Simulation time 154691175 ps
CPU time 4.4 seconds
Started May 26 01:26:48 PM PDT 24
Finished May 26 01:26:53 PM PDT 24
Peak memory 241932 kb
Host smart-0e291ae6-7435-44b8-89af-df76a4aab74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174118556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.3174118556
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.1476544201
Short name T1032
Test name
Test status
Simulation time 2672143018 ps
CPU time 19.45 seconds
Started May 26 01:27:28 PM PDT 24
Finished May 26 01:27:48 PM PDT 24
Peak memory 246200 kb
Host smart-5eaec9d4-cefc-4b01-bf85-9e53195a4127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476544201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.1476544201
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.612010076
Short name T206
Test name
Test status
Simulation time 989615111 ps
CPU time 33.2 seconds
Started May 26 01:26:48 PM PDT 24
Finished May 26 01:27:22 PM PDT 24
Peak memory 242504 kb
Host smart-3f4a2bad-4b90-4a99-8bb8-ce607475c4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612010076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.612010076
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.135709996
Short name T607
Test name
Test status
Simulation time 130862250 ps
CPU time 3.76 seconds
Started May 26 01:26:48 PM PDT 24
Finished May 26 01:26:53 PM PDT 24
Peak memory 242340 kb
Host smart-d722900e-268b-4072-8df8-97955e2bf19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135709996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.135709996
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.3267331495
Short name T650
Test name
Test status
Simulation time 8943177860 ps
CPU time 31.5 seconds
Started May 26 01:26:49 PM PDT 24
Finished May 26 01:27:21 PM PDT 24
Peak memory 242072 kb
Host smart-85c47c1f-0b80-4edc-9f28-64c452796f6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3267331495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.3267331495
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.448266669
Short name T352
Test name
Test status
Simulation time 251674022 ps
CPU time 4.9 seconds
Started May 26 01:26:50 PM PDT 24
Finished May 26 01:26:55 PM PDT 24
Peak memory 248792 kb
Host smart-aae3d84f-adb2-493f-a451-1c75abbd4026
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448266669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.448266669
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.693880006
Short name T867
Test name
Test status
Simulation time 960113670 ps
CPU time 12.24 seconds
Started May 26 01:26:48 PM PDT 24
Finished May 26 01:27:01 PM PDT 24
Peak memory 242092 kb
Host smart-1b283290-f734-477b-bc37-c7b7fa28fc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693880006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.693880006
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.820403153
Short name T255
Test name
Test status
Simulation time 22655031443 ps
CPU time 351.56 seconds
Started May 26 01:26:49 PM PDT 24
Finished May 26 01:32:41 PM PDT 24
Peak memory 289848 kb
Host smart-f7997ad5-9ef0-4618-9616-cc0d61a0b93d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820403153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.
820403153
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.1819424056
Short name T862
Test name
Test status
Simulation time 6323049571 ps
CPU time 43.2 seconds
Started May 26 01:26:51 PM PDT 24
Finished May 26 01:27:35 PM PDT 24
Peak memory 248756 kb
Host smart-d8fa7d1a-2245-4970-9537-82118e0ddf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819424056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.1819424056
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.3260424248
Short name T690
Test name
Test status
Simulation time 293703994 ps
CPU time 4.41 seconds
Started May 26 01:33:14 PM PDT 24
Finished May 26 01:33:19 PM PDT 24
Peak memory 242328 kb
Host smart-298fe84e-b808-4510-87a6-dec803c80672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260424248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.3260424248
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.2342313123
Short name T418
Test name
Test status
Simulation time 215865920 ps
CPU time 4.42 seconds
Started May 26 01:33:08 PM PDT 24
Finished May 26 01:33:13 PM PDT 24
Peak memory 242028 kb
Host smart-f78eebfd-e3a1-406a-8855-0f6f5316cf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342313123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.2342313123
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.1196589072
Short name T520
Test name
Test status
Simulation time 483254223 ps
CPU time 4.18 seconds
Started May 26 01:33:10 PM PDT 24
Finished May 26 01:33:16 PM PDT 24
Peak memory 242060 kb
Host smart-c4a50239-bc30-4213-b334-5b39dd32f3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196589072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.1196589072
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.787235078
Short name T454
Test name
Test status
Simulation time 318441670 ps
CPU time 3.89 seconds
Started May 26 01:33:17 PM PDT 24
Finished May 26 01:33:22 PM PDT 24
Peak memory 242276 kb
Host smart-0ade58c2-ae40-4a99-a5e6-40b2b046965b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787235078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.787235078
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.3719292249
Short name T566
Test name
Test status
Simulation time 163684614 ps
CPU time 3.97 seconds
Started May 26 01:33:13 PM PDT 24
Finished May 26 01:33:17 PM PDT 24
Peak memory 242324 kb
Host smart-5b63ad7a-5af8-44e4-891c-8a9625b80163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719292249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.3719292249
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.1812853704
Short name T60
Test name
Test status
Simulation time 163997354 ps
CPU time 4.17 seconds
Started May 26 01:33:10 PM PDT 24
Finished May 26 01:33:16 PM PDT 24
Peak memory 241940 kb
Host smart-7d153c03-e63b-415b-ade4-1190c445d031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812853704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.1812853704
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.702701742
Short name T539
Test name
Test status
Simulation time 2111755722 ps
CPU time 5 seconds
Started May 26 01:33:16 PM PDT 24
Finished May 26 01:33:22 PM PDT 24
Peak memory 242132 kb
Host smart-dcb0e698-e7ea-4f0b-bcdc-9bb5242d8296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702701742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.702701742
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.2654562277
Short name T874
Test name
Test status
Simulation time 144245958 ps
CPU time 4.72 seconds
Started May 26 01:33:18 PM PDT 24
Finished May 26 01:33:24 PM PDT 24
Peak memory 242408 kb
Host smart-1dbf02e4-d484-435d-9ff6-464d925aaaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654562277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.2654562277
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.2123195571
Short name T446
Test name
Test status
Simulation time 252630765 ps
CPU time 3.76 seconds
Started May 26 01:33:20 PM PDT 24
Finished May 26 01:33:25 PM PDT 24
Peak memory 242152 kb
Host smart-a88fd9df-80f4-4f3f-bec0-b3939d3a3ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123195571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.2123195571
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.166718100
Short name T1002
Test name
Test status
Simulation time 2402524437 ps
CPU time 7.27 seconds
Started May 26 01:33:19 PM PDT 24
Finished May 26 01:33:27 PM PDT 24
Peak memory 242108 kb
Host smart-fd7137cd-0256-41b2-81aa-d1ed24a0b4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166718100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.166718100
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.1349394709
Short name T385
Test name
Test status
Simulation time 144787345 ps
CPU time 2.31 seconds
Started May 26 01:27:06 PM PDT 24
Finished May 26 01:27:09 PM PDT 24
Peak memory 240620 kb
Host smart-70da49ce-164d-448c-b3f9-994b55f8e9f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349394709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.1349394709
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.516523498
Short name T113
Test name
Test status
Simulation time 1740008245 ps
CPU time 39.12 seconds
Started May 26 01:26:56 PM PDT 24
Finished May 26 01:27:36 PM PDT 24
Peak memory 248796 kb
Host smart-af1593bf-21a5-415a-8cd9-00780e5d5e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516523498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.516523498
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.614452026
Short name T508
Test name
Test status
Simulation time 793695237 ps
CPU time 13.17 seconds
Started May 26 01:26:59 PM PDT 24
Finished May 26 01:27:13 PM PDT 24
Peak memory 242092 kb
Host smart-6d5d4d5e-1b01-4b53-9a63-30fa4ff167ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614452026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.614452026
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.1433204862
Short name T756
Test name
Test status
Simulation time 3341873214 ps
CPU time 34.52 seconds
Started May 26 01:26:55 PM PDT 24
Finished May 26 01:27:31 PM PDT 24
Peak memory 242472 kb
Host smart-b9299841-e47f-4a2a-83f3-f95264ab4787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433204862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.1433204862
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.3060567544
Short name T87
Test name
Test status
Simulation time 192669748 ps
CPU time 3.6 seconds
Started May 26 01:26:58 PM PDT 24
Finished May 26 01:27:02 PM PDT 24
Peak memory 242048 kb
Host smart-b6d0c8f4-ea1e-4a06-b590-a98b51781a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060567544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.3060567544
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.540793686
Short name T162
Test name
Test status
Simulation time 1357965131 ps
CPU time 25.41 seconds
Started May 26 01:26:57 PM PDT 24
Finished May 26 01:27:23 PM PDT 24
Peak memory 246148 kb
Host smart-d087be92-21ec-4ff0-9948-55e129fe9f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540793686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.540793686
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.1832818565
Short name T779
Test name
Test status
Simulation time 3983940253 ps
CPU time 36.67 seconds
Started May 26 01:26:56 PM PDT 24
Finished May 26 01:27:33 PM PDT 24
Peak memory 248772 kb
Host smart-8647d852-d4e5-4712-8f52-2ebd0ff2be5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832818565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.1832818565
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.4035028934
Short name T960
Test name
Test status
Simulation time 10512389069 ps
CPU time 27.28 seconds
Started May 26 01:26:56 PM PDT 24
Finished May 26 01:27:24 PM PDT 24
Peak memory 241924 kb
Host smart-e0a64bcf-edaa-4b8a-b01a-36fa0e8baffe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4035028934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.4035028934
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.1084170328
Short name T1069
Test name
Test status
Simulation time 6349160062 ps
CPU time 9.93 seconds
Started May 26 01:26:58 PM PDT 24
Finished May 26 01:27:09 PM PDT 24
Peak memory 241972 kb
Host smart-a097cc92-6609-4a2d-b3be-de3e834041ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084170328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.1084170328
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.2277506446
Short name T11
Test name
Test status
Simulation time 490860226550 ps
CPU time 1339.78 seconds
Started May 26 01:27:08 PM PDT 24
Finished May 26 01:49:28 PM PDT 24
Peak memory 271160 kb
Host smart-64d63279-23fa-40a8-88aa-4b8fd27aab63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277506446 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.2277506446
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.782560587
Short name T276
Test name
Test status
Simulation time 2537170525 ps
CPU time 6.82 seconds
Started May 26 01:27:04 PM PDT 24
Finished May 26 01:27:12 PM PDT 24
Peak memory 241856 kb
Host smart-a841c665-21bf-4d1a-91fc-3a144f8ca3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782560587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.782560587
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.1558582846
Short name T919
Test name
Test status
Simulation time 558699998 ps
CPU time 3.83 seconds
Started May 26 01:33:22 PM PDT 24
Finished May 26 01:33:26 PM PDT 24
Peak memory 242088 kb
Host smart-d14dddb3-a3cf-4d0f-b3d8-bc2bf96c4bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558582846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.1558582846
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.1758921502
Short name T747
Test name
Test status
Simulation time 1588358047 ps
CPU time 5.65 seconds
Started May 26 01:33:20 PM PDT 24
Finished May 26 01:33:27 PM PDT 24
Peak memory 241944 kb
Host smart-5dd764c6-3154-494f-900e-1c8207776ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758921502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.1758921502
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.1199679019
Short name T191
Test name
Test status
Simulation time 537912296 ps
CPU time 4.14 seconds
Started May 26 01:33:20 PM PDT 24
Finished May 26 01:33:25 PM PDT 24
Peak memory 242060 kb
Host smart-997de2fb-ed5e-475d-b83b-ae3ce7f6851f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199679019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.1199679019
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.4258055862
Short name T694
Test name
Test status
Simulation time 192243648 ps
CPU time 3.21 seconds
Started May 26 01:33:17 PM PDT 24
Finished May 26 01:33:21 PM PDT 24
Peak memory 242300 kb
Host smart-461a8a97-2857-4fdf-b83b-e21ca99bbbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258055862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.4258055862
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.1491385418
Short name T785
Test name
Test status
Simulation time 184840483 ps
CPU time 3.96 seconds
Started May 26 01:33:20 PM PDT 24
Finished May 26 01:33:25 PM PDT 24
Peak memory 242096 kb
Host smart-6e058533-223a-4401-91e0-1ba7a5f273f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491385418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.1491385418
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.3577464529
Short name T1124
Test name
Test status
Simulation time 1384885873 ps
CPU time 4.78 seconds
Started May 26 01:33:17 PM PDT 24
Finished May 26 01:33:23 PM PDT 24
Peak memory 242360 kb
Host smart-b6287dfc-04f8-4910-8c45-793be38bcfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577464529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.3577464529
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.2466710177
Short name T744
Test name
Test status
Simulation time 414126980 ps
CPU time 4.87 seconds
Started May 26 01:33:19 PM PDT 24
Finished May 26 01:33:25 PM PDT 24
Peak memory 242100 kb
Host smart-32ffcb8d-6ea7-43ed-84e1-875cc015791e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466710177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.2466710177
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.423327561
Short name T158
Test name
Test status
Simulation time 216106119 ps
CPU time 4.45 seconds
Started May 26 01:33:19 PM PDT 24
Finished May 26 01:33:25 PM PDT 24
Peak memory 242068 kb
Host smart-4e2fead8-86f1-46c5-b71e-302e22ef6140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423327561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.423327561
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.4080775916
Short name T1026
Test name
Test status
Simulation time 172516544 ps
CPU time 3.99 seconds
Started May 26 01:33:18 PM PDT 24
Finished May 26 01:33:23 PM PDT 24
Peak memory 242356 kb
Host smart-f2382b5a-f2ba-4716-9522-1f1d0ac55f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080775916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.4080775916
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.3390935859
Short name T854
Test name
Test status
Simulation time 310557427 ps
CPU time 2.27 seconds
Started May 26 01:27:13 PM PDT 24
Finished May 26 01:27:16 PM PDT 24
Peak memory 240620 kb
Host smart-6f2efb77-0cc2-43db-a75d-d95c64bc805d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390935859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.3390935859
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.2776854569
Short name T82
Test name
Test status
Simulation time 9986819909 ps
CPU time 30.47 seconds
Started May 26 01:27:05 PM PDT 24
Finished May 26 01:27:37 PM PDT 24
Peak memory 245580 kb
Host smart-8e4cb9d5-ec35-4626-b884-2ffafbb022b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776854569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.2776854569
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.956796414
Short name T1146
Test name
Test status
Simulation time 3571365627 ps
CPU time 32.4 seconds
Started May 26 01:27:05 PM PDT 24
Finished May 26 01:27:38 PM PDT 24
Peak memory 247136 kb
Host smart-a4f4feeb-7437-4fd7-b770-4450fdbfbceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956796414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.956796414
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.2984711847
Short name T639
Test name
Test status
Simulation time 24962314443 ps
CPU time 55.51 seconds
Started May 26 01:27:04 PM PDT 24
Finished May 26 01:28:00 PM PDT 24
Peak memory 243392 kb
Host smart-7c2e4c92-b069-4edb-88ad-69c54622b77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984711847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.2984711847
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.1605071952
Short name T1163
Test name
Test status
Simulation time 249547048 ps
CPU time 4.78 seconds
Started May 26 01:27:06 PM PDT 24
Finished May 26 01:27:12 PM PDT 24
Peak memory 241936 kb
Host smart-a41c202d-604c-4814-9f50-3e7ba7933ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605071952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.1605071952
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.718711416
Short name T199
Test name
Test status
Simulation time 402320766 ps
CPU time 13.69 seconds
Started May 26 01:27:12 PM PDT 24
Finished May 26 01:27:26 PM PDT 24
Peak memory 243084 kb
Host smart-4119a307-d795-464f-9db4-6ec73ffeed1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718711416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.718711416
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.3867098101
Short name T1089
Test name
Test status
Simulation time 2163213914 ps
CPU time 20.09 seconds
Started May 26 01:27:13 PM PDT 24
Finished May 26 01:27:34 PM PDT 24
Peak memory 242492 kb
Host smart-c63d0174-08ef-4a3e-9d1b-5d01e579fc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867098101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.3867098101
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.2368769658
Short name T1108
Test name
Test status
Simulation time 112079201 ps
CPU time 3.86 seconds
Started May 26 01:27:04 PM PDT 24
Finished May 26 01:27:09 PM PDT 24
Peak memory 242252 kb
Host smart-553f9755-79e3-4e8d-be04-be9758e2c3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368769658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.2368769658
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.1571285274
Short name T95
Test name
Test status
Simulation time 3739794417 ps
CPU time 11.49 seconds
Started May 26 01:27:05 PM PDT 24
Finished May 26 01:27:17 PM PDT 24
Peak memory 242436 kb
Host smart-270e12d8-e016-4562-93d6-bd0654243986
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1571285274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.1571285274
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.1381199407
Short name T258
Test name
Test status
Simulation time 562662843 ps
CPU time 11.17 seconds
Started May 26 01:27:14 PM PDT 24
Finished May 26 01:27:26 PM PDT 24
Peak memory 242248 kb
Host smart-0c1feb7b-d7be-4295-94fc-1b65c7af0028
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1381199407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.1381199407
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.942406831
Short name T649
Test name
Test status
Simulation time 508206232 ps
CPU time 6.51 seconds
Started May 26 01:27:05 PM PDT 24
Finished May 26 01:27:13 PM PDT 24
Peak memory 248632 kb
Host smart-9f7b1d76-eda7-4296-ba2c-cb30e565764c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942406831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.942406831
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.2572545675
Short name T213
Test name
Test status
Simulation time 11879541329 ps
CPU time 46.91 seconds
Started May 26 01:27:11 PM PDT 24
Finished May 26 01:27:59 PM PDT 24
Peak memory 245864 kb
Host smart-655efa3b-f69a-4cb5-a1e1-1dc12d6056df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572545675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all
.2572545675
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.4244908414
Short name T512
Test name
Test status
Simulation time 66085576159 ps
CPU time 1255.64 seconds
Started May 26 01:27:12 PM PDT 24
Finished May 26 01:48:09 PM PDT 24
Peak memory 394492 kb
Host smart-e945390c-0d25-4377-b7be-f6d35b76a9d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244908414 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.4244908414
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.1763500716
Short name T1040
Test name
Test status
Simulation time 5699089741 ps
CPU time 28.14 seconds
Started May 26 01:27:15 PM PDT 24
Finished May 26 01:27:43 PM PDT 24
Peak memory 242024 kb
Host smart-d604aad3-3ad3-469c-b15c-4025ee127026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763500716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.1763500716
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.2575078518
Short name T308
Test name
Test status
Simulation time 170208069 ps
CPU time 4.14 seconds
Started May 26 01:33:20 PM PDT 24
Finished May 26 01:33:25 PM PDT 24
Peak memory 242024 kb
Host smart-191094b8-fbc7-406f-a622-90249b281eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575078518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.2575078518
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.38854008
Short name T947
Test name
Test status
Simulation time 268258471 ps
CPU time 3.64 seconds
Started May 26 01:33:18 PM PDT 24
Finished May 26 01:33:23 PM PDT 24
Peak memory 242352 kb
Host smart-83683eb1-fce8-424c-85c5-6867f6907445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38854008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.38854008
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.1806728668
Short name T572
Test name
Test status
Simulation time 2356010257 ps
CPU time 4.72 seconds
Started May 26 01:33:17 PM PDT 24
Finished May 26 01:33:23 PM PDT 24
Peak memory 241976 kb
Host smart-d6210ded-f17e-490b-a83e-5568212abbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806728668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.1806728668
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.2714721204
Short name T1017
Test name
Test status
Simulation time 598180523 ps
CPU time 4.11 seconds
Started May 26 01:33:19 PM PDT 24
Finished May 26 01:33:24 PM PDT 24
Peak memory 242292 kb
Host smart-ca2c039c-086d-4e53-8345-3097d35b4017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714721204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.2714721204
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.3172556757
Short name T737
Test name
Test status
Simulation time 134309663 ps
CPU time 5.49 seconds
Started May 26 01:33:19 PM PDT 24
Finished May 26 01:33:25 PM PDT 24
Peak memory 242328 kb
Host smart-4b2001c7-eb6c-4aeb-ad85-0c0fad48f148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172556757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.3172556757
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.1914485562
Short name T182
Test name
Test status
Simulation time 2323710839 ps
CPU time 6.64 seconds
Started May 26 01:33:27 PM PDT 24
Finished May 26 01:33:35 PM PDT 24
Peak memory 242244 kb
Host smart-fdd46227-cdab-42e4-87b9-a611c9d01e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914485562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.1914485562
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.3599371154
Short name T938
Test name
Test status
Simulation time 157734789 ps
CPU time 4.93 seconds
Started May 26 01:33:26 PM PDT 24
Finished May 26 01:33:31 PM PDT 24
Peak memory 242004 kb
Host smart-9ad94ff2-4f64-46ec-99ae-c19b333624ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599371154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.3599371154
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.19073127
Short name T920
Test name
Test status
Simulation time 356119559 ps
CPU time 4.59 seconds
Started May 26 01:33:29 PM PDT 24
Finished May 26 01:33:34 PM PDT 24
Peak memory 242024 kb
Host smart-f5c24f4f-d7eb-4334-8987-716677190694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19073127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.19073127
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.2887178333
Short name T1046
Test name
Test status
Simulation time 515819107 ps
CPU time 4.44 seconds
Started May 26 01:33:26 PM PDT 24
Finished May 26 01:33:32 PM PDT 24
Peak memory 242176 kb
Host smart-46e0c85a-ba76-4c8b-913a-76310db9eeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887178333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.2887178333
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.3622022629
Short name T456
Test name
Test status
Simulation time 497374929 ps
CPU time 3.85 seconds
Started May 26 01:33:32 PM PDT 24
Finished May 26 01:33:36 PM PDT 24
Peak memory 242164 kb
Host smart-13c3fbe8-e9fe-4a04-bc7e-35c8c42acb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622022629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.3622022629
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.4145409534
Short name T614
Test name
Test status
Simulation time 165492227 ps
CPU time 1.58 seconds
Started May 26 01:27:21 PM PDT 24
Finished May 26 01:27:23 PM PDT 24
Peak memory 240584 kb
Host smart-bb4d7700-a839-4af2-b61d-847655a2040d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145409534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.4145409534
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.1467115340
Short name T89
Test name
Test status
Simulation time 15206710285 ps
CPU time 24.26 seconds
Started May 26 01:27:13 PM PDT 24
Finished May 26 01:27:39 PM PDT 24
Peak memory 243452 kb
Host smart-757206db-d582-4614-9a66-4a728234bacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467115340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.1467115340
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.3491959893
Short name T978
Test name
Test status
Simulation time 2413764577 ps
CPU time 19.21 seconds
Started May 26 01:27:13 PM PDT 24
Finished May 26 01:27:33 PM PDT 24
Peak memory 242408 kb
Host smart-88e65f98-95d4-4956-8578-b0b7b3274a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491959893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.3491959893
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.2912187806
Short name T364
Test name
Test status
Simulation time 2311301990 ps
CPU time 29.18 seconds
Started May 26 01:27:13 PM PDT 24
Finished May 26 01:27:43 PM PDT 24
Peak memory 242072 kb
Host smart-dfd11068-8892-41a4-81cf-3cc73f348027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912187806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.2912187806
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.3159249130
Short name T469
Test name
Test status
Simulation time 368558467 ps
CPU time 6.98 seconds
Started May 26 01:27:12 PM PDT 24
Finished May 26 01:27:20 PM PDT 24
Peak memory 242164 kb
Host smart-130ab1ba-ae76-4007-9dd1-3e0646cfa831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159249130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.3159249130
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.3424847539
Short name T406
Test name
Test status
Simulation time 3493572567 ps
CPU time 25.75 seconds
Started May 26 01:27:13 PM PDT 24
Finished May 26 01:27:40 PM PDT 24
Peak memory 242040 kb
Host smart-a22340ab-f5ec-4ac7-a5e6-512e6cbb57c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424847539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.3424847539
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.2398272607
Short name T336
Test name
Test status
Simulation time 819551523 ps
CPU time 21.77 seconds
Started May 26 01:27:14 PM PDT 24
Finished May 26 01:27:36 PM PDT 24
Peak memory 242060 kb
Host smart-eb107cf2-d549-4347-ab55-ca2f4f2a0f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398272607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.2398272607
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.1201603279
Short name T654
Test name
Test status
Simulation time 397439504 ps
CPU time 12.21 seconds
Started May 26 01:27:11 PM PDT 24
Finished May 26 01:27:23 PM PDT 24
Peak memory 248688 kb
Host smart-7516c5bc-d76c-406f-ba1a-cdeaee7e8428
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1201603279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.1201603279
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.793546591
Short name T954
Test name
Test status
Simulation time 186954554 ps
CPU time 4.06 seconds
Started May 26 01:27:14 PM PDT 24
Finished May 26 01:27:19 PM PDT 24
Peak memory 241964 kb
Host smart-2f0ccfb8-8c0e-43e2-925a-8e62510582a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=793546591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.793546591
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.236234713
Short name T1024
Test name
Test status
Simulation time 391640757 ps
CPU time 4.74 seconds
Started May 26 01:27:14 PM PDT 24
Finished May 26 01:27:20 PM PDT 24
Peak memory 242268 kb
Host smart-65219e49-9c50-449e-a55f-4bcde5994135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236234713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.236234713
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.1868326732
Short name T337
Test name
Test status
Simulation time 2392413059 ps
CPU time 28.99 seconds
Started May 26 01:27:13 PM PDT 24
Finished May 26 01:27:43 PM PDT 24
Peak memory 248868 kb
Host smart-5d2f5d03-80e4-41ed-b4ec-265a701b98e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868326732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.1868326732
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.253628705
Short name T325
Test name
Test status
Simulation time 330224343141 ps
CPU time 1192.25 seconds
Started May 26 01:27:13 PM PDT 24
Finished May 26 01:47:06 PM PDT 24
Peak memory 388092 kb
Host smart-a1cd4595-8edd-4039-a4a1-e0e23a675de8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253628705 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.253628705
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.3743057640
Short name T1138
Test name
Test status
Simulation time 672037812 ps
CPU time 5.86 seconds
Started May 26 01:27:12 PM PDT 24
Finished May 26 01:27:19 PM PDT 24
Peak memory 248444 kb
Host smart-0878ac7c-68ef-4078-8983-df8c8a5ddede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743057640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.3743057640
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.2099286883
Short name T1162
Test name
Test status
Simulation time 2356607796 ps
CPU time 5.79 seconds
Started May 26 01:33:28 PM PDT 24
Finished May 26 01:33:35 PM PDT 24
Peak memory 242076 kb
Host smart-bea69db4-deb3-490f-864a-2601edcd9804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099286883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.2099286883
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.2720812058
Short name T403
Test name
Test status
Simulation time 511978505 ps
CPU time 4.63 seconds
Started May 26 01:33:28 PM PDT 24
Finished May 26 01:33:34 PM PDT 24
Peak memory 242160 kb
Host smart-12bc86b9-33f6-4340-8818-f5f8676f345e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720812058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.2720812058
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.905078814
Short name T536
Test name
Test status
Simulation time 240212810 ps
CPU time 3.36 seconds
Started May 26 01:33:29 PM PDT 24
Finished May 26 01:33:33 PM PDT 24
Peak memory 242268 kb
Host smart-4472788b-527e-4672-a9a4-37b2b52aa277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905078814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.905078814
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.1262819421
Short name T700
Test name
Test status
Simulation time 340684312 ps
CPU time 3.46 seconds
Started May 26 01:33:28 PM PDT 24
Finished May 26 01:33:33 PM PDT 24
Peak memory 242076 kb
Host smart-d33ec01e-1caf-4093-a4c4-d65a20437ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262819421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.1262819421
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.3632250322
Short name T75
Test name
Test status
Simulation time 1384658149 ps
CPU time 5.54 seconds
Started May 26 01:33:25 PM PDT 24
Finished May 26 01:33:31 PM PDT 24
Peak memory 242020 kb
Host smart-eeadd70f-dde8-415e-812d-b5e835cc62fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632250322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.3632250322
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.165447233
Short name T460
Test name
Test status
Simulation time 166110307 ps
CPU time 4.44 seconds
Started May 26 01:33:28 PM PDT 24
Finished May 26 01:33:34 PM PDT 24
Peak memory 242264 kb
Host smart-dab0bcef-5464-4e3d-9e96-e2fc50f3ac6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165447233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.165447233
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.2963215407
Short name T54
Test name
Test status
Simulation time 198095504 ps
CPU time 4.65 seconds
Started May 26 01:33:28 PM PDT 24
Finished May 26 01:33:34 PM PDT 24
Peak memory 242532 kb
Host smart-f4311315-3fb6-47fb-b8ae-46e0395d7d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963215407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.2963215407
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.1931524004
Short name T1114
Test name
Test status
Simulation time 214749234 ps
CPU time 4.75 seconds
Started May 26 01:33:27 PM PDT 24
Finished May 26 01:33:34 PM PDT 24
Peak memory 242292 kb
Host smart-d6de48f3-9390-4949-a3bf-ea02b834916c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931524004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.1931524004
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.3855015360
Short name T1037
Test name
Test status
Simulation time 2022099523 ps
CPU time 4.88 seconds
Started May 26 01:33:27 PM PDT 24
Finished May 26 01:33:33 PM PDT 24
Peak memory 242060 kb
Host smart-9a06b8d8-4638-4617-86c3-90d2a8f9c9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855015360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.3855015360
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.84898536
Short name T969
Test name
Test status
Simulation time 105875911 ps
CPU time 1.8 seconds
Started May 26 01:27:24 PM PDT 24
Finished May 26 01:27:27 PM PDT 24
Peak memory 240636 kb
Host smart-d59a19a6-9895-4e48-a334-e09863367293
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84898536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.84898536
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.2263768114
Short name T126
Test name
Test status
Simulation time 23775870222 ps
CPU time 42.79 seconds
Started May 26 01:27:25 PM PDT 24
Finished May 26 01:28:08 PM PDT 24
Peak memory 246624 kb
Host smart-67e26683-a2a5-4cb2-947c-b9492db8c625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263768114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.2263768114
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.1822698308
Short name T1125
Test name
Test status
Simulation time 2941762105 ps
CPU time 30.43 seconds
Started May 26 01:27:24 PM PDT 24
Finished May 26 01:27:55 PM PDT 24
Peak memory 242212 kb
Host smart-05031b8f-00e1-4bb5-8e0e-1956714a2ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822698308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.1822698308
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.543445814
Short name T540
Test name
Test status
Simulation time 3095449372 ps
CPU time 26.76 seconds
Started May 26 01:27:24 PM PDT 24
Finished May 26 01:27:52 PM PDT 24
Peak memory 242060 kb
Host smart-75189f9a-f46c-414c-9046-733411d45a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543445814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.543445814
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.2392420079
Short name T514
Test name
Test status
Simulation time 142447728 ps
CPU time 3.68 seconds
Started May 26 01:27:20 PM PDT 24
Finished May 26 01:27:25 PM PDT 24
Peak memory 242084 kb
Host smart-3d7c5bd8-d1b2-48c8-a978-339e6eb99ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392420079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.2392420079
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.3300546434
Short name T912
Test name
Test status
Simulation time 1664243046 ps
CPU time 14.56 seconds
Started May 26 01:27:25 PM PDT 24
Finished May 26 01:27:40 PM PDT 24
Peak memory 242176 kb
Host smart-c45a20e5-dbf2-46b9-820e-9bd6d4e900f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300546434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.3300546434
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.691035173
Short name T918
Test name
Test status
Simulation time 480316126 ps
CPU time 13.83 seconds
Started May 26 01:27:22 PM PDT 24
Finished May 26 01:27:36 PM PDT 24
Peak memory 241956 kb
Host smart-361acae6-739e-47e3-ac97-946598796fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691035173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.691035173
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.565611462
Short name T1172
Test name
Test status
Simulation time 600177031 ps
CPU time 20.22 seconds
Started May 26 01:27:24 PM PDT 24
Finished May 26 01:27:45 PM PDT 24
Peak memory 241964 kb
Host smart-d45e4ccb-9ad0-4ec5-8716-9e9c67b7b1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565611462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.565611462
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.2603127630
Short name T753
Test name
Test status
Simulation time 13245338095 ps
CPU time 37.05 seconds
Started May 26 01:27:25 PM PDT 24
Finished May 26 01:28:03 PM PDT 24
Peak memory 241880 kb
Host smart-2b77e882-3fb1-4878-95c7-8671bd184311
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2603127630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.2603127630
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.2481114849
Short name T933
Test name
Test status
Simulation time 348445748 ps
CPU time 5.34 seconds
Started May 26 01:27:26 PM PDT 24
Finished May 26 01:27:32 PM PDT 24
Peak memory 242124 kb
Host smart-059c000a-5458-4d09-8e1a-1b27c5294903
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2481114849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.2481114849
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.191295423
Short name T578
Test name
Test status
Simulation time 886918062 ps
CPU time 8.01 seconds
Started May 26 01:27:20 PM PDT 24
Finished May 26 01:27:29 PM PDT 24
Peak memory 248532 kb
Host smart-4cf4dcd8-734c-4c60-8ff4-511e8ae281c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191295423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.191295423
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.349916294
Short name T287
Test name
Test status
Simulation time 535265370311 ps
CPU time 1119.23 seconds
Started May 26 01:27:23 PM PDT 24
Finished May 26 01:46:03 PM PDT 24
Peak memory 347296 kb
Host smart-51300145-e051-4cea-9a56-e67b4f1e7095
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349916294 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.349916294
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.2185990539
Short name T624
Test name
Test status
Simulation time 631944838 ps
CPU time 7.78 seconds
Started May 26 01:27:22 PM PDT 24
Finished May 26 01:27:30 PM PDT 24
Peak memory 248664 kb
Host smart-151db356-0528-4de9-aee5-ef8ac680ed0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185990539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.2185990539
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.2998918799
Short name T438
Test name
Test status
Simulation time 2122985569 ps
CPU time 7.7 seconds
Started May 26 01:33:27 PM PDT 24
Finished May 26 01:33:36 PM PDT 24
Peak memory 241964 kb
Host smart-bec10c54-68ee-4ba0-9299-bc00435305a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998918799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.2998918799
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.965476683
Short name T706
Test name
Test status
Simulation time 577750107 ps
CPU time 4.4 seconds
Started May 26 01:33:45 PM PDT 24
Finished May 26 01:33:50 PM PDT 24
Peak memory 242116 kb
Host smart-c0927c5d-1545-4102-9343-d021e8205bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965476683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.965476683
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.297191781
Short name T1050
Test name
Test status
Simulation time 211966288 ps
CPU time 4.88 seconds
Started May 26 01:33:37 PM PDT 24
Finished May 26 01:33:42 PM PDT 24
Peak memory 242092 kb
Host smart-af6f208f-ae97-4e7d-a7b0-105f204d6200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297191781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.297191781
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.2527657285
Short name T1187
Test name
Test status
Simulation time 273959069 ps
CPU time 4.16 seconds
Started May 26 01:33:51 PM PDT 24
Finished May 26 01:33:56 PM PDT 24
Peak memory 242424 kb
Host smart-1e8827e8-39fd-4a7c-8551-0d12dd0d9b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527657285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.2527657285
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.844231844
Short name T945
Test name
Test status
Simulation time 129964535 ps
CPU time 4.07 seconds
Started May 26 01:33:36 PM PDT 24
Finished May 26 01:33:41 PM PDT 24
Peak memory 242428 kb
Host smart-b4301040-4b0d-4728-9881-e22aa3004a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844231844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.844231844
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.1300511579
Short name T1015
Test name
Test status
Simulation time 119306611 ps
CPU time 3.67 seconds
Started May 26 01:33:34 PM PDT 24
Finished May 26 01:33:38 PM PDT 24
Peak memory 242352 kb
Host smart-a9eaee5c-b5c2-4104-b2d8-061fb199be1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300511579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.1300511579
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.2553245965
Short name T175
Test name
Test status
Simulation time 243973822 ps
CPU time 5.54 seconds
Started May 26 01:33:44 PM PDT 24
Finished May 26 01:33:50 PM PDT 24
Peak memory 242092 kb
Host smart-30d38cdb-9833-4743-8e0d-733e285b8326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553245965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.2553245965
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.4019697173
Short name T441
Test name
Test status
Simulation time 305259374 ps
CPU time 4.66 seconds
Started May 26 01:33:45 PM PDT 24
Finished May 26 01:33:51 PM PDT 24
Peak memory 242060 kb
Host smart-96028a4c-5fcf-4cc1-b075-c783adb60ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019697173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.4019697173
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.3198277135
Short name T478
Test name
Test status
Simulation time 121193808 ps
CPU time 4.59 seconds
Started May 26 01:33:44 PM PDT 24
Finished May 26 01:33:50 PM PDT 24
Peak memory 242280 kb
Host smart-6cfa744c-88dc-4d54-b3a8-b2eab597bb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198277135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.3198277135
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.131036474
Short name T423
Test name
Test status
Simulation time 73443340 ps
CPU time 2.02 seconds
Started May 26 01:27:29 PM PDT 24
Finished May 26 01:27:32 PM PDT 24
Peak memory 240560 kb
Host smart-c24349e8-17aa-4481-a6af-fa2a6c4edceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131036474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.131036474
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.1634526891
Short name T47
Test name
Test status
Simulation time 746120551 ps
CPU time 12.86 seconds
Started May 26 01:27:28 PM PDT 24
Finished May 26 01:27:42 PM PDT 24
Peak memory 242804 kb
Host smart-a4c69882-90a0-43df-9adf-daafd4b90946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634526891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.1634526891
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.83884397
Short name T1110
Test name
Test status
Simulation time 4308483113 ps
CPU time 41.11 seconds
Started May 26 01:27:29 PM PDT 24
Finished May 26 01:28:11 PM PDT 24
Peak memory 249252 kb
Host smart-355f3b11-b9fb-4d64-a716-a5f1fe36cf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83884397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.83884397
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.1787726456
Short name T1171
Test name
Test status
Simulation time 422063858 ps
CPU time 9.77 seconds
Started May 26 01:27:29 PM PDT 24
Finished May 26 01:27:40 PM PDT 24
Peak memory 242092 kb
Host smart-cd7956c0-7298-4749-b974-8692c1a6bda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787726456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.1787726456
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.2640283532
Short name T29
Test name
Test status
Simulation time 2563386837 ps
CPU time 4.69 seconds
Started May 26 01:27:29 PM PDT 24
Finished May 26 01:27:35 PM PDT 24
Peak memory 242240 kb
Host smart-d4c0a569-06a0-4d6a-879c-3ec9113665d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640283532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.2640283532
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.2145368644
Short name T713
Test name
Test status
Simulation time 2620933754 ps
CPU time 23.44 seconds
Started May 26 01:27:29 PM PDT 24
Finished May 26 01:27:53 PM PDT 24
Peak memory 242480 kb
Host smart-5eb8bd86-c4c4-4e8b-beb8-fa7e840a9c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145368644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.2145368644
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.2856728288
Short name T965
Test name
Test status
Simulation time 1200263797 ps
CPU time 22.23 seconds
Started May 26 01:27:30 PM PDT 24
Finished May 26 01:27:54 PM PDT 24
Peak memory 242016 kb
Host smart-96452d1f-3c1b-43b5-8eac-5fee64a37a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856728288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.2856728288
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.3609670418
Short name T474
Test name
Test status
Simulation time 962943407 ps
CPU time 14.58 seconds
Started May 26 01:27:30 PM PDT 24
Finished May 26 01:27:45 PM PDT 24
Peak memory 242056 kb
Host smart-542d2d6d-a99b-4e79-910a-06ccb4918efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609670418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.3609670418
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.1517978833
Short name T171
Test name
Test status
Simulation time 2008613617 ps
CPU time 7.12 seconds
Started May 26 01:27:33 PM PDT 24
Finished May 26 01:27:40 PM PDT 24
Peak memory 241916 kb
Host smart-25435f4c-ba7c-45bc-af68-2c172a9e65b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1517978833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.1517978833
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.3118862204
Short name T985
Test name
Test status
Simulation time 511886654 ps
CPU time 7.33 seconds
Started May 26 01:27:30 PM PDT 24
Finished May 26 01:27:38 PM PDT 24
Peak memory 242080 kb
Host smart-1859244a-3f64-407a-8ec9-283dc33d3006
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3118862204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.3118862204
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.3106735147
Short name T849
Test name
Test status
Simulation time 251876155 ps
CPU time 3.5 seconds
Started May 26 01:27:26 PM PDT 24
Finished May 26 01:27:30 PM PDT 24
Peak memory 247848 kb
Host smart-032989c0-7e20-40bd-a345-96eb68b43187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106735147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.3106735147
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.3048954856
Short name T889
Test name
Test status
Simulation time 5533648855 ps
CPU time 28.04 seconds
Started May 26 01:27:31 PM PDT 24
Finished May 26 01:28:00 PM PDT 24
Peak memory 244628 kb
Host smart-24f324e2-b79b-4a1f-8ca4-4dc877f5c5c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048954856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.3048954856
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.3674085462
Short name T827
Test name
Test status
Simulation time 2719015287 ps
CPU time 25.18 seconds
Started May 26 01:27:33 PM PDT 24
Finished May 26 01:27:59 PM PDT 24
Peak memory 242028 kb
Host smart-dfb158b1-6df7-45f0-b973-2e4106706bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674085462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.3674085462
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.320072086
Short name T241
Test name
Test status
Simulation time 542812826 ps
CPU time 4.73 seconds
Started May 26 01:33:34 PM PDT 24
Finished May 26 01:33:40 PM PDT 24
Peak memory 242260 kb
Host smart-0261e4f4-729b-4854-af72-1025d8d7effc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320072086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.320072086
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.1279336136
Short name T1071
Test name
Test status
Simulation time 199024327 ps
CPU time 4.52 seconds
Started May 26 01:33:51 PM PDT 24
Finished May 26 01:33:57 PM PDT 24
Peak memory 242064 kb
Host smart-2903b8e6-ec7b-4c96-9cce-285f46ea8b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279336136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.1279336136
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.620584896
Short name T651
Test name
Test status
Simulation time 1654624860 ps
CPU time 5.72 seconds
Started May 26 01:33:48 PM PDT 24
Finished May 26 01:33:54 PM PDT 24
Peak memory 242364 kb
Host smart-b5cef447-225e-4036-b5a2-2055017722a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620584896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.620584896
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.2879485510
Short name T667
Test name
Test status
Simulation time 305762911 ps
CPU time 4.05 seconds
Started May 26 01:33:51 PM PDT 24
Finished May 26 01:33:56 PM PDT 24
Peak memory 242392 kb
Host smart-788b363a-c001-4dbd-8f16-deeffc9cde80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879485510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.2879485510
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.3064143048
Short name T42
Test name
Test status
Simulation time 2083490496 ps
CPU time 6.71 seconds
Started May 26 01:33:48 PM PDT 24
Finished May 26 01:33:55 PM PDT 24
Peak memory 242100 kb
Host smart-dc1b014b-ee58-44a8-9572-3167768354bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064143048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.3064143048
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.1630078239
Short name T533
Test name
Test status
Simulation time 233130640 ps
CPU time 4.87 seconds
Started May 26 01:33:44 PM PDT 24
Finished May 26 01:33:49 PM PDT 24
Peak memory 242056 kb
Host smart-b0796134-7187-4675-a3b4-76586ff3f98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630078239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.1630078239
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.871656619
Short name T680
Test name
Test status
Simulation time 1525386818 ps
CPU time 6.04 seconds
Started May 26 01:33:48 PM PDT 24
Finished May 26 01:33:55 PM PDT 24
Peak memory 242116 kb
Host smart-8f1354b3-48d8-4b0e-a956-a799c70ec043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871656619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.871656619
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.1721894633
Short name T81
Test name
Test status
Simulation time 813468488 ps
CPU time 5.29 seconds
Started May 26 01:33:43 PM PDT 24
Finished May 26 01:33:50 PM PDT 24
Peak memory 242360 kb
Host smart-d65a488b-3837-47d6-9c83-adf4265eb332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721894633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.1721894633
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.136295354
Short name T179
Test name
Test status
Simulation time 1569056553 ps
CPU time 5.33 seconds
Started May 26 01:33:46 PM PDT 24
Finished May 26 01:33:53 PM PDT 24
Peak memory 242044 kb
Host smart-7af49154-74ba-45cc-a94e-e63f210311f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136295354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.136295354
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.1264755416
Short name T905
Test name
Test status
Simulation time 235366064 ps
CPU time 3.35 seconds
Started May 26 01:33:46 PM PDT 24
Finished May 26 01:33:50 PM PDT 24
Peak memory 242088 kb
Host smart-547cbc87-703c-46a3-8cdb-5be9a6b63b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264755416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.1264755416
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.18467637
Short name T673
Test name
Test status
Simulation time 121440502 ps
CPU time 2.29 seconds
Started May 26 01:27:52 PM PDT 24
Finished May 26 01:27:55 PM PDT 24
Peak memory 240456 kb
Host smart-b4fe5a38-5e96-4823-9710-7a2ba8fe2062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18467637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.18467637
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.1927857887
Short name T1038
Test name
Test status
Simulation time 9573144881 ps
CPU time 25.96 seconds
Started May 26 01:27:38 PM PDT 24
Finished May 26 01:28:05 PM PDT 24
Peak memory 242172 kb
Host smart-6097adbb-4008-42be-bba7-6ce9980adfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927857887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.1927857887
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.1650911136
Short name T760
Test name
Test status
Simulation time 1998878797 ps
CPU time 18.87 seconds
Started May 26 01:27:38 PM PDT 24
Finished May 26 01:27:57 PM PDT 24
Peak memory 242252 kb
Host smart-7d27f0a5-70a4-4b27-8d3c-9a21d85b3368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650911136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.1650911136
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.3383880679
Short name T806
Test name
Test status
Simulation time 116074710 ps
CPU time 3.25 seconds
Started May 26 01:27:30 PM PDT 24
Finished May 26 01:27:34 PM PDT 24
Peak memory 242180 kb
Host smart-0cf8568b-2445-4930-a59d-fb755dcdb904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383880679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.3383880679
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.1059020587
Short name T272
Test name
Test status
Simulation time 2634986093 ps
CPU time 5.55 seconds
Started May 26 01:27:40 PM PDT 24
Finished May 26 01:27:47 PM PDT 24
Peak memory 242500 kb
Host smart-ad4da9d2-bbf4-44d3-aa14-e00ff9f11d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059020587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.1059020587
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.679502116
Short name T494
Test name
Test status
Simulation time 790069266 ps
CPU time 22.59 seconds
Started May 26 01:27:37 PM PDT 24
Finished May 26 01:28:00 PM PDT 24
Peak memory 242528 kb
Host smart-5a8408b8-e52b-49d7-8778-f4040179df83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679502116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.679502116
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.1303233550
Short name T135
Test name
Test status
Simulation time 620949450 ps
CPU time 9.89 seconds
Started May 26 01:27:38 PM PDT 24
Finished May 26 01:27:49 PM PDT 24
Peak memory 241796 kb
Host smart-a3307a52-0771-4656-b2d7-cddb8a78519a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303233550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.1303233550
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.2698130084
Short name T88
Test name
Test status
Simulation time 577462715 ps
CPU time 11 seconds
Started May 26 01:27:38 PM PDT 24
Finished May 26 01:27:50 PM PDT 24
Peak memory 248712 kb
Host smart-54499671-6a76-4363-a613-5e5e2aae16ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2698130084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.2698130084
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.2986439944
Short name T1175
Test name
Test status
Simulation time 248177451 ps
CPU time 7.36 seconds
Started May 26 01:27:32 PM PDT 24
Finished May 26 01:27:39 PM PDT 24
Peak memory 248540 kb
Host smart-2949a3a4-6584-4b0b-96a7-c61fe4ccd789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986439944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.2986439944
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.2775305301
Short name T1128
Test name
Test status
Simulation time 32338674519 ps
CPU time 150.12 seconds
Started May 26 01:27:39 PM PDT 24
Finished May 26 01:30:10 PM PDT 24
Peak memory 258824 kb
Host smart-c3f3907b-9661-4238-a38f-f4c53abdc536
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775305301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all
.2775305301
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.1584927417
Short name T91
Test name
Test status
Simulation time 6576635423 ps
CPU time 14.46 seconds
Started May 26 01:27:37 PM PDT 24
Finished May 26 01:27:52 PM PDT 24
Peak memory 242800 kb
Host smart-8a06f3b9-3e97-402d-8bfa-8575eaca69ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584927417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.1584927417
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.294394224
Short name T117
Test name
Test status
Simulation time 166846316 ps
CPU time 4.31 seconds
Started May 26 01:33:45 PM PDT 24
Finished May 26 01:33:51 PM PDT 24
Peak memory 241984 kb
Host smart-ee8723e7-4070-48af-8caf-582850514a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294394224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.294394224
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.1275282553
Short name T558
Test name
Test status
Simulation time 338967610 ps
CPU time 3.57 seconds
Started May 26 01:33:45 PM PDT 24
Finished May 26 01:33:50 PM PDT 24
Peak memory 241952 kb
Host smart-88e69483-ca1d-4164-94c3-0e66ace7c9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275282553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.1275282553
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.4007252441
Short name T145
Test name
Test status
Simulation time 497661679 ps
CPU time 4.29 seconds
Started May 26 01:33:47 PM PDT 24
Finished May 26 01:33:52 PM PDT 24
Peak memory 242276 kb
Host smart-5b394f66-39ed-4665-bbe2-9a0f84eabdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007252441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.4007252441
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.2811437225
Short name T751
Test name
Test status
Simulation time 236274222 ps
CPU time 3.83 seconds
Started May 26 01:33:47 PM PDT 24
Finished May 26 01:33:52 PM PDT 24
Peak memory 242084 kb
Host smart-4a1fe061-517c-45ee-b755-047ee9b519f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811437225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.2811437225
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.834378631
Short name T595
Test name
Test status
Simulation time 226260327 ps
CPU time 3.57 seconds
Started May 26 01:33:49 PM PDT 24
Finished May 26 01:33:53 PM PDT 24
Peak memory 242064 kb
Host smart-9c002065-1e37-4bb6-ad6e-227a799689c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834378631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.834378631
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.2741859528
Short name T617
Test name
Test status
Simulation time 163083565 ps
CPU time 4.13 seconds
Started May 26 01:33:45 PM PDT 24
Finished May 26 01:33:50 PM PDT 24
Peak memory 242072 kb
Host smart-68fb0673-5294-42ac-9e25-6a888c1fc354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741859528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.2741859528
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.990367803
Short name T689
Test name
Test status
Simulation time 206273762 ps
CPU time 4.16 seconds
Started May 26 01:33:48 PM PDT 24
Finished May 26 01:33:53 PM PDT 24
Peak memory 242272 kb
Host smart-107daf75-84c0-4b9b-a23a-935f308304f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990367803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.990367803
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.4183905308
Short name T669
Test name
Test status
Simulation time 117407915 ps
CPU time 4.11 seconds
Started May 26 01:33:44 PM PDT 24
Finished May 26 01:33:49 PM PDT 24
Peak memory 241984 kb
Host smart-3baf0e07-ccd0-4a5a-9288-884a7708c56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183905308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.4183905308
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.1634323903
Short name T1033
Test name
Test status
Simulation time 482324990 ps
CPU time 3.91 seconds
Started May 26 01:33:46 PM PDT 24
Finished May 26 01:33:51 PM PDT 24
Peak memory 242348 kb
Host smart-a6798f6c-813c-40a8-be59-bf5e969aa772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634323903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.1634323903
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.65867965
Short name T837
Test name
Test status
Simulation time 492809447 ps
CPU time 3.43 seconds
Started May 26 01:33:45 PM PDT 24
Finished May 26 01:33:50 PM PDT 24
Peak memory 242412 kb
Host smart-afb0232f-f77c-4535-b5a8-dc23c3816f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65867965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.65867965
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.599546929
Short name T229
Test name
Test status
Simulation time 43471486 ps
CPU time 1.65 seconds
Started May 26 01:27:54 PM PDT 24
Finished May 26 01:27:56 PM PDT 24
Peak memory 240452 kb
Host smart-0436d3e6-58be-4a7d-a826-3fd4a106a762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599546929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.599546929
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.2501366504
Short name T194
Test name
Test status
Simulation time 581796668 ps
CPU time 12.83 seconds
Started May 26 01:27:50 PM PDT 24
Finished May 26 01:28:04 PM PDT 24
Peak memory 242712 kb
Host smart-9e197b48-005e-46ea-966c-50844dc7d6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501366504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.2501366504
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.558040858
Short name T638
Test name
Test status
Simulation time 5671369907 ps
CPU time 27.41 seconds
Started May 26 01:27:52 PM PDT 24
Finished May 26 01:28:20 PM PDT 24
Peak memory 242204 kb
Host smart-e3c60403-dec7-42c3-af15-ea2bb0268723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558040858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.558040858
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.369303059
Short name T934
Test name
Test status
Simulation time 241719139 ps
CPU time 3.45 seconds
Started May 26 01:27:52 PM PDT 24
Finished May 26 01:27:56 PM PDT 24
Peak memory 241856 kb
Host smart-7086ec49-0253-40b6-839e-c34ed8c3c3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369303059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.369303059
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.3322766523
Short name T770
Test name
Test status
Simulation time 374456250 ps
CPU time 4.59 seconds
Started May 26 01:27:50 PM PDT 24
Finished May 26 01:27:55 PM PDT 24
Peak memory 242036 kb
Host smart-2f567694-d167-4b4b-b990-6ac53817d8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322766523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.3322766523
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.2181650014
Short name T660
Test name
Test status
Simulation time 570007275 ps
CPU time 13.94 seconds
Started May 26 01:27:50 PM PDT 24
Finished May 26 01:28:05 PM PDT 24
Peak memory 242248 kb
Host smart-81e5bf14-78ea-411a-a052-26d4f5e223ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181650014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.2181650014
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.2886590553
Short name T1054
Test name
Test status
Simulation time 2629915831 ps
CPU time 20.06 seconds
Started May 26 01:27:50 PM PDT 24
Finished May 26 01:28:11 PM PDT 24
Peak memory 242072 kb
Host smart-f2cf6766-ee5b-4208-8bbe-945498e2070c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886590553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.2886590553
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.2463619051
Short name T550
Test name
Test status
Simulation time 499865248 ps
CPU time 14.03 seconds
Started May 26 01:27:53 PM PDT 24
Finished May 26 01:28:08 PM PDT 24
Peak memory 241992 kb
Host smart-27acab90-a6be-4c17-8d5c-0b1ad7d38280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463619051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.2463619051
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.1583449575
Short name T371
Test name
Test status
Simulation time 1117691916 ps
CPU time 10.52 seconds
Started May 26 01:27:51 PM PDT 24
Finished May 26 01:28:03 PM PDT 24
Peak memory 241916 kb
Host smart-0988e440-0b59-4c8e-8091-52c218e0b57e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1583449575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.1583449575
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.4009860208
Short name T417
Test name
Test status
Simulation time 1853092169 ps
CPU time 6.26 seconds
Started May 26 01:27:50 PM PDT 24
Finished May 26 01:27:57 PM PDT 24
Peak memory 241984 kb
Host smart-58fdcfd2-7d9f-4614-b8d0-7c79309be2dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4009860208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.4009860208
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.147735339
Short name T208
Test name
Test status
Simulation time 1187919755 ps
CPU time 9.91 seconds
Started May 26 01:27:50 PM PDT 24
Finished May 26 01:28:01 PM PDT 24
Peak memory 242052 kb
Host smart-b52a686c-3722-4597-89ca-7a92dc9af773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147735339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.147735339
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.1829154446
Short name T967
Test name
Test status
Simulation time 8446507666 ps
CPU time 145.45 seconds
Started May 26 01:27:54 PM PDT 24
Finished May 26 01:30:20 PM PDT 24
Peak memory 250504 kb
Host smart-fb375e42-1a75-4dc6-b962-6fcf10e03a35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829154446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.1829154446
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.4230471829
Short name T704
Test name
Test status
Simulation time 1190699433393 ps
CPU time 2320.36 seconds
Started May 26 01:27:49 PM PDT 24
Finished May 26 02:06:31 PM PDT 24
Peak memory 511148 kb
Host smart-04c3735f-31bf-4c04-b60b-3a173b83f5c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230471829 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.4230471829
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.3331392890
Short name T397
Test name
Test status
Simulation time 2391765575 ps
CPU time 13.97 seconds
Started May 26 01:27:54 PM PDT 24
Finished May 26 01:28:09 PM PDT 24
Peak memory 241892 kb
Host smart-c90141d6-331a-44c6-b153-b76001d3ecf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331392890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.3331392890
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.1026841352
Short name T1006
Test name
Test status
Simulation time 126031987 ps
CPU time 3.47 seconds
Started May 26 01:33:45 PM PDT 24
Finished May 26 01:33:50 PM PDT 24
Peak memory 242004 kb
Host smart-6e7fff31-5caa-42c5-8d27-049c930bf497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026841352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.1026841352
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.69063820
Short name T237
Test name
Test status
Simulation time 1699046712 ps
CPU time 4.02 seconds
Started May 26 01:33:56 PM PDT 24
Finished May 26 01:34:00 PM PDT 24
Peak memory 242040 kb
Host smart-e55ddadd-3172-45f6-a493-9196c4703b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69063820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.69063820
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.4291617617
Short name T721
Test name
Test status
Simulation time 281741826 ps
CPU time 4.27 seconds
Started May 26 01:33:54 PM PDT 24
Finished May 26 01:33:59 PM PDT 24
Peak memory 242160 kb
Host smart-8af707ee-4be1-445f-ae20-3a8dc6b980b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291617617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.4291617617
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.4139825210
Short name T549
Test name
Test status
Simulation time 196889686 ps
CPU time 3.96 seconds
Started May 26 01:33:55 PM PDT 24
Finished May 26 01:34:00 PM PDT 24
Peak memory 242060 kb
Host smart-13772634-c03b-4631-9aaa-f3b504210341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139825210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.4139825210
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.2699372339
Short name T218
Test name
Test status
Simulation time 190803111 ps
CPU time 4.26 seconds
Started May 26 01:33:54 PM PDT 24
Finished May 26 01:33:59 PM PDT 24
Peak memory 241948 kb
Host smart-e74bfeb3-7d39-4a01-ae30-1af94feb6209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699372339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.2699372339
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.2522923972
Short name T489
Test name
Test status
Simulation time 511725647 ps
CPU time 5.16 seconds
Started May 26 01:33:51 PM PDT 24
Finished May 26 01:33:57 PM PDT 24
Peak memory 242432 kb
Host smart-2d812488-5de5-4e07-90f5-843147b48e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522923972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.2522923972
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.4154387830
Short name T892
Test name
Test status
Simulation time 587245161 ps
CPU time 4.72 seconds
Started May 26 01:33:53 PM PDT 24
Finished May 26 01:33:58 PM PDT 24
Peak memory 242056 kb
Host smart-f1e45bef-d34c-4ace-9c29-066dc9ab9403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154387830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.4154387830
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.245662483
Short name T1151
Test name
Test status
Simulation time 2999476988 ps
CPU time 8.25 seconds
Started May 26 01:33:54 PM PDT 24
Finished May 26 01:34:03 PM PDT 24
Peak memory 242356 kb
Host smart-7ca166c1-6ddc-45b5-82f2-7a91b5e665de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245662483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.245662483
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.412573362
Short name T499
Test name
Test status
Simulation time 189852327 ps
CPU time 3.49 seconds
Started May 26 01:33:52 PM PDT 24
Finished May 26 01:33:56 PM PDT 24
Peak memory 241952 kb
Host smart-7cec6d6c-9ae5-4bc2-b056-7fa59aeaa6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412573362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.412573362
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.3292507810
Short name T1134
Test name
Test status
Simulation time 1924385666 ps
CPU time 7.34 seconds
Started May 26 01:33:54 PM PDT 24
Finished May 26 01:34:02 PM PDT 24
Peak memory 241980 kb
Host smart-05b0cd93-0b42-4973-9d73-b1711352f409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292507810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.3292507810
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.571503109
Short name T863
Test name
Test status
Simulation time 156248796 ps
CPU time 1.98 seconds
Started May 26 01:28:09 PM PDT 24
Finished May 26 01:28:12 PM PDT 24
Peak memory 240644 kb
Host smart-6598e955-2efd-429b-88c1-174d0c1368c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571503109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.571503109
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.2657474359
Short name T79
Test name
Test status
Simulation time 1123484461 ps
CPU time 19.09 seconds
Started May 26 01:27:59 PM PDT 24
Finished May 26 01:28:19 PM PDT 24
Peak memory 242056 kb
Host smart-7c284466-b9fa-4ced-aa2a-4e34f0f9a5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657474359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.2657474359
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.2427352484
Short name T1100
Test name
Test status
Simulation time 1815343015 ps
CPU time 17.75 seconds
Started May 26 01:28:09 PM PDT 24
Finished May 26 01:28:28 PM PDT 24
Peak memory 242028 kb
Host smart-d9ed9063-9013-4ad6-86e6-9da48d7ba4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427352484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.2427352484
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.861700459
Short name T204
Test name
Test status
Simulation time 3136253365 ps
CPU time 30.77 seconds
Started May 26 01:28:01 PM PDT 24
Finished May 26 01:28:32 PM PDT 24
Peak memory 242564 kb
Host smart-3e326293-63ef-4bcd-9c8d-a9e2dd52fb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861700459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.861700459
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.2735944230
Short name T459
Test name
Test status
Simulation time 2560613378 ps
CPU time 8.8 seconds
Started May 26 01:27:50 PM PDT 24
Finished May 26 01:28:00 PM PDT 24
Peak memory 242412 kb
Host smart-8f146805-dcef-467e-928c-6eb8d28599bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735944230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.2735944230
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.1755938205
Short name T674
Test name
Test status
Simulation time 20091548441 ps
CPU time 54.71 seconds
Started May 26 01:28:01 PM PDT 24
Finished May 26 01:28:56 PM PDT 24
Peak memory 257068 kb
Host smart-daf01ad1-1617-4e25-a639-476c8a20c4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755938205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.1755938205
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.3322104504
Short name T613
Test name
Test status
Simulation time 1489723486 ps
CPU time 20.2 seconds
Started May 26 01:27:57 PM PDT 24
Finished May 26 01:28:18 PM PDT 24
Peak memory 242332 kb
Host smart-2c07ff25-6ed9-4c42-81fb-552cc6fa1862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322104504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.3322104504
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.1287063410
Short name T911
Test name
Test status
Simulation time 1141924472 ps
CPU time 11.5 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:29 PM PDT 24
Peak memory 241880 kb
Host smart-2f2fa25a-0f0a-4d70-8160-c49faa5ecb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287063410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.1287063410
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.1415322434
Short name T738
Test name
Test status
Simulation time 483056174 ps
CPU time 15.85 seconds
Started May 26 01:27:59 PM PDT 24
Finished May 26 01:28:16 PM PDT 24
Peak memory 241936 kb
Host smart-4b079d3d-4f8d-489d-9747-08473d560d54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1415322434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.1415322434
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.1481110881
Short name T876
Test name
Test status
Simulation time 246087368 ps
CPU time 6.19 seconds
Started May 26 01:27:50 PM PDT 24
Finished May 26 01:27:57 PM PDT 24
Peak memory 242200 kb
Host smart-f63511fa-9896-41fe-a054-89e35d8d618d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481110881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.1481110881
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.2571236544
Short name T941
Test name
Test status
Simulation time 17526947329 ps
CPU time 191.8 seconds
Started May 26 01:27:58 PM PDT 24
Finished May 26 01:31:10 PM PDT 24
Peak memory 273492 kb
Host smart-0fc10c64-f356-4e92-8d02-5fe750cde53d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571236544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all
.2571236544
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.3090045745
Short name T773
Test name
Test status
Simulation time 50467381014 ps
CPU time 711.34 seconds
Started May 26 01:28:01 PM PDT 24
Finished May 26 01:39:53 PM PDT 24
Peak memory 285032 kb
Host smart-9cfaf852-7059-4d2b-a694-138e82001610
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090045745 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.3090045745
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.2717821379
Short name T800
Test name
Test status
Simulation time 6360613340 ps
CPU time 14.48 seconds
Started May 26 01:27:58 PM PDT 24
Finished May 26 01:28:13 PM PDT 24
Peak memory 242832 kb
Host smart-99045b04-10c9-4567-b485-f553e9f74548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717821379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.2717821379
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.2052126030
Short name T1143
Test name
Test status
Simulation time 119018381 ps
CPU time 4.45 seconds
Started May 26 01:33:52 PM PDT 24
Finished May 26 01:33:57 PM PDT 24
Peak memory 242096 kb
Host smart-f1d98569-dd1c-4d6b-84b1-511e1fce5f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052126030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.2052126030
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.97224860
Short name T634
Test name
Test status
Simulation time 91269481 ps
CPU time 3.63 seconds
Started May 26 01:33:53 PM PDT 24
Finished May 26 01:33:57 PM PDT 24
Peak memory 242620 kb
Host smart-246214ef-29ac-4204-aaab-f9b877efb1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97224860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.97224860
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.2956996353
Short name T684
Test name
Test status
Simulation time 202274701 ps
CPU time 4.85 seconds
Started May 26 01:33:53 PM PDT 24
Finished May 26 01:33:58 PM PDT 24
Peak memory 242312 kb
Host smart-30391b2f-213a-412b-90b2-525dc5213c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956996353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.2956996353
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.3766833297
Short name T529
Test name
Test status
Simulation time 424183524 ps
CPU time 3.92 seconds
Started May 26 01:33:53 PM PDT 24
Finished May 26 01:33:58 PM PDT 24
Peak memory 242148 kb
Host smart-833f8a62-883e-4b48-8961-4abae5e4cf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766833297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.3766833297
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.2268697598
Short name T1132
Test name
Test status
Simulation time 2098229794 ps
CPU time 5.18 seconds
Started May 26 01:33:53 PM PDT 24
Finished May 26 01:33:58 PM PDT 24
Peak memory 242016 kb
Host smart-31f6d453-86a4-4f58-9bd4-990ed3c4f8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268697598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.2268697598
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.3165751938
Short name T1039
Test name
Test status
Simulation time 200157251 ps
CPU time 3.81 seconds
Started May 26 01:33:53 PM PDT 24
Finished May 26 01:33:58 PM PDT 24
Peak memory 241948 kb
Host smart-2756cb08-fd74-46e0-9cac-c75fd90e7f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165751938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.3165751938
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.232821006
Short name T189
Test name
Test status
Simulation time 177485222 ps
CPU time 4.18 seconds
Started May 26 01:33:54 PM PDT 24
Finished May 26 01:34:00 PM PDT 24
Peak memory 241996 kb
Host smart-beafa6df-08b2-4d78-8827-660feb281123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232821006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.232821006
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.345940360
Short name T896
Test name
Test status
Simulation time 157362183 ps
CPU time 4.25 seconds
Started May 26 01:33:54 PM PDT 24
Finished May 26 01:33:59 PM PDT 24
Peak memory 241928 kb
Host smart-ba4c5056-4f92-496a-b0bd-e9dd2da02bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345940360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.345940360
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.2637935703
Short name T1016
Test name
Test status
Simulation time 157453862 ps
CPU time 4.5 seconds
Started May 26 01:33:56 PM PDT 24
Finished May 26 01:34:01 PM PDT 24
Peak memory 242068 kb
Host smart-d7c2803e-02bd-4278-b65b-715ef0d64ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637935703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.2637935703
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.1854672067
Short name T686
Test name
Test status
Simulation time 250983040 ps
CPU time 3.91 seconds
Started May 26 01:33:53 PM PDT 24
Finished May 26 01:33:58 PM PDT 24
Peak memory 242164 kb
Host smart-a619ee88-561a-4fab-93ee-cfb4407ad645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854672067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.1854672067
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.1270266039
Short name T801
Test name
Test status
Simulation time 61781782 ps
CPU time 1.9 seconds
Started May 26 01:28:08 PM PDT 24
Finished May 26 01:28:11 PM PDT 24
Peak memory 240628 kb
Host smart-3e3e5732-ea67-401e-8cf2-f2f6f60d1296
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270266039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.1270266039
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.4285350077
Short name T169
Test name
Test status
Simulation time 191442177 ps
CPU time 4.67 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:22 PM PDT 24
Peak memory 247544 kb
Host smart-a753f057-9118-48c7-a0d1-c8c665712369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285350077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.4285350077
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.2162169863
Short name T676
Test name
Test status
Simulation time 3253679995 ps
CPU time 19.64 seconds
Started May 26 01:27:58 PM PDT 24
Finished May 26 01:28:18 PM PDT 24
Peak memory 242044 kb
Host smart-52c7d6ab-0f17-4f1b-9ed0-409044951f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162169863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.2162169863
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.2458395906
Short name T715
Test name
Test status
Simulation time 2723347229 ps
CPU time 27.24 seconds
Started May 26 01:28:15 PM PDT 24
Finished May 26 01:28:43 PM PDT 24
Peak memory 242116 kb
Host smart-afdcf285-d5fb-4bc0-a2dc-92ef2abe5d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458395906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.2458395906
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.3103291878
Short name T184
Test name
Test status
Simulation time 187633507 ps
CPU time 2.84 seconds
Started May 26 01:28:00 PM PDT 24
Finished May 26 01:28:03 PM PDT 24
Peak memory 242296 kb
Host smart-9c43e899-079e-4960-9704-4a57d5f9bf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103291878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.3103291878
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.452250829
Short name T881
Test name
Test status
Simulation time 609352724 ps
CPU time 19.22 seconds
Started May 26 01:28:09 PM PDT 24
Finished May 26 01:28:30 PM PDT 24
Peak memory 244568 kb
Host smart-6c021771-cccc-42d1-9a42-f26bc68b82c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452250829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.452250829
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.1826761235
Short name T604
Test name
Test status
Simulation time 1253466763 ps
CPU time 12.37 seconds
Started May 26 01:28:15 PM PDT 24
Finished May 26 01:28:28 PM PDT 24
Peak memory 241960 kb
Host smart-fd2b36fa-5e4e-4de2-9184-b7863caa5d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826761235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.1826761235
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.2136220803
Short name T803
Test name
Test status
Simulation time 6422704544 ps
CPU time 15.37 seconds
Started May 26 01:27:59 PM PDT 24
Finished May 26 01:28:15 PM PDT 24
Peak memory 242308 kb
Host smart-e0b86696-e589-4181-803d-da345044d0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136220803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.2136220803
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.3633102381
Short name T168
Test name
Test status
Simulation time 7765661748 ps
CPU time 19 seconds
Started May 26 01:28:09 PM PDT 24
Finished May 26 01:28:29 PM PDT 24
Peak memory 242256 kb
Host smart-23d4236f-a750-416e-8c06-ef200f781c3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3633102381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.3633102381
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.911950110
Short name T783
Test name
Test status
Simulation time 471244049 ps
CPU time 4.95 seconds
Started May 26 01:28:07 PM PDT 24
Finished May 26 01:28:13 PM PDT 24
Peak memory 242120 kb
Host smart-e95a9e4d-5a67-4b6e-b662-eed9f5930c2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=911950110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.911950110
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.146023393
Short name T404
Test name
Test status
Simulation time 1135534788 ps
CPU time 11.7 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:29 PM PDT 24
Peak memory 241984 kb
Host smart-aab6ec97-3486-4798-bf0f-e57fc42cbdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146023393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.146023393
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.4284231451
Short name T886
Test name
Test status
Simulation time 64157810850 ps
CPU time 398.62 seconds
Started May 26 01:28:09 PM PDT 24
Finished May 26 01:34:49 PM PDT 24
Peak memory 257108 kb
Host smart-7a80ee21-bbaf-4986-b7dd-c4eaa69a3df8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284231451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.4284231451
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.2603399210
Short name T257
Test name
Test status
Simulation time 101516812705 ps
CPU time 726.47 seconds
Started May 26 01:28:07 PM PDT 24
Finished May 26 01:40:15 PM PDT 24
Peak memory 289120 kb
Host smart-a623a178-4012-41ef-ab28-1f4cd0c2c16b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603399210 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.2603399210
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.3120687775
Short name T1011
Test name
Test status
Simulation time 10604271104 ps
CPU time 33.91 seconds
Started May 26 01:28:04 PM PDT 24
Finished May 26 01:28:38 PM PDT 24
Peak memory 242284 kb
Host smart-d632b052-6197-4e69-8324-f74f0557c0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120687775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.3120687775
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.1248771682
Short name T455
Test name
Test status
Simulation time 240622262 ps
CPU time 4.94 seconds
Started May 26 01:33:53 PM PDT 24
Finished May 26 01:33:59 PM PDT 24
Peak memory 242464 kb
Host smart-5c603ad5-400d-41d6-ae3f-f026cb8dd265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248771682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.1248771682
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.2569832227
Short name T739
Test name
Test status
Simulation time 263859162 ps
CPU time 3.49 seconds
Started May 26 01:33:55 PM PDT 24
Finished May 26 01:33:59 PM PDT 24
Peak memory 242304 kb
Host smart-2009c7e3-78cf-424b-bf41-04ceb2ca1aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569832227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.2569832227
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.651859984
Short name T848
Test name
Test status
Simulation time 142887018 ps
CPU time 3.53 seconds
Started May 26 01:33:53 PM PDT 24
Finished May 26 01:33:57 PM PDT 24
Peak memory 242260 kb
Host smart-bf24ba9c-f605-41bc-ad56-712afd726bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651859984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.651859984
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.748975680
Short name T44
Test name
Test status
Simulation time 402079595 ps
CPU time 4.28 seconds
Started May 26 01:33:53 PM PDT 24
Finished May 26 01:33:59 PM PDT 24
Peak memory 242076 kb
Host smart-d2802357-762a-41f8-8590-21246b675c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748975680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.748975680
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.2612565829
Short name T163
Test name
Test status
Simulation time 662213098 ps
CPU time 5.42 seconds
Started May 26 01:34:01 PM PDT 24
Finished May 26 01:34:08 PM PDT 24
Peak memory 242072 kb
Host smart-ac8a82bf-ac32-4a6e-8a71-7d9823c75aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612565829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.2612565829
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.2669241175
Short name T77
Test name
Test status
Simulation time 1977741754 ps
CPU time 5.8 seconds
Started May 26 01:34:03 PM PDT 24
Finished May 26 01:34:11 PM PDT 24
Peak memory 242080 kb
Host smart-a2bb4234-a3f8-4c2d-8b48-f158d505dae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669241175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.2669241175
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.1943434083
Short name T682
Test name
Test status
Simulation time 124755768 ps
CPU time 4.65 seconds
Started May 26 01:34:01 PM PDT 24
Finished May 26 01:34:08 PM PDT 24
Peak memory 242208 kb
Host smart-88ccfb48-9383-4828-8b22-7f457d5569e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943434083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.1943434083
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.3851046176
Short name T741
Test name
Test status
Simulation time 2760417075 ps
CPU time 6.38 seconds
Started May 26 01:34:03 PM PDT 24
Finished May 26 01:34:12 PM PDT 24
Peak memory 242144 kb
Host smart-7f00573d-b6dc-4c50-82eb-6b2ace921945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851046176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.3851046176
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.2305986630
Short name T221
Test name
Test status
Simulation time 1901709234 ps
CPU time 6.52 seconds
Started May 26 01:34:01 PM PDT 24
Finished May 26 01:34:10 PM PDT 24
Peak memory 242012 kb
Host smart-32d82d57-974e-4083-a114-85dfdcccd3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305986630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.2305986630
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.1688772958
Short name T1035
Test name
Test status
Simulation time 124690965 ps
CPU time 4.48 seconds
Started May 26 01:34:01 PM PDT 24
Finished May 26 01:34:07 PM PDT 24
Peak memory 242108 kb
Host smart-37e57f8e-f6e7-4cfd-a9bd-5c84e3fd7920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688772958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.1688772958
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.1529697525
Short name T795
Test name
Test status
Simulation time 88848471 ps
CPU time 1.85 seconds
Started May 26 01:25:02 PM PDT 24
Finished May 26 01:25:04 PM PDT 24
Peak memory 240820 kb
Host smart-39f12ba2-86f1-4ab2-ac48-2476501dc4fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529697525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.1529697525
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.3939736736
Short name T425
Test name
Test status
Simulation time 442215205 ps
CPU time 12.44 seconds
Started May 26 01:25:01 PM PDT 24
Finished May 26 01:25:14 PM PDT 24
Peak memory 241988 kb
Host smart-440b7377-8d1d-45de-9c5c-a442747527be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939736736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.3939736736
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.1887922340
Short name T307
Test name
Test status
Simulation time 680811579 ps
CPU time 5.82 seconds
Started May 26 01:24:54 PM PDT 24
Finished May 26 01:25:00 PM PDT 24
Peak memory 247840 kb
Host smart-98f75ea9-0306-44d3-85e7-dce1ad819204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887922340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.1887922340
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.2726184904
Short name T746
Test name
Test status
Simulation time 21388486957 ps
CPU time 47.44 seconds
Started May 26 01:24:55 PM PDT 24
Finished May 26 01:25:43 PM PDT 24
Peak memory 251384 kb
Host smart-b37d545e-b94c-40c2-aec5-9a82a8955896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726184904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.2726184904
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.3869516527
Short name T1141
Test name
Test status
Simulation time 918232947 ps
CPU time 10.1 seconds
Started May 26 01:24:54 PM PDT 24
Finished May 26 01:25:05 PM PDT 24
Peak memory 242308 kb
Host smart-66cab586-dbf1-4e6f-9d96-7e9607dedb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869516527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.3869516527
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.330405511
Short name T224
Test name
Test status
Simulation time 132559192 ps
CPU time 3.5 seconds
Started May 26 01:24:54 PM PDT 24
Finished May 26 01:24:58 PM PDT 24
Peak memory 242004 kb
Host smart-a1f8eec9-45dc-48a2-a22a-06374845f378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330405511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.330405511
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.823647915
Short name T648
Test name
Test status
Simulation time 583784888 ps
CPU time 5.06 seconds
Started May 26 01:24:55 PM PDT 24
Finished May 26 01:25:01 PM PDT 24
Peak memory 242144 kb
Host smart-b7e72e43-7522-4eeb-8003-ec6c093bfb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823647915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.823647915
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.1044899809
Short name T570
Test name
Test status
Simulation time 1928869450 ps
CPU time 28.5 seconds
Started May 26 01:24:56 PM PDT 24
Finished May 26 01:25:25 PM PDT 24
Peak memory 242320 kb
Host smart-5c6dcb41-9bf3-4cd6-b96e-c791c298e6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044899809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.1044899809
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.1908822590
Short name T926
Test name
Test status
Simulation time 501509969 ps
CPU time 6.22 seconds
Started May 26 01:24:57 PM PDT 24
Finished May 26 01:25:04 PM PDT 24
Peak memory 242236 kb
Host smart-9ee0581a-8f68-4a60-95ba-f6c011ecffa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908822590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.1908822590
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.317129565
Short name T1179
Test name
Test status
Simulation time 6809252463 ps
CPU time 25.26 seconds
Started May 26 01:24:56 PM PDT 24
Finished May 26 01:25:22 PM PDT 24
Peak memory 242052 kb
Host smart-c6dc870a-e897-4061-b612-4d80987aca83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=317129565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.317129565
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.2236259659
Short name T776
Test name
Test status
Simulation time 2072116460 ps
CPU time 7.77 seconds
Started May 26 01:24:55 PM PDT 24
Finished May 26 01:25:04 PM PDT 24
Peak memory 248828 kb
Host smart-adedde2c-b198-4bf0-9190-9ff3c87df633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2236259659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.2236259659
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.3889321132
Short name T193
Test name
Test status
Simulation time 662892977 ps
CPU time 10.15 seconds
Started May 26 01:24:54 PM PDT 24
Finished May 26 01:25:05 PM PDT 24
Peak memory 241972 kb
Host smart-b227bac2-430e-4888-b60c-e97f4ff0109f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889321132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.3889321132
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.118086974
Short name T805
Test name
Test status
Simulation time 51154771082 ps
CPU time 87.8 seconds
Started May 26 01:24:54 PM PDT 24
Finished May 26 01:26:22 PM PDT 24
Peak memory 265144 kb
Host smart-70c1e982-f890-4730-80dd-c693774ab385
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118086974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.118086974
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.4214323228
Short name T282
Test name
Test status
Simulation time 47910588854 ps
CPU time 1301.76 seconds
Started May 26 01:24:54 PM PDT 24
Finished May 26 01:46:36 PM PDT 24
Peak memory 319492 kb
Host smart-b2d4f6a3-23be-4b2f-9c17-863e0b422e59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214323228 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.4214323228
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.40847047
Short name T712
Test name
Test status
Simulation time 1634868469 ps
CPU time 22.69 seconds
Started May 26 01:24:55 PM PDT 24
Finished May 26 01:25:18 PM PDT 24
Peak memory 242140 kb
Host smart-cd502f91-e9d8-4bef-9e05-3246c067d2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40847047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.40847047
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.1032739238
Short name T901
Test name
Test status
Simulation time 770314055 ps
CPU time 1.94 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:20 PM PDT 24
Peak memory 240624 kb
Host smart-98b4be02-f1d6-4598-ac3d-e123916db0ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032739238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.1032739238
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.3313255458
Short name T894
Test name
Test status
Simulation time 653039157 ps
CPU time 21.06 seconds
Started May 26 01:28:09 PM PDT 24
Finished May 26 01:28:31 PM PDT 24
Peak memory 248804 kb
Host smart-3ad83638-5783-4059-9d45-7befca9d5b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313255458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.3313255458
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.4211005239
Short name T659
Test name
Test status
Simulation time 1299054540 ps
CPU time 37.43 seconds
Started May 26 01:28:09 PM PDT 24
Finished May 26 01:28:48 PM PDT 24
Peak memory 249948 kb
Host smart-12fc11d5-2970-4a68-883b-6c435c989221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211005239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.4211005239
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.4183333000
Short name T626
Test name
Test status
Simulation time 1811263073 ps
CPU time 17.99 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:36 PM PDT 24
Peak memory 242108 kb
Host smart-ff7da24d-be66-44b5-9c86-224628b830f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183333000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.4183333000
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.3553941827
Short name T223
Test name
Test status
Simulation time 1048185822 ps
CPU time 12.58 seconds
Started May 26 01:28:06 PM PDT 24
Finished May 26 01:28:20 PM PDT 24
Peak memory 248776 kb
Host smart-8e3c6e5a-850d-449c-81a9-071527fa408d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553941827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.3553941827
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.1983015268
Short name T1013
Test name
Test status
Simulation time 3347182380 ps
CPU time 38.6 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:56 PM PDT 24
Peak memory 242408 kb
Host smart-8f263ad4-7e40-4d26-8266-04fe98b5eb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983015268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.1983015268
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.4261970140
Short name T625
Test name
Test status
Simulation time 1029488412 ps
CPU time 10.37 seconds
Started May 26 01:28:07 PM PDT 24
Finished May 26 01:28:18 PM PDT 24
Peak memory 242316 kb
Host smart-20a88669-1cfa-47ae-862e-8c7e7a67003b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261970140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.4261970140
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.715256343
Short name T616
Test name
Test status
Simulation time 612411043 ps
CPU time 9.73 seconds
Started May 26 01:28:08 PM PDT 24
Finished May 26 01:28:18 PM PDT 24
Peak memory 242092 kb
Host smart-20cf9d9a-5eeb-44df-a0b6-8a1a856b608c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=715256343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.715256343
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.3264342506
Short name T349
Test name
Test status
Simulation time 560968214 ps
CPU time 8.83 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:26 PM PDT 24
Peak memory 241900 kb
Host smart-c0759194-aff0-4684-ae0a-76f5ffc921ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3264342506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.3264342506
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.3417713508
Short name T8
Test name
Test status
Simulation time 512374040 ps
CPU time 6.65 seconds
Started May 26 01:28:06 PM PDT 24
Finished May 26 01:28:14 PM PDT 24
Peak memory 241944 kb
Host smart-2c840d9d-3988-4a66-80e6-8e9099b13c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417713508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.3417713508
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.787626057
Short name T435
Test name
Test status
Simulation time 1339149426 ps
CPU time 10.45 seconds
Started May 26 01:28:17 PM PDT 24
Finished May 26 01:28:29 PM PDT 24
Peak memory 242108 kb
Host smart-430a61f3-e078-4d73-a191-09f736c8a7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787626057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.787626057
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.1779127536
Short name T723
Test name
Test status
Simulation time 56378022 ps
CPU time 1.62 seconds
Started May 26 01:28:23 PM PDT 24
Finished May 26 01:28:25 PM PDT 24
Peak memory 240548 kb
Host smart-de6cf0c4-39dd-4500-97ad-017fe161ad47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779127536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.1779127536
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.4253028768
Short name T67
Test name
Test status
Simulation time 1941232489 ps
CPU time 14.04 seconds
Started May 26 01:28:17 PM PDT 24
Finished May 26 01:28:32 PM PDT 24
Peak memory 248788 kb
Host smart-37f7e567-2863-446b-975b-10af7c93c3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253028768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.4253028768
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.207984202
Short name T470
Test name
Test status
Simulation time 1983576789 ps
CPU time 22.25 seconds
Started May 26 01:28:17 PM PDT 24
Finished May 26 01:28:41 PM PDT 24
Peak memory 241980 kb
Host smart-9fb782bc-fdc9-45c7-884b-52d79b10e3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207984202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.207984202
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.501240936
Short name T1135
Test name
Test status
Simulation time 661254299 ps
CPU time 11.48 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:29 PM PDT 24
Peak memory 248768 kb
Host smart-d2501faa-1bee-4e4b-8f65-3cd9829ec44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501240936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.501240936
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.2795370833
Short name T115
Test name
Test status
Simulation time 2184703463 ps
CPU time 5.74 seconds
Started May 26 01:28:14 PM PDT 24
Finished May 26 01:28:21 PM PDT 24
Peak memory 242332 kb
Host smart-d41a35cd-8bca-409c-ae74-7b2f411e6f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795370833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.2795370833
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.2104895940
Short name T866
Test name
Test status
Simulation time 2030160380 ps
CPU time 14.12 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:32 PM PDT 24
Peak memory 242052 kb
Host smart-c3c2e244-f5d3-46da-9d8a-25e98d2142e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104895940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.2104895940
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.586097212
Short name T697
Test name
Test status
Simulation time 624815678 ps
CPU time 24.57 seconds
Started May 26 01:28:17 PM PDT 24
Finished May 26 01:28:43 PM PDT 24
Peak memory 242256 kb
Host smart-cd6ec9f0-76c3-4d2c-a947-a5380dc7ef89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586097212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.586097212
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.3245570080
Short name T970
Test name
Test status
Simulation time 1792186707 ps
CPU time 12.04 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:29 PM PDT 24
Peak memory 242004 kb
Host smart-c5921592-bc2c-45f5-9e26-a523c83aa597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245570080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.3245570080
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.702815356
Short name T552
Test name
Test status
Simulation time 306132107 ps
CPU time 9.44 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:27 PM PDT 24
Peak memory 242324 kb
Host smart-ecace51c-cebf-496a-b893-c21661220a5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=702815356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.702815356
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.2600148254
Short name T1166
Test name
Test status
Simulation time 151748390 ps
CPU time 4.75 seconds
Started May 26 01:28:15 PM PDT 24
Finished May 26 01:28:21 PM PDT 24
Peak memory 241924 kb
Host smart-13474485-6e92-4340-bef6-513ef7a2dc62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2600148254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.2600148254
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.2998997159
Short name T447
Test name
Test status
Simulation time 865924259 ps
CPU time 9.85 seconds
Started May 26 01:28:17 PM PDT 24
Finished May 26 01:28:29 PM PDT 24
Peak memory 241984 kb
Host smart-9599b41a-9974-4f5f-8366-f28a3d063c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998997159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.2998997159
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.4103990191
Short name T230
Test name
Test status
Simulation time 16590125082 ps
CPU time 192.05 seconds
Started May 26 01:28:26 PM PDT 24
Finished May 26 01:31:39 PM PDT 24
Peak memory 265784 kb
Host smart-78d5af32-1ebb-4ec0-8017-9b5451e9003a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103990191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.4103990191
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.3297288840
Short name T329
Test name
Test status
Simulation time 283146446705 ps
CPU time 1262.81 seconds
Started May 26 01:28:15 PM PDT 24
Finished May 26 01:49:19 PM PDT 24
Peak memory 366924 kb
Host smart-e899a046-8a05-4c38-851e-6fee58e4deae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297288840 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.3297288840
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.914567297
Short name T1112
Test name
Test status
Simulation time 1444808966 ps
CPU time 29.77 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:48 PM PDT 24
Peak memory 242568 kb
Host smart-5cdba078-f3ae-4f92-91ab-d1fe570b2d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914567297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.914567297
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.745958286
Short name T389
Test name
Test status
Simulation time 215857247 ps
CPU time 2.18 seconds
Started May 26 01:28:27 PM PDT 24
Finished May 26 01:28:29 PM PDT 24
Peak memory 240476 kb
Host smart-e6d0964d-6cd4-4826-9c00-857d310f3715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745958286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.745958286
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.3228590328
Short name T991
Test name
Test status
Simulation time 285167088 ps
CPU time 3.54 seconds
Started May 26 01:28:23 PM PDT 24
Finished May 26 01:28:27 PM PDT 24
Peak memory 242232 kb
Host smart-af14d27e-2a18-4606-b895-751c199f40bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228590328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.3228590328
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.3054948259
Short name T764
Test name
Test status
Simulation time 1247103200 ps
CPU time 35.6 seconds
Started May 26 01:28:22 PM PDT 24
Finished May 26 01:28:59 PM PDT 24
Peak memory 242276 kb
Host smart-691919c3-9a39-4b9e-8ffc-ef8e52728ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054948259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.3054948259
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.1198301266
Short name T400
Test name
Test status
Simulation time 431370657 ps
CPU time 10.24 seconds
Started May 26 01:28:24 PM PDT 24
Finished May 26 01:28:35 PM PDT 24
Peak memory 242092 kb
Host smart-063d403b-1d31-40ab-a3b7-eea407489f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198301266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.1198301266
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.1699262665
Short name T832
Test name
Test status
Simulation time 157275279 ps
CPU time 4.29 seconds
Started May 26 01:28:25 PM PDT 24
Finished May 26 01:28:30 PM PDT 24
Peak memory 242440 kb
Host smart-e7303f9c-2779-4495-ba80-642066188087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699262665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.1699262665
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.2299027508
Short name T225
Test name
Test status
Simulation time 5057754537 ps
CPU time 52.97 seconds
Started May 26 01:28:24 PM PDT 24
Finished May 26 01:29:18 PM PDT 24
Peak memory 258984 kb
Host smart-d0e3de08-119e-489e-a6c1-b4e32ed594be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299027508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.2299027508
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.2229286679
Short name T1149
Test name
Test status
Simulation time 217548884 ps
CPU time 5.41 seconds
Started May 26 01:28:25 PM PDT 24
Finished May 26 01:28:31 PM PDT 24
Peak memory 241884 kb
Host smart-f87bdc47-6080-4e83-8525-82627f9c7309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229286679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.2229286679
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.948993190
Short name T497
Test name
Test status
Simulation time 175319574 ps
CPU time 3.13 seconds
Started May 26 01:28:22 PM PDT 24
Finished May 26 01:28:26 PM PDT 24
Peak memory 242048 kb
Host smart-57e9d163-d877-4bf2-ab7a-a2b3d4ad24fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948993190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.948993190
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.823884337
Short name T1147
Test name
Test status
Simulation time 682619672 ps
CPU time 21.23 seconds
Started May 26 01:28:22 PM PDT 24
Finished May 26 01:28:44 PM PDT 24
Peak memory 241916 kb
Host smart-fe79ef4d-c606-464a-9809-d565ab404ca1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=823884337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.823884337
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.1763034682
Short name T852
Test name
Test status
Simulation time 455276667 ps
CPU time 7.4 seconds
Started May 26 01:28:26 PM PDT 24
Finished May 26 01:28:34 PM PDT 24
Peak memory 242024 kb
Host smart-493607aa-467f-4ec0-b7a5-c13ab05f5cea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1763034682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.1763034682
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.1741235505
Short name T586
Test name
Test status
Simulation time 602031517 ps
CPU time 10.48 seconds
Started May 26 01:28:27 PM PDT 24
Finished May 26 01:28:38 PM PDT 24
Peak memory 242120 kb
Host smart-22bec44f-8e67-4aeb-a4e9-8f315553e90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741235505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.1741235505
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.2284802308
Short name T236
Test name
Test status
Simulation time 13290811958 ps
CPU time 144.6 seconds
Started May 26 01:28:23 PM PDT 24
Finished May 26 01:30:48 PM PDT 24
Peak memory 248860 kb
Host smart-cf44c473-c445-425b-8be1-fee9d82c7c92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284802308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all
.2284802308
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.3705777890
Short name T914
Test name
Test status
Simulation time 157145476599 ps
CPU time 1464.43 seconds
Started May 26 01:28:26 PM PDT 24
Finished May 26 01:52:51 PM PDT 24
Peak memory 410512 kb
Host smart-d49a845b-9417-4e5b-86d7-bb7cf36bb86d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705777890 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.3705777890
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.3972793709
Short name T372
Test name
Test status
Simulation time 1014071160 ps
CPU time 10.74 seconds
Started May 26 01:28:24 PM PDT 24
Finished May 26 01:28:35 PM PDT 24
Peak memory 242192 kb
Host smart-b262f040-12c3-424f-aef1-77df6ad6c565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972793709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.3972793709
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.895244411
Short name T222
Test name
Test status
Simulation time 179518114 ps
CPU time 1.78 seconds
Started May 26 01:28:43 PM PDT 24
Finished May 26 01:28:47 PM PDT 24
Peak memory 240608 kb
Host smart-ae5c93f8-b6a8-42f5-a399-6e474c878dce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895244411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.895244411
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.429941745
Short name T766
Test name
Test status
Simulation time 333769708 ps
CPU time 8.19 seconds
Started May 26 01:28:33 PM PDT 24
Finished May 26 01:28:42 PM PDT 24
Peak memory 242244 kb
Host smart-34c9ccd2-2b59-45bc-b599-0d6cca444360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429941745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.429941745
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.346187431
Short name T731
Test name
Test status
Simulation time 303230354 ps
CPU time 6.81 seconds
Started May 26 01:28:33 PM PDT 24
Finished May 26 01:28:41 PM PDT 24
Peak memory 242312 kb
Host smart-6eaab843-7dfc-46d5-af05-5eafe451ce6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346187431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.346187431
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.3442154929
Short name T714
Test name
Test status
Simulation time 1009491236 ps
CPU time 22.04 seconds
Started May 26 01:28:34 PM PDT 24
Finished May 26 01:28:57 PM PDT 24
Peak memory 241924 kb
Host smart-e6f61b08-7198-475c-abbf-4fe7b40a5892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442154929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.3442154929
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.558593231
Short name T49
Test name
Test status
Simulation time 152105307 ps
CPU time 4.21 seconds
Started May 26 01:28:36 PM PDT 24
Finished May 26 01:28:41 PM PDT 24
Peak memory 242108 kb
Host smart-07452adc-3688-44fe-982e-7656ad9d1215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558593231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.558593231
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.847358180
Short name T824
Test name
Test status
Simulation time 988490224 ps
CPU time 12.92 seconds
Started May 26 01:28:33 PM PDT 24
Finished May 26 01:28:46 PM PDT 24
Peak memory 242224 kb
Host smart-aa605d52-f84c-4ab5-a832-8a6818b73af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847358180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.847358180
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.2915361077
Short name T627
Test name
Test status
Simulation time 1119447529 ps
CPU time 28.68 seconds
Started May 26 01:28:31 PM PDT 24
Finished May 26 01:29:01 PM PDT 24
Peak memory 242352 kb
Host smart-0d95967d-1518-41e4-b7f4-e8af21f38c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915361077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.2915361077
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.1224761511
Short name T823
Test name
Test status
Simulation time 105311954 ps
CPU time 3.53 seconds
Started May 26 01:28:32 PM PDT 24
Finished May 26 01:28:36 PM PDT 24
Peak memory 242152 kb
Host smart-b8237624-ba51-4ddf-b680-01970377daec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224761511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.1224761511
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.380163536
Short name T370
Test name
Test status
Simulation time 7617371085 ps
CPU time 16.09 seconds
Started May 26 01:28:33 PM PDT 24
Finished May 26 01:28:50 PM PDT 24
Peak memory 241956 kb
Host smart-f92fde16-f028-4ea7-b6da-107629e13c46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=380163536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.380163536
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.4155042758
Short name T989
Test name
Test status
Simulation time 264899933 ps
CPU time 5.25 seconds
Started May 26 01:28:34 PM PDT 24
Finished May 26 01:28:40 PM PDT 24
Peak memory 242072 kb
Host smart-0e2b0434-11c5-40bc-bd2a-34399843e537
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4155042758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.4155042758
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.723910808
Short name T582
Test name
Test status
Simulation time 312696954 ps
CPU time 6.52 seconds
Started May 26 01:28:31 PM PDT 24
Finished May 26 01:28:38 PM PDT 24
Peak memory 242280 kb
Host smart-046ff884-2ead-49a3-9f6c-cf5aa86bac33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723910808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.723910808
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.1945556104
Short name T1066
Test name
Test status
Simulation time 346229293 ps
CPU time 4.96 seconds
Started May 26 01:28:33 PM PDT 24
Finished May 26 01:28:39 PM PDT 24
Peak memory 241788 kb
Host smart-1c433f0f-8c6d-40d3-b400-3e2023b4070c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945556104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.1945556104
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.1854112104
Short name T693
Test name
Test status
Simulation time 141467976 ps
CPU time 1.65 seconds
Started May 26 01:28:42 PM PDT 24
Finished May 26 01:28:45 PM PDT 24
Peak memory 240500 kb
Host smart-75df2896-3fd8-4f28-8787-859a5159e792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854112104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.1854112104
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.468654339
Short name T80
Test name
Test status
Simulation time 1948007837 ps
CPU time 31.02 seconds
Started May 26 01:28:42 PM PDT 24
Finished May 26 01:29:15 PM PDT 24
Peak memory 242648 kb
Host smart-5008c0da-9841-4144-8ebf-441d5f67b815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468654339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.468654339
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.1079864379
Short name T1159
Test name
Test status
Simulation time 1194877751 ps
CPU time 20.33 seconds
Started May 26 01:28:42 PM PDT 24
Finished May 26 01:29:04 PM PDT 24
Peak memory 242196 kb
Host smart-bf217ee2-65c7-4f8b-9245-4ba922d93012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079864379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.1079864379
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.1739882465
Short name T865
Test name
Test status
Simulation time 438947389 ps
CPU time 9.01 seconds
Started May 26 01:28:41 PM PDT 24
Finished May 26 01:28:52 PM PDT 24
Peak memory 242288 kb
Host smart-e86750b0-2237-4c37-964b-71191714063d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739882465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.1739882465
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.3212187976
Short name T943
Test name
Test status
Simulation time 1307162998 ps
CPU time 4.79 seconds
Started May 26 01:28:41 PM PDT 24
Finished May 26 01:28:47 PM PDT 24
Peak memory 242284 kb
Host smart-7b549834-4d5f-48b8-8192-0bf5b2758df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212187976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.3212187976
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.3892841591
Short name T227
Test name
Test status
Simulation time 2074067814 ps
CPU time 43.63 seconds
Started May 26 01:28:44 PM PDT 24
Finished May 26 01:29:29 PM PDT 24
Peak memory 248704 kb
Host smart-1f81c89e-efe8-4814-8b75-251dbb2279b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892841591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.3892841591
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.1927090328
Short name T577
Test name
Test status
Simulation time 198890428 ps
CPU time 6.21 seconds
Started May 26 01:28:42 PM PDT 24
Finished May 26 01:28:50 PM PDT 24
Peak memory 242064 kb
Host smart-a4bca2e3-85db-4ccb-8fc5-8c5a47f55e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927090328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.1927090328
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.480754593
Short name T450
Test name
Test status
Simulation time 134018306 ps
CPU time 3.63 seconds
Started May 26 01:28:41 PM PDT 24
Finished May 26 01:28:46 PM PDT 24
Peak memory 241900 kb
Host smart-57bcea31-cdbd-4f4f-af34-53acab8233d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480754593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.480754593
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.2291715932
Short name T831
Test name
Test status
Simulation time 611801548 ps
CPU time 5.73 seconds
Started May 26 01:28:42 PM PDT 24
Finished May 26 01:28:49 PM PDT 24
Peak memory 241892 kb
Host smart-a4277971-4b5a-4da3-88b5-bcb7df3d368d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2291715932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.2291715932
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.2274985830
Short name T994
Test name
Test status
Simulation time 453598976 ps
CPU time 8.22 seconds
Started May 26 01:28:40 PM PDT 24
Finished May 26 01:28:49 PM PDT 24
Peak memory 242048 kb
Host smart-9f675944-b2cc-41d6-96ca-27542d96a0ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2274985830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.2274985830
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.162585497
Short name T105
Test name
Test status
Simulation time 741508089 ps
CPU time 5.99 seconds
Started May 26 01:28:45 PM PDT 24
Finished May 26 01:28:52 PM PDT 24
Peak memory 241896 kb
Host smart-94e6c8e5-bac7-4913-8d39-25aa514d236d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162585497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.162585497
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.4215519209
Short name T950
Test name
Test status
Simulation time 3287969181 ps
CPU time 130.22 seconds
Started May 26 01:28:42 PM PDT 24
Finished May 26 01:30:54 PM PDT 24
Peak memory 257052 kb
Host smart-e3b6d83e-f96f-4983-a67a-f125c14c5cfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215519209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.4215519209
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.1955069685
Short name T373
Test name
Test status
Simulation time 624548137758 ps
CPU time 948.95 seconds
Started May 26 01:28:42 PM PDT 24
Finished May 26 01:44:33 PM PDT 24
Peak memory 364800 kb
Host smart-8cef8163-99f5-49aa-8112-55e693621d06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955069685 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.1955069685
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.3498494850
Short name T1029
Test name
Test status
Simulation time 1489456269 ps
CPU time 32.03 seconds
Started May 26 01:28:40 PM PDT 24
Finished May 26 01:29:14 PM PDT 24
Peak memory 242364 kb
Host smart-7c94398e-606b-4e29-a5ea-ad9d4c97e1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498494850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.3498494850
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.589404887
Short name T571
Test name
Test status
Simulation time 630973440 ps
CPU time 1.99 seconds
Started May 26 01:28:51 PM PDT 24
Finished May 26 01:28:55 PM PDT 24
Peak memory 240592 kb
Host smart-f59f086b-a86a-46ff-ac5c-1ed90c842594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589404887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.589404887
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.1062075307
Short name T120
Test name
Test status
Simulation time 235296496 ps
CPU time 6.68 seconds
Started May 26 01:28:51 PM PDT 24
Finished May 26 01:28:59 PM PDT 24
Peak memory 242872 kb
Host smart-6d5a05e4-d711-4a6e-8468-a37914185d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062075307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.1062075307
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.1272494501
Short name T1008
Test name
Test status
Simulation time 1491628538 ps
CPU time 11.77 seconds
Started May 26 01:28:54 PM PDT 24
Finished May 26 01:29:06 PM PDT 24
Peak memory 242116 kb
Host smart-25429405-485b-4ccb-8d7a-35e57f6eb131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272494501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.1272494501
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.3554011298
Short name T949
Test name
Test status
Simulation time 164769515 ps
CPU time 4.13 seconds
Started May 26 01:28:51 PM PDT 24
Finished May 26 01:28:56 PM PDT 24
Peak memory 242400 kb
Host smart-172f1a72-2112-4986-8909-63e481591e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554011298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.3554011298
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.3023524914
Short name T535
Test name
Test status
Simulation time 2042802435 ps
CPU time 5.88 seconds
Started May 26 01:28:50 PM PDT 24
Finished May 26 01:28:57 PM PDT 24
Peak memory 242356 kb
Host smart-5e7e46de-87f6-4719-8582-3ec6d598b5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023524914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.3023524914
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.62622842
Short name T210
Test name
Test status
Simulation time 2495829479 ps
CPU time 29.98 seconds
Started May 26 01:28:51 PM PDT 24
Finished May 26 01:29:22 PM PDT 24
Peak memory 245540 kb
Host smart-da683cdb-e3cc-45dc-8f4e-c8d0352d1f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62622842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.62622842
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.1005808018
Short name T165
Test name
Test status
Simulation time 734230237 ps
CPU time 13.97 seconds
Started May 26 01:28:52 PM PDT 24
Finished May 26 01:29:07 PM PDT 24
Peak memory 241964 kb
Host smart-1c29090c-5880-49f0-9255-090584ff3ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005808018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1005808018
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.83294035
Short name T948
Test name
Test status
Simulation time 568185406 ps
CPU time 8.85 seconds
Started May 26 01:28:54 PM PDT 24
Finished May 26 01:29:04 PM PDT 24
Peak memory 242016 kb
Host smart-450c35fd-e469-4157-af98-683f12011168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83294035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.83294035
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.2370521059
Short name T830
Test name
Test status
Simulation time 681571108 ps
CPU time 16.94 seconds
Started May 26 01:28:50 PM PDT 24
Finished May 26 01:29:08 PM PDT 24
Peak memory 241848 kb
Host smart-7ed97e03-e878-41d0-803b-aa0d4b5a2171
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2370521059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.2370521059
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.3987450686
Short name T215
Test name
Test status
Simulation time 611890028 ps
CPU time 5.75 seconds
Started May 26 01:28:51 PM PDT 24
Finished May 26 01:28:58 PM PDT 24
Peak memory 242048 kb
Host smart-aa734ffe-7af0-4583-80a5-7d7ec5fe5e96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3987450686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.3987450686
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.498394953
Short name T482
Test name
Test status
Simulation time 2901137802 ps
CPU time 6.01 seconds
Started May 26 01:28:49 PM PDT 24
Finished May 26 01:28:57 PM PDT 24
Peak memory 241948 kb
Host smart-d373309b-8cf9-49bd-bacf-ea800df038bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498394953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.498394953
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.963333100
Short name T312
Test name
Test status
Simulation time 47672255613 ps
CPU time 368.43 seconds
Started May 26 01:28:51 PM PDT 24
Finished May 26 01:35:00 PM PDT 24
Peak memory 277476 kb
Host smart-25975a63-184b-4f1e-8f06-d3ce8ac5e9fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963333100 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.963333100
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.2874380730
Short name T214
Test name
Test status
Simulation time 606121367 ps
CPU time 7.15 seconds
Started May 26 01:28:51 PM PDT 24
Finished May 26 01:28:59 PM PDT 24
Peak memory 248692 kb
Host smart-f9c10ef3-88e9-4711-bdd0-bbdfba2fda4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874380730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.2874380730
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.2349696937
Short name T769
Test name
Test status
Simulation time 785665808 ps
CPU time 2.74 seconds
Started May 26 01:28:58 PM PDT 24
Finished May 26 01:29:02 PM PDT 24
Peak memory 240644 kb
Host smart-7db8b729-81f0-43bc-944c-67ebd6042896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349696937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.2349696937
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.3554819997
Short name T717
Test name
Test status
Simulation time 1826956049 ps
CPU time 35.29 seconds
Started May 26 01:29:07 PM PDT 24
Finished May 26 01:29:43 PM PDT 24
Peak memory 242000 kb
Host smart-b77b00a7-846e-4bb6-8865-30a08889ff43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554819997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.3554819997
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.3848826083
Short name T155
Test name
Test status
Simulation time 359852001 ps
CPU time 10.76 seconds
Started May 26 01:28:58 PM PDT 24
Finished May 26 01:29:09 PM PDT 24
Peak memory 242332 kb
Host smart-2b954f69-2536-4672-bddd-3a44d52f9d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848826083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.3848826083
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.1535676295
Short name T103
Test name
Test status
Simulation time 623685146 ps
CPU time 7.09 seconds
Started May 26 01:28:58 PM PDT 24
Finished May 26 01:29:06 PM PDT 24
Peak memory 241960 kb
Host smart-d6ce1ab7-2f3f-4c4c-a5cd-44f27f04ceaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535676295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.1535676295
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.865653337
Short name T563
Test name
Test status
Simulation time 530950991 ps
CPU time 4.84 seconds
Started May 26 01:28:52 PM PDT 24
Finished May 26 01:28:58 PM PDT 24
Peak memory 242084 kb
Host smart-2a153310-026f-4a2c-8c05-31a6e70e09d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865653337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.865653337
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.3874543206
Short name T853
Test name
Test status
Simulation time 4958541570 ps
CPU time 45.82 seconds
Started May 26 01:28:59 PM PDT 24
Finished May 26 01:29:46 PM PDT 24
Peak memory 257012 kb
Host smart-520520de-dd60-4aed-81d1-35236776481a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874543206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.3874543206
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.43777552
Short name T555
Test name
Test status
Simulation time 11030085069 ps
CPU time 37.07 seconds
Started May 26 01:28:58 PM PDT 24
Finished May 26 01:29:37 PM PDT 24
Peak memory 243044 kb
Host smart-8ca2272d-605a-438a-9365-8876698a4737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43777552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.43777552
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.1903373283
Short name T335
Test name
Test status
Simulation time 366236452 ps
CPU time 5.6 seconds
Started May 26 01:29:00 PM PDT 24
Finished May 26 01:29:06 PM PDT 24
Peak memory 241960 kb
Host smart-5ee4fbc3-aa5d-4c87-a7ee-fbe131e50232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903373283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.1903373283
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.2753859030
Short name T601
Test name
Test status
Simulation time 915480331 ps
CPU time 15.55 seconds
Started May 26 01:28:57 PM PDT 24
Finished May 26 01:29:13 PM PDT 24
Peak memory 241904 kb
Host smart-4b986369-744c-4fa3-b0e0-f97c06dbce31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2753859030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.2753859030
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.4263728073
Short name T521
Test name
Test status
Simulation time 255046168 ps
CPU time 7.49 seconds
Started May 26 01:29:07 PM PDT 24
Finished May 26 01:29:15 PM PDT 24
Peak memory 241892 kb
Host smart-48d85115-8276-4afe-b464-9f3ec63ea8a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4263728073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.4263728073
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.237154368
Short name T1184
Test name
Test status
Simulation time 331049272 ps
CPU time 7.74 seconds
Started May 26 01:28:52 PM PDT 24
Finished May 26 01:29:01 PM PDT 24
Peak memory 242204 kb
Host smart-824126f5-9f18-4d0a-a3f2-7024808de85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237154368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.237154368
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.542975785
Short name T962
Test name
Test status
Simulation time 34246356557 ps
CPU time 276.98 seconds
Started May 26 01:28:58 PM PDT 24
Finished May 26 01:33:37 PM PDT 24
Peak memory 256972 kb
Host smart-1b4b65c6-c2ef-409b-85c5-361c93f53a69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542975785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.
542975785
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.1223342711
Short name T270
Test name
Test status
Simulation time 57711383223 ps
CPU time 917.36 seconds
Started May 26 01:28:58 PM PDT 24
Finished May 26 01:44:16 PM PDT 24
Peak memory 309732 kb
Host smart-8bf510b7-6802-4677-92f0-1ffbd7ae56cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223342711 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.1223342711
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.4177511329
Short name T426
Test name
Test status
Simulation time 806916666 ps
CPU time 20.3 seconds
Started May 26 01:29:01 PM PDT 24
Finished May 26 01:29:22 PM PDT 24
Peak memory 241780 kb
Host smart-d9bfbbaf-fca4-47f0-8d81-01ad0a84a389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177511329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.4177511329
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.1610361634
Short name T410
Test name
Test status
Simulation time 206702614 ps
CPU time 1.68 seconds
Started May 26 01:29:10 PM PDT 24
Finished May 26 01:29:12 PM PDT 24
Peak memory 240916 kb
Host smart-e01885cd-96af-4d5c-985e-5b4e9ac8ac05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610361634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.1610361634
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.4267314828
Short name T109
Test name
Test status
Simulation time 2856650085 ps
CPU time 19.73 seconds
Started May 26 01:29:06 PM PDT 24
Finished May 26 01:29:27 PM PDT 24
Peak memory 245432 kb
Host smart-ac8aa2e2-1a52-49d3-9886-b983482f4444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267314828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.4267314828
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.4032205249
Short name T338
Test name
Test status
Simulation time 23159531176 ps
CPU time 54.22 seconds
Started May 26 01:29:12 PM PDT 24
Finished May 26 01:30:07 PM PDT 24
Peak memory 255336 kb
Host smart-043e77ce-a5b9-4202-ba6b-20eef9333a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032205249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.4032205249
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.2695015875
Short name T468
Test name
Test status
Simulation time 4256752412 ps
CPU time 22.85 seconds
Started May 26 01:28:59 PM PDT 24
Finished May 26 01:29:23 PM PDT 24
Peak memory 242144 kb
Host smart-fd542e3d-8421-4bed-a3c3-848b94b79632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695015875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.2695015875
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.3645361693
Short name T590
Test name
Test status
Simulation time 119772910 ps
CPU time 3.52 seconds
Started May 26 01:29:00 PM PDT 24
Finished May 26 01:29:04 PM PDT 24
Peak memory 242100 kb
Host smart-8823d06d-7e8e-4b00-98cb-8455934c0920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645361693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.3645361693
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.1265017416
Short name T817
Test name
Test status
Simulation time 768741448 ps
CPU time 13.91 seconds
Started May 26 01:29:11 PM PDT 24
Finished May 26 01:29:26 PM PDT 24
Peak memory 248764 kb
Host smart-87a58bc3-4914-4894-9a9b-66b9159f9c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265017416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.1265017416
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.3916979266
Short name T619
Test name
Test status
Simulation time 627780615 ps
CPU time 9.17 seconds
Started May 26 01:29:10 PM PDT 24
Finished May 26 01:29:20 PM PDT 24
Peak memory 242344 kb
Host smart-bee29ea9-c380-4c0d-9e14-819642f61229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916979266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.3916979266
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.1665847632
Short name T382
Test name
Test status
Simulation time 569114491 ps
CPU time 8.14 seconds
Started May 26 01:28:59 PM PDT 24
Finished May 26 01:29:08 PM PDT 24
Peak memory 242280 kb
Host smart-a0bca712-1fc2-4bd9-b98d-11a6918953bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665847632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.1665847632
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.2206450517
Short name T3
Test name
Test status
Simulation time 171516846 ps
CPU time 4.86 seconds
Started May 26 01:29:00 PM PDT 24
Finished May 26 01:29:05 PM PDT 24
Peak memory 241928 kb
Host smart-7cd88eca-76c4-4b9d-a979-e7f5b2299748
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2206450517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.2206450517
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.556027428
Short name T1103
Test name
Test status
Simulation time 266567151 ps
CPU time 4.36 seconds
Started May 26 01:29:11 PM PDT 24
Finished May 26 01:29:16 PM PDT 24
Peak memory 242052 kb
Host smart-5214aeab-c0c7-4ecc-9ba2-c00aa562d805
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=556027428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.556027428
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.2519075929
Short name T205
Test name
Test status
Simulation time 625789299 ps
CPU time 7.27 seconds
Started May 26 01:28:58 PM PDT 24
Finished May 26 01:29:07 PM PDT 24
Peak memory 241936 kb
Host smart-90a5a43b-6631-4567-842d-98560b8d724d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519075929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.2519075929
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.1919787165
Short name T743
Test name
Test status
Simulation time 34703749897 ps
CPU time 505.39 seconds
Started May 26 01:29:08 PM PDT 24
Finished May 26 01:37:35 PM PDT 24
Peak memory 279816 kb
Host smart-69981061-110d-4a63-80ce-cd9b1ba245ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919787165 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.1919787165
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.3397733780
Short name T369
Test name
Test status
Simulation time 8684021240 ps
CPU time 17.1 seconds
Started May 26 01:29:07 PM PDT 24
Finished May 26 01:29:25 PM PDT 24
Peak memory 248708 kb
Host smart-5fc044e8-6c49-4b6c-8715-e97013864869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397733780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.3397733780
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.3141528750
Short name T1158
Test name
Test status
Simulation time 227722484 ps
CPU time 1.86 seconds
Started May 26 01:29:21 PM PDT 24
Finished May 26 01:29:24 PM PDT 24
Peak memory 240820 kb
Host smart-e57c73ad-4da6-44af-946d-ac89efbf85a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141528750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.3141528750
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.760768480
Short name T55
Test name
Test status
Simulation time 2049953293 ps
CPU time 15.26 seconds
Started May 26 01:29:08 PM PDT 24
Finished May 26 01:29:25 PM PDT 24
Peak memory 248812 kb
Host smart-53fccc09-278b-4287-8502-dba32ced8cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760768480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.760768480
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.2502948875
Short name T485
Test name
Test status
Simulation time 232696776 ps
CPU time 11.56 seconds
Started May 26 01:29:10 PM PDT 24
Finished May 26 01:29:22 PM PDT 24
Peak memory 242312 kb
Host smart-eb8dd564-e8a1-4674-9ae2-98aba05b872e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502948875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.2502948875
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.1671307254
Short name T511
Test name
Test status
Simulation time 21626568048 ps
CPU time 38.31 seconds
Started May 26 01:29:06 PM PDT 24
Finished May 26 01:29:45 PM PDT 24
Peak memory 243928 kb
Host smart-4e4211dd-df21-4bf9-baf5-303b11aae1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671307254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.1671307254
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.4052168255
Short name T1140
Test name
Test status
Simulation time 141597869 ps
CPU time 4.73 seconds
Started May 26 01:29:12 PM PDT 24
Finished May 26 01:29:18 PM PDT 24
Peak memory 242320 kb
Host smart-f00220ec-e544-464a-be2d-495c5337c58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052168255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.4052168255
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.1325187681
Short name T621
Test name
Test status
Simulation time 285697811 ps
CPU time 8.51 seconds
Started May 26 01:29:09 PM PDT 24
Finished May 26 01:29:18 PM PDT 24
Peak memory 248856 kb
Host smart-8f9d9dd5-b0a2-485b-84f7-5ad5ea6a289a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325187681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.1325187681
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.2753893988
Short name T661
Test name
Test status
Simulation time 1253732701 ps
CPU time 17.16 seconds
Started May 26 01:29:08 PM PDT 24
Finished May 26 01:29:27 PM PDT 24
Peak memory 242280 kb
Host smart-81051060-9a09-4570-918c-67f19604ba40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753893988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.2753893988
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.541630682
Short name T944
Test name
Test status
Simulation time 936700354 ps
CPU time 15.63 seconds
Started May 26 01:29:11 PM PDT 24
Finished May 26 01:29:28 PM PDT 24
Peak memory 241812 kb
Host smart-60d4c8b4-f51c-45e8-9f30-26b65b45624c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541630682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.541630682
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.4201900153
Short name T243
Test name
Test status
Simulation time 457965428 ps
CPU time 14.78 seconds
Started May 26 01:29:08 PM PDT 24
Finished May 26 01:29:24 PM PDT 24
Peak memory 248712 kb
Host smart-baa6e095-65cd-4e40-a239-9a262eb137b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4201900153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.4201900153
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.2951806833
Short name T537
Test name
Test status
Simulation time 125395915 ps
CPU time 5.11 seconds
Started May 26 01:29:08 PM PDT 24
Finished May 26 01:29:14 PM PDT 24
Peak memory 242168 kb
Host smart-e9c7a3a1-66d1-4b46-b491-d79c76e613db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2951806833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.2951806833
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.1045515365
Short name T663
Test name
Test status
Simulation time 355152476 ps
CPU time 4.38 seconds
Started May 26 01:29:06 PM PDT 24
Finished May 26 01:29:12 PM PDT 24
Peak memory 248680 kb
Host smart-9b034371-537e-4f1b-8356-32c24ce9fa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045515365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.1045515365
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.508735922
Short name T1020
Test name
Test status
Simulation time 19130418217 ps
CPU time 322.15 seconds
Started May 26 01:29:17 PM PDT 24
Finished May 26 01:34:40 PM PDT 24
Peak memory 277884 kb
Host smart-f203944d-dd5a-4a8b-85a9-32ccf80a1396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508735922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.
508735922
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.156634846
Short name T284
Test name
Test status
Simulation time 115896862950 ps
CPU time 1268.6 seconds
Started May 26 01:29:09 PM PDT 24
Finished May 26 01:50:19 PM PDT 24
Peak memory 267676 kb
Host smart-327168bb-e93c-42ab-b188-2bc12cadcb38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156634846 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.156634846
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.1634409085
Short name T1012
Test name
Test status
Simulation time 1407659496 ps
CPU time 22.36 seconds
Started May 26 01:29:09 PM PDT 24
Finished May 26 01:29:33 PM PDT 24
Peak memory 241996 kb
Host smart-c1b079ca-dfe9-40fc-ab6c-023494f684f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634409085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.1634409085
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.52650527
Short name T631
Test name
Test status
Simulation time 54663079 ps
CPU time 1.75 seconds
Started May 26 01:29:20 PM PDT 24
Finished May 26 01:29:22 PM PDT 24
Peak memory 240672 kb
Host smart-b88bd54c-e43a-41a4-8291-f0c4a4c85f70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52650527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.52650527
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.1681313891
Short name T76
Test name
Test status
Simulation time 2647728501 ps
CPU time 14.81 seconds
Started May 26 01:29:18 PM PDT 24
Finished May 26 01:29:34 PM PDT 24
Peak memory 248856 kb
Host smart-2038e61b-237d-4b4c-b480-8576731d48ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681313891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.1681313891
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.3121233742
Short name T507
Test name
Test status
Simulation time 1389649708 ps
CPU time 26.11 seconds
Started May 26 01:29:16 PM PDT 24
Finished May 26 01:29:43 PM PDT 24
Peak memory 242268 kb
Host smart-a77b3762-e735-4535-9a8a-29aada78f6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121233742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.3121233742
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.3930236590
Short name T1131
Test name
Test status
Simulation time 21662617006 ps
CPU time 43.14 seconds
Started May 26 01:29:16 PM PDT 24
Finished May 26 01:30:00 PM PDT 24
Peak memory 243456 kb
Host smart-b9b961e2-927d-46bf-b949-c32f67a20fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930236590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.3930236590
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.3296358189
Short name T219
Test name
Test status
Simulation time 151473012 ps
CPU time 4.58 seconds
Started May 26 01:29:18 PM PDT 24
Finished May 26 01:29:23 PM PDT 24
Peak memory 242008 kb
Host smart-b95fad89-111c-4122-b7ec-32e204f5680f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296358189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.3296358189
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.3548961227
Short name T1178
Test name
Test status
Simulation time 791028020 ps
CPU time 29.51 seconds
Started May 26 01:29:21 PM PDT 24
Finished May 26 01:29:51 PM PDT 24
Peak memory 242700 kb
Host smart-a1450df0-0ea8-4326-9a20-9957e4f78752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548961227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.3548961227
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.3972309327
Short name T394
Test name
Test status
Simulation time 229505660 ps
CPU time 2.95 seconds
Started May 26 01:29:16 PM PDT 24
Finished May 26 01:29:20 PM PDT 24
Peak memory 248756 kb
Host smart-67cc0ee6-d818-4d14-ab9c-dc517f54745a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972309327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.3972309327
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.1042415901
Short name T1014
Test name
Test status
Simulation time 5937723048 ps
CPU time 13.86 seconds
Started May 26 01:29:16 PM PDT 24
Finished May 26 01:29:30 PM PDT 24
Peak memory 242032 kb
Host smart-af113e04-a7ce-44da-970f-b6f218355fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042415901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.1042415901
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.1053945176
Short name T569
Test name
Test status
Simulation time 502046662 ps
CPU time 15.29 seconds
Started May 26 01:29:17 PM PDT 24
Finished May 26 01:29:33 PM PDT 24
Peak memory 241812 kb
Host smart-bd753418-dafb-4f82-b752-09bb9e9a206b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1053945176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.1053945176
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.3603919548
Short name T361
Test name
Test status
Simulation time 939704308 ps
CPU time 8.55 seconds
Started May 26 01:29:16 PM PDT 24
Finished May 26 01:29:26 PM PDT 24
Peak memory 242052 kb
Host smart-37762741-a23a-4236-984d-9dd48e55d568
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3603919548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.3603919548
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.574487378
Short name T1045
Test name
Test status
Simulation time 715312945 ps
CPU time 10.69 seconds
Started May 26 01:29:23 PM PDT 24
Finished May 26 01:29:35 PM PDT 24
Peak memory 241852 kb
Host smart-2533befa-9693-4735-a836-921e5d93a200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574487378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.574487378
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.567237140
Short name T248
Test name
Test status
Simulation time 20128024777 ps
CPU time 198.71 seconds
Started May 26 01:29:16 PM PDT 24
Finished May 26 01:32:36 PM PDT 24
Peak memory 248844 kb
Host smart-ee86070f-51b2-4696-a8a0-78909685aecd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567237140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.
567237140
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.1843208548
Short name T637
Test name
Test status
Simulation time 15272628446 ps
CPU time 434.56 seconds
Started May 26 01:29:23 PM PDT 24
Finished May 26 01:36:39 PM PDT 24
Peak memory 289252 kb
Host smart-e264e1f7-49cd-49cc-b311-261b2e1d73d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843208548 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.1843208548
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.810522087
Short name T605
Test name
Test status
Simulation time 422752819 ps
CPU time 9.07 seconds
Started May 26 01:29:23 PM PDT 24
Finished May 26 01:29:32 PM PDT 24
Peak memory 241968 kb
Host smart-51d72d50-4d9d-4acb-b95e-60fd303dd651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810522087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.810522087
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.939920123
Short name T275
Test name
Test status
Simulation time 81026049 ps
CPU time 2.05 seconds
Started May 26 01:25:09 PM PDT 24
Finished May 26 01:25:12 PM PDT 24
Peak memory 240840 kb
Host smart-2e677fb0-12c8-48d3-a080-7644976733d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939920123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.939920123
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.2825112029
Short name T564
Test name
Test status
Simulation time 3566944560 ps
CPU time 27.27 seconds
Started May 26 01:25:02 PM PDT 24
Finished May 26 01:25:30 PM PDT 24
Peak memory 243136 kb
Host smart-6909d7ac-7869-4266-a922-4ee7876f018c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825112029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.2825112029
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.3350273038
Short name T929
Test name
Test status
Simulation time 1396965357 ps
CPU time 14.39 seconds
Started May 26 01:25:03 PM PDT 24
Finished May 26 01:25:18 PM PDT 24
Peak memory 243552 kb
Host smart-33b70a37-8701-4a14-8264-1ba67748d579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350273038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.3350273038
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.2074088425
Short name T641
Test name
Test status
Simulation time 836728694 ps
CPU time 29.56 seconds
Started May 26 01:25:03 PM PDT 24
Finished May 26 01:25:33 PM PDT 24
Peak memory 243528 kb
Host smart-0e4a676e-bc2c-4eea-bfb4-5a06f4d929a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074088425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.2074088425
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.3897006113
Short name T167
Test name
Test status
Simulation time 830310073 ps
CPU time 19 seconds
Started May 26 01:25:04 PM PDT 24
Finished May 26 01:25:23 PM PDT 24
Peak memory 248672 kb
Host smart-f43e5e95-b63b-4e0d-bbd2-bfa6f54210f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897006113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.3897006113
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.2110103659
Short name T884
Test name
Test status
Simulation time 117340889 ps
CPU time 4.89 seconds
Started May 26 01:25:03 PM PDT 24
Finished May 26 01:25:09 PM PDT 24
Peak memory 242212 kb
Host smart-6f5f2ff0-02f2-4c5f-a8f8-e9527404dbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110103659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.2110103659
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.1266335391
Short name T157
Test name
Test status
Simulation time 1249652126 ps
CPU time 16.02 seconds
Started May 26 01:25:03 PM PDT 24
Finished May 26 01:25:20 PM PDT 24
Peak memory 242500 kb
Host smart-8fc5c27a-7608-430a-9ab4-4dfbe8c1c715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266335391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.1266335391
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.711184919
Short name T979
Test name
Test status
Simulation time 11562603643 ps
CPU time 36.6 seconds
Started May 26 01:25:03 PM PDT 24
Finished May 26 01:25:40 PM PDT 24
Peak memory 243280 kb
Host smart-8a5dd0dc-e95a-48bf-a027-96b79c4a156e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711184919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.711184919
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.1850178947
Short name T851
Test name
Test status
Simulation time 381452368 ps
CPU time 5.82 seconds
Started May 26 01:25:02 PM PDT 24
Finished May 26 01:25:09 PM PDT 24
Peak memory 242344 kb
Host smart-f0fd6d43-8f94-4c99-8218-7e4d932960b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850178947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.1850178947
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.2026313350
Short name T414
Test name
Test status
Simulation time 189566841 ps
CPU time 5.83 seconds
Started May 26 01:25:04 PM PDT 24
Finished May 26 01:25:10 PM PDT 24
Peak memory 241996 kb
Host smart-f44f8d4e-0ce7-4585-925f-1fb76410804e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2026313350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.2026313350
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.3092990467
Short name T675
Test name
Test status
Simulation time 4658507505 ps
CPU time 14.94 seconds
Started May 26 01:25:02 PM PDT 24
Finished May 26 01:25:18 PM PDT 24
Peak memory 242124 kb
Host smart-19bf3ff4-60f4-4308-a981-50c57d65a473
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3092990467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.3092990467
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.1460777964
Short name T19
Test name
Test status
Simulation time 12545156564 ps
CPU time 205.12 seconds
Started May 26 01:25:05 PM PDT 24
Finished May 26 01:28:30 PM PDT 24
Peak memory 280108 kb
Host smart-78e86324-95a5-4fa1-9dca-86b66b2f6bf8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460777964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.1460777964
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.4206618960
Short name T984
Test name
Test status
Simulation time 258521930 ps
CPU time 4.12 seconds
Started May 26 01:25:02 PM PDT 24
Finished May 26 01:25:07 PM PDT 24
Peak memory 248656 kb
Host smart-cb150563-b20b-45eb-9889-b71188fd2421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206618960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.4206618960
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.580487451
Short name T856
Test name
Test status
Simulation time 30537267626 ps
CPU time 128.35 seconds
Started May 26 01:25:09 PM PDT 24
Finished May 26 01:27:18 PM PDT 24
Peak memory 250612 kb
Host smart-d4c06d22-861d-46ef-bb04-8d062955823e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580487451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.580487451
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.4025862822
Short name T289
Test name
Test status
Simulation time 507279576578 ps
CPU time 1666.78 seconds
Started May 26 01:25:09 PM PDT 24
Finished May 26 01:52:57 PM PDT 24
Peak memory 277276 kb
Host smart-b9c4a99c-23c8-4193-a4ef-3b25b5c5db48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025862822 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.4025862822
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.2940578790
Short name T677
Test name
Test status
Simulation time 790257300 ps
CPU time 26.08 seconds
Started May 26 01:25:04 PM PDT 24
Finished May 26 01:25:31 PM PDT 24
Peak memory 242412 kb
Host smart-711448f6-de12-491d-9d85-067fe07169ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940578790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.2940578790
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.3083894157
Short name T174
Test name
Test status
Simulation time 93715253 ps
CPU time 1.55 seconds
Started May 26 01:29:26 PM PDT 24
Finished May 26 01:29:28 PM PDT 24
Peak memory 240628 kb
Host smart-98291dc4-fc0d-42df-af4a-7ff346ad0b2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083894157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.3083894157
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.566411294
Short name T565
Test name
Test status
Simulation time 1273735315 ps
CPU time 8.74 seconds
Started May 26 01:29:23 PM PDT 24
Finished May 26 01:29:33 PM PDT 24
Peak memory 248692 kb
Host smart-ecab3b22-6a6a-4613-ab3b-a257c34c6611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566411294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.566411294
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.607971304
Short name T757
Test name
Test status
Simulation time 1619981655 ps
CPU time 16.64 seconds
Started May 26 01:29:21 PM PDT 24
Finished May 26 01:29:38 PM PDT 24
Peak memory 241908 kb
Host smart-881a7343-8d08-4e4f-9c67-d494c332ee13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607971304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.607971304
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.352370834
Short name T1127
Test name
Test status
Simulation time 27627669201 ps
CPU time 45.46 seconds
Started May 26 01:29:21 PM PDT 24
Finished May 26 01:30:07 PM PDT 24
Peak memory 248728 kb
Host smart-7f97d76a-8fd5-47e7-8808-e9a555d1de39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352370834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.352370834
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.3099278231
Short name T51
Test name
Test status
Simulation time 157711478 ps
CPU time 4.62 seconds
Started May 26 01:29:22 PM PDT 24
Finished May 26 01:29:27 PM PDT 24
Peak memory 242408 kb
Host smart-a973c4b1-1f17-4c17-b2bc-5e7b9c7b4fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099278231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.3099278231
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.3842559793
Short name T598
Test name
Test status
Simulation time 375200236 ps
CPU time 13.12 seconds
Started May 26 01:29:26 PM PDT 24
Finished May 26 01:29:40 PM PDT 24
Peak memory 243640 kb
Host smart-4e366ed3-d4a5-41c6-a478-7744a957c456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842559793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.3842559793
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.630779752
Short name T1086
Test name
Test status
Simulation time 2630102757 ps
CPU time 6.5 seconds
Started May 26 01:29:23 PM PDT 24
Finished May 26 01:29:30 PM PDT 24
Peak memory 248832 kb
Host smart-0939d4ba-6dbf-4930-b6eb-cc38ee763a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630779752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.630779752
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.1504013187
Short name T916
Test name
Test status
Simulation time 202068141 ps
CPU time 6.41 seconds
Started May 26 01:29:23 PM PDT 24
Finished May 26 01:29:31 PM PDT 24
Peak memory 241872 kb
Host smart-b62a24d3-182b-483f-bc3c-9ac2aefe70b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504013187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.1504013187
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.4138030333
Short name T377
Test name
Test status
Simulation time 1787904067 ps
CPU time 25.99 seconds
Started May 26 01:29:17 PM PDT 24
Finished May 26 01:29:43 PM PDT 24
Peak memory 248732 kb
Host smart-a170676e-5fcb-48b3-9c95-aa556cb47cce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4138030333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.4138030333
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.105524217
Short name T1156
Test name
Test status
Simulation time 522821178 ps
CPU time 3.76 seconds
Started May 26 01:29:27 PM PDT 24
Finished May 26 01:29:31 PM PDT 24
Peak memory 242104 kb
Host smart-35fcff3d-d172-454b-b553-4ad26d306de8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105524217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.105524217
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.1571529307
Short name T424
Test name
Test status
Simulation time 4053095709 ps
CPU time 7.07 seconds
Started May 26 01:29:17 PM PDT 24
Finished May 26 01:29:25 PM PDT 24
Peak memory 242268 kb
Host smart-8a0fb850-d573-4fb8-aed9-63de6b715ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571529307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.1571529307
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.993662122
Short name T763
Test name
Test status
Simulation time 57367574149 ps
CPU time 240.3 seconds
Started May 26 01:29:25 PM PDT 24
Finished May 26 01:33:27 PM PDT 24
Peak memory 296600 kb
Host smart-64b4210f-daff-45b2-a105-bdfa74bfec12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993662122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.
993662122
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.2539710398
Short name T927
Test name
Test status
Simulation time 3604323502 ps
CPU time 30.33 seconds
Started May 26 01:29:24 PM PDT 24
Finished May 26 01:29:55 PM PDT 24
Peak memory 241984 kb
Host smart-1b999a8b-dfb2-462e-87ac-e0c6b835fb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539710398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.2539710398
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.1193212139
Short name T1106
Test name
Test status
Simulation time 755853725 ps
CPU time 2.05 seconds
Started May 26 01:29:32 PM PDT 24
Finished May 26 01:29:34 PM PDT 24
Peak memory 240612 kb
Host smart-2ad1f3ee-4a51-4965-a7a3-1120dca23356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193212139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.1193212139
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.2460431765
Short name T57
Test name
Test status
Simulation time 9326066777 ps
CPU time 40.63 seconds
Started May 26 01:29:25 PM PDT 24
Finished May 26 01:30:07 PM PDT 24
Peak memory 243368 kb
Host smart-6b28941d-507d-4d13-889a-e081397613aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460431765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.2460431765
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.3906235796
Short name T475
Test name
Test status
Simulation time 1786656170 ps
CPU time 15.54 seconds
Started May 26 01:29:25 PM PDT 24
Finished May 26 01:29:41 PM PDT 24
Peak memory 242172 kb
Host smart-c7b57a89-a679-44f1-8523-c548e63065a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906235796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.3906235796
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.3891540356
Short name T591
Test name
Test status
Simulation time 2563769679 ps
CPU time 15.78 seconds
Started May 26 01:29:24 PM PDT 24
Finished May 26 01:29:41 PM PDT 24
Peak memory 242472 kb
Host smart-4cdc835f-ff9f-4c57-af18-c79a00470d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891540356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.3891540356
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.2095580651
Short name T679
Test name
Test status
Simulation time 638475565 ps
CPU time 3.95 seconds
Started May 26 01:29:24 PM PDT 24
Finished May 26 01:29:29 PM PDT 24
Peak memory 242128 kb
Host smart-fda31ada-a214-4fcd-a5bd-9745e0b19360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095580651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.2095580651
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.316081556
Short name T332
Test name
Test status
Simulation time 843887391 ps
CPU time 14.86 seconds
Started May 26 01:29:25 PM PDT 24
Finished May 26 01:29:41 PM PDT 24
Peak memory 242632 kb
Host smart-2879de24-1a73-4f09-873b-dc4a493c26d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316081556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.316081556
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.1328739337
Short name T841
Test name
Test status
Simulation time 560508181 ps
CPU time 8.37 seconds
Started May 26 01:29:23 PM PDT 24
Finished May 26 01:29:32 PM PDT 24
Peak memory 241980 kb
Host smart-b9b27208-509f-4764-81b1-900d8923e39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328739337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.1328739337
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.579788323
Short name T602
Test name
Test status
Simulation time 641402536 ps
CPU time 19.45 seconds
Started May 26 01:29:26 PM PDT 24
Finished May 26 01:29:46 PM PDT 24
Peak memory 242020 kb
Host smart-07805f62-0572-4459-a5ce-1429f76b0649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579788323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.579788323
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.2811290704
Short name T100
Test name
Test status
Simulation time 365286520 ps
CPU time 12.36 seconds
Started May 26 01:29:27 PM PDT 24
Finished May 26 01:29:40 PM PDT 24
Peak memory 242012 kb
Host smart-6c63277c-c34f-498f-83ff-438ba825828c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2811290704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.2811290704
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.3820980016
Short name T357
Test name
Test status
Simulation time 448049520 ps
CPU time 7.58 seconds
Started May 26 01:29:23 PM PDT 24
Finished May 26 01:29:32 PM PDT 24
Peak memory 242044 kb
Host smart-14958b06-6728-4864-be74-9292e97f20b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3820980016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.3820980016
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.2915746848
Short name T399
Test name
Test status
Simulation time 407709224 ps
CPU time 4.34 seconds
Started May 26 01:29:26 PM PDT 24
Finished May 26 01:29:31 PM PDT 24
Peak memory 241840 kb
Host smart-7c6d6d15-a3b7-4b9f-b44c-2c90bc5b5174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915746848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.2915746848
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.3868038423
Short name T116
Test name
Test status
Simulation time 2857684298 ps
CPU time 94.66 seconds
Started May 26 01:29:34 PM PDT 24
Finished May 26 01:31:09 PM PDT 24
Peak memory 248872 kb
Host smart-0d0c86db-88e1-4b23-9878-1c9c37bf65dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868038423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.3868038423
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.3072803629
Short name T203
Test name
Test status
Simulation time 27756095831 ps
CPU time 586.62 seconds
Started May 26 01:29:34 PM PDT 24
Finished May 26 01:39:21 PM PDT 24
Peak memory 259080 kb
Host smart-99365a8c-9e43-47c1-a42a-6158e228c2de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072803629 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.3072803629
Directory /workspace/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.1848519911
Short name T7
Test name
Test status
Simulation time 2863022307 ps
CPU time 20.87 seconds
Started May 26 01:29:33 PM PDT 24
Finished May 26 01:29:54 PM PDT 24
Peak memory 242084 kb
Host smart-f3e266f4-5b91-438c-a9cb-06632d51f93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848519911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.1848519911
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.3670839114
Short name T653
Test name
Test status
Simulation time 67328623 ps
CPU time 1.81 seconds
Started May 26 01:29:47 PM PDT 24
Finished May 26 01:29:49 PM PDT 24
Peak memory 240596 kb
Host smart-323879d7-1306-4024-a2d6-b1839241f2c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670839114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.3670839114
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.308239448
Short name T238
Test name
Test status
Simulation time 592620496 ps
CPU time 9.35 seconds
Started May 26 01:29:40 PM PDT 24
Finished May 26 01:29:50 PM PDT 24
Peak memory 248820 kb
Host smart-b3afb529-6e74-47c9-bcb4-f9f2cb52ce23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308239448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.308239448
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.3742588285
Short name T523
Test name
Test status
Simulation time 1016462663 ps
CPU time 15.76 seconds
Started May 26 01:29:32 PM PDT 24
Finished May 26 01:29:48 PM PDT 24
Peak memory 241924 kb
Host smart-57eaf64a-be3b-4cc3-93e2-36a6b8379d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742588285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.3742588285
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.114974755
Short name T729
Test name
Test status
Simulation time 1443581858 ps
CPU time 10.88 seconds
Started May 26 01:29:36 PM PDT 24
Finished May 26 01:29:48 PM PDT 24
Peak memory 241996 kb
Host smart-33e560a9-7bbc-4ed2-93d6-4d5457aa7c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114974755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.114974755
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.549088010
Short name T983
Test name
Test status
Simulation time 1601753944 ps
CPU time 5.13 seconds
Started May 26 01:29:34 PM PDT 24
Finished May 26 01:29:40 PM PDT 24
Peak memory 242140 kb
Host smart-62513951-af43-4468-9ab0-78264875fc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549088010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.549088010
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.1221546786
Short name T1182
Test name
Test status
Simulation time 1383901368 ps
CPU time 24.02 seconds
Started May 26 01:29:42 PM PDT 24
Finished May 26 01:30:07 PM PDT 24
Peak memory 244916 kb
Host smart-82e46abb-eb46-4427-be5d-81f300b4cecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221546786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.1221546786
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.316739166
Short name T24
Test name
Test status
Simulation time 2613936413 ps
CPU time 16.6 seconds
Started May 26 01:29:41 PM PDT 24
Finished May 26 01:29:59 PM PDT 24
Peak memory 242104 kb
Host smart-c3e3e070-cb6c-4f6c-b54e-bc6ba3d22201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316739166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.316739166
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.524020882
Short name T138
Test name
Test status
Simulation time 2397182433 ps
CPU time 6.76 seconds
Started May 26 01:29:34 PM PDT 24
Finished May 26 01:29:41 PM PDT 24
Peak memory 248248 kb
Host smart-2f7ddf79-08e2-4c9b-a26d-71a68f37fe99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524020882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.524020882
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.3256643851
Short name T374
Test name
Test status
Simulation time 852118378 ps
CPU time 26.62 seconds
Started May 26 01:29:34 PM PDT 24
Finished May 26 01:30:01 PM PDT 24
Peak memory 242144 kb
Host smart-c6814762-2e78-480f-97f1-be5ff610ed10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3256643851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.3256643851
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.3478399879
Short name T768
Test name
Test status
Simulation time 147954478 ps
CPU time 4.64 seconds
Started May 26 01:29:42 PM PDT 24
Finished May 26 01:29:47 PM PDT 24
Peak memory 242308 kb
Host smart-22614f14-8a33-4eee-8ee7-a52e51edf3e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3478399879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.3478399879
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.803120765
Short name T655
Test name
Test status
Simulation time 168405525 ps
CPU time 4.4 seconds
Started May 26 01:29:32 PM PDT 24
Finished May 26 01:29:37 PM PDT 24
Peak memory 242324 kb
Host smart-20f0276d-d995-43ca-874c-cd8b4db7a5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803120765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.803120765
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.124791326
Short name T1144
Test name
Test status
Simulation time 87614342707 ps
CPU time 249.73 seconds
Started May 26 01:29:41 PM PDT 24
Finished May 26 01:33:51 PM PDT 24
Peak memory 262148 kb
Host smart-d65177d8-198c-47aa-89a1-0ad47b5e0545
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124791326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.
124791326
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.1287336357
Short name T647
Test name
Test status
Simulation time 2219244013 ps
CPU time 28.31 seconds
Started May 26 01:29:42 PM PDT 24
Finished May 26 01:30:11 PM PDT 24
Peak memory 242092 kb
Host smart-b83390c9-afa6-4a40-b603-aec79e19114f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287336357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.1287336357
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.945578795
Short name T956
Test name
Test status
Simulation time 132297580 ps
CPU time 2.76 seconds
Started May 26 01:29:52 PM PDT 24
Finished May 26 01:29:56 PM PDT 24
Peak memory 240936 kb
Host smart-a6d555fa-59f9-476f-9ea9-a88cd2ce6a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945578795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.945578795
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.84598212
Short name T1118
Test name
Test status
Simulation time 556001726 ps
CPU time 7.18 seconds
Started May 26 01:29:40 PM PDT 24
Finished May 26 01:29:48 PM PDT 24
Peak memory 242324 kb
Host smart-177c7adc-9b79-419f-bcc4-fc19a852b92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84598212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.84598212
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.4127975624
Short name T952
Test name
Test status
Simulation time 598283962 ps
CPU time 17 seconds
Started May 26 01:29:40 PM PDT 24
Finished May 26 01:29:59 PM PDT 24
Peak memory 242080 kb
Host smart-e7d24593-8362-4992-8391-ce745222464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127975624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.4127975624
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.208214690
Short name T793
Test name
Test status
Simulation time 557721225 ps
CPU time 13.57 seconds
Started May 26 01:29:41 PM PDT 24
Finished May 26 01:29:56 PM PDT 24
Peak memory 242324 kb
Host smart-eb524815-e839-4e05-ba0a-509d93189210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208214690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.208214690
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.2331600522
Short name T111
Test name
Test status
Simulation time 130581429 ps
CPU time 3.15 seconds
Started May 26 01:29:42 PM PDT 24
Finished May 26 01:29:46 PM PDT 24
Peak memory 242348 kb
Host smart-9ca53d78-a736-4d2c-9d89-d748bf5e5ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331600522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.2331600522
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.3559593954
Short name T726
Test name
Test status
Simulation time 201163457 ps
CPU time 5.55 seconds
Started May 26 01:29:43 PM PDT 24
Finished May 26 01:29:49 PM PDT 24
Peak memory 248712 kb
Host smart-7681534d-a7c8-46c9-9c5d-5e2ba6bae122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559593954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.3559593954
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.3981401349
Short name T416
Test name
Test status
Simulation time 4018394683 ps
CPU time 31.47 seconds
Started May 26 01:29:40 PM PDT 24
Finished May 26 01:30:12 PM PDT 24
Peak memory 242236 kb
Host smart-d334a76a-fc01-4f9e-9532-e8ba4d6ff0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981401349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.3981401349
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.2791376841
Short name T890
Test name
Test status
Simulation time 458244893 ps
CPU time 11.61 seconds
Started May 26 01:29:41 PM PDT 24
Finished May 26 01:29:54 PM PDT 24
Peak memory 242284 kb
Host smart-96f78699-54d8-4f94-9f1b-0d36a2f25759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791376841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.2791376841
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.3687600356
Short name T311
Test name
Test status
Simulation time 2122090747 ps
CPU time 20.92 seconds
Started May 26 01:29:40 PM PDT 24
Finished May 26 01:30:02 PM PDT 24
Peak memory 241960 kb
Host smart-cfc4e4fb-c7d5-44b2-b17b-54cc3238bb3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3687600356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.3687600356
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.639202681
Short name T411
Test name
Test status
Simulation time 378998067 ps
CPU time 4.68 seconds
Started May 26 01:29:40 PM PDT 24
Finished May 26 01:29:45 PM PDT 24
Peak memory 242100 kb
Host smart-f4be6786-37c6-428b-aba5-0bf3ac6f1c34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=639202681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.639202681
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.504487479
Short name T980
Test name
Test status
Simulation time 1043646842 ps
CPU time 8.2 seconds
Started May 26 01:29:46 PM PDT 24
Finished May 26 01:29:55 PM PDT 24
Peak memory 242288 kb
Host smart-df0da3af-5683-4841-86ed-f4734d96a5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504487479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.504487479
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.3130144902
Short name T1004
Test name
Test status
Simulation time 8263919269 ps
CPU time 98.18 seconds
Started May 26 01:29:53 PM PDT 24
Finished May 26 01:31:32 PM PDT 24
Peak memory 244724 kb
Host smart-0beb15ec-ba27-4895-9b22-4c90560bdbb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130144902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.3130144902
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.3241933281
Short name T127
Test name
Test status
Simulation time 76348837291 ps
CPU time 515.75 seconds
Started May 26 01:29:55 PM PDT 24
Finished May 26 01:38:31 PM PDT 24
Peak memory 259144 kb
Host smart-74427477-0f8c-4c71-9b10-017fddb2ef65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241933281 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.3241933281
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.97530355
Short name T906
Test name
Test status
Simulation time 644241605 ps
CPU time 11.35 seconds
Started May 26 01:29:54 PM PDT 24
Finished May 26 01:30:06 PM PDT 24
Peak memory 241864 kb
Host smart-ce3b1398-0899-402c-8742-36b9d4c55cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97530355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.97530355
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.74609884
Short name T527
Test name
Test status
Simulation time 824156753 ps
CPU time 2.72 seconds
Started May 26 01:30:05 PM PDT 24
Finished May 26 01:30:09 PM PDT 24
Peak memory 240420 kb
Host smart-1a48caeb-85cb-4a21-b985-c373c693ea62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74609884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.74609884
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.2876653317
Short name T84
Test name
Test status
Simulation time 636992908 ps
CPU time 15.41 seconds
Started May 26 01:29:54 PM PDT 24
Finished May 26 01:30:10 PM PDT 24
Peak memory 242324 kb
Host smart-3e9edaa9-beb8-4b9d-b738-87fafb6cc96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876653317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.2876653317
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.990004733
Short name T402
Test name
Test status
Simulation time 4327662785 ps
CPU time 19.66 seconds
Started May 26 01:29:57 PM PDT 24
Finished May 26 01:30:17 PM PDT 24
Peak memory 242352 kb
Host smart-72b2b69d-1864-4a63-9d9c-135ab7d0773a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990004733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.990004733
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.2764341427
Short name T366
Test name
Test status
Simulation time 12621323905 ps
CPU time 25.62 seconds
Started May 26 01:29:53 PM PDT 24
Finished May 26 01:30:20 PM PDT 24
Peak memory 241996 kb
Host smart-7568fd6c-6c6b-44b2-af3f-5c01abb79283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764341427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.2764341427
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.157758826
Short name T517
Test name
Test status
Simulation time 151334138 ps
CPU time 4.77 seconds
Started May 26 01:29:53 PM PDT 24
Finished May 26 01:29:59 PM PDT 24
Peak memory 242088 kb
Host smart-1b0420eb-ebb9-43cb-977f-7a80f295909a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157758826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.157758826
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.2596437595
Short name T150
Test name
Test status
Simulation time 1892626960 ps
CPU time 37.61 seconds
Started May 26 01:29:52 PM PDT 24
Finished May 26 01:30:31 PM PDT 24
Peak memory 243920 kb
Host smart-68f6b86f-d331-43d3-8ef7-50a53a6c176b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596437595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.2596437595
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.3626938137
Short name T1173
Test name
Test status
Simulation time 193252870 ps
CPU time 5.79 seconds
Started May 26 01:29:53 PM PDT 24
Finished May 26 01:29:59 PM PDT 24
Peak memory 242352 kb
Host smart-a4981e28-4b9e-4010-b53b-190440e523bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626938137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.3626938137
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.94918879
Short name T123
Test name
Test status
Simulation time 277336684 ps
CPU time 13.6 seconds
Started May 26 01:29:52 PM PDT 24
Finished May 26 01:30:06 PM PDT 24
Peak memory 242096 kb
Host smart-dc5330ea-68bd-4194-8e07-96b2280adc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94918879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.94918879
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.15728853
Short name T592
Test name
Test status
Simulation time 1265795683 ps
CPU time 10.14 seconds
Started May 26 01:29:56 PM PDT 24
Finished May 26 01:30:07 PM PDT 24
Peak memory 241796 kb
Host smart-dcde6ce9-ace7-4454-85bf-5f75e6b5c099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15728853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.15728853
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.2886373035
Short name T362
Test name
Test status
Simulation time 300229159 ps
CPU time 14.06 seconds
Started May 26 01:29:54 PM PDT 24
Finished May 26 01:30:09 PM PDT 24
Peak memory 242048 kb
Host smart-cee20760-2f23-4a52-b33a-46d38da40460
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2886373035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.2886373035
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.288924110
Short name T388
Test name
Test status
Simulation time 1872052574 ps
CPU time 4.92 seconds
Started May 26 01:29:52 PM PDT 24
Finished May 26 01:29:58 PM PDT 24
Peak memory 242044 kb
Host smart-847615cc-f846-4a63-baa6-03648a025795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288924110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.288924110
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.818145325
Short name T305
Test name
Test status
Simulation time 15202506711 ps
CPU time 162.61 seconds
Started May 26 01:30:05 PM PDT 24
Finished May 26 01:32:48 PM PDT 24
Peak memory 246068 kb
Host smart-b981f1cd-a573-4810-8082-9c0588d921df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818145325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.
818145325
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.1932511590
Short name T252
Test name
Test status
Simulation time 856046226108 ps
CPU time 3663.65 seconds
Started May 26 01:30:07 PM PDT 24
Finished May 26 02:31:12 PM PDT 24
Peak memory 527672 kb
Host smart-83804deb-ad38-49c3-ae27-a08ace3b09b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932511590 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.1932511590
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.3608861383
Short name T767
Test name
Test status
Simulation time 4665429164 ps
CPU time 27.43 seconds
Started May 26 01:29:53 PM PDT 24
Finished May 26 01:30:21 PM PDT 24
Peak memory 242068 kb
Host smart-9ee09ac1-7de4-49cb-ac22-a37bd4ecbd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608861383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.3608861383
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.1633125209
Short name T665
Test name
Test status
Simulation time 46630498 ps
CPU time 1.53 seconds
Started May 26 01:30:07 PM PDT 24
Finished May 26 01:30:09 PM PDT 24
Peak memory 240456 kb
Host smart-be167d06-5c24-446a-9942-a33fe0d02eaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633125209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.1633125209
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.4130110271
Short name T405
Test name
Test status
Simulation time 4112522451 ps
CPU time 10.82 seconds
Started May 26 01:30:04 PM PDT 24
Finished May 26 01:30:16 PM PDT 24
Peak memory 242548 kb
Host smart-54f7b731-66be-4bac-a87f-a000a2ef5760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130110271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.4130110271
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.740710373
Short name T515
Test name
Test status
Simulation time 5073264043 ps
CPU time 17.99 seconds
Started May 26 01:30:04 PM PDT 24
Finished May 26 01:30:23 PM PDT 24
Peak memory 242148 kb
Host smart-cfcb05f4-7831-4b41-97be-7cf4dad195b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740710373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.740710373
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.151264429
Short name T1168
Test name
Test status
Simulation time 505526951 ps
CPU time 19.64 seconds
Started May 26 01:30:07 PM PDT 24
Finished May 26 01:30:28 PM PDT 24
Peak memory 248692 kb
Host smart-7661a033-ff6b-42e8-99ab-bc346e0fc1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151264429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.151264429
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.3058988315
Short name T185
Test name
Test status
Simulation time 1522707950 ps
CPU time 5.01 seconds
Started May 26 01:30:03 PM PDT 24
Finished May 26 01:30:09 PM PDT 24
Peak memory 242424 kb
Host smart-fce41470-c7cd-456d-b447-35f0733b780c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058988315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.3058988315
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.1702373786
Short name T935
Test name
Test status
Simulation time 2144070315 ps
CPU time 22.1 seconds
Started May 26 01:30:04 PM PDT 24
Finished May 26 01:30:27 PM PDT 24
Peak memory 245088 kb
Host smart-d5eb343b-cc46-4d6e-9293-32bcfa7e1d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702373786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.1702373786
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.3659438530
Short name T774
Test name
Test status
Simulation time 627698003 ps
CPU time 9.4 seconds
Started May 26 01:30:03 PM PDT 24
Finished May 26 01:30:14 PM PDT 24
Peak memory 242404 kb
Host smart-e82140a7-6e77-4ebb-b554-e36c61ef31f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659438530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.3659438530
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.3237522134
Short name T873
Test name
Test status
Simulation time 376413264 ps
CPU time 5.77 seconds
Started May 26 01:30:06 PM PDT 24
Finished May 26 01:30:12 PM PDT 24
Peak memory 241932 kb
Host smart-a2f78831-9dc0-4b6b-b3e9-81929a0c0bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237522134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.3237522134
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.1551162971
Short name T1165
Test name
Test status
Simulation time 406555630 ps
CPU time 3.76 seconds
Started May 26 01:30:03 PM PDT 24
Finished May 26 01:30:08 PM PDT 24
Peak memory 241868 kb
Host smart-cc8a75dd-7eb3-42e7-8baa-12265b29be61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1551162971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.1551162971
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.2497484430
Short name T955
Test name
Test status
Simulation time 146391794 ps
CPU time 4.33 seconds
Started May 26 01:30:02 PM PDT 24
Finished May 26 01:30:07 PM PDT 24
Peak memory 242064 kb
Host smart-07aaf18e-ab76-4478-b028-eb2ba8d07a1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2497484430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.2497484430
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.890589900
Short name T473
Test name
Test status
Simulation time 892911321 ps
CPU time 10.24 seconds
Started May 26 01:30:02 PM PDT 24
Finished May 26 01:30:13 PM PDT 24
Peak memory 241976 kb
Host smart-7f779d1e-7b5e-4082-8e3b-83345a98aaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890589900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.890589900
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.584504291
Short name T922
Test name
Test status
Simulation time 500213737512 ps
CPU time 1126.34 seconds
Started May 26 01:30:05 PM PDT 24
Finished May 26 01:48:53 PM PDT 24
Peak memory 429848 kb
Host smart-4c79a572-5368-4527-abf4-bbc849fda69a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584504291 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.584504291
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.3456996173
Short name T1142
Test name
Test status
Simulation time 39098406720 ps
CPU time 52.92 seconds
Started May 26 01:30:07 PM PDT 24
Finished May 26 01:31:01 PM PDT 24
Peak memory 243244 kb
Host smart-b0828fc2-6049-400e-bef0-0591644e8ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456996173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.3456996173
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.472239108
Short name T331
Test name
Test status
Simulation time 56028815 ps
CPU time 1.65 seconds
Started May 26 01:30:16 PM PDT 24
Finished May 26 01:30:18 PM PDT 24
Peak memory 240572 kb
Host smart-15ed3393-bd7b-4cd7-aa28-91c0da42867f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472239108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.472239108
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.3562304582
Short name T25
Test name
Test status
Simulation time 18684634055 ps
CPU time 46.61 seconds
Started May 26 01:30:02 PM PDT 24
Finished May 26 01:30:49 PM PDT 24
Peak memory 246844 kb
Host smart-3d764c90-14e7-4dde-97fe-965bbe26ea73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562304582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.3562304582
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.2691801506
Short name T1034
Test name
Test status
Simulation time 762448678 ps
CPU time 12.72 seconds
Started May 26 01:30:05 PM PDT 24
Finished May 26 01:30:19 PM PDT 24
Peak memory 242316 kb
Host smart-fe34d9ce-74c3-408b-96b5-ca2c1fb8d65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691801506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.2691801506
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.2356514709
Short name T1003
Test name
Test status
Simulation time 2116492979 ps
CPU time 13.41 seconds
Started May 26 01:30:06 PM PDT 24
Finished May 26 01:30:20 PM PDT 24
Peak memory 242600 kb
Host smart-888349f0-4076-44db-b4a1-33ddd6499df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356514709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.2356514709
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.4144742908
Short name T1123
Test name
Test status
Simulation time 150631044 ps
CPU time 4.34 seconds
Started May 26 01:30:06 PM PDT 24
Finished May 26 01:30:11 PM PDT 24
Peak memory 242424 kb
Host smart-31c9fc66-b069-4256-8a97-238261b7ad94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144742908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.4144742908
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.460414719
Short name T491
Test name
Test status
Simulation time 393355705 ps
CPU time 3.66 seconds
Started May 26 01:30:06 PM PDT 24
Finished May 26 01:30:10 PM PDT 24
Peak memory 242192 kb
Host smart-80eac7f0-6623-4d25-a328-ef3cae27326f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460414719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.460414719
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.1966922315
Short name T379
Test name
Test status
Simulation time 1264305347 ps
CPU time 39.73 seconds
Started May 26 01:30:05 PM PDT 24
Finished May 26 01:30:46 PM PDT 24
Peak memory 242236 kb
Host smart-fbd296e6-4a77-46cd-831b-d5bcd0bb8fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966922315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.1966922315
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.108575590
Short name T323
Test name
Test status
Simulation time 245724586 ps
CPU time 3.59 seconds
Started May 26 01:30:03 PM PDT 24
Finished May 26 01:30:07 PM PDT 24
Peak memory 242312 kb
Host smart-cec1c59c-0c29-4842-9481-1e2d686ca8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108575590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.108575590
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.3608688660
Short name T834
Test name
Test status
Simulation time 2288787975 ps
CPU time 23.14 seconds
Started May 26 01:30:05 PM PDT 24
Finished May 26 01:30:29 PM PDT 24
Peak memory 241936 kb
Host smart-f0ae987e-912a-4cee-a630-bb47fc35eaf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3608688660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.3608688660
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.2527176330
Short name T620
Test name
Test status
Simulation time 333492795 ps
CPU time 7.8 seconds
Started May 26 01:30:03 PM PDT 24
Finished May 26 01:30:12 PM PDT 24
Peak memory 242052 kb
Host smart-e12f26ba-6eae-4a6e-959f-24e1c3012b2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2527176330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.2527176330
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.2807814114
Short name T1170
Test name
Test status
Simulation time 1447412330 ps
CPU time 11.51 seconds
Started May 26 01:30:04 PM PDT 24
Finished May 26 01:30:16 PM PDT 24
Peak memory 242176 kb
Host smart-3cd49b9a-7a92-474b-82a4-ee62a3a63088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807814114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.2807814114
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.3315611534
Short name T16
Test name
Test status
Simulation time 69083662596 ps
CPU time 2011.97 seconds
Started May 26 01:30:07 PM PDT 24
Finished May 26 02:03:40 PM PDT 24
Peak memory 299308 kb
Host smart-2b2b0f6f-8c68-41ed-83b9-d7f7c503c15b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315611534 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.3315611534
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.2815217405
Short name T797
Test name
Test status
Simulation time 1975875234 ps
CPU time 14.99 seconds
Started May 26 01:30:05 PM PDT 24
Finished May 26 01:30:21 PM PDT 24
Peak memory 242236 kb
Host smart-c0ce8dcc-8434-4315-82cc-c61511eaff35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815217405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.2815217405
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.1338292066
Short name T392
Test name
Test status
Simulation time 98205798 ps
CPU time 2.08 seconds
Started May 26 01:30:19 PM PDT 24
Finished May 26 01:30:22 PM PDT 24
Peak memory 240748 kb
Host smart-9a9e961d-fd08-452c-ae99-1566e30d87c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338292066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.1338292066
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.3008990597
Short name T622
Test name
Test status
Simulation time 2611630905 ps
CPU time 9.14 seconds
Started May 26 01:30:15 PM PDT 24
Finished May 26 01:30:24 PM PDT 24
Peak memory 241996 kb
Host smart-4c11a88b-809f-4300-8636-a2c2b1e0399e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008990597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.3008990597
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.2131397600
Short name T458
Test name
Test status
Simulation time 6645512863 ps
CPU time 10.52 seconds
Started May 26 01:30:19 PM PDT 24
Finished May 26 01:30:31 PM PDT 24
Peak memory 243000 kb
Host smart-29a3c6b7-31a6-457b-802f-74238619baa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131397600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.2131397600
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.3468454924
Short name T38
Test name
Test status
Simulation time 145701932 ps
CPU time 3.65 seconds
Started May 26 01:30:12 PM PDT 24
Finished May 26 01:30:17 PM PDT 24
Peak memory 242056 kb
Host smart-a4039674-533a-41a6-b0ec-f0e941cda59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468454924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.3468454924
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.493044452
Short name T931
Test name
Test status
Simulation time 401609815 ps
CPU time 7.56 seconds
Started May 26 01:30:11 PM PDT 24
Finished May 26 01:30:20 PM PDT 24
Peak memory 242072 kb
Host smart-f1e1501d-b2c3-44b7-b28a-46ba93043580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493044452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.493044452
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.2644769125
Short name T790
Test name
Test status
Simulation time 997828537 ps
CPU time 16.96 seconds
Started May 26 01:30:12 PM PDT 24
Finished May 26 01:30:30 PM PDT 24
Peak memory 248768 kb
Host smart-db0eddda-ef0c-489b-b90b-ed5d5063f6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644769125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.2644769125
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.2569925539
Short name T963
Test name
Test status
Simulation time 649901472 ps
CPU time 9.71 seconds
Started May 26 01:30:11 PM PDT 24
Finished May 26 01:30:21 PM PDT 24
Peak memory 242220 kb
Host smart-ba25eb56-2c20-4215-b017-b2d91e5b08cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569925539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.2569925539
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.2609593976
Short name T1136
Test name
Test status
Simulation time 224310198 ps
CPU time 7.17 seconds
Started May 26 01:30:10 PM PDT 24
Finished May 26 01:30:18 PM PDT 24
Peak memory 242412 kb
Host smart-62e6fda5-7e94-491c-9fc8-e57dcf428850
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609593976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.2609593976
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.825580453
Short name T273
Test name
Test status
Simulation time 398110172 ps
CPU time 3.64 seconds
Started May 26 01:30:11 PM PDT 24
Finished May 26 01:30:16 PM PDT 24
Peak memory 242008 kb
Host smart-8b596cd9-9a26-4a26-bb65-01f09eeefc10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=825580453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.825580453
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.3241059929
Short name T463
Test name
Test status
Simulation time 1159776355 ps
CPU time 9.17 seconds
Started May 26 01:30:13 PM PDT 24
Finished May 26 01:30:23 PM PDT 24
Peak memory 242220 kb
Host smart-1be5713e-8f98-4185-8262-3e8123301c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241059929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.3241059929
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.2110423176
Short name T380
Test name
Test status
Simulation time 32955479508 ps
CPU time 134.13 seconds
Started May 26 01:30:13 PM PDT 24
Finished May 26 01:32:28 PM PDT 24
Peak memory 249892 kb
Host smart-53cbdac0-aa06-43ec-8ed8-d958905c8440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110423176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all
.2110423176
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.2301455698
Short name T274
Test name
Test status
Simulation time 30555849140 ps
CPU time 471.72 seconds
Started May 26 01:30:11 PM PDT 24
Finished May 26 01:38:05 PM PDT 24
Peak memory 264836 kb
Host smart-97020bf3-22fc-440b-8969-1ace4470f0ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301455698 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.2301455698
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.4135286590
Short name T1167
Test name
Test status
Simulation time 2338043366 ps
CPU time 7.21 seconds
Started May 26 01:30:12 PM PDT 24
Finished May 26 01:30:20 PM PDT 24
Peak memory 242104 kb
Host smart-b4aa5bbb-edd1-46d4-8578-97d0920a6c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135286590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.4135286590
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.1858679470
Short name T879
Test name
Test status
Simulation time 125031063 ps
CPU time 1.93 seconds
Started May 26 01:30:19 PM PDT 24
Finished May 26 01:30:22 PM PDT 24
Peak memory 240552 kb
Host smart-dcbeee61-730d-4c29-a9e0-b2639c730a12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858679470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.1858679470
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.2542189494
Short name T792
Test name
Test status
Simulation time 1137852245 ps
CPU time 18.68 seconds
Started May 26 01:30:16 PM PDT 24
Finished May 26 01:30:36 PM PDT 24
Peak memory 242188 kb
Host smart-559b30c9-9576-45ec-b858-34f22052f8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542189494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.2542189494
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.1065283857
Short name T958
Test name
Test status
Simulation time 91296488 ps
CPU time 3.59 seconds
Started May 26 01:30:11 PM PDT 24
Finished May 26 01:30:16 PM PDT 24
Peak memory 241892 kb
Host smart-4880273c-619f-4484-ad88-397a63c8753f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065283857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.1065283857
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.3839136356
Short name T481
Test name
Test status
Simulation time 1826669561 ps
CPU time 6.74 seconds
Started May 26 01:30:16 PM PDT 24
Finished May 26 01:30:23 PM PDT 24
Peak memory 241980 kb
Host smart-3c90765d-6c18-426d-b9de-308b9fdfd67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839136356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.3839136356
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.3626256607
Short name T1001
Test name
Test status
Simulation time 7749411218 ps
CPU time 16.34 seconds
Started May 26 01:30:14 PM PDT 24
Finished May 26 01:30:31 PM PDT 24
Peak memory 243108 kb
Host smart-a0d8f160-4460-4161-98c5-87e7f2b042e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626256607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.3626256607
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.2969278745
Short name T976
Test name
Test status
Simulation time 2977274920 ps
CPU time 35.24 seconds
Started May 26 01:30:20 PM PDT 24
Finished May 26 01:30:56 PM PDT 24
Peak memory 242568 kb
Host smart-68b64521-54d1-4117-8131-8788ef957d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969278745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.2969278745
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.96817761
Short name T133
Test name
Test status
Simulation time 141598233 ps
CPU time 4 seconds
Started May 26 01:30:11 PM PDT 24
Finished May 26 01:30:16 PM PDT 24
Peak memory 241976 kb
Host smart-39bbab77-cf4d-45a1-a006-0c29fb9eff8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96817761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.96817761
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.2368741841
Short name T1095
Test name
Test status
Simulation time 732257281 ps
CPU time 18.25 seconds
Started May 26 01:30:11 PM PDT 24
Finished May 26 01:30:31 PM PDT 24
Peak memory 248096 kb
Host smart-7f2117a9-6712-4df4-9111-30b47e01c282
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2368741841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.2368741841
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.4212896392
Short name T1036
Test name
Test status
Simulation time 122017214 ps
CPU time 5.48 seconds
Started May 26 01:30:21 PM PDT 24
Finished May 26 01:30:27 PM PDT 24
Peak memory 241912 kb
Host smart-6349baa1-fbe9-4b4c-973d-e5cf8848fe89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4212896392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.4212896392
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.1418074165
Short name T465
Test name
Test status
Simulation time 451950334 ps
CPU time 6.21 seconds
Started May 26 01:30:12 PM PDT 24
Finished May 26 01:30:20 PM PDT 24
Peak memory 241928 kb
Host smart-93867bc5-884e-4e83-9f45-c1ea8a61ada0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418074165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.1418074165
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.968482330
Short name T240
Test name
Test status
Simulation time 584439274146 ps
CPU time 1473.86 seconds
Started May 26 01:30:21 PM PDT 24
Finished May 26 01:54:56 PM PDT 24
Peak memory 344456 kb
Host smart-407cf2c2-7346-4aa4-b1ab-8c5938d0b6f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968482330 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.968482330
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.2421674763
Short name T164
Test name
Test status
Simulation time 937971967 ps
CPU time 10.05 seconds
Started May 26 01:30:20 PM PDT 24
Finished May 26 01:30:31 PM PDT 24
Peak memory 242400 kb
Host smart-0ae30ab1-5b63-47a8-bfe2-311e2981040a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421674763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.2421674763
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.4067179215
Short name T513
Test name
Test status
Simulation time 45299799 ps
CPU time 1.58 seconds
Started May 26 01:30:30 PM PDT 24
Finished May 26 01:30:32 PM PDT 24
Peak memory 240584 kb
Host smart-d0c624e5-15de-4a57-8299-ccc4d0f4404b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067179215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.4067179215
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.2007513273
Short name T462
Test name
Test status
Simulation time 772739107 ps
CPU time 7.4 seconds
Started May 26 01:30:17 PM PDT 24
Finished May 26 01:30:25 PM PDT 24
Peak memory 242252 kb
Host smart-b6fb4acf-b789-4e36-a03c-e92a6e50b1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007513273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.2007513273
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.642859737
Short name T156
Test name
Test status
Simulation time 298659105 ps
CPU time 15.34 seconds
Started May 26 01:30:17 PM PDT 24
Finished May 26 01:30:33 PM PDT 24
Peak memory 241900 kb
Host smart-3ff55583-7d2d-4ea5-b00e-7b287e60f051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642859737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.642859737
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.2600778576
Short name T953
Test name
Test status
Simulation time 770998270 ps
CPU time 28.92 seconds
Started May 26 01:30:19 PM PDT 24
Finished May 26 01:30:49 PM PDT 24
Peak memory 242364 kb
Host smart-83792562-2f14-47a4-a19d-18d7a45efa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600778576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.2600778576
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.2766761369
Short name T1097
Test name
Test status
Simulation time 547373764 ps
CPU time 4.07 seconds
Started May 26 01:30:18 PM PDT 24
Finished May 26 01:30:23 PM PDT 24
Peak memory 242352 kb
Host smart-9351ea4a-d6b9-467b-850a-66fb1a2442a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766761369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.2766761369
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.2529433319
Short name T745
Test name
Test status
Simulation time 4030996739 ps
CPU time 11.96 seconds
Started May 26 01:30:22 PM PDT 24
Finished May 26 01:30:35 PM PDT 24
Peak memory 242624 kb
Host smart-c8402e86-6ce7-4b4e-9f64-05c5d6324fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529433319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.2529433319
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.3454105849
Short name T997
Test name
Test status
Simulation time 212179024 ps
CPU time 9.64 seconds
Started May 26 01:30:19 PM PDT 24
Finished May 26 01:30:29 PM PDT 24
Peak memory 248788 kb
Host smart-b1997211-9cd7-4901-97d9-34ff72561a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454105849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.3454105849
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.69620953
Short name T408
Test name
Test status
Simulation time 368502905 ps
CPU time 15.53 seconds
Started May 26 01:30:18 PM PDT 24
Finished May 26 01:30:35 PM PDT 24
Peak memory 242264 kb
Host smart-0ebd3ff1-1ca4-40b0-b400-a9356c009937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69620953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.69620953
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.3189122142
Short name T1031
Test name
Test status
Simulation time 298324765 ps
CPU time 4.79 seconds
Started May 26 01:30:23 PM PDT 24
Finished May 26 01:30:29 PM PDT 24
Peak memory 242360 kb
Host smart-7229715f-d7fe-42da-88b6-eb46b60874b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3189122142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.3189122142
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.3830603759
Short name T546
Test name
Test status
Simulation time 311926701 ps
CPU time 5.03 seconds
Started May 26 01:30:35 PM PDT 24
Finished May 26 01:30:41 PM PDT 24
Peak memory 242288 kb
Host smart-c3f9ae5e-f0ef-4967-b4fb-215b6a6739df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3830603759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.3830603759
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.2264653988
Short name T1099
Test name
Test status
Simulation time 236113902 ps
CPU time 4.39 seconds
Started May 26 01:30:21 PM PDT 24
Finished May 26 01:30:26 PM PDT 24
Peak memory 241852 kb
Host smart-3a2b4a59-e989-4238-bcbb-f9ccc44f58f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264653988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.2264653988
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.4093350848
Short name T921
Test name
Test status
Simulation time 20803385095 ps
CPU time 270.8 seconds
Started May 26 01:30:30 PM PDT 24
Finished May 26 01:35:01 PM PDT 24
Peak memory 257004 kb
Host smart-0b943886-66e5-4876-a102-7e35aa31b235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093350848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all
.4093350848
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.2090691095
Short name T777
Test name
Test status
Simulation time 37997236370 ps
CPU time 1103.56 seconds
Started May 26 01:30:28 PM PDT 24
Finished May 26 01:48:53 PM PDT 24
Peak memory 294676 kb
Host smart-42c38654-c00c-4191-a884-ee98d978699e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090691095 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.2090691095
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.57764122
Short name T1072
Test name
Test status
Simulation time 719998623 ps
CPU time 2.2 seconds
Started May 26 01:25:16 PM PDT 24
Finished May 26 01:25:19 PM PDT 24
Peak memory 240488 kb
Host smart-31ac39d3-0b26-4f3e-ae2c-66cf32b22efd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57764122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.57764122
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.944298076
Short name T724
Test name
Test status
Simulation time 906390401 ps
CPU time 20.64 seconds
Started May 26 01:25:12 PM PDT 24
Finished May 26 01:25:33 PM PDT 24
Peak memory 242228 kb
Host smart-698002db-05c4-44a7-a75d-769e70cfc8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944298076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.944298076
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.4280542976
Short name T526
Test name
Test status
Simulation time 829763466 ps
CPU time 22.81 seconds
Started May 26 01:25:13 PM PDT 24
Finished May 26 01:25:36 PM PDT 24
Peak memory 242128 kb
Host smart-cf952f85-0762-4df1-a1a1-248daef59513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280542976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.4280542976
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.2271649339
Short name T1043
Test name
Test status
Simulation time 626757425 ps
CPU time 19.74 seconds
Started May 26 01:25:12 PM PDT 24
Finished May 26 01:25:33 PM PDT 24
Peak memory 242004 kb
Host smart-3238491e-b0d4-4520-b2d5-379365be4927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271649339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.2271649339
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.3585443808
Short name T207
Test name
Test status
Simulation time 286436369 ps
CPU time 4.41 seconds
Started May 26 01:25:18 PM PDT 24
Finished May 26 01:25:24 PM PDT 24
Peak memory 242044 kb
Host smart-58ff3302-b4ce-4021-87e3-32078185838e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585443808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.3585443808
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.2035112164
Short name T200
Test name
Test status
Simulation time 8883177190 ps
CPU time 64.7 seconds
Started May 26 01:25:14 PM PDT 24
Finished May 26 01:26:19 PM PDT 24
Peak memory 264028 kb
Host smart-d8fea2d7-4057-49d2-a9a2-ecef479ae91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035112164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.2035112164
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.378306489
Short name T1056
Test name
Test status
Simulation time 657341217 ps
CPU time 17.64 seconds
Started May 26 01:25:13 PM PDT 24
Finished May 26 01:25:31 PM PDT 24
Peak memory 248768 kb
Host smart-c92b7e91-2ce3-41be-aa7c-480445aa9a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378306489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.378306489
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.404178979
Short name T652
Test name
Test status
Simulation time 860958110 ps
CPU time 16.69 seconds
Started May 26 01:25:14 PM PDT 24
Finished May 26 01:25:32 PM PDT 24
Peak memory 242400 kb
Host smart-04bbcd7c-5683-4c85-ac06-f7ab55a75403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404178979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.404178979
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.3029182611
Short name T1094
Test name
Test status
Simulation time 927348333 ps
CPU time 7.95 seconds
Started May 26 01:25:15 PM PDT 24
Finished May 26 01:25:23 PM PDT 24
Peak memory 241884 kb
Host smart-46a1eeb1-f084-476c-abee-0a5b3aa37a00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3029182611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.3029182611
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.170168006
Short name T576
Test name
Test status
Simulation time 1073740395 ps
CPU time 10.01 seconds
Started May 26 01:25:14 PM PDT 24
Finished May 26 01:25:24 PM PDT 24
Peak memory 242328 kb
Host smart-8e3701af-7f46-4cf8-bc92-a8e20db77254
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=170168006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.170168006
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.3171251276
Short name T734
Test name
Test status
Simulation time 138127373 ps
CPU time 5.17 seconds
Started May 26 01:25:02 PM PDT 24
Finished May 26 01:25:08 PM PDT 24
Peak memory 241960 kb
Host smart-9f9efd1e-1888-4c70-8a7f-d605eff7eadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171251276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.3171251276
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.947345710
Short name T574
Test name
Test status
Simulation time 24407233221 ps
CPU time 151.59 seconds
Started May 26 01:25:15 PM PDT 24
Finished May 26 01:27:47 PM PDT 24
Peak memory 256972 kb
Host smart-79090731-9526-49be-8fb0-bf064ac4cf80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947345710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.947345710
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.96644351
Short name T251
Test name
Test status
Simulation time 363946605380 ps
CPU time 2264.66 seconds
Started May 26 01:25:12 PM PDT 24
Finished May 26 02:02:57 PM PDT 24
Peak memory 563948 kb
Host smart-80b54972-a1c5-4571-9df3-705bce7f5b53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96644351 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.96644351
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.62797210
Short name T486
Test name
Test status
Simulation time 9084520473 ps
CPU time 25.85 seconds
Started May 26 01:25:14 PM PDT 24
Finished May 26 01:25:41 PM PDT 24
Peak memory 242488 kb
Host smart-a6547368-0aa6-4c0f-8cb1-2d7e6e686f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62797210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.62797210
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.228396936
Short name T32
Test name
Test status
Simulation time 136850127 ps
CPU time 3.35 seconds
Started May 26 01:30:27 PM PDT 24
Finished May 26 01:30:31 PM PDT 24
Peak memory 242028 kb
Host smart-35a2c21a-db49-4ea6-9eda-32b6edff48d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228396936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.228396936
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.1144481456
Short name T144
Test name
Test status
Simulation time 307826273 ps
CPU time 8.81 seconds
Started May 26 01:30:27 PM PDT 24
Finished May 26 01:30:37 PM PDT 24
Peak memory 241960 kb
Host smart-1170bb90-78ca-402d-9221-9337ef41b7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144481456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.1144481456
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.1025410859
Short name T134
Test name
Test status
Simulation time 223963983448 ps
CPU time 1595.8 seconds
Started May 26 01:30:28 PM PDT 24
Finished May 26 01:57:05 PM PDT 24
Peak memory 409200 kb
Host smart-66229101-1ca3-4b4e-b436-b47f9882ee85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025410859 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.1025410859
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.1226598482
Short name T971
Test name
Test status
Simulation time 1483303624 ps
CPU time 5.52 seconds
Started May 26 01:30:30 PM PDT 24
Finished May 26 01:30:36 PM PDT 24
Peak memory 242060 kb
Host smart-24391166-244e-42f7-bb34-649aba624c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226598482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.1226598482
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.2946431250
Short name T735
Test name
Test status
Simulation time 1487980554 ps
CPU time 11.17 seconds
Started May 26 01:30:28 PM PDT 24
Finished May 26 01:30:40 PM PDT 24
Peak memory 241908 kb
Host smart-dd085ea8-2a4c-4fbb-a2f1-0aef4130e2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946431250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.2946431250
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.3386931029
Short name T895
Test name
Test status
Simulation time 28264870309 ps
CPU time 654.29 seconds
Started May 26 01:30:30 PM PDT 24
Finished May 26 01:41:25 PM PDT 24
Peak memory 304512 kb
Host smart-03cd6c24-e067-41f8-bc97-f67bdbf0a4db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386931029 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.3386931029
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.448202848
Short name T701
Test name
Test status
Simulation time 228857466 ps
CPU time 4.22 seconds
Started May 26 01:30:36 PM PDT 24
Finished May 26 01:30:42 PM PDT 24
Peak memory 241976 kb
Host smart-caac0d83-c8c5-4a46-9e55-a0cba61f706f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448202848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.448202848
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.1074941373
Short name T483
Test name
Test status
Simulation time 1820530062 ps
CPU time 5.84 seconds
Started May 26 01:30:36 PM PDT 24
Finished May 26 01:30:42 PM PDT 24
Peak memory 241860 kb
Host smart-556b738b-c70f-4620-9012-63d6a922cd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074941373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.1074941373
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.2104968017
Short name T1082
Test name
Test status
Simulation time 117676581235 ps
CPU time 1696.36 seconds
Started May 26 01:30:27 PM PDT 24
Finished May 26 01:58:44 PM PDT 24
Peak memory 307508 kb
Host smart-37d83d9d-d9df-4b19-9f34-c79a0d4d6e30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104968017 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.2104968017
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.62209016
Short name T855
Test name
Test status
Simulation time 1928149553 ps
CPU time 4.97 seconds
Started May 26 01:30:43 PM PDT 24
Finished May 26 01:30:48 PM PDT 24
Peak memory 242064 kb
Host smart-cc07251e-f2f5-4e08-8ef9-71509f0ff058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62209016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.62209016
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.2291155301
Short name T383
Test name
Test status
Simulation time 2657264675 ps
CPU time 19.86 seconds
Started May 26 01:30:36 PM PDT 24
Finished May 26 01:30:57 PM PDT 24
Peak memory 242440 kb
Host smart-a54290b0-e913-44d9-8c6a-858b3d450e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291155301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.2291155301
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.2268976156
Short name T910
Test name
Test status
Simulation time 47609341330 ps
CPU time 607.56 seconds
Started May 26 01:30:40 PM PDT 24
Finished May 26 01:40:48 PM PDT 24
Peak memory 278908 kb
Host smart-725d726e-5953-46f0-9642-114eb3e977b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268976156 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.2268976156
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.3433365472
Short name T108
Test name
Test status
Simulation time 226697478 ps
CPU time 3.57 seconds
Started May 26 01:30:37 PM PDT 24
Finished May 26 01:30:42 PM PDT 24
Peak memory 242180 kb
Host smart-916ae129-5e94-415d-9996-e529b12ada1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433365472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.3433365472
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.1220791341
Short name T740
Test name
Test status
Simulation time 403779497 ps
CPU time 4.91 seconds
Started May 26 01:30:38 PM PDT 24
Finished May 26 01:30:43 PM PDT 24
Peak memory 241892 kb
Host smart-f8bff146-5bf2-4335-9f69-a4fd65d0e77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220791341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.1220791341
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.3052135741
Short name T334
Test name
Test status
Simulation time 97934608 ps
CPU time 2.98 seconds
Started May 26 01:30:44 PM PDT 24
Finished May 26 01:30:48 PM PDT 24
Peak memory 241876 kb
Host smart-96718dc6-9b14-48ad-941e-12625ccc38dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052135741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.3052135741
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.186863205
Short name T698
Test name
Test status
Simulation time 199653765 ps
CPU time 3.36 seconds
Started May 26 01:30:36 PM PDT 24
Finished May 26 01:30:41 PM PDT 24
Peak memory 242056 kb
Host smart-546f1e61-cb8d-4fa2-bc72-2dc6c97f2082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186863205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.186863205
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.2083854773
Short name T420
Test name
Test status
Simulation time 207749850 ps
CPU time 5.52 seconds
Started May 26 01:30:35 PM PDT 24
Finished May 26 01:30:41 PM PDT 24
Peak memory 241912 kb
Host smart-50ab1c85-8c8b-46de-baf8-7bb59df0c84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083854773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.2083854773
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.2242985085
Short name T326
Test name
Test status
Simulation time 154235165467 ps
CPU time 1332.93 seconds
Started May 26 01:30:36 PM PDT 24
Finished May 26 01:52:50 PM PDT 24
Peak memory 265244 kb
Host smart-8078bc03-9012-4cd7-a2f4-f70dc654503d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242985085 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.2242985085
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.1156530394
Short name T1018
Test name
Test status
Simulation time 173051949 ps
CPU time 4.1 seconds
Started May 26 01:30:44 PM PDT 24
Finished May 26 01:30:49 PM PDT 24
Peak memory 242308 kb
Host smart-3f9efaf3-c0e5-437e-8e9f-a5f33ab55cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156530394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.1156530394
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.407081089
Short name T807
Test name
Test status
Simulation time 985703440 ps
CPU time 8.3 seconds
Started May 26 01:30:34 PM PDT 24
Finished May 26 01:30:43 PM PDT 24
Peak memory 242364 kb
Host smart-23146fd0-f195-4679-a042-bb3c743960c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407081089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.407081089
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.1489997926
Short name T477
Test name
Test status
Simulation time 273193868 ps
CPU time 3.82 seconds
Started May 26 01:30:44 PM PDT 24
Finished May 26 01:30:49 PM PDT 24
Peak memory 242320 kb
Host smart-0cf3ac2b-2900-4382-8c9a-f804a5faa7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489997926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.1489997926
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.3087119638
Short name T195
Test name
Test status
Simulation time 173087100 ps
CPU time 7.46 seconds
Started May 26 01:30:44 PM PDT 24
Finished May 26 01:30:53 PM PDT 24
Peak memory 242180 kb
Host smart-b657b461-758b-45a0-871f-3ee5edaec9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087119638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.3087119638
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.1650693048
Short name T285
Test name
Test status
Simulation time 87398585570 ps
CPU time 1237.92 seconds
Started May 26 01:30:45 PM PDT 24
Finished May 26 01:51:25 PM PDT 24
Peak memory 326324 kb
Host smart-262c75d2-505b-4ccd-b373-081b059f63fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650693048 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.1650693048
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.2698813480
Short name T541
Test name
Test status
Simulation time 244704687 ps
CPU time 4.16 seconds
Started May 26 01:30:43 PM PDT 24
Finished May 26 01:30:48 PM PDT 24
Peak memory 242068 kb
Host smart-269285cc-6df3-4f33-9c9c-10307e2196ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698813480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.2698813480
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.1927633858
Short name T987
Test name
Test status
Simulation time 133226614 ps
CPU time 3.5 seconds
Started May 26 01:30:45 PM PDT 24
Finished May 26 01:30:50 PM PDT 24
Peak memory 241972 kb
Host smart-14e1e304-cbff-4ac6-b511-740a7195c6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927633858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.1927633858
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.1217487780
Short name T1081
Test name
Test status
Simulation time 48108850 ps
CPU time 1.77 seconds
Started May 26 01:25:20 PM PDT 24
Finished May 26 01:25:22 PM PDT 24
Peak memory 240568 kb
Host smart-da7ec4f8-b554-4c62-a68c-88bbd98b107a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217487780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.1217487780
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.2643225710
Short name T754
Test name
Test status
Simulation time 868965532 ps
CPU time 18.06 seconds
Started May 26 01:25:12 PM PDT 24
Finished May 26 01:25:30 PM PDT 24
Peak memory 242132 kb
Host smart-53e8579f-3529-4622-bfcc-ab9ce3117542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643225710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.2643225710
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.1371144236
Short name T702
Test name
Test status
Simulation time 5955605788 ps
CPU time 11.85 seconds
Started May 26 01:25:14 PM PDT 24
Finished May 26 01:25:27 PM PDT 24
Peak memory 243316 kb
Host smart-651abd83-7ac7-4c1d-8eb4-78c6eb2740cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371144236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.1371144236
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.3024178860
Short name T968
Test name
Test status
Simulation time 1408990794 ps
CPU time 20.91 seconds
Started May 26 01:25:12 PM PDT 24
Finished May 26 01:25:33 PM PDT 24
Peak memory 242164 kb
Host smart-c617819a-f917-42a0-b20c-fd5060c04c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024178860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.3024178860
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.1176456672
Short name T579
Test name
Test status
Simulation time 599604213 ps
CPU time 15.86 seconds
Started May 26 01:25:14 PM PDT 24
Finished May 26 01:25:30 PM PDT 24
Peak memory 248788 kb
Host smart-0a63bc4c-94ee-4007-b65e-81c2b5c1741b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176456672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.1176456672
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.858713497
Short name T492
Test name
Test status
Simulation time 326501767 ps
CPU time 4.87 seconds
Started May 26 01:25:16 PM PDT 24
Finished May 26 01:25:21 PM PDT 24
Peak memory 242368 kb
Host smart-6a27a263-186f-40d7-b982-bea48b28e89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858713497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.858713497
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.3615526492
Short name T524
Test name
Test status
Simulation time 2714418265 ps
CPU time 20.34 seconds
Started May 26 01:25:12 PM PDT 24
Finished May 26 01:25:33 PM PDT 24
Peak memory 242080 kb
Host smart-e4228411-4fc6-4492-a9a4-8e40b09dd95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615526492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.3615526492
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.2668897435
Short name T365
Test name
Test status
Simulation time 1447088817 ps
CPU time 17.79 seconds
Started May 26 01:25:13 PM PDT 24
Finished May 26 01:25:32 PM PDT 24
Peak memory 242212 kb
Host smart-905223ec-626e-4e38-a504-7909cd3b4ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668897435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.2668897435
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.1325471553
Short name T902
Test name
Test status
Simulation time 278077048 ps
CPU time 7.67 seconds
Started May 26 01:25:15 PM PDT 24
Finished May 26 01:25:23 PM PDT 24
Peak memory 241936 kb
Host smart-0eba7d19-467b-4882-9df8-d08cd9678bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325471553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.1325471553
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.648607263
Short name T437
Test name
Test status
Simulation time 2580765195 ps
CPU time 19.81 seconds
Started May 26 01:25:15 PM PDT 24
Finished May 26 01:25:36 PM PDT 24
Peak memory 242288 kb
Host smart-8cf86b53-b5ac-45d7-b806-0b1fa2c7b1c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=648607263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.648607263
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.2502697219
Short name T583
Test name
Test status
Simulation time 402460117 ps
CPU time 7.37 seconds
Started May 26 01:25:13 PM PDT 24
Finished May 26 01:25:21 PM PDT 24
Peak memory 242180 kb
Host smart-308371f4-6861-4ce4-8127-29e6618da32f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2502697219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.2502697219
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.241297311
Short name T1177
Test name
Test status
Simulation time 1959729064 ps
CPU time 12.73 seconds
Started May 26 01:25:16 PM PDT 24
Finished May 26 01:25:29 PM PDT 24
Peak memory 241896 kb
Host smart-49937d71-89bf-4ef6-b459-db477ccf3c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241297311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.241297311
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.3548568814
Short name T883
Test name
Test status
Simulation time 2494613944 ps
CPU time 63.24 seconds
Started May 26 01:25:15 PM PDT 24
Finished May 26 01:26:19 PM PDT 24
Peak memory 242804 kb
Host smart-47f2e55d-ec41-4d55-bf7b-ff36f372d9e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548568814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.
3548568814
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.2960157228
Short name T593
Test name
Test status
Simulation time 2181357667 ps
CPU time 36.85 seconds
Started May 26 01:25:13 PM PDT 24
Finished May 26 01:25:51 PM PDT 24
Peak memory 241976 kb
Host smart-adda97c9-b55b-42b9-b7b0-0df01f7f8517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960157228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.2960157228
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.1224620128
Short name T588
Test name
Test status
Simulation time 304372159 ps
CPU time 5.48 seconds
Started May 26 01:30:48 PM PDT 24
Finished May 26 01:30:54 PM PDT 24
Peak memory 242100 kb
Host smart-84a03188-0325-4b9b-b6f3-693f137165fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224620128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.1224620128
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.1419419438
Short name T547
Test name
Test status
Simulation time 2255681126 ps
CPU time 16.83 seconds
Started May 26 01:30:45 PM PDT 24
Finished May 26 01:31:03 PM PDT 24
Peak memory 241984 kb
Host smart-a5ebedf5-961f-4f06-8ef8-335da96a3eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419419438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1419419438
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.772754841
Short name T942
Test name
Test status
Simulation time 181050838867 ps
CPU time 514.64 seconds
Started May 26 01:30:45 PM PDT 24
Finished May 26 01:39:21 PM PDT 24
Peak memory 248936 kb
Host smart-de256fe5-a7df-4639-90e6-170fefa33d80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772754841 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.772754841
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.779301720
Short name T10
Test name
Test status
Simulation time 637310426 ps
CPU time 5.55 seconds
Started May 26 01:30:45 PM PDT 24
Finished May 26 01:30:52 PM PDT 24
Peak memory 242316 kb
Host smart-c0877923-6c38-4185-a854-9f4bfdffb2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779301720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.779301720
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.789356715
Short name T707
Test name
Test status
Simulation time 7351819494 ps
CPU time 14.78 seconds
Started May 26 01:30:44 PM PDT 24
Finished May 26 01:31:00 PM PDT 24
Peak memory 242520 kb
Host smart-f7d9fe86-485d-4137-ab7f-f47e1931e454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789356715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.789356715
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.2024976357
Short name T683
Test name
Test status
Simulation time 283069072948 ps
CPU time 2152.7 seconds
Started May 26 01:30:44 PM PDT 24
Finished May 26 02:06:38 PM PDT 24
Peak memory 579364 kb
Host smart-0ddc57e5-53b7-452f-aadb-a07e04e6bd1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024976357 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.2024976357
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.1074299378
Short name T534
Test name
Test status
Simulation time 307970799 ps
CPU time 5.37 seconds
Started May 26 01:30:46 PM PDT 24
Finished May 26 01:30:52 PM PDT 24
Peak memory 241936 kb
Host smart-f6a81eba-3e8f-4f40-87f8-89ed2221afd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074299378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.1074299378
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.3474919110
Short name T799
Test name
Test status
Simulation time 434025100 ps
CPU time 6.51 seconds
Started May 26 01:30:44 PM PDT 24
Finished May 26 01:30:51 PM PDT 24
Peak memory 242324 kb
Host smart-d9d9f8c7-a381-47cc-8f68-470148e44c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474919110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.3474919110
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.3531512025
Short name T278
Test name
Test status
Simulation time 992243549709 ps
CPU time 2005.21 seconds
Started May 26 01:30:44 PM PDT 24
Finished May 26 02:04:10 PM PDT 24
Peak memory 341132 kb
Host smart-e21f99e6-10dc-48d3-bb4e-19bd1f2a89c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531512025 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.3531512025
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.1419155564
Short name T505
Test name
Test status
Simulation time 2783287813 ps
CPU time 5.88 seconds
Started May 26 01:30:44 PM PDT 24
Finished May 26 01:30:52 PM PDT 24
Peak memory 242056 kb
Host smart-3d7dc362-eb41-47d9-9e41-0d7dd50edb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419155564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.1419155564
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.3396534275
Short name T72
Test name
Test status
Simulation time 576932211 ps
CPU time 7.49 seconds
Started May 26 01:30:55 PM PDT 24
Finished May 26 01:31:03 PM PDT 24
Peak memory 242048 kb
Host smart-83d3d09b-e0fb-45ce-8a00-d29a5eb2e9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396534275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.3396534275
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.2744850229
Short name T250
Test name
Test status
Simulation time 67735529348 ps
CPU time 704.61 seconds
Started May 26 01:30:53 PM PDT 24
Finished May 26 01:42:38 PM PDT 24
Peak memory 298004 kb
Host smart-44d62309-8a22-49e5-93f0-6ed922245b65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744850229 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.2744850229
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.4044200617
Short name T720
Test name
Test status
Simulation time 278749412 ps
CPU time 3.92 seconds
Started May 26 01:30:53 PM PDT 24
Finished May 26 01:30:58 PM PDT 24
Peak memory 241992 kb
Host smart-b8417887-3178-4323-81a8-4dfc20b18fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044200617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.4044200617
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.1655534333
Short name T401
Test name
Test status
Simulation time 6582176815 ps
CPU time 15.93 seconds
Started May 26 01:30:53 PM PDT 24
Finished May 26 01:31:09 PM PDT 24
Peak memory 241952 kb
Host smart-1a71dcd8-7722-4d9a-bee6-cf1fc0284af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655534333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.1655534333
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.2993222255
Short name T125
Test name
Test status
Simulation time 307770319 ps
CPU time 5.04 seconds
Started May 26 01:30:54 PM PDT 24
Finished May 26 01:31:00 PM PDT 24
Peak memory 241940 kb
Host smart-1dba10d1-4a18-43af-b5dd-09a0a70b993c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993222255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.2993222255
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.2475491243
Short name T758
Test name
Test status
Simulation time 2839747832 ps
CPU time 19.97 seconds
Started May 26 01:30:53 PM PDT 24
Finished May 26 01:31:13 PM PDT 24
Peak memory 242112 kb
Host smart-b4739a26-e33b-4235-96b6-6b45dca2c9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475491243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.2475491243
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.1297397464
Short name T1074
Test name
Test status
Simulation time 312854506 ps
CPU time 4.3 seconds
Started May 26 01:30:53 PM PDT 24
Finished May 26 01:30:58 PM PDT 24
Peak memory 242240 kb
Host smart-5d872c19-90df-435e-9660-f30af2ef2b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297397464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.1297397464
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.117838722
Short name T1087
Test name
Test status
Simulation time 576982806 ps
CPU time 8.52 seconds
Started May 26 01:30:54 PM PDT 24
Finished May 26 01:31:04 PM PDT 24
Peak memory 241984 kb
Host smart-19a98256-20d0-4643-bb99-7db5b02025b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117838722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.117838722
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.1031110685
Short name T279
Test name
Test status
Simulation time 577547805572 ps
CPU time 1516.64 seconds
Started May 26 01:30:53 PM PDT 24
Finished May 26 01:56:11 PM PDT 24
Peak memory 454108 kb
Host smart-13ea83d5-ddb2-4b51-a318-fca966cbb2e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031110685 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.1031110685
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.2163035297
Short name T209
Test name
Test status
Simulation time 304007714 ps
CPU time 15.23 seconds
Started May 26 01:30:54 PM PDT 24
Finished May 26 01:31:10 PM PDT 24
Peak memory 241996 kb
Host smart-69ca18a4-19ea-4b49-a974-484e247087b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163035297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.2163035297
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.3217483825
Short name T1065
Test name
Test status
Simulation time 29894400885 ps
CPU time 761.57 seconds
Started May 26 01:30:55 PM PDT 24
Finished May 26 01:43:38 PM PDT 24
Peak memory 265376 kb
Host smart-f91bf510-668c-45d4-ad7c-319042bd8f9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217483825 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.3217483825
Directory /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.897560576
Short name T589
Test name
Test status
Simulation time 413560010 ps
CPU time 4.98 seconds
Started May 26 01:30:53 PM PDT 24
Finished May 26 01:30:59 PM PDT 24
Peak memory 242180 kb
Host smart-9f88a01d-0e3d-4434-8e1f-310d6ade1f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897560576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.897560576
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.803907356
Short name T525
Test name
Test status
Simulation time 884535434 ps
CPU time 6.49 seconds
Started May 26 01:31:02 PM PDT 24
Finished May 26 01:31:10 PM PDT 24
Peak memory 242236 kb
Host smart-0a274e8c-da82-4718-b872-644fa59efc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803907356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.803907356
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.4026016967
Short name T750
Test name
Test status
Simulation time 190883729 ps
CPU time 4.41 seconds
Started May 26 01:31:03 PM PDT 24
Finished May 26 01:31:08 PM PDT 24
Peak memory 242392 kb
Host smart-46bfa21a-7f76-4275-8690-994a8f9bf387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026016967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.4026016967
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.1379932366
Short name T907
Test name
Test status
Simulation time 393360151 ps
CPU time 4.61 seconds
Started May 26 01:31:02 PM PDT 24
Finished May 26 01:31:08 PM PDT 24
Peak memory 242380 kb
Host smart-657a683b-eb71-4c8b-87a2-3c6bdfd4bb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379932366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.1379932366
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.457482979
Short name T888
Test name
Test status
Simulation time 218890362 ps
CPU time 1.91 seconds
Started May 26 01:25:28 PM PDT 24
Finished May 26 01:25:31 PM PDT 24
Peak memory 240584 kb
Host smart-55e7ba03-9381-48d3-a4f4-fff46f1c122f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457482979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.457482979
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.1271474044
Short name T428
Test name
Test status
Simulation time 1034731137 ps
CPU time 23.21 seconds
Started May 26 01:25:21 PM PDT 24
Finished May 26 01:25:46 PM PDT 24
Peak memory 242544 kb
Host smart-53d118d3-c169-4c6e-bffe-94c760bbd0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271474044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.1271474044
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.1786317499
Short name T107
Test name
Test status
Simulation time 742297183 ps
CPU time 5.84 seconds
Started May 26 01:25:21 PM PDT 24
Finished May 26 01:25:28 PM PDT 24
Peak memory 248656 kb
Host smart-f7e3eef4-9d7b-49ba-a5f6-6b6def431eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786317499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.1786317499
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.3844791410
Short name T233
Test name
Test status
Simulation time 1537591607 ps
CPU time 43.45 seconds
Started May 26 01:25:22 PM PDT 24
Finished May 26 01:26:06 PM PDT 24
Peak memory 248812 kb
Host smart-94928296-97da-4d8d-ba78-573117f78b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844791410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.3844791410
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.3692357087
Short name T1129
Test name
Test status
Simulation time 774288029 ps
CPU time 12.14 seconds
Started May 26 01:25:20 PM PDT 24
Finished May 26 01:25:33 PM PDT 24
Peak memory 248696 kb
Host smart-75936c1f-126b-4de0-9105-1520d26be4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692357087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.3692357087
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.1932255219
Short name T434
Test name
Test status
Simulation time 603272922 ps
CPU time 4.81 seconds
Started May 26 01:25:20 PM PDT 24
Finished May 26 01:25:27 PM PDT 24
Peak memory 241992 kb
Host smart-0ab08b8b-0944-4301-9cb0-f7586bcca4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932255219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.1932255219
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.3844219535
Short name T1084
Test name
Test status
Simulation time 13854284196 ps
CPU time 52.08 seconds
Started May 26 01:25:19 PM PDT 24
Finished May 26 01:26:12 PM PDT 24
Peak memory 248948 kb
Host smart-b4dff5fe-02d6-4e34-a517-4720265b3f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844219535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.3844219535
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.2975559068
Short name T930
Test name
Test status
Simulation time 629647647 ps
CPU time 28.25 seconds
Started May 26 01:25:20 PM PDT 24
Finished May 26 01:25:49 PM PDT 24
Peak memory 242232 kb
Host smart-3fec1041-a092-4f09-9397-5f8e97b43eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975559068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.2975559068
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.2447093284
Short name T748
Test name
Test status
Simulation time 294449088 ps
CPU time 4.86 seconds
Started May 26 01:25:19 PM PDT 24
Finished May 26 01:25:24 PM PDT 24
Peak memory 242376 kb
Host smart-41045d5d-1b1d-4068-b0de-65cbe8d73f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447093284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.2447093284
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.328929787
Short name T393
Test name
Test status
Simulation time 541908085 ps
CPU time 4.3 seconds
Started May 26 01:25:19 PM PDT 24
Finished May 26 01:25:24 PM PDT 24
Peak memory 241864 kb
Host smart-1e125d79-70a5-42da-b31d-c9142ccf6dcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=328929787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.328929787
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.451941582
Short name T1030
Test name
Test status
Simulation time 2639278376 ps
CPU time 7.83 seconds
Started May 26 01:25:21 PM PDT 24
Finished May 26 01:25:30 PM PDT 24
Peak memory 242128 kb
Host smart-ff3d6767-71fe-4529-a8a8-b53b3353b7b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=451941582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.451941582
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.2860459511
Short name T597
Test name
Test status
Simulation time 245451280 ps
CPU time 8.95 seconds
Started May 26 01:25:20 PM PDT 24
Finished May 26 01:25:30 PM PDT 24
Peak memory 242188 kb
Host smart-a076f5fa-832f-49a5-abd1-0eb4d4f98b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860459511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.2860459511
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.3807883422
Short name T310
Test name
Test status
Simulation time 40812064844 ps
CPU time 347.85 seconds
Started May 26 01:25:20 PM PDT 24
Finished May 26 01:31:09 PM PDT 24
Peak memory 286188 kb
Host smart-4856d75f-52dc-4fcf-938f-f50608d28f71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807883422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
3807883422
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.3037851733
Short name T172
Test name
Test status
Simulation time 139869821949 ps
CPU time 2088.67 seconds
Started May 26 01:25:21 PM PDT 24
Finished May 26 02:00:11 PM PDT 24
Peak memory 265508 kb
Host smart-4cc95255-649c-4b88-9209-69e96cb203d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037851733 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.3037851733
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.4185146413
Short name T461
Test name
Test status
Simulation time 222936763 ps
CPU time 5.47 seconds
Started May 26 01:25:20 PM PDT 24
Finished May 26 01:25:27 PM PDT 24
Peak memory 241888 kb
Host smart-cf75357e-94c7-41fa-95cd-41b8acf9be57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185146413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.4185146413
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.3750841631
Short name T59
Test name
Test status
Simulation time 570514570 ps
CPU time 5.62 seconds
Started May 26 01:31:01 PM PDT 24
Finished May 26 01:31:08 PM PDT 24
Peak memory 242228 kb
Host smart-13edcfa6-3995-4ef7-8ffc-3e26f47ba2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750841631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.3750841631
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.4118551781
Short name T467
Test name
Test status
Simulation time 237599641 ps
CPU time 9.93 seconds
Started May 26 01:31:07 PM PDT 24
Finished May 26 01:31:18 PM PDT 24
Peak memory 241816 kb
Host smart-71f4ae15-001e-44ef-93cc-3b3f2193270f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118551781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.4118551781
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.3137525667
Short name T784
Test name
Test status
Simulation time 52401813123 ps
CPU time 381.76 seconds
Started May 26 01:31:01 PM PDT 24
Finished May 26 01:37:23 PM PDT 24
Peak memory 257060 kb
Host smart-3aee91e8-c059-49ce-99f4-68db14a3c3e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137525667 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.3137525667
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.3759728185
Short name T780
Test name
Test status
Simulation time 108921614 ps
CPU time 4.23 seconds
Started May 26 01:31:03 PM PDT 24
Finished May 26 01:31:08 PM PDT 24
Peak memory 242116 kb
Host smart-d4a8b6e6-9dbd-4456-8758-33ca5a4e8a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759728185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.3759728185
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.4113648602
Short name T124
Test name
Test status
Simulation time 555560981 ps
CPU time 13.91 seconds
Started May 26 01:31:01 PM PDT 24
Finished May 26 01:31:16 PM PDT 24
Peak memory 241944 kb
Host smart-07179b00-d6f1-4a1b-9ede-3a58fd9ddd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113648602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.4113648602
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.2861791911
Short name T13
Test name
Test status
Simulation time 28761253984 ps
CPU time 934.76 seconds
Started May 26 01:31:02 PM PDT 24
Finished May 26 01:46:38 PM PDT 24
Peak memory 310616 kb
Host smart-e9f0c8f3-b3ba-4cf2-aef3-41cf570702b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861791911 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.2861791911
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.843665513
Short name T542
Test name
Test status
Simulation time 139755458 ps
CPU time 3.82 seconds
Started May 26 01:31:02 PM PDT 24
Finished May 26 01:31:07 PM PDT 24
Peak memory 242192 kb
Host smart-b1b521e4-1213-40e2-aece-953a3c541c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843665513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.843665513
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.121160944
Short name T201
Test name
Test status
Simulation time 361467074 ps
CPU time 10.29 seconds
Started May 26 01:31:02 PM PDT 24
Finished May 26 01:31:14 PM PDT 24
Peak memory 241972 kb
Host smart-7b4eca29-5fbb-49a3-a028-df10c9ffa95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121160944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.121160944
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.620308831
Short name T786
Test name
Test status
Simulation time 492653061 ps
CPU time 3.46 seconds
Started May 26 01:31:02 PM PDT 24
Finished May 26 01:31:07 PM PDT 24
Peak memory 242104 kb
Host smart-177d8512-9683-4692-af13-ecffa90b8b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620308831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.620308831
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.1626421487
Short name T1044
Test name
Test status
Simulation time 712864546 ps
CPU time 5.52 seconds
Started May 26 01:31:01 PM PDT 24
Finished May 26 01:31:07 PM PDT 24
Peak memory 241984 kb
Host smart-0ade9de6-b275-4322-94d6-6e6953309c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626421487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.1626421487
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.2829411693
Short name T1098
Test name
Test status
Simulation time 157647128450 ps
CPU time 2096.8 seconds
Started May 26 01:31:03 PM PDT 24
Finished May 26 02:06:01 PM PDT 24
Peak memory 368396 kb
Host smart-780e0109-2757-4360-8666-214cd89536ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829411693 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.2829411693
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.2585963218
Short name T409
Test name
Test status
Simulation time 258296083 ps
CPU time 3.73 seconds
Started May 26 01:31:01 PM PDT 24
Finished May 26 01:31:06 PM PDT 24
Peak memory 242020 kb
Host smart-b93b7f33-70a4-4de3-8ef8-f1391d4689d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585963218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.2585963218
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.1857192592
Short name T618
Test name
Test status
Simulation time 356927444 ps
CPU time 8.76 seconds
Started May 26 01:31:06 PM PDT 24
Finished May 26 01:31:16 PM PDT 24
Peak memory 242120 kb
Host smart-4bae952c-2f72-497d-905a-c1b4ee9389d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857192592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.1857192592
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.1375121841
Short name T1105
Test name
Test status
Simulation time 50214945722 ps
CPU time 429.82 seconds
Started May 26 01:31:12 PM PDT 24
Finished May 26 01:38:23 PM PDT 24
Peak memory 296104 kb
Host smart-7435a231-0fab-40b1-a963-9d62500f19f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375121841 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.1375121841
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.3494666289
Short name T923
Test name
Test status
Simulation time 283613255 ps
CPU time 3.49 seconds
Started May 26 01:31:05 PM PDT 24
Finished May 26 01:31:09 PM PDT 24
Peak memory 242044 kb
Host smart-bc318177-4c3f-4851-bb00-66c2ee2e7bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494666289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.3494666289
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.757094008
Short name T146
Test name
Test status
Simulation time 696471117 ps
CPU time 7.98 seconds
Started May 26 01:31:05 PM PDT 24
Finished May 26 01:31:14 PM PDT 24
Peak memory 241960 kb
Host smart-e2d7b452-6c43-4abe-855d-12afaa304028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757094008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.757094008
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.1877505335
Short name T765
Test name
Test status
Simulation time 147796168147 ps
CPU time 1205.15 seconds
Started May 26 01:31:07 PM PDT 24
Finished May 26 01:51:13 PM PDT 24
Peak memory 478356 kb
Host smart-79410c07-63ff-421f-916a-74bb160c8475
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877505335 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.1877505335
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.2506119321
Short name T900
Test name
Test status
Simulation time 178047983 ps
CPU time 4.8 seconds
Started May 26 01:31:06 PM PDT 24
Finished May 26 01:31:11 PM PDT 24
Peak memory 242388 kb
Host smart-e43b46bb-9d07-4f5c-b2ae-33c54bcacbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506119321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.2506119321
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.78081668
Short name T858
Test name
Test status
Simulation time 225674371 ps
CPU time 5.91 seconds
Started May 26 01:31:02 PM PDT 24
Finished May 26 01:31:09 PM PDT 24
Peak memory 242052 kb
Host smart-41edb3d6-97da-4dc6-8bf2-8ea8a39418b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78081668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.78081668
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.318207974
Short name T798
Test name
Test status
Simulation time 99376219 ps
CPU time 3.61 seconds
Started May 26 01:31:03 PM PDT 24
Finished May 26 01:31:08 PM PDT 24
Peak memory 242064 kb
Host smart-e9cb41d4-bac9-4010-a35e-362282fb7a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318207974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.318207974
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.1580397184
Short name T877
Test name
Test status
Simulation time 440174133 ps
CPU time 5.35 seconds
Started May 26 01:31:02 PM PDT 24
Finished May 26 01:31:08 PM PDT 24
Peak memory 241920 kb
Host smart-baaa9650-2f1e-4ebf-a4dc-fef45cf330ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580397184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.1580397184
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.2345095112
Short name T495
Test name
Test status
Simulation time 219081094 ps
CPU time 4.34 seconds
Started May 26 01:31:09 PM PDT 24
Finished May 26 01:31:14 PM PDT 24
Peak memory 242420 kb
Host smart-022db39f-7d9f-45c3-9182-4476a8dde26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345095112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.2345095112
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.3465671434
Short name T327
Test name
Test status
Simulation time 339615604551 ps
CPU time 1035.49 seconds
Started May 26 01:31:09 PM PDT 24
Finished May 26 01:48:25 PM PDT 24
Peak memory 325096 kb
Host smart-8cdfb69e-1bd3-4919-bd66-3ab7c9dcd079
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465671434 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.3465671434
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.871586410
Short name T632
Test name
Test status
Simulation time 196391746 ps
CPU time 3.77 seconds
Started May 26 01:31:09 PM PDT 24
Finished May 26 01:31:14 PM PDT 24
Peak memory 242036 kb
Host smart-e0dd18bd-5e8b-45d8-b997-d4b620656c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871586410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.871586410
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.798236411
Short name T1186
Test name
Test status
Simulation time 10354279858 ps
CPU time 21.06 seconds
Started May 26 01:31:10 PM PDT 24
Finished May 26 01:31:32 PM PDT 24
Peak memory 242004 kb
Host smart-34c17ec4-95ab-46c0-8921-a71b9ad54823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798236411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.798236411
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.127227714
Short name T975
Test name
Test status
Simulation time 57855384598 ps
CPU time 1757.12 seconds
Started May 26 01:31:12 PM PDT 24
Finished May 26 02:00:30 PM PDT 24
Peak memory 454972 kb
Host smart-aab1c724-8764-444d-9f33-2e199dbcbbb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127227714 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.127227714
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.3657798506
Short name T429
Test name
Test status
Simulation time 90942336 ps
CPU time 1.72 seconds
Started May 26 01:25:29 PM PDT 24
Finished May 26 01:25:33 PM PDT 24
Peak memory 240828 kb
Host smart-8b2cc2c6-6555-47e9-a82d-98f38cd2465b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657798506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.3657798506
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.468013577
Short name T496
Test name
Test status
Simulation time 3253802269 ps
CPU time 20 seconds
Started May 26 01:25:19 PM PDT 24
Finished May 26 01:25:40 PM PDT 24
Peak memory 242444 kb
Host smart-8b22dbe8-09c7-429c-800f-0fb17898a006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468013577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.468013577
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.3855150320
Short name T119
Test name
Test status
Simulation time 2072690871 ps
CPU time 22.97 seconds
Started May 26 01:25:21 PM PDT 24
Finished May 26 01:25:45 PM PDT 24
Peak memory 242108 kb
Host smart-e41b29b1-9f9c-4f5f-95d9-c30db7986112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855150320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.3855150320
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.3780559703
Short name T1102
Test name
Test status
Simulation time 15367549481 ps
CPU time 55.6 seconds
Started May 26 01:25:20 PM PDT 24
Finished May 26 01:26:17 PM PDT 24
Peak memory 248012 kb
Host smart-83df7a74-7d08-4988-acea-a02358dc44e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780559703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.3780559703
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.2916273274
Short name T587
Test name
Test status
Simulation time 1726868384 ps
CPU time 21.16 seconds
Started May 26 01:25:21 PM PDT 24
Finished May 26 01:25:43 PM PDT 24
Peak memory 242096 kb
Host smart-9d6ac56a-8bfe-458d-a824-19d3af250d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916273274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.2916273274
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.2519206910
Short name T1137
Test name
Test status
Simulation time 129824281 ps
CPU time 4.17 seconds
Started May 26 01:25:20 PM PDT 24
Finished May 26 01:25:26 PM PDT 24
Peak memory 242196 kb
Host smart-9c676858-b74e-49da-baca-8cdf8035bef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519206910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.2519206910
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.871760563
Short name T528
Test name
Test status
Simulation time 868079786 ps
CPU time 24.35 seconds
Started May 26 01:25:21 PM PDT 24
Finished May 26 01:25:46 PM PDT 24
Peak memory 242532 kb
Host smart-1675c469-32d7-464d-a154-0798a51238dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871760563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.871760563
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.3406757283
Short name T368
Test name
Test status
Simulation time 2458278513 ps
CPU time 42.35 seconds
Started May 26 01:25:20 PM PDT 24
Finished May 26 01:26:03 PM PDT 24
Peak memory 242532 kb
Host smart-8c3c65fe-934d-4bdb-9a02-d9e032c9922d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406757283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.3406757283
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.2122922642
Short name T828
Test name
Test status
Simulation time 356470254 ps
CPU time 7.52 seconds
Started May 26 01:25:25 PM PDT 24
Finished May 26 01:25:33 PM PDT 24
Peak memory 242048 kb
Host smart-3b09ae9a-3db5-4b4a-8a40-49fe70998154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122922642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.2122922642
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.2056981390
Short name T842
Test name
Test status
Simulation time 770473090 ps
CPU time 7.38 seconds
Started May 26 01:25:20 PM PDT 24
Finished May 26 01:25:29 PM PDT 24
Peak memory 248808 kb
Host smart-decb78cf-07c4-4fce-ab6e-78cd75a1f535
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2056981390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.2056981390
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.3389524031
Short name T825
Test name
Test status
Simulation time 303381743 ps
CPU time 9.73 seconds
Started May 26 01:25:23 PM PDT 24
Finished May 26 01:25:34 PM PDT 24
Peak memory 242232 kb
Host smart-f033d331-7876-48c1-9973-f4944f3878bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3389524031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.3389524031
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.150107341
Short name T789
Test name
Test status
Simulation time 5764465941 ps
CPU time 10.7 seconds
Started May 26 01:25:22 PM PDT 24
Finished May 26 01:25:34 PM PDT 24
Peak memory 242636 kb
Host smart-42e58248-39f3-4a54-8a1c-63e3b40fc3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150107341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.150107341
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.3210062967
Short name T9
Test name
Test status
Simulation time 5414332714 ps
CPU time 36.43 seconds
Started May 26 01:25:28 PM PDT 24
Finished May 26 01:26:07 PM PDT 24
Peak memory 241996 kb
Host smart-058ffb95-b292-4bab-8ca2-3e118c705599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210062967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.
3210062967
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.1282601915
Short name T725
Test name
Test status
Simulation time 113980213135 ps
CPU time 1159.03 seconds
Started May 26 01:25:29 PM PDT 24
Finished May 26 01:44:50 PM PDT 24
Peak memory 291844 kb
Host smart-d63558bf-8801-4afe-840d-a2e1f24441d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282601915 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.1282601915
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.1630951623
Short name T974
Test name
Test status
Simulation time 1724718976 ps
CPU time 43.74 seconds
Started May 26 01:25:24 PM PDT 24
Finished May 26 01:26:08 PM PDT 24
Peak memory 242664 kb
Host smart-7f075c20-8c27-424d-8d5c-41e715529d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630951623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.1630951623
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.3337057349
Short name T22
Test name
Test status
Simulation time 191915775 ps
CPU time 4.52 seconds
Started May 26 01:31:11 PM PDT 24
Finished May 26 01:31:17 PM PDT 24
Peak memory 242044 kb
Host smart-8d2f5c88-a341-403a-90fd-0a6a300e9fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337057349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.3337057349
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.1634619647
Short name T640
Test name
Test status
Simulation time 137299493 ps
CPU time 2.95 seconds
Started May 26 01:31:18 PM PDT 24
Finished May 26 01:31:22 PM PDT 24
Peak memory 241840 kb
Host smart-87b00106-8cd2-4a4e-87a5-1fb07ae5969f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634619647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.1634619647
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.2682825005
Short name T479
Test name
Test status
Simulation time 533828072 ps
CPU time 7.45 seconds
Started May 26 01:31:10 PM PDT 24
Finished May 26 01:31:19 PM PDT 24
Peak memory 241988 kb
Host smart-7d5eb4fd-3aa6-4511-8019-1f2deaeef405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682825005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.2682825005
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.1799560746
Short name T62
Test name
Test status
Simulation time 555536130 ps
CPU time 4.47 seconds
Started May 26 01:31:12 PM PDT 24
Finished May 26 01:31:18 PM PDT 24
Peak memory 242052 kb
Host smart-e14a7056-b813-470f-bf03-559928cfd88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799560746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.1799560746
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.2829374234
Short name T480
Test name
Test status
Simulation time 1336814846 ps
CPU time 19.82 seconds
Started May 26 01:31:10 PM PDT 24
Finished May 26 01:31:31 PM PDT 24
Peak memory 241928 kb
Host smart-ab96b54f-1ee1-4e7f-89f8-f4a4b8111d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829374234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.2829374234
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.2388414385
Short name T904
Test name
Test status
Simulation time 2844189563 ps
CPU time 15.25 seconds
Started May 26 01:31:14 PM PDT 24
Finished May 26 01:31:29 PM PDT 24
Peak memory 242380 kb
Host smart-78cc275a-3f38-4726-8cc1-41f42156800c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388414385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.2388414385
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.3481626181
Short name T1063
Test name
Test status
Simulation time 46482150482 ps
CPU time 823.98 seconds
Started May 26 01:31:10 PM PDT 24
Finished May 26 01:44:55 PM PDT 24
Peak memory 263476 kb
Host smart-e82d063c-1073-4790-9c45-1fc3967dd477
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481626181 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.3481626181
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.708980253
Short name T118
Test name
Test status
Simulation time 478639587 ps
CPU time 3.4 seconds
Started May 26 01:31:12 PM PDT 24
Finished May 26 01:31:16 PM PDT 24
Peak memory 242076 kb
Host smart-1290df9d-09d2-43e2-8c81-a8610f21d157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708980253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.708980253
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.3101910209
Short name T759
Test name
Test status
Simulation time 2648318385 ps
CPU time 13.15 seconds
Started May 26 01:31:10 PM PDT 24
Finished May 26 01:31:24 PM PDT 24
Peak memory 241988 kb
Host smart-dc61c733-32f0-4fe9-91a8-7b74cdd61e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101910209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.3101910209
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.2138935706
Short name T500
Test name
Test status
Simulation time 82806593493 ps
CPU time 2237.87 seconds
Started May 26 01:31:11 PM PDT 24
Finished May 26 02:08:30 PM PDT 24
Peak memory 276076 kb
Host smart-3ad9b5b3-d01a-4788-8035-07928e37cfee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138935706 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.2138935706
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.2967053287
Short name T839
Test name
Test status
Simulation time 416491378 ps
CPU time 4.15 seconds
Started May 26 01:31:09 PM PDT 24
Finished May 26 01:31:14 PM PDT 24
Peak memory 242028 kb
Host smart-9bc74d54-054e-48b9-af3f-501b4ed11dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967053287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.2967053287
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.602721519
Short name T692
Test name
Test status
Simulation time 356916469 ps
CPU time 9.4 seconds
Started May 26 01:31:17 PM PDT 24
Finished May 26 01:31:28 PM PDT 24
Peak memory 241900 kb
Host smart-9fcf378e-21b0-438b-bdc1-b7bd4d99deb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602721519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.602721519
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.2119214575
Short name T281
Test name
Test status
Simulation time 204956874760 ps
CPU time 985.66 seconds
Started May 26 01:31:18 PM PDT 24
Finished May 26 01:47:44 PM PDT 24
Peak memory 298152 kb
Host smart-6524d1f1-8b8d-4ed8-b62f-9056028d675f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119214575 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.2119214575
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.3549396042
Short name T1093
Test name
Test status
Simulation time 179204262 ps
CPU time 3.82 seconds
Started May 26 01:31:20 PM PDT 24
Finished May 26 01:31:24 PM PDT 24
Peak memory 242216 kb
Host smart-43c46341-6a9e-4884-aab2-f38c2ebf1e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549396042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.3549396042
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.2660163644
Short name T1053
Test name
Test status
Simulation time 262331438 ps
CPU time 5.46 seconds
Started May 26 01:31:20 PM PDT 24
Finished May 26 01:31:26 PM PDT 24
Peak memory 241800 kb
Host smart-b03b4fc0-f12a-4131-9457-e7f97bf67503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660163644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.2660163644
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.1237378055
Short name T471
Test name
Test status
Simulation time 143128573310 ps
CPU time 1384.19 seconds
Started May 26 01:31:19 PM PDT 24
Finished May 26 01:54:24 PM PDT 24
Peak memory 331856 kb
Host smart-55da42a4-b09f-467f-a180-0ee215698092
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237378055 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.1237378055
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.2539979462
Short name T575
Test name
Test status
Simulation time 1994967993 ps
CPU time 6.48 seconds
Started May 26 01:31:20 PM PDT 24
Finished May 26 01:31:27 PM PDT 24
Peak memory 241940 kb
Host smart-7c5a025e-cc9e-4d4c-a1fd-9a6862145b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539979462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.2539979462
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.3982707146
Short name T490
Test name
Test status
Simulation time 2060508696 ps
CPU time 13.9 seconds
Started May 26 01:31:18 PM PDT 24
Finished May 26 01:31:33 PM PDT 24
Peak memory 242408 kb
Host smart-8fd76779-74ee-472f-806a-7af38dc47a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982707146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.3982707146
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.3524504244
Short name T1157
Test name
Test status
Simulation time 1600580411 ps
CPU time 4.83 seconds
Started May 26 01:31:21 PM PDT 24
Finished May 26 01:31:26 PM PDT 24
Peak memory 242036 kb
Host smart-52925a33-6f36-4e39-946a-cf9fbb2fb796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524504244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.3524504244
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.813413228
Short name T580
Test name
Test status
Simulation time 481374348 ps
CPU time 14.4 seconds
Started May 26 01:31:21 PM PDT 24
Finished May 26 01:31:36 PM PDT 24
Peak memory 242060 kb
Host smart-f3bcba2f-b128-4157-999d-af74e719a2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813413228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.813413228
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.1351959362
Short name T154
Test name
Test status
Simulation time 85256610863 ps
CPU time 2064.25 seconds
Started May 26 01:31:20 PM PDT 24
Finished May 26 02:05:45 PM PDT 24
Peak memory 279408 kb
Host smart-370bf229-da99-45d7-978c-49a2e269708f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351959362 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.1351959362
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.1962656534
Short name T160
Test name
Test status
Simulation time 270277363 ps
CPU time 3.98 seconds
Started May 26 01:31:19 PM PDT 24
Finished May 26 01:31:24 PM PDT 24
Peak memory 242324 kb
Host smart-04dfcd6c-e23f-4fa8-9f55-0390e67887ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962656534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.1962656534
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.1684907619
Short name T1101
Test name
Test status
Simulation time 2525238165 ps
CPU time 6.93 seconds
Started May 26 01:31:27 PM PDT 24
Finished May 26 01:31:35 PM PDT 24
Peak memory 242360 kb
Host smart-8a4a5f48-8cfa-466c-9fdb-d2416efe874a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684907619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.1684907619
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.3496214057
Short name T280
Test name
Test status
Simulation time 115870782736 ps
CPU time 867.25 seconds
Started May 26 01:31:26 PM PDT 24
Finished May 26 01:45:54 PM PDT 24
Peak memory 292400 kb
Host smart-41c13482-6781-457d-829a-3b1a67b98629
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496214057 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.3496214057
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.3198918557
Short name T217
Test name
Test status
Simulation time 216168160 ps
CPU time 2.11 seconds
Started May 26 01:25:30 PM PDT 24
Finished May 26 01:25:35 PM PDT 24
Peak memory 240820 kb
Host smart-02ff6748-371e-4fc5-9475-1f7ea618eb4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198918557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.3198918557
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.3151264983
Short name T466
Test name
Test status
Simulation time 13783808548 ps
CPU time 40.09 seconds
Started May 26 01:25:29 PM PDT 24
Finished May 26 01:26:11 PM PDT 24
Peak memory 243144 kb
Host smart-1022a16b-404a-4055-8b05-f946c941a152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151264983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.3151264983
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.66441067
Short name T110
Test name
Test status
Simulation time 2324368676 ps
CPU time 17.07 seconds
Started May 26 01:25:32 PM PDT 24
Finished May 26 01:25:50 PM PDT 24
Peak memory 248792 kb
Host smart-7ba58731-8170-4e08-8aef-327ed9e0a520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66441067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.66441067
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.3257635926
Short name T271
Test name
Test status
Simulation time 331809692 ps
CPU time 17.67 seconds
Started May 26 01:25:28 PM PDT 24
Finished May 26 01:25:48 PM PDT 24
Peak memory 242224 kb
Host smart-b3d4c201-9aff-4b94-88e5-d43b1dde5a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257635926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.3257635926
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.2297333669
Short name T559
Test name
Test status
Simulation time 325846099 ps
CPU time 6.49 seconds
Started May 26 01:25:29 PM PDT 24
Finished May 26 01:25:37 PM PDT 24
Peak memory 242344 kb
Host smart-f1266b84-4663-4705-9971-103faae0e506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297333669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.2297333669
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.2569376894
Short name T864
Test name
Test status
Simulation time 474435563 ps
CPU time 4.22 seconds
Started May 26 01:25:31 PM PDT 24
Finished May 26 01:25:37 PM PDT 24
Peak memory 242400 kb
Host smart-8ebf3fb8-9e2a-4489-9013-8dc6288b5c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569376894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.2569376894
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.3374544681
Short name T1021
Test name
Test status
Simulation time 1130719530 ps
CPU time 8.68 seconds
Started May 26 01:25:29 PM PDT 24
Finished May 26 01:25:40 PM PDT 24
Peak memory 242092 kb
Host smart-157d7723-1002-4a31-9895-72d5fcd4c3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374544681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.3374544681
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.2310600186
Short name T897
Test name
Test status
Simulation time 6579260470 ps
CPU time 16.75 seconds
Started May 26 01:25:30 PM PDT 24
Finished May 26 01:25:49 PM PDT 24
Peak memory 243156 kb
Host smart-e65e4f7a-8b85-4010-b952-2fa49943c6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310600186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.2310600186
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.1669215531
Short name T259
Test name
Test status
Simulation time 675456981 ps
CPU time 7.57 seconds
Started May 26 01:25:28 PM PDT 24
Finished May 26 01:25:38 PM PDT 24
Peak memory 242296 kb
Host smart-cf03e8ff-a0a3-4d47-9529-1788bb39761e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669215531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.1669215531
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.2116465759
Short name T556
Test name
Test status
Simulation time 1159066096 ps
CPU time 27.66 seconds
Started May 26 01:25:30 PM PDT 24
Finished May 26 01:26:00 PM PDT 24
Peak memory 241840 kb
Host smart-6dd48151-a991-4de6-9411-8e1154b9e5e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2116465759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.2116465759
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.1539827725
Short name T360
Test name
Test status
Simulation time 383735560 ps
CPU time 2.86 seconds
Started May 26 01:25:28 PM PDT 24
Finished May 26 01:25:33 PM PDT 24
Peak memory 242312 kb
Host smart-f9455e6d-6ae9-472b-9992-5f2dff84a884
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1539827725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.1539827725
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.2008279800
Short name T821
Test name
Test status
Simulation time 2230863530 ps
CPU time 7.5 seconds
Started May 26 01:25:28 PM PDT 24
Finished May 26 01:25:37 PM PDT 24
Peak memory 242112 kb
Host smart-b30c89d1-e79a-45b9-a0b6-f23944ffb3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008279800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.2008279800
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.1270252699
Short name T1145
Test name
Test status
Simulation time 7684773666 ps
CPU time 17.69 seconds
Started May 26 01:25:27 PM PDT 24
Finished May 26 01:25:45 PM PDT 24
Peak memory 248844 kb
Host smart-2612012a-230a-428c-86a7-f273c1496575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270252699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.1270252699
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.2217784509
Short name T937
Test name
Test status
Simulation time 182824592 ps
CPU time 4 seconds
Started May 26 01:31:27 PM PDT 24
Finished May 26 01:31:33 PM PDT 24
Peak memory 242016 kb
Host smart-1592fce3-422f-4c82-8b09-c61d16eabe78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217784509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.2217784509
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.3641454594
Short name T140
Test name
Test status
Simulation time 598447823 ps
CPU time 15.96 seconds
Started May 26 01:31:26 PM PDT 24
Finished May 26 01:31:43 PM PDT 24
Peak memory 242032 kb
Host smart-94578230-a9c7-48a7-bc5d-f36d81dfc0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641454594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.3641454594
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.1144634025
Short name T909
Test name
Test status
Simulation time 171849426742 ps
CPU time 1032.78 seconds
Started May 26 01:31:27 PM PDT 24
Finished May 26 01:48:41 PM PDT 24
Peak memory 281580 kb
Host smart-25bd86ab-e510-4f3c-8e57-94380d28338e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144634025 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.1144634025
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.2646345486
Short name T691
Test name
Test status
Simulation time 1708246404 ps
CPU time 6.99 seconds
Started May 26 01:31:28 PM PDT 24
Finished May 26 01:31:36 PM PDT 24
Peak memory 242184 kb
Host smart-872b44a8-1f4f-446a-a305-580ba0964b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646345486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.2646345486
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.323378536
Short name T585
Test name
Test status
Simulation time 955087392 ps
CPU time 11.83 seconds
Started May 26 01:31:27 PM PDT 24
Finished May 26 01:31:40 PM PDT 24
Peak memory 242040 kb
Host smart-7c5b278a-3646-4051-9f73-995a67c570f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323378536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.323378536
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.2098715059
Short name T283
Test name
Test status
Simulation time 23917447843 ps
CPU time 579.63 seconds
Started May 26 01:31:28 PM PDT 24
Finished May 26 01:41:09 PM PDT 24
Peak memory 302760 kb
Host smart-9cde3d59-3d63-4f12-b6f1-367b1c3f7b7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098715059 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.2098715059
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.2957483336
Short name T802
Test name
Test status
Simulation time 210310183 ps
CPU time 4.12 seconds
Started May 26 01:31:31 PM PDT 24
Finished May 26 01:31:35 PM PDT 24
Peak memory 242404 kb
Host smart-10324f12-8bc0-4ea6-afdd-879ff1e03354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957483336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.2957483336
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.1781667503
Short name T1161
Test name
Test status
Simulation time 7561515567 ps
CPU time 18.16 seconds
Started May 26 01:31:28 PM PDT 24
Finished May 26 01:31:48 PM PDT 24
Peak memory 242520 kb
Host smart-0ded875f-2ac4-49cf-a376-747d0198d1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781667503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.1781667503
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.1733060853
Short name T166
Test name
Test status
Simulation time 734559824789 ps
CPU time 1445.85 seconds
Started May 26 01:31:25 PM PDT 24
Finished May 26 01:55:31 PM PDT 24
Peak memory 259916 kb
Host smart-0ee5afa5-e13e-4242-b06f-1e48e921e2f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733060853 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.1733060853
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.2584981459
Short name T709
Test name
Test status
Simulation time 302857940 ps
CPU time 4.51 seconds
Started May 26 01:31:27 PM PDT 24
Finished May 26 01:31:33 PM PDT 24
Peak memory 242068 kb
Host smart-2882ec6f-b9cf-49ea-9f57-794c692d603b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584981459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.2584981459
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.1034900243
Short name T878
Test name
Test status
Simulation time 586461739 ps
CPU time 4.68 seconds
Started May 26 01:31:28 PM PDT 24
Finished May 26 01:31:34 PM PDT 24
Peak memory 242036 kb
Host smart-537bedea-8984-49d6-8ee0-bd844d24a950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034900243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.1034900243
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.3604654635
Short name T1152
Test name
Test status
Simulation time 71834304843 ps
CPU time 571.44 seconds
Started May 26 01:31:27 PM PDT 24
Finished May 26 01:40:59 PM PDT 24
Peak memory 273588 kb
Host smart-a1405b1c-0fe5-4c1b-ac44-dc7d329c006f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604654635 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.3604654635
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.427236103
Short name T1059
Test name
Test status
Simulation time 2654191774 ps
CPU time 6.85 seconds
Started May 26 01:31:28 PM PDT 24
Finished May 26 01:31:36 PM PDT 24
Peak memory 242264 kb
Host smart-6241161f-f702-42d1-a106-8281a7056e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427236103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.427236103
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.550390729
Short name T1183
Test name
Test status
Simulation time 2821512767 ps
CPU time 9.52 seconds
Started May 26 01:31:37 PM PDT 24
Finished May 26 01:31:47 PM PDT 24
Peak memory 241928 kb
Host smart-ed4fb363-1bb1-42e1-aa4e-5be0efbe6db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550390729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.550390729
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.2740651306
Short name T977
Test name
Test status
Simulation time 411502325 ps
CPU time 4.79 seconds
Started May 26 01:31:40 PM PDT 24
Finished May 26 01:31:45 PM PDT 24
Peak memory 242092 kb
Host smart-9e8876eb-3af1-4c55-bf66-fc3f2d77e7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740651306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.2740651306
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.1343721437
Short name T658
Test name
Test status
Simulation time 696341600 ps
CPU time 6.55 seconds
Started May 26 01:31:39 PM PDT 24
Finished May 26 01:31:46 PM PDT 24
Peak memory 242228 kb
Host smart-2340a58c-f17e-4f5a-bf86-3a06722456e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343721437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.1343721437
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.2858750136
Short name T14
Test name
Test status
Simulation time 1006944069350 ps
CPU time 2454.44 seconds
Started May 26 01:31:37 PM PDT 24
Finished May 26 02:12:32 PM PDT 24
Peak memory 382376 kb
Host smart-b5e225db-aede-4175-b383-7aeb0ca5e8b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858750136 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.2858750136
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.3644883685
Short name T957
Test name
Test status
Simulation time 409282139 ps
CPU time 4.21 seconds
Started May 26 01:31:37 PM PDT 24
Finished May 26 01:31:42 PM PDT 24
Peak memory 242300 kb
Host smart-e7f6a06a-8b55-4e74-87ff-96a2f3847f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644883685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.3644883685
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.3553129850
Short name T363
Test name
Test status
Simulation time 711759712 ps
CPU time 20.54 seconds
Started May 26 01:31:38 PM PDT 24
Finished May 26 01:31:59 PM PDT 24
Peak memory 242428 kb
Host smart-8e4ed4c7-8dfa-46f3-8fd7-8084d5be1156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553129850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.3553129850
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.1788236469
Short name T288
Test name
Test status
Simulation time 197307274817 ps
CPU time 1667.17 seconds
Started May 26 01:31:36 PM PDT 24
Finished May 26 01:59:24 PM PDT 24
Peak memory 518180 kb
Host smart-aadce441-04c0-4dba-9990-5d555ddaa79e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788236469 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.1788236469
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.2234798007
Short name T1064
Test name
Test status
Simulation time 223267240 ps
CPU time 4.2 seconds
Started May 26 01:31:37 PM PDT 24
Finished May 26 01:31:41 PM PDT 24
Peak memory 242096 kb
Host smart-b5d09b7f-254b-4810-87ab-3e564dd72025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234798007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.2234798007
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.3783640637
Short name T1091
Test name
Test status
Simulation time 652073844 ps
CPU time 6.29 seconds
Started May 26 01:31:36 PM PDT 24
Finished May 26 01:31:43 PM PDT 24
Peak memory 242324 kb
Host smart-962d519f-4a28-493b-a5e2-942ac37d3619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783640637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.3783640637
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.2069438205
Short name T286
Test name
Test status
Simulation time 51072588301 ps
CPU time 667.67 seconds
Started May 26 01:31:40 PM PDT 24
Finished May 26 01:42:48 PM PDT 24
Peak memory 296252 kb
Host smart-4db0277c-6752-4b11-8a76-e5d07f6258ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069438205 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.2069438205
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.1849522317
Short name T681
Test name
Test status
Simulation time 464216387 ps
CPU time 4.33 seconds
Started May 26 01:31:38 PM PDT 24
Finished May 26 01:31:44 PM PDT 24
Peak memory 242296 kb
Host smart-3b6df056-c895-498c-ad82-ea367266d0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849522317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.1849522317
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.1388007096
Short name T143
Test name
Test status
Simulation time 417679685 ps
CPU time 15 seconds
Started May 26 01:31:35 PM PDT 24
Finished May 26 01:31:50 PM PDT 24
Peak memory 242040 kb
Host smart-be1ebc47-b156-401f-91bb-410a36960434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388007096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.1388007096
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.535173480
Short name T73
Test name
Test status
Simulation time 179170506 ps
CPU time 5.34 seconds
Started May 26 01:31:46 PM PDT 24
Finished May 26 01:31:52 PM PDT 24
Peak memory 242092 kb
Host smart-c60223e9-6dfc-4598-be3e-e2cdc639a188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535173480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.535173480
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.973474368
Short name T642
Test name
Test status
Simulation time 1700914773 ps
CPU time 7.83 seconds
Started May 26 01:31:44 PM PDT 24
Finished May 26 01:31:52 PM PDT 24
Peak memory 241928 kb
Host smart-1d8e78e1-f00b-43dc-8a87-5d152b524331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973474368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.973474368
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.1198333630
Short name T762
Test name
Test status
Simulation time 467646117379 ps
CPU time 1021.04 seconds
Started May 26 01:31:47 PM PDT 24
Finished May 26 01:48:49 PM PDT 24
Peak memory 347220 kb
Host smart-d7f362e5-37ec-4e36-8744-aea589cfddde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198333630 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.1198333630
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
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