SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 55031 | 1 | T2 | 186 | T3 | 138 | T7 | 377 | ||||
access_err | 58085 | 1 | T2 | 50 | T3 | 60 | T7 | 8 | ||||
write_blank_err | 379 | 1 | T3 | 1 | T4 | 5 | T5 | 1 | ||||
ecc_uncorr_err | 66460 | 1 | T3 | 497 | T4 | 220 | T5 | 556 | ||||
ecc_corr_err | 1453 | 1 | T2 | 19 | T9 | 38 | T4 | 1 | ||||
no_err | 85759 | 1 | T1 | 21 | T2 | 53 | T3 | 78 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 669 | 1 | T3 | 3 | T4 | 2 | T5 | 6 | ||||
secret2 | 24140 | 1 | T2 | 15 | T3 | 27 | T6 | 5 | ||||
secret1 | 28915 | 1 | T1 | 2 | T2 | 7 | T3 | 6 | ||||
secret0 | 38912 | 1 | T2 | 2 | T3 | 9 | T6 | 5 | ||||
hw_cfg1 | 36693 | 1 | T1 | 6 | T2 | 5 | T3 | 623 | ||||
hw_cfg0 | 22625 | 1 | T1 | 2 | T2 | 10 | T3 | 5 | ||||
rot_creator_auth_state | 23655 | 1 | T1 | 3 | T2 | 16 | T3 | 9 | ||||
rot_creator_auth_codesign | 23592 | 1 | T1 | 5 | T2 | 10 | T3 | 13 | ||||
owner_sw_cfg | 20239 | 1 | T1 | 2 | T2 | 19 | T3 | 40 | ||||
creator_sw_cfg | 19039 | 1 | T1 | 1 | T2 | 24 | T3 | 28 | ||||
vendor_test | 28688 | 1 | T2 | 200 | T3 | 11 | T6 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 4288 | 1 | T188 | 35 | T16 | 31 | T215 | 44 | ||||
fsm_err | secret1 | 7062 | 1 | T236 | 63 | T310 | 433 | T311 | 451 | ||||
fsm_err | secret0 | 3985 | 1 | T7 | 377 | T165 | 230 | T67 | 191 | ||||
fsm_err | hw_cfg1 | 7154 | 1 | T3 | 112 | T146 | 602 | T223 | 429 | ||||
fsm_err | hw_cfg0 | 5255 | 1 | T152 | 56 | T139 | 517 | T15 | 21 | ||||
fsm_err | rot_creator_auth_state | 3557 | 1 | T148 | 121 | T154 | 49 | T105 | 17 | ||||
fsm_err | rot_creator_auth_codesign | 6554 | 1 | T212 | 156 | T322 | 89 | T99 | 294 | ||||
fsm_err | owner_sw_cfg | 3223 | 1 | T3 | 26 | T188 | 36 | T323 | 45 | ||||
fsm_err | creator_sw_cfg | 1940 | 1 | T67 | 183 | T198 | 306 | T119 | 181 | ||||
fsm_err | vendor_test | 12013 | 1 | T2 | 186 | T4 | 98 | T70 | 13 | ||||
access_err | life_cycle | 669 | 1 | T3 | 3 | T4 | 2 | T5 | 6 | ||||
access_err | secret2 | 9896 | 1 | T2 | 14 | T3 | 26 | T7 | 5 | ||||
access_err | secret1 | 5946 | 1 | T2 | 4 | T9 | 10 | T10 | 1 | ||||
access_err | secret0 | 4300 | 1 | T2 | 1 | T9 | 17 | T10 | 3 | ||||
access_err | hw_cfg1 | 1204 | 1 | T3 | 2 | T7 | 1 | T9 | 6 | ||||
access_err | hw_cfg0 | 2101 | 1 | T9 | 6 | T4 | 15 | T70 | 1 | ||||
access_err | rot_creator_auth_state | 5456 | 1 | T2 | 7 | T3 | 4 | T7 | 1 | ||||
access_err | rot_creator_auth_codesign | 7474 | 1 | T3 | 1 | T9 | 23 | T10 | 6 | ||||
access_err | owner_sw_cfg | 6356 | 1 | T2 | 7 | T3 | 7 | T7 | 1 | ||||
access_err | creator_sw_cfg | 7581 | 1 | T2 | 6 | T3 | 14 | T9 | 13 | ||||
access_err | vendor_test | 7102 | 1 | T2 | 11 | T3 | 3 | T9 | 18 | ||||
write_blank_err | secret2 | 13 | 1 | T265 | 1 | T217 | 1 | T324 | 1 | ||||
write_blank_err | secret1 | 14 | 1 | T67 | 1 | T325 | 1 | T169 | 1 | ||||
write_blank_err | secret0 | 56 | 1 | T4 | 1 | T67 | 1 | T153 | 1 | ||||
write_blank_err | hw_cfg1 | 58 | 1 | T3 | 1 | T4 | 1 | T15 | 1 | ||||
write_blank_err | hw_cfg0 | 14 | 1 | T118 | 1 | T313 | 1 | T203 | 1 | ||||
write_blank_err | rot_creator_auth_state | 114 | 1 | T4 | 2 | T5 | 1 | T321 | 1 | ||||
write_blank_err | rot_creator_auth_codesign | 31 | 1 | T67 | 1 | T265 | 5 | T217 | 1 | ||||
write_blank_err | owner_sw_cfg | 32 | 1 | T67 | 1 | T118 | 1 | T223 | 1 | ||||
write_blank_err | creator_sw_cfg | 15 | 1 | T321 | 1 | T113 | 1 | T326 | 7 | ||||
write_blank_err | vendor_test | 32 | 1 | T4 | 1 | T327 | 1 | T223 | 1 | ||||
ecc_uncorr_err | secret2 | 4817 | 1 | T188 | 76 | T206 | 50 | T265 | 286 | ||||
ecc_uncorr_err | secret1 | 7265 | 1 | T152 | 56 | T67 | 318 | T148 | 126 | ||||
ecc_uncorr_err | secret0 | 22407 | 1 | T4 | 220 | T152 | 106 | T67 | 679 | ||||
ecc_uncorr_err | hw_cfg1 | 17821 | 1 | T3 | 497 | T152 | 78 | T15 | 233 | ||||
ecc_uncorr_err | hw_cfg0 | 3627 | 1 | T152 | 50 | T118 | 679 | T188 | 29 | ||||
ecc_uncorr_err | rot_creator_auth_state | 6406 | 1 | T5 | 556 | T152 | 50 | T148 | 60 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 970 | 1 | T148 | 58 | T188 | 36 | T237 | 20 | ||||
ecc_uncorr_err | owner_sw_cfg | 1796 | 1 | T148 | 58 | T184 | 63 | T118 | 508 | ||||
ecc_uncorr_err | creator_sw_cfg | 1351 | 1 | T148 | 61 | T154 | 47 | T237 | 52 | ||||
ecc_corr_err | secret2 | 88 | 1 | T9 | 3 | T70 | 3 | T86 | 3 | ||||
ecc_corr_err | secret1 | 151 | 1 | T9 | 2 | T66 | 6 | T86 | 1 | ||||
ecc_corr_err | secret0 | 167 | 1 | T9 | 3 | T152 | 2 | T66 | 4 | ||||
ecc_corr_err | hw_cfg1 | 261 | 1 | T2 | 5 | T9 | 8 | T4 | 1 | ||||
ecc_corr_err | hw_cfg0 | 283 | 1 | T2 | 2 | T9 | 7 | T70 | 7 | ||||
ecc_corr_err | rot_creator_auth_state | 136 | 1 | T9 | 7 | T152 | 1 | T86 | 13 | ||||
ecc_corr_err | rot_creator_auth_codesign | 113 | 1 | T2 | 1 | T9 | 2 | T86 | 12 | ||||
ecc_corr_err | owner_sw_cfg | 130 | 1 | T2 | 1 | T9 | 4 | T70 | 1 | ||||
ecc_corr_err | creator_sw_cfg | 124 | 1 | T2 | 10 | T9 | 2 | T152 | 1 | ||||
no_err | secret2 | 5038 | 1 | T2 | 1 | T3 | 1 | T6 | 5 | ||||
no_err | secret1 | 8477 | 1 | T1 | 2 | T2 | 3 | T3 | 6 | ||||
no_err | secret0 | 7997 | 1 | T2 | 1 | T3 | 9 | T6 | 5 | ||||
no_err | hw_cfg1 | 10195 | 1 | T1 | 6 | T3 | 11 | T6 | 6 | ||||
no_err | hw_cfg0 | 11345 | 1 | T1 | 2 | T2 | 8 | T3 | 5 | ||||
no_err | rot_creator_auth_state | 7986 | 1 | T1 | 3 | T2 | 9 | T3 | 5 | ||||
no_err | rot_creator_auth_codesign | 8450 | 1 | T1 | 5 | T2 | 9 | T3 | 12 | ||||
no_err | owner_sw_cfg | 8702 | 1 | T1 | 2 | T2 | 11 | T3 | 7 | ||||
no_err | creator_sw_cfg | 8028 | 1 | T1 | 1 | T2 | 8 | T3 | 14 | ||||
no_err | vendor_test | 9541 | 1 | T2 | 3 | T3 | 8 | T6 | 6 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |