SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 22 | 0 | 22 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
creator_sw_cfg_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
hw_cfg0_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
hw_cfg1_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
lc_esc | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
owner_sw_cfg_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
rot_creator_auth_codesign_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
rot_creator_auth_state_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
secret0_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
secret1_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
secret2_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
vendor_test_lock | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7693 | 1 | T1 | 5 | T2 | 22 | T3 | 9 | ||||
auto[1] | 4596 | 1 | T7 | 1 | T9 | 9 | T10 | 21 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7381 | 1 | T1 | 3 | T2 | 9 | T3 | 9 | ||||
auto[1] | 4908 | 1 | T1 | 2 | T2 | 13 | T6 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7460 | 1 | T1 | 5 | T2 | 11 | T3 | 9 | ||||
auto[1] | 4829 | 1 | T2 | 11 | T9 | 9 | T10 | 19 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 12254 | 1 | T1 | 5 | T2 | 22 | T3 | 9 | ||||
auto[1] | 35 | 1 | T77 | 1 | T78 | 1 | T79 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 9275 | 1 | T1 | 5 | T2 | 22 | T3 | 9 | ||||
auto[1] | 3014 | 1 | T10 | 21 | T4 | 15 | T36 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7870 | 1 | T1 | 5 | T2 | 22 | T3 | 9 | ||||
auto[1] | 4419 | 1 | T7 | 1 | T9 | 7 | T10 | 21 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 10382 | 1 | T1 | 5 | T2 | 22 | T3 | 9 | ||||
auto[1] | 1907 | 1 | T7 | 1 | T9 | 9 | T4 | 22 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7513 | 1 | T1 | 5 | T2 | 13 | T3 | 9 | ||||
auto[1] | 4776 | 1 | T2 | 9 | T6 | 2 | T9 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7387 | 1 | T1 | 5 | T2 | 9 | T3 | 9 | ||||
auto[1] | 4902 | 1 | T2 | 13 | T6 | 2 | T9 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 8794 | 1 | T1 | 5 | T2 | 13 | T3 | 9 | ||||
auto[1] | 3495 | 1 | T2 | 9 | T9 | 7 | T10 | 21 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 7613 | 1 | T1 | 5 | T2 | 22 | T3 | 9 | ||||
auto[1] | 4676 | 1 | T7 | 1 | T9 | 9 | T10 | 21 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |