Group : tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
flash_addr_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
flash_addr_req_during_lc_esc 2 0 2 100.00 100 1 1 0
flash_addr_req_during_otbn_req 2 0 2 100.00 100 1 1 2
flash_addr_req_during_otp_idle 2 0 2 100.00 100 1 1 2
flash_addr_req_during_sram_0_req 2 0 2 100.00 100 1 1 2
flash_addr_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable flash_addr_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12489 1 T2 15 T3 2 T4 17
auto[1] 2343 1 T2 1 T4 1 T8 4



Summary for Variable flash_addr_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for flash_addr_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 14792 1 T2 16 T3 2 T4 18
lc_esc_on 40 1 T106 1 T211 1 T7 1



Summary for Variable flash_addr_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13791 1 T2 16 T3 2 T4 18
auto[1] 1041 1 T17 12 T6 16 T95 3



Summary for Variable flash_addr_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2156 1 T12 2 T28 5 T116 1
auto[1] 12676 1 T2 16 T3 2 T4 18



Summary for Variable flash_addr_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13991 1 T2 16 T3 2 T4 18
auto[1] 841 1 T17 15 T6 15 T95 2



Summary for Variable flash_addr_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14387 1 T2 16 T3 2 T4 18
auto[1] 445 1 T17 1 T95 1 T14 7

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