Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	52629	1			T2	53		T4	183		T67	165
access_err	69362	1			T2	32		T3	3		T4	207
write_blank_err	480	1			T3	8		T5	1		T17	2
ecc_uncorr_err	68807	1			T2	410		T3	428		T5	176
ecc_corr_err	1364	1			T2	49		T4	51		T11	1
no_err	99408	1			T2	51		T3	42		T4	109

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	700	1			T5	2		T6	8		T15	3
secret2	25819	1			T2	2		T3	3		T4	36
secret1	30112	1			T2	70		T3	5		T4	46
secret0	43820	1			T2	25		T3	5		T4	40
hw_cfg1	44533	1			T2	199		T3	435		T4	25
hw_cfg0	23593	1			T2	5		T3	3		T4	45
rot_creator_auth_state	21613	1			T2	127		T3	6		T4	37
rot_creator_auth_codesign	24760	1			T2	105		T3	3		T4	33
owner_sw_cfg	23004	1			T2	21		T3	4		T4	38
creator_sw_cfg	21684	1			T2	12		T3	14		T4	22
vendor_test	32412	1			T2	29		T3	3		T4	228

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	4852	1			T18	96		T326	470		T201	6
fsm_err	secret1	5725	1			T106	523		T97	133		T322	35
fsm_err	secret0	6389	1			T105	251		T97	20		T18	15
fsm_err	hw_cfg1	3087	1			T116	264		T327	286		T328	284
fsm_err	hw_cfg0	3997	1			T211	468		T96	48		T93	56
fsm_err	rot_creator_auth_state	3049	1			T2	53		T13	1		T193	518
fsm_err	rot_creator_auth_codesign	5165	1			T13	272		T329	256		T233	271
fsm_err	owner_sw_cfg	4408	1			T17	206		T14	462		T330	55
fsm_err	creator_sw_cfg	2744	1			T234	37		T154	68		T331	127
fsm_err	vendor_test	13213	1			T4	183		T67	165		T17	69
access_err	life_cycle	700	1			T5	2		T6	8		T15	3
access_err	secret2	12248	1			T2	1		T3	3		T4	28
access_err	secret1	7040	1			T4	43		T8	2		T67	2
access_err	secret0	5202	1			T4	21		T5	1		T28	1
access_err	hw_cfg1	1431	1			T11	2		T28	1		T116	1
access_err	hw_cfg0	2276	1			T4	9		T28	1		T67	1
access_err	rot_creator_auth_state	6590	1			T4	26		T17	50		T105	3
access_err	rot_creator_auth_codesign	8824	1			T2	3		T4	26		T28	7
access_err	owner_sw_cfg	7773	1			T2	16		T4	22		T28	1
access_err	creator_sw_cfg	9023	1			T4	8		T28	5		T67	2
access_err	vendor_test	8255	1			T2	12		T4	24		T67	3
write_blank_err	secret2	7	1			T7	1		T240	1		T332	1
write_blank_err	secret1	21	1			T6	1		T99	1		T333	2
write_blank_err	secret0	57	1			T107	1		T14	2		T96	1
write_blank_err	hw_cfg1	86	1			T3	1		T5	1		T17	1
write_blank_err	hw_cfg0	11	1			T143	1		T334	1		T335	1
write_blank_err	rot_creator_auth_state	168	1			T17	1		T107	2		T6	5
write_blank_err	rot_creator_auth_codesign	45	1			T96	1		T99	2		T138	1
write_blank_err	owner_sw_cfg	33	1			T336	2		T240	3		T337	2
write_blank_err	creator_sw_cfg	21	1			T3	7		T333	1		T338	1
write_blank_err	vendor_test	31	1			T6	4		T7	1		T99	1
ecc_uncorr_err	secret2	2855	1			T7	485		T249	63		T93	44
ecc_uncorr_err	secret1	7421	1			T2	57		T108	106		T6	371
ecc_uncorr_err	secret0	22249	1			T2	9		T107	476		T108	95
ecc_uncorr_err	hw_cfg1	27986	1			T2	188		T3	428		T5	176
ecc_uncorr_err	hw_cfg0	3694	1			T249	71		T93	52		T154	131
ecc_uncorr_err	rot_creator_auth_state	2693	1			T2	67		T11	16		T97	804
ecc_uncorr_err	rot_creator_auth_codesign	615	1			T2	89		T93	51		T201	19
ecc_uncorr_err	owner_sw_cfg	633	1			T165	54		T154	75		T155	11
ecc_uncorr_err	creator_sw_cfg	661	1			T108	45		T165	56		T93	40
ecc_corr_err	secret2	75	1			T2	1		T4	3		T11	1
ecc_corr_err	secret1	143	1			T2	7		T4	1		T67	9
ecc_corr_err	secret0	150	1			T2	13		T4	5		T67	1
ecc_corr_err	hw_cfg1	267	1			T2	11		T4	11		T249	1
ecc_corr_err	hw_cfg0	248	1			T2	1		T4	17		T67	5
ecc_corr_err	rot_creator_auth_state	121	1			T2	4		T67	1		T17	2
ecc_corr_err	rot_creator_auth_codesign	119	1			T2	4		T4	2		T67	9
ecc_corr_err	owner_sw_cfg	106	1			T2	2		T4	2		T67	1
ecc_corr_err	creator_sw_cfg	135	1			T2	6		T4	10		T212	1
no_err	secret2	5782	1			T4	5		T8	3		T12	2
no_err	secret1	9762	1			T2	6		T3	5		T4	2
no_err	secret0	9773	1			T2	3		T3	5		T4	14
no_err	hw_cfg1	11676	1			T3	6		T4	14		T5	4
no_err	hw_cfg0	13367	1			T2	4		T3	3		T4	19
no_err	rot_creator_auth_state	8992	1			T2	3		T3	6		T4	11
no_err	rot_creator_auth_codesign	9992	1			T2	9		T3	3		T4	5
no_err	owner_sw_cfg	10051	1			T2	3		T3	4		T4	14
no_err	creator_sw_cfg	9100	1			T2	6		T3	7		T4	4
no_err	vendor_test	10913	1			T2	17		T3	3		T4	21

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded