Group : tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg
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Group : tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
sram_1_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
sram_1_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
sram_1_req_during_lc_esc 2 0 2 100.00 100 1 1 0
sram_1_req_during_otbn_req 2 0 2 100.00 100 1 1 2
sram_1_req_during_otp_idle 2 0 2 100.00 100 1 1 2
sram_1_req_during_sram_0_req 2 0 2 100.00 100 1 1 2


Summary for Variable sram_1_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14160 1 T2 16 T4 72 T5 12
auto[1] 824 1 T10 4 T93 2 T13 2



Summary for Variable sram_1_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14105 1 T2 16 T4 72 T5 12
auto[1] 879 1 T10 8 T26 1 T93 2



Summary for Variable sram_1_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for sram_1_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 14939 1 T2 16 T4 72 T5 12
lc_esc_on 45 1 T15 1 T14 1 T34 1



Summary for Variable sram_1_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14234 1 T2 16 T4 72 T5 12
auto[1] 750 1 T10 4 T26 2 T93 2



Summary for Variable sram_1_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1967 1 T4 8 T10 18 T26 2
auto[1] 13017 1 T2 16 T4 64 T5 12



Summary for Variable sram_1_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14775 1 T2 16 T4 72 T5 12
auto[1] 209 1 T10 1 T34 2 T118 1

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