Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	52860	1			T5	6		T10	106		T12	57
access_err	71984	1			T2	148		T4	300		T5	2
write_blank_err	403	1			T6	1		T13	6		T15	3
ecc_uncorr_err	71618	1			T5	37		T6	280		T13	447
ecc_corr_err	1567	1			T5	6		T12	33		T62	42
no_err	102004	1			T2	153		T4	447		T5	20

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	681	1			T6	1		T13	12		T14	3
secret2	24636	1			T2	22		T4	89		T5	2
secret1	32204	1			T2	40		T4	50		T5	10
secret0	44060	1			T2	27		T4	52		T5	14
hw_cfg1	38659	1			T2	20		T4	52		T5	2
hw_cfg0	28115	1			T2	44		T4	75		T5	5
rot_creator_auth_state	24669	1			T2	17		T4	66		T10	71
rot_creator_auth_codesign	24845	1			T2	38		T4	101		T5	10
owner_sw_cfg	24178	1			T2	21		T4	88		T5	13
creator_sw_cfg	23615	1			T2	37		T4	104		T5	6
vendor_test	34774	1			T2	35		T4	70		T5	9

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3929	1			T349	468		T133	142		T259	53
fsm_err	secret1	6159	1			T10	76		T350	1		T20	757
fsm_err	secret0	5326	1			T15	341		T140	7		T141	576
fsm_err	hw_cfg1	4420	1			T262	103		T132	272		T351	33
fsm_err	hw_cfg0	6287	1			T10	30		T34	743		T352	150
fsm_err	rot_creator_auth_state	1322	1			T353	10		T230	110		T354	49
fsm_err	rot_creator_auth_codesign	3355	1			T14	91		T206	219		T255	359
fsm_err	owner_sw_cfg	4180	1			T244	85		T14	244		T161	30
fsm_err	creator_sw_cfg	3030	1			T151	17		T202	1		T118	233
fsm_err	vendor_test	14852	1			T5	6		T12	57		T62	124
access_err	life_cycle	681	1			T6	1		T13	12		T14	3
access_err	secret2	12510	1			T2	21		T4	72		T5	2
access_err	secret1	6601	1			T2	36		T10	57		T12	10
access_err	secret0	5135	1			T2	5		T10	52		T12	3
access_err	hw_cfg1	1371	1			T2	8		T4	3		T10	12
access_err	hw_cfg0	2478	1			T2	8		T10	27		T12	4
access_err	rot_creator_auth_state	7154	1			T2	2		T4	35		T10	17
access_err	rot_creator_auth_codesign	9472	1			T2	25		T4	55		T10	48
access_err	owner_sw_cfg	8178	1			T2	12		T4	42		T10	41
access_err	creator_sw_cfg	9347	1			T2	14		T4	57		T10	31
access_err	vendor_test	9057	1			T2	17		T4	36		T10	37
write_blank_err	secret2	6	1			T34	1		T325	1		T344	1
write_blank_err	secret1	23	1			T6	1		T206	1		T118	1
write_blank_err	secret0	54	1			T13	1		T14	1		T16	1
write_blank_err	hw_cfg1	70	1			T13	2		T15	1		T96	1
write_blank_err	hw_cfg0	20	1			T18	1		T221	1		T311	1
write_blank_err	rot_creator_auth_state	120	1			T13	3		T15	2		T96	1
write_blank_err	rot_creator_auth_codesign	46	1			T34	1		T201	1		T118	1
write_blank_err	owner_sw_cfg	25	1			T313	1		T287	1		T289	1
write_blank_err	creator_sw_cfg	15	1			T243	1		T289	1		T137	1
write_blank_err	vendor_test	24	1			T355	1		T204	1		T342	1
ecc_uncorr_err	secret2	2568	1			T34	576		T325	625		T223	6
ecc_uncorr_err	secret1	8993	1			T5	6		T6	280		T161	34
ecc_uncorr_err	secret0	23716	1			T5	13		T13	223		T151	34
ecc_uncorr_err	hw_cfg1	20535	1			T13	224		T15	122		T151	37
ecc_uncorr_err	hw_cfg0	5134	1			T151	22		T155	2		T18	248
ecc_uncorr_err	rot_creator_auth_state	6383	1			T151	42		T356	53		T18	274
ecc_uncorr_err	rot_creator_auth_codesign	1638	1			T5	10		T165	115		T224	47
ecc_uncorr_err	owner_sw_cfg	995	1			T5	8		T151	32		T161	15
ecc_uncorr_err	creator_sw_cfg	1656	1			T243	66		T165	167		T357	39
ecc_corr_err	secret2	78	1			T12	1		T151	3		T155	1
ecc_corr_err	secret1	142	1			T12	2		T62	3		T151	1
ecc_corr_err	secret0	170	1			T12	6		T62	1		T46	3
ecc_corr_err	hw_cfg1	288	1			T5	2		T12	2		T62	17
ecc_corr_err	hw_cfg0	302	1			T5	1		T12	10		T62	8
ecc_corr_err	rot_creator_auth_state	135	1			T12	3		T62	4		T151	1
ecc_corr_err	rot_creator_auth_codesign	137	1			T12	7		T62	3		T46	1
ecc_corr_err	owner_sw_cfg	166	1			T12	2		T62	4		T151	6
ecc_corr_err	creator_sw_cfg	149	1			T5	3		T62	2		T151	3
no_err	secret2	5545	1			T2	1		T4	17		T10	48
no_err	secret1	10286	1			T2	4		T4	50		T5	4
no_err	secret0	9659	1			T2	22		T4	52		T5	1
no_err	hw_cfg1	11975	1			T2	12		T4	49		T10	58
no_err	hw_cfg0	13894	1			T2	36		T4	75		T5	4
no_err	rot_creator_auth_state	9555	1			T2	15		T4	31		T10	54
no_err	rot_creator_auth_codesign	10197	1			T2	13		T4	46		T10	44
no_err	owner_sw_cfg	10634	1			T2	9		T4	46		T5	5
no_err	creator_sw_cfg	9418	1			T2	23		T4	47		T5	3
no_err	vendor_test	10841	1			T2	18		T4	34		T5	3

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded