Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv



Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
secret1_lock 2 0 2 100.00 100 1 1 2
sram_index 4 0 4 100.00 100 1 1 0


Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sram_req_lock_cross 8 0 8 100.00 100 1 1 0


Summary for Variable secret1_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for secret1_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1533 1 T13 35 T103 4 T16 36
auto[1] 977 1 T26 5 T63 1 T103 15



Summary for Variable sram_index

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for sram_index

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sram_key[0x0] 74 1 T26 2 T103 3 T16 1
sram_key[0x1] 789 1 T26 2 T13 11 T103 6
sram_key[0x2] 817 1 T63 1 T13 11 T103 8
sram_key[0x3] 830 1 T26 1 T13 13 T103 2



Summary for Cross sram_req_lock_cross

Samples crossed: sram_index secret1_lock
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for sram_req_lock_cross

Bins
sram_indexsecret1_lockCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sram_key[0x0] auto[0] 51 1 T103 1 T16 1 T254 1
sram_key[0x0] auto[1] 23 1 T26 2 T103 2 T209 2
sram_key[0x1] auto[0] 479 1 T13 11 T103 1 T16 11
sram_key[0x1] auto[1] 310 1 T26 2 T103 5 T171 1
sram_key[0x2] auto[0] 485 1 T13 11 T103 2 T16 12
sram_key[0x2] auto[1] 332 1 T63 1 T103 6 T171 1
sram_key[0x3] auto[0] 518 1 T13 13 T16 12 T269 3
sram_key[0x3] auto[1] 312 1 T26 1 T103 2 T383 9

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%