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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.94 93.89 96.27 95.48 92.12 97.10 96.33 93.35


Total test records in report: 1327
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T1264 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.691025438 Jun 02 03:05:21 PM PDT 24 Jun 02 03:05:25 PM PDT 24 123411820 ps
T310 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.4243748454 Jun 02 03:05:19 PM PDT 24 Jun 02 03:05:21 PM PDT 24 81258468 ps
T1265 /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.863171204 Jun 02 03:05:22 PM PDT 24 Jun 02 03:05:24 PM PDT 24 42917093 ps
T1266 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2779044394 Jun 02 03:04:52 PM PDT 24 Jun 02 03:04:54 PM PDT 24 133601666 ps
T1267 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.2905317574 Jun 02 03:05:30 PM PDT 24 Jun 02 03:05:32 PM PDT 24 139998635 ps
T365 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1557380548 Jun 02 03:05:22 PM PDT 24 Jun 02 03:05:33 PM PDT 24 1240398448 ps
T1268 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.3885592639 Jun 02 03:05:23 PM PDT 24 Jun 02 03:05:25 PM PDT 24 149269187 ps
T1269 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.163616157 Jun 02 03:05:10 PM PDT 24 Jun 02 03:05:15 PM PDT 24 121324802 ps
T1270 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.2307561926 Jun 02 03:05:22 PM PDT 24 Jun 02 03:05:23 PM PDT 24 138120609 ps
T1271 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3266932209 Jun 02 03:04:56 PM PDT 24 Jun 02 03:05:02 PM PDT 24 394979007 ps
T1272 /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.3349464661 Jun 02 03:05:30 PM PDT 24 Jun 02 03:05:32 PM PDT 24 73430669 ps
T1273 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.756874045 Jun 02 03:04:50 PM PDT 24 Jun 02 03:04:58 PM PDT 24 1986835567 ps
T1274 /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.1218893225 Jun 02 03:05:33 PM PDT 24 Jun 02 03:05:35 PM PDT 24 134631278 ps
T366 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.435107984 Jun 02 03:04:47 PM PDT 24 Jun 02 03:05:11 PM PDT 24 5067312701 ps
T318 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.4272630449 Jun 02 03:05:09 PM PDT 24 Jun 02 03:05:12 PM PDT 24 93706011 ps
T1275 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.2885470430 Jun 02 03:05:09 PM PDT 24 Jun 02 03:05:11 PM PDT 24 44899160 ps
T1276 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.1539184597 Jun 02 03:05:22 PM PDT 24 Jun 02 03:05:24 PM PDT 24 139364234 ps
T319 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3369276453 Jun 02 03:04:53 PM PDT 24 Jun 02 03:05:01 PM PDT 24 190762753 ps
T1277 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.1875839176 Jun 02 03:05:25 PM PDT 24 Jun 02 03:05:27 PM PDT 24 39462903 ps
T1278 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1289448811 Jun 02 03:05:05 PM PDT 24 Jun 02 03:05:08 PM PDT 24 67590972 ps
T1279 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.4000981297 Jun 02 03:05:21 PM PDT 24 Jun 02 03:05:26 PM PDT 24 199694421 ps
T358 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.838852902 Jun 02 03:05:16 PM PDT 24 Jun 02 03:05:35 PM PDT 24 3106780554 ps
T1280 /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.3292675487 Jun 02 03:04:53 PM PDT 24 Jun 02 03:04:55 PM PDT 24 41475762 ps
T1281 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.1646685767 Jun 02 03:05:16 PM PDT 24 Jun 02 03:05:18 PM PDT 24 40314401 ps
T362 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.870362764 Jun 02 03:05:14 PM PDT 24 Jun 02 03:05:32 PM PDT 24 4019425336 ps
T1282 /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.3841597532 Jun 02 03:04:56 PM PDT 24 Jun 02 03:04:59 PM PDT 24 135473639 ps
T1283 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2691281303 Jun 02 03:04:53 PM PDT 24 Jun 02 03:04:56 PM PDT 24 39948478 ps
T1284 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1412331585 Jun 02 03:04:52 PM PDT 24 Jun 02 03:04:55 PM PDT 24 283898127 ps
T1285 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1337097199 Jun 02 03:04:56 PM PDT 24 Jun 02 03:04:59 PM PDT 24 42565059 ps
T1286 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1421576348 Jun 02 03:05:15 PM PDT 24 Jun 02 03:05:20 PM PDT 24 109818205 ps
T1287 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1524594918 Jun 02 03:05:15 PM PDT 24 Jun 02 03:05:28 PM PDT 24 1048373825 ps
T1288 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.1190761860 Jun 02 03:05:02 PM PDT 24 Jun 02 03:05:05 PM PDT 24 189438317 ps
T1289 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.1537387708 Jun 02 03:05:27 PM PDT 24 Jun 02 03:05:29 PM PDT 24 139602063 ps
T1290 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.125101992 Jun 02 03:05:16 PM PDT 24 Jun 02 03:05:27 PM PDT 24 668297421 ps
T1291 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.4026694410 Jun 02 03:04:56 PM PDT 24 Jun 02 03:05:05 PM PDT 24 903429356 ps
T1292 /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.1546185707 Jun 02 03:05:27 PM PDT 24 Jun 02 03:05:29 PM PDT 24 41250644 ps
T1293 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.2215875648 Jun 02 03:04:57 PM PDT 24 Jun 02 03:05:02 PM PDT 24 1064461856 ps
T1294 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.1856051763 Jun 02 03:04:47 PM PDT 24 Jun 02 03:04:49 PM PDT 24 136680735 ps
T1295 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2833326630 Jun 02 03:05:23 PM PDT 24 Jun 02 03:05:36 PM PDT 24 2460216624 ps
T1296 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.517463039 Jun 02 03:05:00 PM PDT 24 Jun 02 03:05:04 PM PDT 24 67225050 ps
T1297 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.3959839073 Jun 02 03:05:08 PM PDT 24 Jun 02 03:05:10 PM PDT 24 532963935 ps
T1298 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.3389645973 Jun 02 03:05:03 PM PDT 24 Jun 02 03:05:06 PM PDT 24 530177248 ps
T1299 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1175491527 Jun 02 03:05:15 PM PDT 24 Jun 02 03:05:19 PM PDT 24 122800535 ps
T1300 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2649889526 Jun 02 03:04:50 PM PDT 24 Jun 02 03:04:53 PM PDT 24 209537343 ps
T1301 /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2160534539 Jun 02 03:05:27 PM PDT 24 Jun 02 03:05:29 PM PDT 24 96921427 ps
T281 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1516700077 Jun 02 03:04:59 PM PDT 24 Jun 02 03:05:20 PM PDT 24 6180323510 ps
T1302 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.2966940622 Jun 02 03:04:59 PM PDT 24 Jun 02 03:05:06 PM PDT 24 302671574 ps
T1303 /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2725965081 Jun 02 03:05:16 PM PDT 24 Jun 02 03:05:18 PM PDT 24 36312547 ps
T320 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1197574982 Jun 02 03:04:58 PM PDT 24 Jun 02 03:05:03 PM PDT 24 838027620 ps
T1304 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1062427045 Jun 02 03:05:22 PM PDT 24 Jun 02 03:05:24 PM PDT 24 42305634 ps
T1305 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.740029809 Jun 02 03:05:09 PM PDT 24 Jun 02 03:05:20 PM PDT 24 645382216 ps
T1306 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.1159774339 Jun 02 03:05:25 PM PDT 24 Jun 02 03:05:27 PM PDT 24 135217571 ps
T1307 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.553549462 Jun 02 03:05:06 PM PDT 24 Jun 02 03:05:08 PM PDT 24 62859116 ps
T1308 /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.417126109 Jun 02 03:05:25 PM PDT 24 Jun 02 03:05:27 PM PDT 24 44388829 ps
T321 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.1356107182 Jun 02 03:04:56 PM PDT 24 Jun 02 03:05:00 PM PDT 24 129346246 ps
T1309 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.145330421 Jun 02 03:05:22 PM PDT 24 Jun 02 03:05:25 PM PDT 24 143560359 ps
T1310 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.203444584 Jun 02 03:05:02 PM PDT 24 Jun 02 03:05:05 PM PDT 24 48898192 ps
T1311 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.983499232 Jun 02 03:04:59 PM PDT 24 Jun 02 03:05:03 PM PDT 24 49798211 ps
T1312 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.3257926900 Jun 02 03:05:17 PM PDT 24 Jun 02 03:05:20 PM PDT 24 1064618061 ps
T1313 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1070389763 Jun 02 03:04:56 PM PDT 24 Jun 02 03:04:59 PM PDT 24 40526241 ps
T1314 /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1359096819 Jun 02 03:05:06 PM PDT 24 Jun 02 03:05:10 PM PDT 24 82285055 ps
T323 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.52834165 Jun 02 03:05:15 PM PDT 24 Jun 02 03:05:17 PM PDT 24 142569853 ps
T1315 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2524345246 Jun 02 03:05:21 PM PDT 24 Jun 02 03:05:25 PM PDT 24 111731786 ps
T1316 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.837803483 Jun 02 03:04:56 PM PDT 24 Jun 02 03:05:00 PM PDT 24 75652509 ps
T324 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3236696446 Jun 02 03:05:21 PM PDT 24 Jun 02 03:05:23 PM PDT 24 155115056 ps
T1317 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2704119498 Jun 02 03:04:51 PM PDT 24 Jun 02 03:04:53 PM PDT 24 136841086 ps
T1318 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1433044160 Jun 02 03:04:56 PM PDT 24 Jun 02 03:04:59 PM PDT 24 47589892 ps
T1319 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.2329788452 Jun 02 03:04:57 PM PDT 24 Jun 02 03:05:02 PM PDT 24 99807980 ps
T1320 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1128973795 Jun 02 03:05:22 PM PDT 24 Jun 02 03:05:25 PM PDT 24 1000189050 ps
T1321 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.83240627 Jun 02 03:04:58 PM PDT 24 Jun 02 03:05:04 PM PDT 24 149764093 ps
T1322 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.1185457719 Jun 02 03:05:01 PM PDT 24 Jun 02 03:05:04 PM PDT 24 37385631 ps
T329 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.908432607 Jun 02 03:05:19 PM PDT 24 Jun 02 03:05:22 PM PDT 24 43228422 ps
T1323 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.2352853454 Jun 02 03:05:17 PM PDT 24 Jun 02 03:05:19 PM PDT 24 46276174 ps
T1324 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.1384157479 Jun 02 03:04:59 PM PDT 24 Jun 02 03:05:02 PM PDT 24 37589852 ps
T1325 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3832825302 Jun 02 03:05:13 PM PDT 24 Jun 02 03:05:16 PM PDT 24 106835692 ps
T1326 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.4171330142 Jun 02 03:05:09 PM PDT 24 Jun 02 03:05:12 PM PDT 24 65248854 ps
T1327 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3692270988 Jun 02 03:05:12 PM PDT 24 Jun 02 03:05:14 PM PDT 24 72663134 ps

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.3026387099
Short name T10
Test name
Test status
Simulation time 10101630799 ps
CPU time 122.15 seconds
Started Jun 02 03:08:51 PM PDT 24
Finished Jun 02 03:10:54 PM PDT 24
Peak memory 246272 kb
Host smart-ede46b7a-151a-487e-9678-542074e65f14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026387099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.3026387099
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.238348786
Short name T4
Test name
Test status
Simulation time 746264535289 ps
CPU time 1952.51 seconds
Started Jun 02 03:10:34 PM PDT 24
Finished Jun 02 03:43:08 PM PDT 24
Peak memory 375964 kb
Host smart-135451b2-971a-4270-a726-2c9f55026679
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238348786 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.238348786
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.3513485696
Short name T209
Test name
Test status
Simulation time 21274575485 ps
CPU time 251.97 seconds
Started Jun 02 03:08:01 PM PDT 24
Finished Jun 02 03:12:14 PM PDT 24
Peak memory 265576 kb
Host smart-4e5ab21c-b423-47ca-8ce0-f0c0ad8157da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513485696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.3513485696
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.3240610234
Short name T130
Test name
Test status
Simulation time 12565661542 ps
CPU time 216.53 seconds
Started Jun 02 03:09:28 PM PDT 24
Finished Jun 02 03:13:06 PM PDT 24
Peak memory 257208 kb
Host smart-c7693f37-9d9c-4515-9bc8-cd2177adfd8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240610234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.3240610234
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.241971596
Short name T62
Test name
Test status
Simulation time 2986055492 ps
CPU time 28.77 seconds
Started Jun 02 03:10:08 PM PDT 24
Finished Jun 02 03:10:38 PM PDT 24
Peak memory 249052 kb
Host smart-2dad5878-cd77-48ef-9710-0aab954ca47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241971596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.241971596
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.1599409420
Short name T157
Test name
Test status
Simulation time 1950297224 ps
CPU time 3.96 seconds
Started Jun 02 03:11:35 PM PDT 24
Finished Jun 02 03:11:39 PM PDT 24
Peak memory 242652 kb
Host smart-4306cab8-fa49-4cb4-9610-c588f50583cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599409420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.1599409420
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.1773723327
Short name T22
Test name
Test status
Simulation time 154684796384 ps
CPU time 344.87 seconds
Started Jun 02 03:07:37 PM PDT 24
Finished Jun 02 03:13:22 PM PDT 24
Peak memory 270424 kb
Host smart-09c44a5b-c752-45dd-808c-35cb62df9fb8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773723327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.1773723327
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.1229113204
Short name T96
Test name
Test status
Simulation time 13545775183 ps
CPU time 113.98 seconds
Started Jun 02 03:08:09 PM PDT 24
Finished Jun 02 03:10:04 PM PDT 24
Peak memory 249016 kb
Host smart-f27bbd25-dbea-46cf-b464-1b8fb2efb6fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229113204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all
.1229113204
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.2839550304
Short name T3
Test name
Test status
Simulation time 244123578 ps
CPU time 4.65 seconds
Started Jun 02 03:07:32 PM PDT 24
Finished Jun 02 03:07:37 PM PDT 24
Peak memory 242244 kb
Host smart-19efa8f1-0966-4601-a17a-019742f23875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839550304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.2839550304
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.3088608983
Short name T255
Test name
Test status
Simulation time 314006661602 ps
CPU time 2981.7 seconds
Started Jun 02 03:10:32 PM PDT 24
Finished Jun 02 04:00:15 PM PDT 24
Peak memory 647180 kb
Host smart-0bd1a377-6428-44ce-9a69-7b98271bd470
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088608983 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.3088608983
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.3470917088
Short name T275
Test name
Test status
Simulation time 2913539703 ps
CPU time 20.51 seconds
Started Jun 02 03:05:03 PM PDT 24
Finished Jun 02 03:05:25 PM PDT 24
Peak memory 244440 kb
Host smart-7f82be05-7dda-4d2d-bc8b-d4ae410ee4c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470917088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.3470917088
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.2978472783
Short name T9
Test name
Test status
Simulation time 2491094500 ps
CPU time 6.45 seconds
Started Jun 02 03:12:04 PM PDT 24
Finished Jun 02 03:12:11 PM PDT 24
Peak memory 242508 kb
Host smart-5aae0a88-6167-4e69-ae99-6d885d0c2613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978472783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.2978472783
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.371586498
Short name T46
Test name
Test status
Simulation time 12169714922 ps
CPU time 38.67 seconds
Started Jun 02 03:08:15 PM PDT 24
Finished Jun 02 03:08:55 PM PDT 24
Peak memory 245356 kb
Host smart-3d22eab2-127f-4cac-92d0-82a6faf38918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371586498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.371586498
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.220372705
Short name T285
Test name
Test status
Simulation time 20213520502 ps
CPU time 306.24 seconds
Started Jun 02 03:07:53 PM PDT 24
Finished Jun 02 03:13:00 PM PDT 24
Peak memory 257232 kb
Host smart-2df13765-0f82-4544-949a-9fb465372139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220372705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.220372705
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.4047458742
Short name T76
Test name
Test status
Simulation time 148060507 ps
CPU time 3.95 seconds
Started Jun 02 03:12:06 PM PDT 24
Finished Jun 02 03:12:11 PM PDT 24
Peak memory 242568 kb
Host smart-8324646a-32a6-4e4e-b469-87e78921ee3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047458742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.4047458742
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.4117348888
Short name T20
Test name
Test status
Simulation time 377895238571 ps
CPU time 1457.82 seconds
Started Jun 02 03:08:04 PM PDT 24
Finished Jun 02 03:32:23 PM PDT 24
Peak memory 334304 kb
Host smart-ccf266aa-335b-44f8-af42-e51285466151
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117348888 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.4117348888
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.288475807
Short name T78
Test name
Test status
Simulation time 105560810 ps
CPU time 3.84 seconds
Started Jun 02 03:10:42 PM PDT 24
Finished Jun 02 03:10:47 PM PDT 24
Peak memory 242656 kb
Host smart-2d618481-454b-46c7-864c-51c86da8282b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288475807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.288475807
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.1248882504
Short name T48
Test name
Test status
Simulation time 660066309 ps
CPU time 4.8 seconds
Started Jun 02 03:07:46 PM PDT 24
Finished Jun 02 03:07:51 PM PDT 24
Peak memory 242772 kb
Host smart-7836e266-c10e-42d3-bf9a-c7b93ccaf758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248882504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.1248882504
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.362221257
Short name T215
Test name
Test status
Simulation time 1922395294 ps
CPU time 29.68 seconds
Started Jun 02 03:09:28 PM PDT 24
Finished Jun 02 03:09:59 PM PDT 24
Peak memory 248908 kb
Host smart-a1c8f2b1-ecc1-474f-a1d2-32a227aeb423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362221257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.362221257
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.3454168291
Short name T118
Test name
Test status
Simulation time 83437544302 ps
CPU time 1402.38 seconds
Started Jun 02 03:08:58 PM PDT 24
Finished Jun 02 03:32:21 PM PDT 24
Peak memory 436200 kb
Host smart-63ece371-af85-4e38-a1b8-8d1ada08ef7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454168291 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.3454168291
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.1113737934
Short name T249
Test name
Test status
Simulation time 91603407 ps
CPU time 1.67 seconds
Started Jun 02 03:07:35 PM PDT 24
Finished Jun 02 03:07:38 PM PDT 24
Peak memory 240880 kb
Host smart-49165c0f-0148-49a0-b15d-6ca5de274fdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113737934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.1113737934
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.3055830191
Short name T61
Test name
Test status
Simulation time 321088888 ps
CPU time 4.39 seconds
Started Jun 02 03:11:20 PM PDT 24
Finished Jun 02 03:11:25 PM PDT 24
Peak memory 242476 kb
Host smart-9c89119c-31ee-4461-999a-e84ab1692ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055830191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.3055830191
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.3558932594
Short name T36
Test name
Test status
Simulation time 1818626693 ps
CPU time 43.66 seconds
Started Jun 02 03:07:48 PM PDT 24
Finished Jun 02 03:08:32 PM PDT 24
Peak memory 249212 kb
Host smart-242a5941-79a0-4a98-9eeb-956147cb3734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558932594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.3558932594
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.1717016617
Short name T51
Test name
Test status
Simulation time 1989359680 ps
CPU time 7.03 seconds
Started Jun 02 03:11:57 PM PDT 24
Finished Jun 02 03:12:04 PM PDT 24
Peak memory 242692 kb
Host smart-8e40bcb0-8a32-43b4-882b-5b4990450148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717016617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.1717016617
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.3121052587
Short name T160
Test name
Test status
Simulation time 1795257544 ps
CPU time 5.05 seconds
Started Jun 02 03:11:44 PM PDT 24
Finished Jun 02 03:11:49 PM PDT 24
Peak memory 242324 kb
Host smart-d527f514-3d23-47de-8901-1c70bc1fb5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121052587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.3121052587
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.1630273461
Short name T137
Test name
Test status
Simulation time 155458179820 ps
CPU time 2730.12 seconds
Started Jun 02 03:10:43 PM PDT 24
Finished Jun 02 03:56:14 PM PDT 24
Peak memory 314660 kb
Host smart-e75125b1-771b-4f37-a1f2-f653d0aeae3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630273461 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.1630273461
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.1024918130
Short name T38
Test name
Test status
Simulation time 252322377 ps
CPU time 5.34 seconds
Started Jun 02 03:10:35 PM PDT 24
Finished Jun 02 03:10:41 PM PDT 24
Peak memory 242400 kb
Host smart-562b0a3e-b058-4e69-826b-9dd87e33195e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024918130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.1024918130
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.2087195261
Short name T43
Test name
Test status
Simulation time 2214192369 ps
CPU time 5.06 seconds
Started Jun 02 03:07:27 PM PDT 24
Finished Jun 02 03:07:33 PM PDT 24
Peak memory 242468 kb
Host smart-f6b4de27-8c4d-4b29-911d-f1d262dbe143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087195261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.2087195261
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.2999325284
Short name T188
Test name
Test status
Simulation time 1673489018 ps
CPU time 4.3 seconds
Started Jun 02 03:10:55 PM PDT 24
Finished Jun 02 03:10:59 PM PDT 24
Peak memory 242608 kb
Host smart-b4c75202-552b-4af9-883a-b819c50bf9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999325284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.2999325284
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.399014759
Short name T31
Test name
Test status
Simulation time 210646650 ps
CPU time 4.31 seconds
Started Jun 02 03:10:59 PM PDT 24
Finished Jun 02 03:11:04 PM PDT 24
Peak memory 242248 kb
Host smart-ca41763f-99e7-44ae-8bfa-b1451ea2e167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399014759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.399014759
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.2623345009
Short name T552
Test name
Test status
Simulation time 1372481689 ps
CPU time 29.79 seconds
Started Jun 02 03:09:12 PM PDT 24
Finished Jun 02 03:09:43 PM PDT 24
Peak memory 259916 kb
Host smart-48e1b7d8-6719-4266-9395-3bbbf7523cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623345009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.2623345009
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.808226613
Short name T120
Test name
Test status
Simulation time 22824280403 ps
CPU time 237.93 seconds
Started Jun 02 03:09:19 PM PDT 24
Finished Jun 02 03:13:17 PM PDT 24
Peak memory 257188 kb
Host smart-c1f0deae-6c52-4949-8874-13883908e143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808226613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all.
808226613
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.2662317932
Short name T34
Test name
Test status
Simulation time 494974023849 ps
CPU time 2382.48 seconds
Started Jun 02 03:10:24 PM PDT 24
Finished Jun 02 03:50:07 PM PDT 24
Peak memory 379204 kb
Host smart-8838d4e4-5c87-4a62-8aad-a5dea34c6275
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662317932 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.2662317932
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.921132349
Short name T257
Test name
Test status
Simulation time 26922539771 ps
CPU time 180.29 seconds
Started Jun 02 03:09:00 PM PDT 24
Finished Jun 02 03:12:01 PM PDT 24
Peak memory 256336 kb
Host smart-f920f07c-dcf8-421c-bd1d-893ded1275e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921132349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.
921132349
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.1606229599
Short name T134
Test name
Test status
Simulation time 421827079 ps
CPU time 6.14 seconds
Started Jun 02 03:11:19 PM PDT 24
Finished Jun 02 03:11:26 PM PDT 24
Peak memory 242588 kb
Host smart-b1dd4e1a-54b0-4e10-8a3b-fc9d9829e09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606229599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.1606229599
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.2136528191
Short name T65
Test name
Test status
Simulation time 238187032 ps
CPU time 3.79 seconds
Started Jun 02 03:11:56 PM PDT 24
Finished Jun 02 03:12:01 PM PDT 24
Peak memory 242324 kb
Host smart-56227da8-fe76-42dc-b36f-d653aaa750e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136528191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.2136528191
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.2956000488
Short name T149
Test name
Test status
Simulation time 111243502 ps
CPU time 4.49 seconds
Started Jun 02 03:10:49 PM PDT 24
Finished Jun 02 03:10:54 PM PDT 24
Peak memory 242220 kb
Host smart-30bde861-14ce-44eb-871b-22e05be3efa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956000488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.2956000488
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.100049016
Short name T198
Test name
Test status
Simulation time 477232627 ps
CPU time 3.94 seconds
Started Jun 02 03:10:54 PM PDT 24
Finished Jun 02 03:10:59 PM PDT 24
Peak memory 242668 kb
Host smart-3aafd897-d2d6-451b-8a03-a11c576e483b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100049016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.100049016
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.54065294
Short name T646
Test name
Test status
Simulation time 470087810 ps
CPU time 9.89 seconds
Started Jun 02 03:08:32 PM PDT 24
Finished Jun 02 03:08:43 PM PDT 24
Peak memory 242244 kb
Host smart-599251fa-e80d-4c7e-a906-e3ea3c0ffb42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=54065294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.54065294
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.3558057921
Short name T32
Test name
Test status
Simulation time 149130849 ps
CPU time 3.96 seconds
Started Jun 02 03:10:55 PM PDT 24
Finished Jun 02 03:11:00 PM PDT 24
Peak memory 242328 kb
Host smart-b24cccd0-46c5-49ad-ac8e-b1b46513e9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558057921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.3558057921
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.3602282737
Short name T53
Test name
Test status
Simulation time 888115656 ps
CPU time 15.22 seconds
Started Jun 02 03:09:45 PM PDT 24
Finished Jun 02 03:10:01 PM PDT 24
Peak memory 242412 kb
Host smart-87fa13c7-a729-40c5-83bb-403d6b8b78fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602282737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.3602282737
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3393115167
Short name T308
Test name
Test status
Simulation time 42626017 ps
CPU time 1.54 seconds
Started Jun 02 03:05:16 PM PDT 24
Finished Jun 02 03:05:18 PM PDT 24
Peak memory 239172 kb
Host smart-06e52f59-f2de-4330-b2c1-0a801909dad1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393115167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.3393115167
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.3463184562
Short name T55
Test name
Test status
Simulation time 597443764 ps
CPU time 4.48 seconds
Started Jun 02 03:11:56 PM PDT 24
Finished Jun 02 03:12:01 PM PDT 24
Peak memory 242456 kb
Host smart-4f748c7f-91c4-4b93-90a1-32f4cf7e90bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463184562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.3463184562
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.2480387821
Short name T45
Test name
Test status
Simulation time 136315510 ps
CPU time 4.07 seconds
Started Jun 02 03:08:26 PM PDT 24
Finished Jun 02 03:08:31 PM PDT 24
Peak memory 242356 kb
Host smart-0b241810-30df-4167-9c52-981f973cb14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480387821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.2480387821
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.4033485417
Short name T146
Test name
Test status
Simulation time 123719514497 ps
CPU time 243.98 seconds
Started Jun 02 03:07:45 PM PDT 24
Finished Jun 02 03:11:50 PM PDT 24
Peak memory 264492 kb
Host smart-ebbc63c3-ae85-4a71-8e74-3e77a5d10ec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033485417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.
4033485417
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.2951212178
Short name T152
Test name
Test status
Simulation time 1652313208 ps
CPU time 11.13 seconds
Started Jun 02 03:08:05 PM PDT 24
Finished Jun 02 03:08:17 PM PDT 24
Peak memory 243556 kb
Host smart-388d1f2c-3711-4c65-a370-82321c251015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951212178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.2951212178
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.983368121
Short name T139
Test name
Test status
Simulation time 11906950796 ps
CPU time 158.72 seconds
Started Jun 02 03:09:58 PM PDT 24
Finished Jun 02 03:12:38 PM PDT 24
Peak memory 248960 kb
Host smart-cbf07490-57d7-4799-b40b-c7df7bbb93fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983368121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.
983368121
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.3599222214
Short name T57
Test name
Test status
Simulation time 2937051844 ps
CPU time 18.73 seconds
Started Jun 02 03:09:21 PM PDT 24
Finished Jun 02 03:09:41 PM PDT 24
Peak memory 248948 kb
Host smart-744d929f-8fcc-43f2-a513-1bfb728d8f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599222214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.3599222214
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.140330862
Short name T313
Test name
Test status
Simulation time 93972727891 ps
CPU time 994.72 seconds
Started Jun 02 03:08:57 PM PDT 24
Finished Jun 02 03:25:33 PM PDT 24
Peak memory 266756 kb
Host smart-8ed11de5-133a-4ba0-b455-93428cfc7283
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140330862 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.140330862
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.1461260796
Short name T264
Test name
Test status
Simulation time 21319600940 ps
CPU time 165.93 seconds
Started Jun 02 03:09:50 PM PDT 24
Finished Jun 02 03:12:37 PM PDT 24
Peak memory 257260 kb
Host smart-01cece51-9c31-4bd6-8454-88539b9e6339
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461260796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.1461260796
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.31257725
Short name T66
Test name
Test status
Simulation time 2497799999 ps
CPU time 8.96 seconds
Started Jun 02 03:10:20 PM PDT 24
Finished Jun 02 03:10:30 PM PDT 24
Peak memory 242352 kb
Host smart-41f686fc-e12f-436a-b74e-bfafb99d0608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31257725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.31257725
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1832523094
Short name T282
Test name
Test status
Simulation time 1863150856 ps
CPU time 21.84 seconds
Started Jun 02 03:05:25 PM PDT 24
Finished Jun 02 03:05:47 PM PDT 24
Peak memory 238428 kb
Host smart-f35fea9b-4f6c-4915-9b72-6ab3ed5fecae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832523094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.1832523094
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.1987918200
Short name T213
Test name
Test status
Simulation time 664162871 ps
CPU time 10.41 seconds
Started Jun 02 03:11:02 PM PDT 24
Finished Jun 02 03:11:12 PM PDT 24
Peak memory 242780 kb
Host smart-a0a8f764-a590-481f-9363-c6b186e5000b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987918200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.1987918200
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.3337855698
Short name T124
Test name
Test status
Simulation time 2496494918 ps
CPU time 20.81 seconds
Started Jun 02 03:11:10 PM PDT 24
Finished Jun 02 03:11:31 PM PDT 24
Peak memory 242932 kb
Host smart-8c22821d-a255-4ea7-8cef-87ab2e852ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337855698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.3337855698
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.2768548197
Short name T260
Test name
Test status
Simulation time 942430689 ps
CPU time 6.21 seconds
Started Jun 02 03:11:16 PM PDT 24
Finished Jun 02 03:11:23 PM PDT 24
Peak memory 242616 kb
Host smart-acc3c5a1-20e8-4556-9bdf-b60e4a0a1118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768548197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.2768548197
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.1562209038
Short name T25
Test name
Test status
Simulation time 143975668 ps
CPU time 3.87 seconds
Started Jun 02 03:11:40 PM PDT 24
Finished Jun 02 03:11:44 PM PDT 24
Peak memory 242416 kb
Host smart-d1d76f36-6f6d-4804-a4b0-5d09cf1dd015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562209038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.1562209038
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.956351053
Short name T64
Test name
Test status
Simulation time 2872575626 ps
CPU time 9.02 seconds
Started Jun 02 03:09:41 PM PDT 24
Finished Jun 02 03:09:51 PM PDT 24
Peak memory 242364 kb
Host smart-2b4ed91d-c4d9-433b-8509-30d78575841a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956351053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.956351053
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.3285026365
Short name T377
Test name
Test status
Simulation time 933098501 ps
CPU time 7.32 seconds
Started Jun 02 03:07:46 PM PDT 24
Finished Jun 02 03:07:53 PM PDT 24
Peak memory 248908 kb
Host smart-6c084d25-c3be-4e3f-bbb4-211672273d12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3285026365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.3285026365
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.4227446894
Short name T395
Test name
Test status
Simulation time 53795384659 ps
CPU time 1250.54 seconds
Started Jun 02 03:10:23 PM PDT 24
Finished Jun 02 03:31:14 PM PDT 24
Peak memory 374812 kb
Host smart-fbedac48-4cea-4e68-8340-7bd110264c26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227446894 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.4227446894
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.2434615761
Short name T289
Test name
Test status
Simulation time 16123914570 ps
CPU time 260.5 seconds
Started Jun 02 03:09:50 PM PDT 24
Finished Jun 02 03:14:11 PM PDT 24
Peak memory 261832 kb
Host smart-ff613e69-1ea7-407c-8815-f5f54855fdd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434615761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all
.2434615761
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1516700077
Short name T281
Test name
Test status
Simulation time 6180323510 ps
CPU time 19.35 seconds
Started Jun 02 03:04:59 PM PDT 24
Finished Jun 02 03:05:20 PM PDT 24
Peak memory 244368 kb
Host smart-6bd19a43-87ae-4445-855c-d3eb76369a3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516700077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.1516700077
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.1376695894
Short name T28
Test name
Test status
Simulation time 5535023819 ps
CPU time 11.53 seconds
Started Jun 02 03:07:34 PM PDT 24
Finished Jun 02 03:07:46 PM PDT 24
Peak memory 248956 kb
Host smart-f4012ecf-e441-4a5e-8571-09dc1f5dda72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376695894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.1376695894
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.3795598399
Short name T42
Test name
Test status
Simulation time 25348624237 ps
CPU time 49.08 seconds
Started Jun 02 03:09:39 PM PDT 24
Finished Jun 02 03:10:28 PM PDT 24
Peak memory 249028 kb
Host smart-5b3b6cca-70ac-4aca-9514-a6d6612416ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795598399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.3795598399
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.246627107
Short name T276
Test name
Test status
Simulation time 2180622265 ps
CPU time 17.83 seconds
Started Jun 02 03:04:50 PM PDT 24
Finished Jun 02 03:05:08 PM PDT 24
Peak memory 244008 kb
Host smart-35790ba2-1a9a-4d60-af7b-21f11e085fc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246627107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_int
g_err.246627107
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.4178193985
Short name T307
Test name
Test status
Simulation time 156717174 ps
CPU time 1.9 seconds
Started Jun 02 03:04:58 PM PDT 24
Finished Jun 02 03:05:01 PM PDT 24
Peak memory 238356 kb
Host smart-f8938b11-cc38-4f24-b0b7-e9c64dc6d421
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178193985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.4178193985
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.2349966078
Short name T14
Test name
Test status
Simulation time 72032302287 ps
CPU time 125.14 seconds
Started Jun 02 03:08:48 PM PDT 24
Finished Jun 02 03:10:53 PM PDT 24
Peak memory 267532 kb
Host smart-80ab9adb-2224-4849-8a3f-734ccfeecbf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349966078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.2349966078
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.3175265344
Short name T80
Test name
Test status
Simulation time 198118344 ps
CPU time 4.35 seconds
Started Jun 02 03:11:47 PM PDT 24
Finished Jun 02 03:11:53 PM PDT 24
Peak memory 242680 kb
Host smart-d71ec2d0-e6e3-41d9-95d9-d417c2b86e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175265344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.3175265344
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.1074301851
Short name T228
Test name
Test status
Simulation time 481292239 ps
CPU time 4.29 seconds
Started Jun 02 03:10:56 PM PDT 24
Finished Jun 02 03:11:01 PM PDT 24
Peak memory 242392 kb
Host smart-c8b7eb3f-9f90-49c8-872b-ceb1a27a4fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074301851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.1074301851
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.1541042414
Short name T271
Test name
Test status
Simulation time 173898442 ps
CPU time 5.85 seconds
Started Jun 02 03:07:41 PM PDT 24
Finished Jun 02 03:07:48 PM PDT 24
Peak memory 242284 kb
Host smart-c7c4f7c9-7952-4470-afdc-54fde3ed805c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541042414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.1541042414
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.1055332960
Short name T317
Test name
Test status
Simulation time 285162716 ps
CPU time 8.22 seconds
Started Jun 02 03:09:28 PM PDT 24
Finished Jun 02 03:09:37 PM PDT 24
Peak memory 242596 kb
Host smart-0667ab74-afce-4040-96ac-e1e830a6e1ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1055332960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.1055332960
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.1139277965
Short name T691
Test name
Test status
Simulation time 1826760753 ps
CPU time 28.35 seconds
Started Jun 02 03:08:04 PM PDT 24
Finished Jun 02 03:08:34 PM PDT 24
Peak memory 248952 kb
Host smart-6019c42a-0c51-40b2-a609-90a2f57f0da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139277965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.1139277965
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.1766679572
Short name T345
Test name
Test status
Simulation time 322498814838 ps
CPU time 2236.6 seconds
Started Jun 02 03:08:15 PM PDT 24
Finished Jun 02 03:45:34 PM PDT 24
Peak memory 414456 kb
Host smart-6256c61b-d351-4714-95a2-6dee9f17c87f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766679572 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.1766679572
Directory /workspace/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.3456935144
Short name T11
Test name
Test status
Simulation time 106359903 ps
CPU time 1.74 seconds
Started Jun 02 03:07:21 PM PDT 24
Finished Jun 02 03:07:23 PM PDT 24
Peak memory 240840 kb
Host smart-7b06cb4e-1700-4488-9eac-255ded31845d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3456935144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.3456935144
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.2423531790
Short name T325
Test name
Test status
Simulation time 17391823290 ps
CPU time 98.65 seconds
Started Jun 02 03:09:23 PM PDT 24
Finished Jun 02 03:11:02 PM PDT 24
Peak memory 250216 kb
Host smart-393ce930-c2d9-4873-8b02-f9fd1cbffc59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423531790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all
.2423531790
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.2999182122
Short name T431
Test name
Test status
Simulation time 1463550915 ps
CPU time 18.61 seconds
Started Jun 02 03:08:49 PM PDT 24
Finished Jun 02 03:09:08 PM PDT 24
Peak memory 242584 kb
Host smart-5caf7f4d-20f8-421e-a65b-443e4ce10216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999182122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.2999182122
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.3810490963
Short name T680
Test name
Test status
Simulation time 21115160321 ps
CPU time 88.7 seconds
Started Jun 02 03:08:53 PM PDT 24
Finished Jun 02 03:10:23 PM PDT 24
Peak memory 246380 kb
Host smart-2ce8f764-0c0e-460c-a93e-fc67aab8ab56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810490963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all
.3810490963
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.625745881
Short name T701
Test name
Test status
Simulation time 3564721191 ps
CPU time 27.99 seconds
Started Jun 02 03:09:22 PM PDT 24
Finished Jun 02 03:09:50 PM PDT 24
Peak memory 248948 kb
Host smart-7c64cc7b-a28b-4624-9ea2-563221fc34e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625745881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.625745881
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.25901591
Short name T274
Test name
Test status
Simulation time 1361445321 ps
CPU time 20.39 seconds
Started Jun 02 03:04:56 PM PDT 24
Finished Jun 02 03:05:17 PM PDT 24
Peak memory 238696 kb
Host smart-9e310c74-7d90-4bd4-9e4e-8a2a38238f97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25901591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg
_err.25901591
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3602993373
Short name T280
Test name
Test status
Simulation time 678085854 ps
CPU time 9.32 seconds
Started Jun 02 03:05:05 PM PDT 24
Finished Jun 02 03:05:15 PM PDT 24
Peak memory 238476 kb
Host smart-3f56255f-158e-40eb-82d6-b40fc9e53c30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602993373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in
tg_err.3602993373
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.1827514582
Short name T254
Test name
Test status
Simulation time 23729421125 ps
CPU time 180.38 seconds
Started Jun 02 03:08:26 PM PDT 24
Finished Jun 02 03:11:27 PM PDT 24
Peak memory 249112 kb
Host smart-6db8d1b9-48bf-4701-b2e1-f41c20affbc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827514582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.1827514582
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.1237727013
Short name T509
Test name
Test status
Simulation time 1274079739 ps
CPU time 31.16 seconds
Started Jun 02 03:07:31 PM PDT 24
Finished Jun 02 03:08:03 PM PDT 24
Peak memory 242796 kb
Host smart-b9aa2b75-b35d-4742-81d0-0db2c1f31fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237727013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.1237727013
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3369276453
Short name T319
Test name
Test status
Simulation time 190762753 ps
CPU time 6.59 seconds
Started Jun 02 03:04:53 PM PDT 24
Finished Jun 02 03:05:01 PM PDT 24
Peak memory 230228 kb
Host smart-a2ee2b0d-9e5a-49e2-b1bb-2ac6e9612fd8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369276453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.3369276453
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.756874045
Short name T1273
Test name
Test status
Simulation time 1986835567 ps
CPU time 7.44 seconds
Started Jun 02 03:04:50 PM PDT 24
Finished Jun 02 03:04:58 PM PDT 24
Peak memory 238368 kb
Host smart-9c7e13ad-b13d-4081-8101-91edaab61f12
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756874045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_b
ash.756874045
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.3478510459
Short name T1252
Test name
Test status
Simulation time 379845634 ps
CPU time 2.77 seconds
Started Jun 02 03:04:50 PM PDT 24
Finished Jun 02 03:04:54 PM PDT 24
Peak memory 238464 kb
Host smart-6e87d1dc-a9be-4501-8bad-4fd007134698
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478510459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r
eset.3478510459
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2649889526
Short name T1300
Test name
Test status
Simulation time 209537343 ps
CPU time 2.79 seconds
Started Jun 02 03:04:50 PM PDT 24
Finished Jun 02 03:04:53 PM PDT 24
Peak memory 246616 kb
Host smart-7c0b1699-e3c2-4d8d-82f6-4cad9e5ae4c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649889526 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.2649889526
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.163180297
Short name T304
Test name
Test status
Simulation time 77369754 ps
CPU time 1.66 seconds
Started Jun 02 03:04:49 PM PDT 24
Finished Jun 02 03:04:51 PM PDT 24
Peak memory 238444 kb
Host smart-ca43f5b7-5788-4cbc-9e81-a6b6dd612e9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163180297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.163180297
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.1856051763
Short name T1294
Test name
Test status
Simulation time 136680735 ps
CPU time 1.49 seconds
Started Jun 02 03:04:47 PM PDT 24
Finished Jun 02 03:04:49 PM PDT 24
Peak memory 230280 kb
Host smart-eb0aa8a1-6841-4fd7-b5e7-686b5c104b05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856051763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.1856051763
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2691281303
Short name T1283
Test name
Test status
Simulation time 39948478 ps
CPU time 1.36 seconds
Started Jun 02 03:04:53 PM PDT 24
Finished Jun 02 03:04:56 PM PDT 24
Peak memory 229964 kb
Host smart-8c5e6602-8dcd-4095-b63f-bd1978d63589
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691281303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.2691281303
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3230335475
Short name T1230
Test name
Test status
Simulation time 525466955 ps
CPU time 1.69 seconds
Started Jun 02 03:04:48 PM PDT 24
Finished Jun 02 03:04:50 PM PDT 24
Peak memory 229056 kb
Host smart-bf73241a-169b-431a-abfd-d46f4245f7a0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230335475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.3230335475
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1412331585
Short name T1284
Test name
Test status
Simulation time 283898127 ps
CPU time 2.38 seconds
Started Jun 02 03:04:52 PM PDT 24
Finished Jun 02 03:04:55 PM PDT 24
Peak memory 237632 kb
Host smart-625fe6e6-d4f7-4598-afdd-4a04a5bf620e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412331585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.1412331585
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3974688867
Short name T1210
Test name
Test status
Simulation time 97311130 ps
CPU time 3.59 seconds
Started Jun 02 03:04:47 PM PDT 24
Finished Jun 02 03:04:51 PM PDT 24
Peak memory 238492 kb
Host smart-18de6c67-4476-45c4-b8c2-0b4fc93f1346
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974688867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.3974688867
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.435107984
Short name T366
Test name
Test status
Simulation time 5067312701 ps
CPU time 23.98 seconds
Started Jun 02 03:04:47 PM PDT 24
Finished Jun 02 03:05:11 PM PDT 24
Peak memory 244436 kb
Host smart-a88cbdb2-a331-4312-b45a-a393cbc6ef5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435107984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_int
g_err.435107984
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1197574982
Short name T320
Test name
Test status
Simulation time 838027620 ps
CPU time 3.85 seconds
Started Jun 02 03:04:58 PM PDT 24
Finished Jun 02 03:05:03 PM PDT 24
Peak memory 237372 kb
Host smart-b3578eca-327d-43b7-9ff1-2fc38550abf4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197574982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia
sing.1197574982
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1665832761
Short name T338
Test name
Test status
Simulation time 243528830 ps
CPU time 6.65 seconds
Started Jun 02 03:04:54 PM PDT 24
Finished Jun 02 03:05:02 PM PDT 24
Peak memory 237660 kb
Host smart-9e63e702-cf77-4d0e-a9a9-4854da3b3c9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665832761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_
bash.1665832761
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2704119498
Short name T1317
Test name
Test status
Simulation time 136841086 ps
CPU time 1.9 seconds
Started Jun 02 03:04:51 PM PDT 24
Finished Jun 02 03:04:53 PM PDT 24
Peak memory 237108 kb
Host smart-b304a961-158a-4bbe-8aa5-b7716dfa0824
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704119498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.2704119498
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.2329788452
Short name T1319
Test name
Test status
Simulation time 99807980 ps
CPU time 2.89 seconds
Started Jun 02 03:04:57 PM PDT 24
Finished Jun 02 03:05:02 PM PDT 24
Peak memory 246580 kb
Host smart-dcd35795-c540-4cea-8e32-ff0abc670cf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329788452 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.2329788452
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1339700618
Short name T1238
Test name
Test status
Simulation time 79187262 ps
CPU time 1.55 seconds
Started Jun 02 03:04:53 PM PDT 24
Finished Jun 02 03:04:55 PM PDT 24
Peak memory 238428 kb
Host smart-0665bc24-d977-4075-9886-6126018b9117
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339700618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.1339700618
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.3292675487
Short name T1280
Test name
Test status
Simulation time 41475762 ps
CPU time 1.49 seconds
Started Jun 02 03:04:53 PM PDT 24
Finished Jun 02 03:04:55 PM PDT 24
Peak memory 230172 kb
Host smart-2b1bccdf-5aa7-42f7-a937-ffaa5f3e9d3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292675487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.3292675487
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2779044394
Short name T1266
Test name
Test status
Simulation time 133601666 ps
CPU time 1.36 seconds
Started Jun 02 03:04:52 PM PDT 24
Finished Jun 02 03:04:54 PM PDT 24
Peak memory 229080 kb
Host smart-db679ae4-a532-4883-ab18-6477715f06d5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779044394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.2779044394
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.1574925103
Short name T1239
Test name
Test status
Simulation time 135119265 ps
CPU time 1.42 seconds
Started Jun 02 03:04:50 PM PDT 24
Finished Jun 02 03:04:52 PM PDT 24
Peak memory 229080 kb
Host smart-f0062282-8b17-4b42-b560-dbeca026c01a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574925103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.1574925103
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.837803483
Short name T1316
Test name
Test status
Simulation time 75652509 ps
CPU time 2.14 seconds
Started Jun 02 03:04:56 PM PDT 24
Finished Jun 02 03:05:00 PM PDT 24
Peak memory 237424 kb
Host smart-e87bc49b-c32e-4572-b187-b50211abf638
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837803483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ct
rl_same_csr_outstanding.837803483
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3727169568
Short name T1202
Test name
Test status
Simulation time 382004845 ps
CPU time 6.95 seconds
Started Jun 02 03:04:54 PM PDT 24
Finished Jun 02 03:05:02 PM PDT 24
Peak memory 238484 kb
Host smart-309d7579-9a38-479e-86e9-de03ec0ae09f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727169568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.3727169568
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3832825302
Short name T1325
Test name
Test status
Simulation time 106835692 ps
CPU time 2.72 seconds
Started Jun 02 03:05:13 PM PDT 24
Finished Jun 02 03:05:16 PM PDT 24
Peak memory 245284 kb
Host smart-bf4f42f7-d960-42f2-b375-9dd62ab86f21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832825302 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.3832825302
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.4272630449
Short name T318
Test name
Test status
Simulation time 93706011 ps
CPU time 1.61 seconds
Started Jun 02 03:05:09 PM PDT 24
Finished Jun 02 03:05:12 PM PDT 24
Peak memory 238428 kb
Host smart-196a1f37-86fd-4167-8e52-b0cf1964404a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272630449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.4272630449
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.2885470430
Short name T1275
Test name
Test status
Simulation time 44899160 ps
CPU time 1.34 seconds
Started Jun 02 03:05:09 PM PDT 24
Finished Jun 02 03:05:11 PM PDT 24
Peak memory 228852 kb
Host smart-2bda65d6-2496-4ecd-9810-f7a43aa57377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885470430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.2885470430
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1128503799
Short name T332
Test name
Test status
Simulation time 84085262 ps
CPU time 2.86 seconds
Started Jun 02 03:05:09 PM PDT 24
Finished Jun 02 03:05:13 PM PDT 24
Peak memory 238508 kb
Host smart-c2304a05-ea3f-4d54-9668-e77c9b01ed77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128503799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.1128503799
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.1439135402
Short name T1211
Test name
Test status
Simulation time 1540484164 ps
CPU time 6.28 seconds
Started Jun 02 03:05:09 PM PDT 24
Finished Jun 02 03:05:16 PM PDT 24
Peak memory 246132 kb
Host smart-9035742e-c83c-4806-a3bc-bd5b57b8a01e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439135402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.1439135402
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.438683503
Short name T1237
Test name
Test status
Simulation time 617102730 ps
CPU time 9.53 seconds
Started Jun 02 03:05:10 PM PDT 24
Finished Jun 02 03:05:20 PM PDT 24
Peak memory 243324 kb
Host smart-8ebce82d-aa5d-4c7f-92c2-19730e832121
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438683503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_in
tg_err.438683503
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3697492364
Short name T1262
Test name
Test status
Simulation time 1658812232 ps
CPU time 5.76 seconds
Started Jun 02 03:05:19 PM PDT 24
Finished Jun 02 03:05:26 PM PDT 24
Peak memory 245992 kb
Host smart-af7ebdd2-1cbd-4f20-a93d-d421611c7d04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697492364 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.3697492364
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3367105410
Short name T1256
Test name
Test status
Simulation time 586098644 ps
CPU time 1.64 seconds
Started Jun 02 03:05:16 PM PDT 24
Finished Jun 02 03:05:18 PM PDT 24
Peak memory 238380 kb
Host smart-3b5c3f36-8817-45d2-b7af-cee94c343dc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367105410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.3367105410
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2509094343
Short name T1231
Test name
Test status
Simulation time 82553464 ps
CPU time 1.43 seconds
Started Jun 02 03:05:16 PM PDT 24
Finished Jun 02 03:05:18 PM PDT 24
Peak memory 229312 kb
Host smart-a9e3f06b-da96-4695-b343-e203f3aadc64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509094343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.2509094343
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3724400415
Short name T334
Test name
Test status
Simulation time 251372646 ps
CPU time 3.71 seconds
Started Jun 02 03:05:15 PM PDT 24
Finished Jun 02 03:05:19 PM PDT 24
Peak memory 238340 kb
Host smart-f2473211-2e6b-4365-9e2d-0ca1f7019e6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724400415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.3724400415
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2981385266
Short name T1253
Test name
Test status
Simulation time 151380891 ps
CPU time 5.14 seconds
Started Jun 02 03:05:11 PM PDT 24
Finished Jun 02 03:05:16 PM PDT 24
Peak memory 246292 kb
Host smart-78ee8743-3e3d-44d7-8c0a-f4fe796749df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981385266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.2981385266
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.77769447
Short name T361
Test name
Test status
Simulation time 4299954530 ps
CPU time 19.92 seconds
Started Jun 02 03:05:09 PM PDT 24
Finished Jun 02 03:05:30 PM PDT 24
Peak memory 244400 kb
Host smart-3e54466d-72b1-492a-8746-b26c04a20c9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77769447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_int
g_err.77769447
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1175491527
Short name T1299
Test name
Test status
Simulation time 122800535 ps
CPU time 3.06 seconds
Started Jun 02 03:05:15 PM PDT 24
Finished Jun 02 03:05:19 PM PDT 24
Peak memory 245796 kb
Host smart-7483a8e5-f5be-48a4-9445-6ab52c3cdc19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175491527 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.1175491527
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.4243748454
Short name T310
Test name
Test status
Simulation time 81258468 ps
CPU time 1.67 seconds
Started Jun 02 03:05:19 PM PDT 24
Finished Jun 02 03:05:21 PM PDT 24
Peak memory 239368 kb
Host smart-8114b680-89c1-48a4-a953-023d80b2ab20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243748454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.4243748454
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.1646685767
Short name T1281
Test name
Test status
Simulation time 40314401 ps
CPU time 1.47 seconds
Started Jun 02 03:05:16 PM PDT 24
Finished Jun 02 03:05:18 PM PDT 24
Peak memory 229152 kb
Host smart-abdff3eb-5473-4b9b-89a0-2cb0634e8e22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646685767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.1646685767
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.577093849
Short name T1251
Test name
Test status
Simulation time 499376978 ps
CPU time 3.38 seconds
Started Jun 02 03:05:15 PM PDT 24
Finished Jun 02 03:05:19 PM PDT 24
Peak memory 237492 kb
Host smart-418c076c-78a0-4bac-ad57-3553eae23869
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577093849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_c
trl_same_csr_outstanding.577093849
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2822854867
Short name T1244
Test name
Test status
Simulation time 235004887 ps
CPU time 3.7 seconds
Started Jun 02 03:05:20 PM PDT 24
Finished Jun 02 03:05:24 PM PDT 24
Peak memory 245844 kb
Host smart-7818eedd-84b9-47e0-a211-c6c9d95a111b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822854867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.2822854867
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.838852902
Short name T358
Test name
Test status
Simulation time 3106780554 ps
CPU time 19.18 seconds
Started Jun 02 03:05:16 PM PDT 24
Finished Jun 02 03:05:35 PM PDT 24
Peak memory 245660 kb
Host smart-eef34306-6e2e-4105-8979-8716e76ea8d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838852902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_in
tg_err.838852902
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1421576348
Short name T1286
Test name
Test status
Simulation time 109818205 ps
CPU time 4.55 seconds
Started Jun 02 03:05:15 PM PDT 24
Finished Jun 02 03:05:20 PM PDT 24
Peak memory 246612 kb
Host smart-f1fce69e-2712-4a8f-9c19-f7d6c935fe23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421576348 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.1421576348
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.908432607
Short name T329
Test name
Test status
Simulation time 43228422 ps
CPU time 1.7 seconds
Started Jun 02 03:05:19 PM PDT 24
Finished Jun 02 03:05:22 PM PDT 24
Peak memory 240020 kb
Host smart-9e4391e2-db7d-46d9-ab23-45cd382d9f26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908432607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.908432607
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2725965081
Short name T1303
Test name
Test status
Simulation time 36312547 ps
CPU time 1.4 seconds
Started Jun 02 03:05:16 PM PDT 24
Finished Jun 02 03:05:18 PM PDT 24
Peak memory 229020 kb
Host smart-d707f973-25e0-4e0c-acdd-551c5fba93d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725965081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.2725965081
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1873330499
Short name T1247
Test name
Test status
Simulation time 104593253 ps
CPU time 2.26 seconds
Started Jun 02 03:05:16 PM PDT 24
Finished Jun 02 03:05:19 PM PDT 24
Peak memory 238568 kb
Host smart-5e9f7e58-9f0c-4f1e-aafd-bbba346fd060
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873330499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.1873330499
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1541601556
Short name T1225
Test name
Test status
Simulation time 146706608 ps
CPU time 6.53 seconds
Started Jun 02 03:05:14 PM PDT 24
Finished Jun 02 03:05:22 PM PDT 24
Peak memory 238492 kb
Host smart-858271ab-d87e-482f-8133-cad637046deb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541601556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.1541601556
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1524594918
Short name T1287
Test name
Test status
Simulation time 1048373825 ps
CPU time 12.75 seconds
Started Jun 02 03:05:15 PM PDT 24
Finished Jun 02 03:05:28 PM PDT 24
Peak memory 238344 kb
Host smart-de3bf7de-48c5-4020-ba8b-309f1b76873d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524594918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.1524594918
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.3637391118
Short name T1206
Test name
Test status
Simulation time 1067721315 ps
CPU time 4.13 seconds
Started Jun 02 03:05:17 PM PDT 24
Finished Jun 02 03:05:21 PM PDT 24
Peak memory 246660 kb
Host smart-44c41c4d-77dd-402f-aa4d-740742f6a53b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637391118 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.3637391118
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.52834165
Short name T323
Test name
Test status
Simulation time 142569853 ps
CPU time 1.63 seconds
Started Jun 02 03:05:15 PM PDT 24
Finished Jun 02 03:05:17 PM PDT 24
Peak memory 238440 kb
Host smart-e8d01427-cc55-4ef4-bbbd-3ce64678a1c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52834165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.52834165
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.1644690711
Short name T1215
Test name
Test status
Simulation time 115486987 ps
CPU time 1.63 seconds
Started Jun 02 03:05:17 PM PDT 24
Finished Jun 02 03:05:19 PM PDT 24
Peak memory 229008 kb
Host smart-f6d85e6d-4b48-4f6f-bed6-1bcc13b1e2cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644690711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.1644690711
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1615680179
Short name T330
Test name
Test status
Simulation time 101150168 ps
CPU time 3.15 seconds
Started Jun 02 03:05:17 PM PDT 24
Finished Jun 02 03:05:21 PM PDT 24
Peak memory 237528 kb
Host smart-0a138cfc-8a7d-4710-9981-2296468c8645
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615680179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.1615680179
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3394965032
Short name T1220
Test name
Test status
Simulation time 2193174994 ps
CPU time 8.7 seconds
Started Jun 02 03:05:17 PM PDT 24
Finished Jun 02 03:05:27 PM PDT 24
Peak memory 238604 kb
Host smart-25b86deb-cf5f-4288-a2d2-ac567da8a807
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394965032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.3394965032
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3793371037
Short name T364
Test name
Test status
Simulation time 1204574515 ps
CPU time 10.31 seconds
Started Jun 02 03:05:17 PM PDT 24
Finished Jun 02 03:05:28 PM PDT 24
Peak memory 238324 kb
Host smart-8cc1f404-37c0-4a79-8503-fd64caace81c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793371037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.3793371037
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.2609531239
Short name T1250
Test name
Test status
Simulation time 1715892197 ps
CPU time 4.06 seconds
Started Jun 02 03:05:17 PM PDT 24
Finished Jun 02 03:05:22 PM PDT 24
Peak memory 246608 kb
Host smart-27fb1282-b0eb-4d7f-b242-2a578c278666
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609531239 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.2609531239
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.865240212
Short name T1258
Test name
Test status
Simulation time 96082218 ps
CPU time 1.44 seconds
Started Jun 02 03:05:18 PM PDT 24
Finished Jun 02 03:05:20 PM PDT 24
Peak memory 229008 kb
Host smart-a3f57bfe-4b98-4b5c-97d2-6cdd5404d730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865240212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.865240212
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.1970009047
Short name T1248
Test name
Test status
Simulation time 130319438 ps
CPU time 1.92 seconds
Started Jun 02 03:05:20 PM PDT 24
Finished Jun 02 03:05:22 PM PDT 24
Peak memory 237464 kb
Host smart-24c4c693-cca6-4a29-a47b-df49d2654ea0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970009047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_
ctrl_same_csr_outstanding.1970009047
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.2561037639
Short name T1224
Test name
Test status
Simulation time 93411087 ps
CPU time 3.42 seconds
Started Jun 02 03:05:20 PM PDT 24
Finished Jun 02 03:05:24 PM PDT 24
Peak memory 245268 kb
Host smart-4ca92870-0f48-458e-a359-0db14d5a5e84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561037639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.2561037639
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.870362764
Short name T362
Test name
Test status
Simulation time 4019425336 ps
CPU time 16.8 seconds
Started Jun 02 03:05:14 PM PDT 24
Finished Jun 02 03:05:32 PM PDT 24
Peak memory 244384 kb
Host smart-52dd54a4-0ade-4192-bf7a-04d100b6d882
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870362764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_in
tg_err.870362764
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.3257926900
Short name T1312
Test name
Test status
Simulation time 1064618061 ps
CPU time 2.54 seconds
Started Jun 02 03:05:17 PM PDT 24
Finished Jun 02 03:05:20 PM PDT 24
Peak memory 243708 kb
Host smart-488aaa8d-dd51-4a43-a525-8e45d2f54760
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257926900 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.3257926900
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.2352853454
Short name T1323
Test name
Test status
Simulation time 46276174 ps
CPU time 1.76 seconds
Started Jun 02 03:05:17 PM PDT 24
Finished Jun 02 03:05:19 PM PDT 24
Peak memory 239520 kb
Host smart-dfabf89e-6433-4bcc-aad6-8a074bd4a249
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352853454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.2352853454
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.2760794307
Short name T1201
Test name
Test status
Simulation time 40524986 ps
CPU time 1.5 seconds
Started Jun 02 03:05:17 PM PDT 24
Finished Jun 02 03:05:19 PM PDT 24
Peak memory 229380 kb
Host smart-a1651847-218c-4104-b407-576b4ca85f4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760794307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.2760794307
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.2868963292
Short name T335
Test name
Test status
Simulation time 125792001 ps
CPU time 3.53 seconds
Started Jun 02 03:05:18 PM PDT 24
Finished Jun 02 03:05:22 PM PDT 24
Peak memory 237644 kb
Host smart-cc009b7f-f7e1-4838-b772-b893ca1370a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868963292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_
ctrl_same_csr_outstanding.2868963292
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1513899581
Short name T1198
Test name
Test status
Simulation time 571672420 ps
CPU time 6.24 seconds
Started Jun 02 03:05:15 PM PDT 24
Finished Jun 02 03:05:22 PM PDT 24
Peak memory 246292 kb
Host smart-1152acfd-deb7-480e-b7fe-727f2555f0b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513899581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.1513899581
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.125101992
Short name T1290
Test name
Test status
Simulation time 668297421 ps
CPU time 10.59 seconds
Started Jun 02 03:05:16 PM PDT 24
Finished Jun 02 03:05:27 PM PDT 24
Peak memory 243480 kb
Host smart-39840552-75ab-4ddf-91c6-4d9f60b3c1c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125101992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_in
tg_err.125101992
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.12770245
Short name T1259
Test name
Test status
Simulation time 73696354 ps
CPU time 2.39 seconds
Started Jun 02 03:05:21 PM PDT 24
Finished Jun 02 03:05:24 PM PDT 24
Peak memory 246480 kb
Host smart-8416decb-e4fa-4b4e-bb1c-f31a6fe39c32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12770245 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.12770245
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2854314375
Short name T305
Test name
Test status
Simulation time 596693158 ps
CPU time 2.14 seconds
Started Jun 02 03:05:24 PM PDT 24
Finished Jun 02 03:05:27 PM PDT 24
Peak memory 239884 kb
Host smart-8526188e-f248-4f8e-bb7f-0c22ccdd708b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854314375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.2854314375
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.3885592639
Short name T1268
Test name
Test status
Simulation time 149269187 ps
CPU time 1.48 seconds
Started Jun 02 03:05:23 PM PDT 24
Finished Jun 02 03:05:25 PM PDT 24
Peak memory 230236 kb
Host smart-237aaa9f-d1d3-403b-8b81-f8e901a37230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885592639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.3885592639
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1017768275
Short name T336
Test name
Test status
Simulation time 266635980 ps
CPU time 3.61 seconds
Started Jun 02 03:05:25 PM PDT 24
Finished Jun 02 03:05:29 PM PDT 24
Peak memory 237492 kb
Host smart-243e97b6-0d2e-4b72-9d20-80645c142662
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017768275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.1017768275
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.4000981297
Short name T1279
Test name
Test status
Simulation time 199694421 ps
CPU time 4.34 seconds
Started Jun 02 03:05:21 PM PDT 24
Finished Jun 02 03:05:26 PM PDT 24
Peak memory 246488 kb
Host smart-07e7028d-622f-410e-88e5-27248b080cc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000981297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.4000981297
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2833326630
Short name T1295
Test name
Test status
Simulation time 2460216624 ps
CPU time 12.63 seconds
Started Jun 02 03:05:23 PM PDT 24
Finished Jun 02 03:05:36 PM PDT 24
Peak memory 243724 kb
Host smart-917650b4-04a8-486b-b305-19d4fa491b21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833326630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.2833326630
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.145330421
Short name T1309
Test name
Test status
Simulation time 143560359 ps
CPU time 2.13 seconds
Started Jun 02 03:05:22 PM PDT 24
Finished Jun 02 03:05:25 PM PDT 24
Peak memory 244784 kb
Host smart-6dac6fd1-652b-4eba-b417-becf647733b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145330421 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.145330421
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.342946094
Short name T278
Test name
Test status
Simulation time 86861546 ps
CPU time 1.72 seconds
Started Jun 02 03:05:23 PM PDT 24
Finished Jun 02 03:05:25 PM PDT 24
Peak memory 240152 kb
Host smart-f9cab1ce-155b-4536-bdf9-60a64f8e58e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342946094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.342946094
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.3411652140
Short name T1199
Test name
Test status
Simulation time 41565279 ps
CPU time 1.45 seconds
Started Jun 02 03:05:22 PM PDT 24
Finished Jun 02 03:05:24 PM PDT 24
Peak memory 229004 kb
Host smart-fbcf953b-04bb-4907-ad3a-116c8165ada4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411652140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.3411652140
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1128973795
Short name T1320
Test name
Test status
Simulation time 1000189050 ps
CPU time 3.03 seconds
Started Jun 02 03:05:22 PM PDT 24
Finished Jun 02 03:05:25 PM PDT 24
Peak memory 238376 kb
Host smart-f19731ce-9306-44f8-95fe-9bffed88eb30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128973795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.1128973795
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.691025438
Short name T1264
Test name
Test status
Simulation time 123411820 ps
CPU time 3.99 seconds
Started Jun 02 03:05:21 PM PDT 24
Finished Jun 02 03:05:25 PM PDT 24
Peak memory 246644 kb
Host smart-88f99247-273b-4e3a-be0e-b86f4359d52d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691025438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.691025438
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2524345246
Short name T1315
Test name
Test status
Simulation time 111731786 ps
CPU time 3.19 seconds
Started Jun 02 03:05:21 PM PDT 24
Finished Jun 02 03:05:25 PM PDT 24
Peak memory 238424 kb
Host smart-2c59c1f2-864d-46de-ad9a-7f1a8d8a5a3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524345246 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.2524345246
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3236696446
Short name T324
Test name
Test status
Simulation time 155115056 ps
CPU time 1.81 seconds
Started Jun 02 03:05:21 PM PDT 24
Finished Jun 02 03:05:23 PM PDT 24
Peak memory 239640 kb
Host smart-f5ee2828-f370-4e2d-94d5-7908fa282f8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236696446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.3236696446
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1062427045
Short name T1304
Test name
Test status
Simulation time 42305634 ps
CPU time 1.51 seconds
Started Jun 02 03:05:22 PM PDT 24
Finished Jun 02 03:05:24 PM PDT 24
Peak memory 230188 kb
Host smart-ff0f0a93-4a6c-44e5-8ec1-a3f8ed8ecfbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062427045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.1062427045
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1788455743
Short name T1254
Test name
Test status
Simulation time 308351365 ps
CPU time 3.5 seconds
Started Jun 02 03:05:23 PM PDT 24
Finished Jun 02 03:05:27 PM PDT 24
Peak memory 237512 kb
Host smart-5b706b57-f637-48cc-a808-f6971443055e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788455743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.1788455743
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2846153487
Short name T1260
Test name
Test status
Simulation time 1368282080 ps
CPU time 5.44 seconds
Started Jun 02 03:05:20 PM PDT 24
Finished Jun 02 03:05:26 PM PDT 24
Peak memory 246432 kb
Host smart-b9ceebcd-42b7-47ab-88a5-d8b2c4e29750
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846153487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.2846153487
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1557380548
Short name T365
Test name
Test status
Simulation time 1240398448 ps
CPU time 9.83 seconds
Started Jun 02 03:05:22 PM PDT 24
Finished Jun 02 03:05:33 PM PDT 24
Peak memory 238456 kb
Host smart-32652d8d-3f53-4512-8d27-77dda6e5d885
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557380548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.1557380548
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.2966940622
Short name T1302
Test name
Test status
Simulation time 302671574 ps
CPU time 5.14 seconds
Started Jun 02 03:04:59 PM PDT 24
Finished Jun 02 03:05:06 PM PDT 24
Peak memory 237476 kb
Host smart-7a405e98-3b63-4f22-bf7e-277c11ece11d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966940622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.2966940622
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.4026694410
Short name T1291
Test name
Test status
Simulation time 903429356 ps
CPU time 7.04 seconds
Started Jun 02 03:04:56 PM PDT 24
Finished Jun 02 03:05:05 PM PDT 24
Peak memory 237284 kb
Host smart-fba9c826-3c27-4b17-abf6-a73e5cacaccc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026694410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.4026694410
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1051539903
Short name T322
Test name
Test status
Simulation time 367985513 ps
CPU time 2.34 seconds
Started Jun 02 03:05:02 PM PDT 24
Finished Jun 02 03:05:06 PM PDT 24
Peak memory 237288 kb
Host smart-26a54caf-a1d2-4a77-b53e-573a50db4891
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051539903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r
eset.1051539903
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.2215875648
Short name T1293
Test name
Test status
Simulation time 1064461856 ps
CPU time 3.07 seconds
Started Jun 02 03:04:57 PM PDT 24
Finished Jun 02 03:05:02 PM PDT 24
Peak memory 245652 kb
Host smart-e42e451d-311d-46f0-8043-90488dc23f8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215875648 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.2215875648
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.4182168300
Short name T1200
Test name
Test status
Simulation time 40923565 ps
CPU time 1.44 seconds
Started Jun 02 03:04:57 PM PDT 24
Finished Jun 02 03:05:00 PM PDT 24
Peak memory 228936 kb
Host smart-070dacb4-48a5-41c2-be9f-babd2680782d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182168300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.4182168300
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.3541040783
Short name T1240
Test name
Test status
Simulation time 37480669 ps
CPU time 1.52 seconds
Started Jun 02 03:04:59 PM PDT 24
Finished Jun 02 03:05:02 PM PDT 24
Peak memory 229200 kb
Host smart-6e8f1cfc-c86a-4c66-a2be-d7a688c385a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541040783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.3541040783
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.1384157479
Short name T1324
Test name
Test status
Simulation time 37589852 ps
CPU time 1.37 seconds
Started Jun 02 03:04:59 PM PDT 24
Finished Jun 02 03:05:02 PM PDT 24
Peak memory 228784 kb
Host smart-d01aec30-fe0b-42a3-a54d-f90d84da7e9f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384157479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.1384157479
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.983499232
Short name T1311
Test name
Test status
Simulation time 49798211 ps
CPU time 2.09 seconds
Started Jun 02 03:04:59 PM PDT 24
Finished Jun 02 03:05:03 PM PDT 24
Peak memory 238488 kb
Host smart-628b0bb8-a83a-45ff-a945-74f983f345f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983499232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ct
rl_same_csr_outstanding.983499232
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3266932209
Short name T1271
Test name
Test status
Simulation time 394979007 ps
CPU time 3.76 seconds
Started Jun 02 03:04:56 PM PDT 24
Finished Jun 02 03:05:02 PM PDT 24
Peak memory 238532 kb
Host smart-aece4845-b86e-4d08-becd-8b04ccf138b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266932209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3266932209
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.2307561926
Short name T1270
Test name
Test status
Simulation time 138120609 ps
CPU time 1.43 seconds
Started Jun 02 03:05:22 PM PDT 24
Finished Jun 02 03:05:23 PM PDT 24
Peak memory 229004 kb
Host smart-cdd6cd58-58d3-48a7-9839-09203510386a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307561926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.2307561926
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.1539184597
Short name T1276
Test name
Test status
Simulation time 139364234 ps
CPU time 1.64 seconds
Started Jun 02 03:05:22 PM PDT 24
Finished Jun 02 03:05:24 PM PDT 24
Peak memory 228908 kb
Host smart-35b8d460-d134-43f7-91fb-496441587d5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539184597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.1539184597
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2920468592
Short name T1228
Test name
Test status
Simulation time 123901074 ps
CPU time 1.42 seconds
Started Jun 02 03:05:24 PM PDT 24
Finished Jun 02 03:05:26 PM PDT 24
Peak memory 230200 kb
Host smart-b2b116f7-904f-4f20-a611-7561c7029f2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920468592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.2920468592
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.1955637934
Short name T1207
Test name
Test status
Simulation time 142715444 ps
CPU time 1.47 seconds
Started Jun 02 03:05:23 PM PDT 24
Finished Jun 02 03:05:25 PM PDT 24
Peak memory 229228 kb
Host smart-dd569ef3-d5a7-461d-8660-73e459837f0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955637934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.1955637934
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2986908918
Short name T1227
Test name
Test status
Simulation time 77635525 ps
CPU time 1.48 seconds
Started Jun 02 03:05:22 PM PDT 24
Finished Jun 02 03:05:24 PM PDT 24
Peak memory 228956 kb
Host smart-ac4e8d0f-a0b1-40c4-b280-e20e7121ceb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986908918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.2986908918
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.863171204
Short name T1265
Test name
Test status
Simulation time 42917093 ps
CPU time 1.44 seconds
Started Jun 02 03:05:22 PM PDT 24
Finished Jun 02 03:05:24 PM PDT 24
Peak memory 228992 kb
Host smart-6b1598cc-aa81-44e6-a1c2-38887186f282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863171204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.863171204
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.3759467190
Short name T1233
Test name
Test status
Simulation time 518347592 ps
CPU time 1.7 seconds
Started Jun 02 03:05:26 PM PDT 24
Finished Jun 02 03:05:28 PM PDT 24
Peak memory 229048 kb
Host smart-a6ec2ce9-297e-4df7-99bd-41703cafd8ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759467190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.3759467190
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.2151217208
Short name T1197
Test name
Test status
Simulation time 72456551 ps
CPU time 1.42 seconds
Started Jun 02 03:05:31 PM PDT 24
Finished Jun 02 03:05:33 PM PDT 24
Peak memory 228940 kb
Host smart-e2079641-809d-469b-845a-b748453e29e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151217208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.2151217208
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.1555118110
Short name T1246
Test name
Test status
Simulation time 519854781 ps
CPU time 1.88 seconds
Started Jun 02 03:05:26 PM PDT 24
Finished Jun 02 03:05:28 PM PDT 24
Peak memory 229044 kb
Host smart-13ec756b-69e5-4518-a948-48c907b73ec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555118110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.1555118110
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.203680250
Short name T1263
Test name
Test status
Simulation time 75870497 ps
CPU time 1.43 seconds
Started Jun 02 03:05:28 PM PDT 24
Finished Jun 02 03:05:30 PM PDT 24
Peak memory 229028 kb
Host smart-6f44c8ef-c395-407f-9dd1-fc828b36bd08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203680250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.203680250
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.1667602622
Short name T1245
Test name
Test status
Simulation time 1543042177 ps
CPU time 4.39 seconds
Started Jun 02 03:04:59 PM PDT 24
Finished Jun 02 03:05:05 PM PDT 24
Peak memory 237316 kb
Host smart-9496dbf6-6775-472f-b821-32c27b3dd3b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667602622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.1667602622
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.109164063
Short name T339
Test name
Test status
Simulation time 258062736 ps
CPU time 4 seconds
Started Jun 02 03:04:57 PM PDT 24
Finished Jun 02 03:05:03 PM PDT 24
Peak memory 237188 kb
Host smart-c3afbc84-6901-433d-990c-6d6eb1c8477f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109164063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_b
ash.109164063
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2303753574
Short name T1226
Test name
Test status
Simulation time 113335629 ps
CPU time 1.85 seconds
Started Jun 02 03:04:56 PM PDT 24
Finished Jun 02 03:05:00 PM PDT 24
Peak memory 237264 kb
Host smart-892f0220-5d4e-4703-bba8-828d9f4fa81c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303753574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.2303753574
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.3885857045
Short name T277
Test name
Test status
Simulation time 75631202 ps
CPU time 2.19 seconds
Started Jun 02 03:04:56 PM PDT 24
Finished Jun 02 03:05:00 PM PDT 24
Peak memory 244272 kb
Host smart-04c9657f-9849-4c84-9403-8c804b5f1553
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885857045 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.3885857045
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.1356107182
Short name T321
Test name
Test status
Simulation time 129346246 ps
CPU time 1.47 seconds
Started Jun 02 03:04:56 PM PDT 24
Finished Jun 02 03:05:00 PM PDT 24
Peak memory 239320 kb
Host smart-84bfb86b-9813-4364-a7db-03b7b553343f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356107182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.1356107182
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.3841597532
Short name T1282
Test name
Test status
Simulation time 135473639 ps
CPU time 1.4 seconds
Started Jun 02 03:04:56 PM PDT 24
Finished Jun 02 03:04:59 PM PDT 24
Peak memory 230240 kb
Host smart-a60abee6-cedb-4558-ad20-b025a58c2b63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841597532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.3841597532
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.4080082925
Short name T1216
Test name
Test status
Simulation time 139301799 ps
CPU time 1.34 seconds
Started Jun 02 03:04:59 PM PDT 24
Finished Jun 02 03:05:02 PM PDT 24
Peak memory 228912 kb
Host smart-933504e1-1802-4238-a03d-92b4970f24fa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080082925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_mem_partial_access.4080082925
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.1185457719
Short name T1322
Test name
Test status
Simulation time 37385631 ps
CPU time 1.43 seconds
Started Jun 02 03:05:01 PM PDT 24
Finished Jun 02 03:05:04 PM PDT 24
Peak memory 229112 kb
Host smart-0e2ce2eb-1ac5-4933-8b66-e9af7dbeae8a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185457719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.1185457719
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1433044160
Short name T1318
Test name
Test status
Simulation time 47589892 ps
CPU time 1.92 seconds
Started Jun 02 03:04:56 PM PDT 24
Finished Jun 02 03:04:59 PM PDT 24
Peak memory 238404 kb
Host smart-115e682c-15d5-4982-be5e-24a654eb9e66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433044160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.1433044160
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3799678482
Short name T1249
Test name
Test status
Simulation time 72954137 ps
CPU time 5.16 seconds
Started Jun 02 03:04:59 PM PDT 24
Finished Jun 02 03:05:06 PM PDT 24
Peak memory 245636 kb
Host smart-4b58a206-9b46-45d9-8e6a-b858a85b9e24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799678482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.3799678482
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.1546185707
Short name T1292
Test name
Test status
Simulation time 41250644 ps
CPU time 1.42 seconds
Started Jun 02 03:05:27 PM PDT 24
Finished Jun 02 03:05:29 PM PDT 24
Peak memory 230244 kb
Host smart-1b04c24b-03e3-47de-8a71-fcd2bb319a06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546185707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.1546185707
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.1537387708
Short name T1289
Test name
Test status
Simulation time 139602063 ps
CPU time 1.4 seconds
Started Jun 02 03:05:27 PM PDT 24
Finished Jun 02 03:05:29 PM PDT 24
Peak memory 228972 kb
Host smart-0a1cceef-1ba9-4065-90f3-3055a88db4a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537387708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.1537387708
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.1218893225
Short name T1274
Test name
Test status
Simulation time 134631278 ps
CPU time 1.42 seconds
Started Jun 02 03:05:33 PM PDT 24
Finished Jun 02 03:05:35 PM PDT 24
Peak memory 228944 kb
Host smart-350ee2f5-7ff4-46eb-8326-bf7eba118c14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218893225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.1218893225
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.1159774339
Short name T1306
Test name
Test status
Simulation time 135217571 ps
CPU time 1.37 seconds
Started Jun 02 03:05:25 PM PDT 24
Finished Jun 02 03:05:27 PM PDT 24
Peak memory 230196 kb
Host smart-1dded981-7aa3-4897-b567-c0b373f6d2c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159774339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.1159774339
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.417126109
Short name T1308
Test name
Test status
Simulation time 44388829 ps
CPU time 1.5 seconds
Started Jun 02 03:05:25 PM PDT 24
Finished Jun 02 03:05:27 PM PDT 24
Peak memory 230184 kb
Host smart-02e31eff-0947-4ffa-b156-379e44485993
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417126109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.417126109
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.2179405958
Short name T1241
Test name
Test status
Simulation time 74507316 ps
CPU time 1.52 seconds
Started Jun 02 03:05:30 PM PDT 24
Finished Jun 02 03:05:32 PM PDT 24
Peak memory 228972 kb
Host smart-3c219829-9c10-4c04-94a9-9ff9ab1df514
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179405958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.2179405958
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.2482255815
Short name T1212
Test name
Test status
Simulation time 155828689 ps
CPU time 1.54 seconds
Started Jun 02 03:05:26 PM PDT 24
Finished Jun 02 03:05:28 PM PDT 24
Peak memory 229244 kb
Host smart-b9030dd2-e8eb-43d2-8efa-8c321acba9c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482255815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.2482255815
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.468876160
Short name T1205
Test name
Test status
Simulation time 39734824 ps
CPU time 1.39 seconds
Started Jun 02 03:05:33 PM PDT 24
Finished Jun 02 03:05:35 PM PDT 24
Peak memory 229280 kb
Host smart-5bf705f7-e2b4-4466-b58e-8dea250b8a8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468876160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.468876160
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.3351817891
Short name T1219
Test name
Test status
Simulation time 549441827 ps
CPU time 1.65 seconds
Started Jun 02 03:05:29 PM PDT 24
Finished Jun 02 03:05:31 PM PDT 24
Peak memory 228940 kb
Host smart-d0e473e5-2ce5-4f62-a260-0fe492fa749d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351817891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.3351817891
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.671906365
Short name T1243
Test name
Test status
Simulation time 133677767 ps
CPU time 1.54 seconds
Started Jun 02 03:05:29 PM PDT 24
Finished Jun 02 03:05:31 PM PDT 24
Peak memory 229328 kb
Host smart-89c3bba7-0dbf-4eeb-b839-1ddc7c04b71a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671906365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.671906365
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.83240627
Short name T1321
Test name
Test status
Simulation time 149764093 ps
CPU time 4.71 seconds
Started Jun 02 03:04:58 PM PDT 24
Finished Jun 02 03:05:04 PM PDT 24
Peak memory 238384 kb
Host smart-58d1e4d5-942f-4243-be6a-09c0cae021ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83240627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_aliasi
ng.83240627
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.272925534
Short name T337
Test name
Test status
Simulation time 223378187 ps
CPU time 5.74 seconds
Started Jun 02 03:04:57 PM PDT 24
Finished Jun 02 03:05:04 PM PDT 24
Peak memory 237260 kb
Host smart-b266d4e4-72d2-4a85-b811-1439e3cd1110
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272925534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_b
ash.272925534
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.2235352536
Short name T306
Test name
Test status
Simulation time 381014881 ps
CPU time 2.4 seconds
Started Jun 02 03:05:06 PM PDT 24
Finished Jun 02 03:05:08 PM PDT 24
Peak memory 237532 kb
Host smart-74ea9d3f-e016-4967-94ba-3efa8dc5b231
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235352536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.2235352536
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3880879276
Short name T1235
Test name
Test status
Simulation time 175542735 ps
CPU time 2.62 seconds
Started Jun 02 03:04:59 PM PDT 24
Finished Jun 02 03:05:03 PM PDT 24
Peak memory 245864 kb
Host smart-c0ec5f88-3263-4f06-9224-3da267e16753
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880879276 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.3880879276
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.203444584
Short name T1310
Test name
Test status
Simulation time 48898192 ps
CPU time 1.48 seconds
Started Jun 02 03:05:02 PM PDT 24
Finished Jun 02 03:05:05 PM PDT 24
Peak memory 239308 kb
Host smart-84f60d16-4438-4626-9394-f5837611caf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203444584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.203444584
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1337097199
Short name T1285
Test name
Test status
Simulation time 42565059 ps
CPU time 1.41 seconds
Started Jun 02 03:04:56 PM PDT 24
Finished Jun 02 03:04:59 PM PDT 24
Peak memory 230232 kb
Host smart-2a6551b8-2a97-4bf1-8cbb-7004361d1f30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337097199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.1337097199
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1070389763
Short name T1313
Test name
Test status
Simulation time 40526241 ps
CPU time 1.36 seconds
Started Jun 02 03:04:56 PM PDT 24
Finished Jun 02 03:04:59 PM PDT 24
Peak memory 228904 kb
Host smart-72c285c9-fb45-4eac-b785-0af88cd26b80
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070389763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_mem_partial_access.1070389763
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.3389645973
Short name T1298
Test name
Test status
Simulation time 530177248 ps
CPU time 1.77 seconds
Started Jun 02 03:05:03 PM PDT 24
Finished Jun 02 03:05:06 PM PDT 24
Peak memory 229128 kb
Host smart-e1c6dd80-fda4-4337-bf37-fd9184dafe9b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389645973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.3389645973
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.517463039
Short name T1296
Test name
Test status
Simulation time 67225050 ps
CPU time 2.67 seconds
Started Jun 02 03:05:00 PM PDT 24
Finished Jun 02 03:05:04 PM PDT 24
Peak memory 238412 kb
Host smart-f9ea6e5b-28f0-4c13-9b1d-b9d319255151
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517463039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ct
rl_same_csr_outstanding.517463039
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3568612787
Short name T1204
Test name
Test status
Simulation time 314673138 ps
CPU time 5.46 seconds
Started Jun 02 03:04:59 PM PDT 24
Finished Jun 02 03:05:06 PM PDT 24
Peak memory 246228 kb
Host smart-6fab2ccd-f3ac-4c9a-b6d0-d8972b2f309f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568612787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.3568612787
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.1875839176
Short name T1277
Test name
Test status
Simulation time 39462903 ps
CPU time 1.34 seconds
Started Jun 02 03:05:25 PM PDT 24
Finished Jun 02 03:05:27 PM PDT 24
Peak memory 229036 kb
Host smart-cd2dc0e6-4491-4e1f-9260-0678ba2af9b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875839176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.1875839176
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.215321517
Short name T1229
Test name
Test status
Simulation time 556043986 ps
CPU time 1.62 seconds
Started Jun 02 03:05:28 PM PDT 24
Finished Jun 02 03:05:31 PM PDT 24
Peak memory 228984 kb
Host smart-8cde0ee2-1ab3-4b02-b566-94cccc4e346a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215321517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.215321517
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.4079226387
Short name T1218
Test name
Test status
Simulation time 78467568 ps
CPU time 1.48 seconds
Started Jun 02 03:05:30 PM PDT 24
Finished Jun 02 03:05:32 PM PDT 24
Peak memory 228776 kb
Host smart-779e816a-60d4-4457-ac91-695c2ab023b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079226387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.4079226387
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.3349464661
Short name T1272
Test name
Test status
Simulation time 73430669 ps
CPU time 1.49 seconds
Started Jun 02 03:05:30 PM PDT 24
Finished Jun 02 03:05:32 PM PDT 24
Peak memory 230068 kb
Host smart-f59db7e2-a1e8-45fb-a704-db76ba3707ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349464661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.3349464661
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.2905317574
Short name T1267
Test name
Test status
Simulation time 139998635 ps
CPU time 1.61 seconds
Started Jun 02 03:05:30 PM PDT 24
Finished Jun 02 03:05:32 PM PDT 24
Peak memory 229236 kb
Host smart-05efc9e2-76fa-46bc-b4f4-fe890c45a7f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905317574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.2905317574
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.3839886528
Short name T1222
Test name
Test status
Simulation time 547332065 ps
CPU time 1.62 seconds
Started Jun 02 03:05:30 PM PDT 24
Finished Jun 02 03:05:32 PM PDT 24
Peak memory 229068 kb
Host smart-65caa3aa-b522-48a1-9ac5-91c169467cdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839886528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.3839886528
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2160534539
Short name T1301
Test name
Test status
Simulation time 96921427 ps
CPU time 1.47 seconds
Started Jun 02 03:05:27 PM PDT 24
Finished Jun 02 03:05:29 PM PDT 24
Peak memory 230240 kb
Host smart-4c3d3bd3-8699-4b8e-b1a5-798e23f49687
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160534539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.2160534539
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.1440804186
Short name T1236
Test name
Test status
Simulation time 39497664 ps
CPU time 1.42 seconds
Started Jun 02 03:05:27 PM PDT 24
Finished Jun 02 03:05:29 PM PDT 24
Peak memory 229168 kb
Host smart-dd9fad42-0f9f-477d-b613-4b9733f94ef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440804186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.1440804186
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.3647711288
Short name T1221
Test name
Test status
Simulation time 73629714 ps
CPU time 1.44 seconds
Started Jun 02 03:05:26 PM PDT 24
Finished Jun 02 03:05:28 PM PDT 24
Peak memory 229324 kb
Host smart-6ba2b1b3-a644-4911-8c15-adf56606e140
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647711288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.3647711288
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.2003860463
Short name T1234
Test name
Test status
Simulation time 118119019 ps
CPU time 1.49 seconds
Started Jun 02 03:05:28 PM PDT 24
Finished Jun 02 03:05:30 PM PDT 24
Peak memory 230208 kb
Host smart-89c16d74-5360-4679-9996-69af7631840a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003860463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.2003860463
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.3293295094
Short name T1217
Test name
Test status
Simulation time 1097530823 ps
CPU time 3.47 seconds
Started Jun 02 03:05:04 PM PDT 24
Finished Jun 02 03:05:08 PM PDT 24
Peak memory 246596 kb
Host smart-b774ff05-6cff-4433-9579-80cdb7901b5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293295094 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.3293295094
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3006822664
Short name T333
Test name
Test status
Simulation time 87936231 ps
CPU time 1.92 seconds
Started Jun 02 03:04:56 PM PDT 24
Finished Jun 02 03:05:00 PM PDT 24
Peak memory 239356 kb
Host smart-d787dce0-def2-473d-ab42-655f01f15b93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006822664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.3006822664
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.2295831509
Short name T1223
Test name
Test status
Simulation time 90193064 ps
CPU time 1.47 seconds
Started Jun 02 03:04:59 PM PDT 24
Finished Jun 02 03:05:02 PM PDT 24
Peak memory 229004 kb
Host smart-0b85f924-59fd-4372-9fdb-eecc833d5a23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295831509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.2295831509
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1289448811
Short name T1278
Test name
Test status
Simulation time 67590972 ps
CPU time 2.16 seconds
Started Jun 02 03:05:05 PM PDT 24
Finished Jun 02 03:05:08 PM PDT 24
Peak memory 237516 kb
Host smart-a629c025-f3e2-441c-bc2e-8b79b413ea38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289448811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.1289448811
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3700254585
Short name T1213
Test name
Test status
Simulation time 80001537 ps
CPU time 4.76 seconds
Started Jun 02 03:05:01 PM PDT 24
Finished Jun 02 03:05:07 PM PDT 24
Peak memory 246368 kb
Host smart-18d8e729-2195-43d5-9f40-4135efcf8f64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700254585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.3700254585
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2388386144
Short name T359
Test name
Test status
Simulation time 4570835663 ps
CPU time 20.06 seconds
Started Jun 02 03:04:57 PM PDT 24
Finished Jun 02 03:05:19 PM PDT 24
Peak memory 243752 kb
Host smart-92e97831-4b3d-4a32-b367-3c5d77cd755c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388386144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.2388386144
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.636116081
Short name T379
Test name
Test status
Simulation time 262599110 ps
CPU time 2.36 seconds
Started Jun 02 03:05:03 PM PDT 24
Finished Jun 02 03:05:07 PM PDT 24
Peak memory 244928 kb
Host smart-b9f3efb3-af4e-4efb-997e-216385775dd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636116081 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.636116081
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.1190761860
Short name T1288
Test name
Test status
Simulation time 189438317 ps
CPU time 2.08 seconds
Started Jun 02 03:05:02 PM PDT 24
Finished Jun 02 03:05:05 PM PDT 24
Peak memory 238436 kb
Host smart-b9156da2-1b9e-4fed-a97f-8025a5426043
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190761860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.1190761860
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.3775743482
Short name T1214
Test name
Test status
Simulation time 533160268 ps
CPU time 1.6 seconds
Started Jun 02 03:05:02 PM PDT 24
Finished Jun 02 03:05:05 PM PDT 24
Peak memory 228984 kb
Host smart-2bf80505-0e52-41d8-a3e7-dc24132f2526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775743482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.3775743482
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1359096819
Short name T1314
Test name
Test status
Simulation time 82285055 ps
CPU time 2.92 seconds
Started Jun 02 03:05:06 PM PDT 24
Finished Jun 02 03:05:10 PM PDT 24
Peak memory 237664 kb
Host smart-f58e101a-3bf3-4083-a5d4-d860ec864859
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359096819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.1359096819
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.3561292554
Short name T1209
Test name
Test status
Simulation time 161888406 ps
CPU time 4.4 seconds
Started Jun 02 03:05:03 PM PDT 24
Finished Jun 02 03:05:09 PM PDT 24
Peak memory 246128 kb
Host smart-7e023819-28ef-4064-a3d5-e3cc5a914f82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561292554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.3561292554
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2761608765
Short name T360
Test name
Test status
Simulation time 10273659002 ps
CPU time 14.73 seconds
Started Jun 02 03:05:04 PM PDT 24
Finished Jun 02 03:05:20 PM PDT 24
Peak memory 243652 kb
Host smart-12484d74-5a6f-4a2e-81a7-17f209aa4ec5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761608765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.2761608765
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3943630123
Short name T1232
Test name
Test status
Simulation time 1073855698 ps
CPU time 2.33 seconds
Started Jun 02 03:05:08 PM PDT 24
Finished Jun 02 03:05:10 PM PDT 24
Peak memory 244860 kb
Host smart-532caf2c-8ff0-4d09-a56f-5eed61af8612
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943630123 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.3943630123
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.2445587824
Short name T309
Test name
Test status
Simulation time 151666934 ps
CPU time 1.68 seconds
Started Jun 02 03:05:06 PM PDT 24
Finished Jun 02 03:05:09 PM PDT 24
Peak memory 239432 kb
Host smart-2b2e4750-e196-4544-9583-591f87582883
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445587824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.2445587824
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.1609780500
Short name T1208
Test name
Test status
Simulation time 580033099 ps
CPU time 1.92 seconds
Started Jun 02 03:05:03 PM PDT 24
Finished Jun 02 03:05:06 PM PDT 24
Peak memory 229044 kb
Host smart-3701d0f4-618b-43a8-9b07-4144b5ba2985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609780500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.1609780500
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.553549462
Short name T1307
Test name
Test status
Simulation time 62859116 ps
CPU time 2.19 seconds
Started Jun 02 03:05:06 PM PDT 24
Finished Jun 02 03:05:08 PM PDT 24
Peak memory 237596 kb
Host smart-e2a2422d-8da1-41f2-abc7-a7458c8ab6c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553549462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ct
rl_same_csr_outstanding.553549462
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.2133009021
Short name T1255
Test name
Test status
Simulation time 609307893 ps
CPU time 6.68 seconds
Started Jun 02 03:05:02 PM PDT 24
Finished Jun 02 03:05:10 PM PDT 24
Peak memory 246168 kb
Host smart-f62779f3-4ef2-43b7-a913-44c15fe760bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133009021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.2133009021
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2300235090
Short name T1242
Test name
Test status
Simulation time 69159379 ps
CPU time 1.97 seconds
Started Jun 02 03:05:09 PM PDT 24
Finished Jun 02 03:05:12 PM PDT 24
Peak memory 243656 kb
Host smart-0c64641f-c368-4ff0-9eb4-b9d8bfaf89d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300235090 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.2300235090
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3692270988
Short name T1327
Test name
Test status
Simulation time 72663134 ps
CPU time 1.56 seconds
Started Jun 02 03:05:12 PM PDT 24
Finished Jun 02 03:05:14 PM PDT 24
Peak memory 239216 kb
Host smart-6d84ddbb-5909-4c9a-aab7-2499a9459893
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692270988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.3692270988
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.3053707105
Short name T1257
Test name
Test status
Simulation time 593932687 ps
CPU time 2.18 seconds
Started Jun 02 03:05:10 PM PDT 24
Finished Jun 02 03:05:13 PM PDT 24
Peak memory 228992 kb
Host smart-8237ae45-6376-4b7b-aaa0-d120e3e7f395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053707105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.3053707105
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.380290253
Short name T331
Test name
Test status
Simulation time 214196960 ps
CPU time 2.7 seconds
Started Jun 02 03:05:08 PM PDT 24
Finished Jun 02 03:05:12 PM PDT 24
Peak memory 238600 kb
Host smart-bb13e767-5414-4ff5-9d08-7f1b9a95a950
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380290253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ct
rl_same_csr_outstanding.380290253
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.163616157
Short name T1269
Test name
Test status
Simulation time 121324802 ps
CPU time 4.17 seconds
Started Jun 02 03:05:10 PM PDT 24
Finished Jun 02 03:05:15 PM PDT 24
Peak memory 246208 kb
Host smart-c99037db-c669-4833-becf-f97f11d9e191
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163616157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.163616157
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.81982926
Short name T363
Test name
Test status
Simulation time 1400809187 ps
CPU time 9.71 seconds
Started Jun 02 03:05:14 PM PDT 24
Finished Jun 02 03:05:24 PM PDT 24
Peak memory 243204 kb
Host smart-61098ab0-7c8b-45dc-a077-cd005ad1afe7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81982926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_intg
_err.81982926
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.4171330142
Short name T1326
Test name
Test status
Simulation time 65248854 ps
CPU time 2 seconds
Started Jun 02 03:05:09 PM PDT 24
Finished Jun 02 03:05:12 PM PDT 24
Peak memory 243956 kb
Host smart-0609ec42-a584-4785-8848-1bce6ecb6325
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171330142 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.4171330142
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.4285265638
Short name T1261
Test name
Test status
Simulation time 81318442 ps
CPU time 1.66 seconds
Started Jun 02 03:05:12 PM PDT 24
Finished Jun 02 03:05:14 PM PDT 24
Peak memory 238320 kb
Host smart-6b33ce0b-33a9-44e8-b7df-f749197ebf9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285265638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.4285265638
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.3959839073
Short name T1297
Test name
Test status
Simulation time 532963935 ps
CPU time 1.64 seconds
Started Jun 02 03:05:08 PM PDT 24
Finished Jun 02 03:05:10 PM PDT 24
Peak memory 229276 kb
Host smart-37886a9b-8213-4168-8444-f0b99dd4374e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959839073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.3959839073
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3124157685
Short name T279
Test name
Test status
Simulation time 1710773039 ps
CPU time 3.36 seconds
Started Jun 02 03:05:09 PM PDT 24
Finished Jun 02 03:05:14 PM PDT 24
Peak memory 238352 kb
Host smart-c096d6ce-9152-4cac-8d49-b1cdd9fd5713
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124157685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.3124157685
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3897412852
Short name T1203
Test name
Test status
Simulation time 158547592 ps
CPU time 5.94 seconds
Started Jun 02 03:05:09 PM PDT 24
Finished Jun 02 03:05:16 PM PDT 24
Peak memory 246512 kb
Host smart-c5c1e137-9f89-48f8-87c0-c0b4a67c4924
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897412852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.3897412852
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.740029809
Short name T1305
Test name
Test status
Simulation time 645382216 ps
CPU time 9.61 seconds
Started Jun 02 03:05:09 PM PDT 24
Finished Jun 02 03:05:20 PM PDT 24
Peak memory 242588 kb
Host smart-4855adc3-ce73-4b80-825d-f7f0e9eb4ebe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740029809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_int
g_err.740029809
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.3424117136
Short name T1000
Test name
Test status
Simulation time 850544211 ps
CPU time 1.88 seconds
Started Jun 02 03:07:26 PM PDT 24
Finished Jun 02 03:07:29 PM PDT 24
Peak memory 241032 kb
Host smart-e5568d96-b2e7-4813-aeda-88aaee9249e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424117136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.3424117136
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.543164392
Short name T630
Test name
Test status
Simulation time 6708032183 ps
CPU time 12.13 seconds
Started Jun 02 03:07:19 PM PDT 24
Finished Jun 02 03:07:32 PM PDT 24
Peak memory 242468 kb
Host smart-5b254737-841e-45b5-9018-5fe351afcaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543164392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.543164392
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.869546687
Short name T438
Test name
Test status
Simulation time 1892763066 ps
CPU time 10.3 seconds
Started Jun 02 03:07:20 PM PDT 24
Finished Jun 02 03:07:30 PM PDT 24
Peak memory 248960 kb
Host smart-f6c6f97f-5e61-4d5d-922a-58f4548268ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869546687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.869546687
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.455353593
Short name T1172
Test name
Test status
Simulation time 2102082572 ps
CPU time 36.64 seconds
Started Jun 02 03:07:20 PM PDT 24
Finished Jun 02 03:07:57 PM PDT 24
Peak memory 244136 kb
Host smart-214bf123-89e8-4811-999e-5ddcb4eb2455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455353593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.455353593
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.570916007
Short name T446
Test name
Test status
Simulation time 772856669 ps
CPU time 20.92 seconds
Started Jun 02 03:07:18 PM PDT 24
Finished Jun 02 03:07:39 PM PDT 24
Peak memory 242160 kb
Host smart-59cfd3c5-ac1e-409b-81f0-49c6e7cf3b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570916007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.570916007
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.1052417925
Short name T1081
Test name
Test status
Simulation time 116174702 ps
CPU time 4.08 seconds
Started Jun 02 03:07:20 PM PDT 24
Finished Jun 02 03:07:24 PM PDT 24
Peak memory 242676 kb
Host smart-398a366f-c91b-4181-a859-a435cad9d370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052417925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.1052417925
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.2584769852
Short name T471
Test name
Test status
Simulation time 3049419155 ps
CPU time 12.16 seconds
Started Jun 02 03:07:18 PM PDT 24
Finished Jun 02 03:07:31 PM PDT 24
Peak memory 241712 kb
Host smart-29ffe94b-2a5e-499f-8357-ebae199f381e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584769852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.2584769852
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.3455772163
Short name T214
Test name
Test status
Simulation time 6230533037 ps
CPU time 42.68 seconds
Started Jun 02 03:07:18 PM PDT 24
Finished Jun 02 03:08:01 PM PDT 24
Peak memory 249064 kb
Host smart-bbfbe6ee-ffdc-4b48-bfd3-c1f27518da31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455772163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.3455772163
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.1722133423
Short name T1086
Test name
Test status
Simulation time 1843352751 ps
CPU time 18.59 seconds
Started Jun 02 03:07:19 PM PDT 24
Finished Jun 02 03:07:38 PM PDT 24
Peak memory 242220 kb
Host smart-dad7f881-1744-4d7b-9d14-0e390f5ae001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722133423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.1722133423
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.538995997
Short name T666
Test name
Test status
Simulation time 321250711 ps
CPU time 8.69 seconds
Started Jun 02 03:07:20 PM PDT 24
Finished Jun 02 03:07:30 PM PDT 24
Peak memory 242240 kb
Host smart-92146d69-2290-4e92-be8b-64a0c8b8cfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538995997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.538995997
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.2583555072
Short name T253
Test name
Test status
Simulation time 2139689275 ps
CPU time 19.4 seconds
Started Jun 02 03:07:18 PM PDT 24
Finished Jun 02 03:07:38 PM PDT 24
Peak memory 242504 kb
Host smart-fb314e49-c71c-4873-a1e5-b6fae7bcef00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2583555072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.2583555072
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.3172691614
Short name T294
Test name
Test status
Simulation time 609912899 ps
CPU time 20.22 seconds
Started Jun 02 03:07:19 PM PDT 24
Finished Jun 02 03:07:40 PM PDT 24
Peak memory 241668 kb
Host smart-476ad4ea-17d0-4315-ba43-10bb87b4ed76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172691614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.3172691614
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.4081073668
Short name T1099
Test name
Test status
Simulation time 228460478 ps
CPU time 3.47 seconds
Started Jun 02 03:07:21 PM PDT 24
Finished Jun 02 03:07:25 PM PDT 24
Peak memory 242292 kb
Host smart-39374c99-5ad5-4e4b-9ca9-fda2214b547e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4081073668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.4081073668
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.4122650931
Short name T21
Test name
Test status
Simulation time 21366989157 ps
CPU time 195.59 seconds
Started Jun 02 03:07:27 PM PDT 24
Finished Jun 02 03:10:43 PM PDT 24
Peak memory 278988 kb
Host smart-781b4627-26a0-48b2-aa55-febd68db040a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122650931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.4122650931
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.3263325860
Short name T1084
Test name
Test status
Simulation time 860427011 ps
CPU time 6.38 seconds
Started Jun 02 03:07:17 PM PDT 24
Finished Jun 02 03:07:24 PM PDT 24
Peak memory 242228 kb
Host smart-f4c94503-2592-45a8-9c6b-a04c4c0fde5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263325860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.3263325860
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.2031768826
Short name T589
Test name
Test status
Simulation time 67295861683 ps
CPU time 141.26 seconds
Started Jun 02 03:07:22 PM PDT 24
Finished Jun 02 03:09:44 PM PDT 24
Peak memory 259940 kb
Host smart-c65c50f0-8840-412a-9f18-47d3d9f250e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031768826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
2031768826
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.2441867908
Short name T1170
Test name
Test status
Simulation time 890946003305 ps
CPU time 2114.64 seconds
Started Jun 02 03:07:24 PM PDT 24
Finished Jun 02 03:42:39 PM PDT 24
Peak memory 519540 kb
Host smart-ca1337be-77e8-4379-9406-8c2027790c9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441867908 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.2441867908
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.655539637
Short name T1010
Test name
Test status
Simulation time 1886569474 ps
CPU time 32.68 seconds
Started Jun 02 03:07:18 PM PDT 24
Finished Jun 02 03:07:52 PM PDT 24
Peak memory 242196 kb
Host smart-45344aeb-0d5f-4804-8c89-d39473f21e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655539637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.655539637
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.2619986195
Short name T875
Test name
Test status
Simulation time 121475102 ps
CPU time 1.89 seconds
Started Jun 02 03:07:33 PM PDT 24
Finished Jun 02 03:07:36 PM PDT 24
Peak memory 240816 kb
Host smart-18f514d4-d401-47f6-aa26-c8c19a3392d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619986195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.2619986195
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.1446454357
Short name T677
Test name
Test status
Simulation time 449865295 ps
CPU time 12.97 seconds
Started Jun 02 03:07:23 PM PDT 24
Finished Jun 02 03:07:37 PM PDT 24
Peak memory 242352 kb
Host smart-8f4d597a-4d24-4a32-8d91-0d0e94968911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446454357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.1446454357
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.1408443092
Short name T445
Test name
Test status
Simulation time 2281528660 ps
CPU time 28.31 seconds
Started Jun 02 03:07:24 PM PDT 24
Finished Jun 02 03:07:53 PM PDT 24
Peak memory 242660 kb
Host smart-81011b39-87e0-4840-9050-9f2b8e74bf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408443092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.1408443092
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.3386513708
Short name T386
Test name
Test status
Simulation time 7737001164 ps
CPU time 27.33 seconds
Started Jun 02 03:07:32 PM PDT 24
Finished Jun 02 03:08:00 PM PDT 24
Peak memory 242988 kb
Host smart-b4267c13-d71d-4698-a00e-789580d2470f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386513708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.3386513708
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.1228070712
Short name T1103
Test name
Test status
Simulation time 2711468406 ps
CPU time 28.22 seconds
Started Jun 02 03:07:32 PM PDT 24
Finished Jun 02 03:08:01 PM PDT 24
Peak memory 249276 kb
Host smart-6979a561-1ba8-4d13-86ba-8bbaace4c9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228070712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.1228070712
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.570399816
Short name T852
Test name
Test status
Simulation time 1065616906 ps
CPU time 14.03 seconds
Started Jun 02 03:07:24 PM PDT 24
Finished Jun 02 03:07:38 PM PDT 24
Peak memory 242204 kb
Host smart-e96b8c3c-ce84-4d6c-ae26-9246ced6f2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570399816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.570399816
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.1367645041
Short name T244
Test name
Test status
Simulation time 286506106 ps
CPU time 6.26 seconds
Started Jun 02 03:07:26 PM PDT 24
Finished Jun 02 03:07:33 PM PDT 24
Peak memory 242256 kb
Host smart-81bca7ea-1a3f-4f6d-bc36-421454d395ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367645041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.1367645041
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.2333245425
Short name T689
Test name
Test status
Simulation time 2144733617 ps
CPU time 18.07 seconds
Started Jun 02 03:07:25 PM PDT 24
Finished Jun 02 03:07:43 PM PDT 24
Peak memory 248860 kb
Host smart-5ba71a1d-a2bc-49bb-8bd0-aac6c7aad29b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2333245425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.2333245425
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.1789491379
Short name T1085
Test name
Test status
Simulation time 657371982 ps
CPU time 10.46 seconds
Started Jun 02 03:07:27 PM PDT 24
Finished Jun 02 03:07:38 PM PDT 24
Peak memory 242324 kb
Host smart-8bb32298-1c51-4bd5-9997-6a15191a8b88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1789491379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.1789491379
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.1307633122
Short name T245
Test name
Test status
Simulation time 10305905648 ps
CPU time 196.52 seconds
Started Jun 02 03:07:29 PM PDT 24
Finished Jun 02 03:10:47 PM PDT 24
Peak memory 274060 kb
Host smart-f0ab5e0a-b5fc-4859-a184-7bba08a39522
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307633122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.1307633122
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.2039465294
Short name T669
Test name
Test status
Simulation time 170456979 ps
CPU time 4.86 seconds
Started Jun 02 03:07:26 PM PDT 24
Finished Jun 02 03:07:32 PM PDT 24
Peak memory 242524 kb
Host smart-fb8a43b0-6ae0-4c52-b3d5-7ade50d2f05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039465294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.2039465294
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.58646397
Short name T1167
Test name
Test status
Simulation time 17833953928 ps
CPU time 249.77 seconds
Started Jun 02 03:07:31 PM PDT 24
Finished Jun 02 03:11:41 PM PDT 24
Peak memory 279864 kb
Host smart-da9c57cf-f7a0-4dfa-9c6d-726220437332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58646397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.58646397
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.256321565
Short name T180
Test name
Test status
Simulation time 823303179 ps
CPU time 10.84 seconds
Started Jun 02 03:07:29 PM PDT 24
Finished Jun 02 03:07:41 PM PDT 24
Peak memory 242196 kb
Host smart-bcad6139-8dbc-414f-af86-88aee7932727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256321565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.256321565
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.2266002507
Short name T890
Test name
Test status
Simulation time 1056788007 ps
CPU time 2.54 seconds
Started Jun 02 03:08:03 PM PDT 24
Finished Jun 02 03:08:06 PM PDT 24
Peak memory 240764 kb
Host smart-eae91534-7f0c-4374-99ec-92527e2e21d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266002507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.2266002507
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.2677484620
Short name T110
Test name
Test status
Simulation time 1050876581 ps
CPU time 13.49 seconds
Started Jun 02 03:08:08 PM PDT 24
Finished Jun 02 03:08:22 PM PDT 24
Peak memory 248916 kb
Host smart-98f98b60-347a-4e3b-a1cc-f68b24d7ff8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677484620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.2677484620
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.1639747171
Short name T173
Test name
Test status
Simulation time 1491505006 ps
CPU time 20.82 seconds
Started Jun 02 03:08:05 PM PDT 24
Finished Jun 02 03:08:27 PM PDT 24
Peak memory 242724 kb
Host smart-3abcd05e-1685-474c-96f2-7738aa3676f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639747171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.1639747171
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.2652958453
Short name T829
Test name
Test status
Simulation time 1604873415 ps
CPU time 19.5 seconds
Started Jun 02 03:08:05 PM PDT 24
Finished Jun 02 03:08:25 PM PDT 24
Peak memory 248852 kb
Host smart-1dd83e93-45f6-43df-b91d-f75643396fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652958453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.2652958453
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.761540273
Short name T1045
Test name
Test status
Simulation time 583918675 ps
CPU time 4.67 seconds
Started Jun 02 03:07:58 PM PDT 24
Finished Jun 02 03:08:04 PM PDT 24
Peak memory 242328 kb
Host smart-d452cfcc-7a57-4dcc-8a78-56125a8689bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761540273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.761540273
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.2632634226
Short name T95
Test name
Test status
Simulation time 672369538 ps
CPU time 26.62 seconds
Started Jun 02 03:08:08 PM PDT 24
Finished Jun 02 03:08:36 PM PDT 24
Peak memory 242520 kb
Host smart-b6e50a55-67e8-441b-9c23-f861603add4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632634226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.2632634226
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.3980898110
Short name T136
Test name
Test status
Simulation time 2266447099 ps
CPU time 7.03 seconds
Started Jun 02 03:07:58 PM PDT 24
Finished Jun 02 03:08:06 PM PDT 24
Peak memory 242616 kb
Host smart-2d9c4d44-61d3-4bf8-ba9c-280fa11d3ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980898110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.3980898110
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.2364450320
Short name T569
Test name
Test status
Simulation time 751209612 ps
CPU time 20.51 seconds
Started Jun 02 03:07:57 PM PDT 24
Finished Jun 02 03:08:18 PM PDT 24
Peak memory 242288 kb
Host smart-64c2565e-7e69-4980-9c78-8a048b57d965
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2364450320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.2364450320
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.1826778221
Short name T107
Test name
Test status
Simulation time 225415104 ps
CPU time 6.32 seconds
Started Jun 02 03:08:02 PM PDT 24
Finished Jun 02 03:08:09 PM PDT 24
Peak memory 242204 kb
Host smart-d3670d41-2ffe-4ec3-8072-87d854351bdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826778221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.1826778221
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.1965373566
Short name T994
Test name
Test status
Simulation time 569267326 ps
CPU time 13.9 seconds
Started Jun 02 03:07:58 PM PDT 24
Finished Jun 02 03:08:13 PM PDT 24
Peak memory 242300 kb
Host smart-9d777e7a-32ab-4776-95aa-b5f32d813b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965373566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.1965373566
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.4135281282
Short name T728
Test name
Test status
Simulation time 218974243479 ps
CPU time 364.61 seconds
Started Jun 02 03:08:02 PM PDT 24
Finished Jun 02 03:14:08 PM PDT 24
Peak memory 298196 kb
Host smart-d98277e6-ed58-4fd6-97f9-bbb2a6dea3d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135281282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all
.4135281282
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.2200036833
Short name T150
Test name
Test status
Simulation time 199204632344 ps
CPU time 1717.38 seconds
Started Jun 02 03:08:05 PM PDT 24
Finished Jun 02 03:36:44 PM PDT 24
Peak memory 346788 kb
Host smart-9b300674-375b-4b46-8bb3-2d12c56ef97d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200036833 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.2200036833
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.2208712114
Short name T391
Test name
Test status
Simulation time 13384858102 ps
CPU time 68.32 seconds
Started Jun 02 03:08:04 PM PDT 24
Finished Jun 02 03:09:13 PM PDT 24
Peak memory 242872 kb
Host smart-05e87d0c-9c57-4d3c-ac16-7db349d834c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208712114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.2208712114
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.2365418925
Short name T1012
Test name
Test status
Simulation time 709946639 ps
CPU time 10.21 seconds
Started Jun 02 03:10:57 PM PDT 24
Finished Jun 02 03:11:07 PM PDT 24
Peak memory 242456 kb
Host smart-05a0588f-a495-4963-9ce3-2b58a7e9ee57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365418925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.2365418925
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.3826354631
Short name T780
Test name
Test status
Simulation time 461306485 ps
CPU time 3.75 seconds
Started Jun 02 03:10:58 PM PDT 24
Finished Jun 02 03:11:03 PM PDT 24
Peak memory 242404 kb
Host smart-1be20100-2ef3-4e10-a682-b591ba98b647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826354631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.3826354631
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.799558464
Short name T951
Test name
Test status
Simulation time 749724865 ps
CPU time 18.48 seconds
Started Jun 02 03:10:55 PM PDT 24
Finished Jun 02 03:11:14 PM PDT 24
Peak memory 242548 kb
Host smart-ccefbd41-b68b-4919-83f0-5954ffb68003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799558464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.799558464
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.296124663
Short name T618
Test name
Test status
Simulation time 138099933 ps
CPU time 4.12 seconds
Started Jun 02 03:10:55 PM PDT 24
Finished Jun 02 03:11:00 PM PDT 24
Peak memory 242448 kb
Host smart-2d69920b-875a-4712-8ac5-fc4804bc5c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296124663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.296124663
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.1684922532
Short name T421
Test name
Test status
Simulation time 171995091 ps
CPU time 9.8 seconds
Started Jun 02 03:10:56 PM PDT 24
Finished Jun 02 03:11:07 PM PDT 24
Peak memory 242436 kb
Host smart-dafe1633-56a3-4be9-8c18-ce96daf228bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684922532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.1684922532
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.3605728030
Short name T692
Test name
Test status
Simulation time 156066928 ps
CPU time 5.92 seconds
Started Jun 02 03:10:54 PM PDT 24
Finished Jun 02 03:11:01 PM PDT 24
Peak memory 242568 kb
Host smart-fe4010b6-bfb6-4741-bef9-29b316ba5c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605728030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.3605728030
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.535688191
Short name T747
Test name
Test status
Simulation time 72770501 ps
CPU time 2.44 seconds
Started Jun 02 03:10:58 PM PDT 24
Finished Jun 02 03:11:01 PM PDT 24
Peak memory 242740 kb
Host smart-75ec0d1d-4036-45ae-a706-ec4f7e791df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535688191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.535688191
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.1664241685
Short name T1064
Test name
Test status
Simulation time 219266359 ps
CPU time 3.99 seconds
Started Jun 02 03:10:57 PM PDT 24
Finished Jun 02 03:11:01 PM PDT 24
Peak memory 242404 kb
Host smart-3b19a5a8-44e7-4bee-9704-c820e221039c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664241685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.1664241685
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.3658602577
Short name T481
Test name
Test status
Simulation time 164261661 ps
CPU time 3.63 seconds
Started Jun 02 03:10:55 PM PDT 24
Finished Jun 02 03:10:59 PM PDT 24
Peak memory 242184 kb
Host smart-763087cb-1b8e-4ccd-9910-7b2712366f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658602577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.3658602577
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.1033593861
Short name T167
Test name
Test status
Simulation time 150156210 ps
CPU time 4.29 seconds
Started Jun 02 03:10:57 PM PDT 24
Finished Jun 02 03:11:01 PM PDT 24
Peak memory 242860 kb
Host smart-220ef66e-c6ee-41e6-936d-6be67bc2fa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033593861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.1033593861
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.3032503716
Short name T560
Test name
Test status
Simulation time 377697903 ps
CPU time 3.16 seconds
Started Jun 02 03:10:57 PM PDT 24
Finished Jun 02 03:11:01 PM PDT 24
Peak memory 242272 kb
Host smart-e0903a25-1344-4e80-aebf-6237223da872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032503716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.3032503716
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.3594265417
Short name T776
Test name
Test status
Simulation time 442642817 ps
CPU time 10.9 seconds
Started Jun 02 03:10:57 PM PDT 24
Finished Jun 02 03:11:09 PM PDT 24
Peak memory 242200 kb
Host smart-f7399aec-7244-4b24-a336-39ac9680cac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594265417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.3594265417
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.3449908255
Short name T733
Test name
Test status
Simulation time 744862582 ps
CPU time 5.68 seconds
Started Jun 02 03:10:53 PM PDT 24
Finished Jun 02 03:10:59 PM PDT 24
Peak memory 242416 kb
Host smart-ac36a62b-dc5a-4fa9-af43-3639044da8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449908255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.3449908255
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.1220418494
Short name T300
Test name
Test status
Simulation time 440535192 ps
CPU time 3.97 seconds
Started Jun 02 03:10:54 PM PDT 24
Finished Jun 02 03:10:58 PM PDT 24
Peak memory 242300 kb
Host smart-a40d16fc-1725-41d7-96c8-6ea603874540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220418494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.1220418494
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.3221957374
Short name T1180
Test name
Test status
Simulation time 1940002688 ps
CPU time 6.19 seconds
Started Jun 02 03:10:58 PM PDT 24
Finished Jun 02 03:11:04 PM PDT 24
Peak memory 242292 kb
Host smart-375fda92-3466-4361-93c6-cfbd79d105db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221957374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.3221957374
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.3201252575
Short name T141
Test name
Test status
Simulation time 929078329 ps
CPU time 25.92 seconds
Started Jun 02 03:10:58 PM PDT 24
Finished Jun 02 03:11:24 PM PDT 24
Peak memory 242292 kb
Host smart-86380ea8-a29a-496d-82e4-0e44bac98222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201252575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.3201252575
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.2994738826
Short name T927
Test name
Test status
Simulation time 191658584 ps
CPU time 1.9 seconds
Started Jun 02 03:08:05 PM PDT 24
Finished Jun 02 03:08:07 PM PDT 24
Peak memory 240812 kb
Host smart-3f261be3-2e16-48af-9e19-2a83b52b43b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994738826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.2994738826
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.4287896375
Short name T69
Test name
Test status
Simulation time 859168403 ps
CPU time 21.55 seconds
Started Jun 02 03:08:05 PM PDT 24
Finished Jun 02 03:08:27 PM PDT 24
Peak memory 242520 kb
Host smart-070acbc6-a02a-4447-a03b-da2013125ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287896375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.4287896375
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.760499597
Short name T950
Test name
Test status
Simulation time 668478027 ps
CPU time 15.72 seconds
Started Jun 02 03:08:15 PM PDT 24
Finished Jun 02 03:08:33 PM PDT 24
Peak memory 241580 kb
Host smart-dad0ae13-25c4-4218-8c3a-3e549f19d728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760499597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.760499597
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.2814785235
Short name T411
Test name
Test status
Simulation time 1686809776 ps
CPU time 21.6 seconds
Started Jun 02 03:08:03 PM PDT 24
Finished Jun 02 03:08:25 PM PDT 24
Peak memory 248844 kb
Host smart-dff70e0c-241f-4dc8-9e61-6d9dea767845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814785235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.2814785235
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.3150579878
Short name T883
Test name
Test status
Simulation time 1522414449 ps
CPU time 6.61 seconds
Started Jun 02 03:08:15 PM PDT 24
Finished Jun 02 03:08:23 PM PDT 24
Peak memory 242348 kb
Host smart-a2fd05c9-f065-465c-bbfa-881900bb8329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150579878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.3150579878
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.1834097167
Short name T676
Test name
Test status
Simulation time 10418657998 ps
CPU time 22.42 seconds
Started Jun 02 03:08:05 PM PDT 24
Finished Jun 02 03:08:28 PM PDT 24
Peak memory 246940 kb
Host smart-6423951c-4f99-44bc-bf79-a36c64f817e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834097167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.1834097167
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.1769007704
Short name T541
Test name
Test status
Simulation time 313938652 ps
CPU time 13.72 seconds
Started Jun 02 03:08:08 PM PDT 24
Finished Jun 02 03:08:23 PM PDT 24
Peak memory 242564 kb
Host smart-083453f9-56b8-4420-aeaf-d7b48fde828e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769007704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.1769007704
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.2333187778
Short name T919
Test name
Test status
Simulation time 1507861776 ps
CPU time 18.87 seconds
Started Jun 02 03:08:04 PM PDT 24
Finished Jun 02 03:08:24 PM PDT 24
Peak memory 242760 kb
Host smart-74294b7f-c07c-4b5f-8f1d-f5678c748bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333187778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.2333187778
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.1258334903
Short name T1190
Test name
Test status
Simulation time 502777677 ps
CPU time 15.71 seconds
Started Jun 02 03:08:04 PM PDT 24
Finished Jun 02 03:08:20 PM PDT 24
Peak memory 248868 kb
Host smart-ee4a76fc-8da6-475b-be36-ff4dcb0a3c40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1258334903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.1258334903
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.2936317250
Short name T270
Test name
Test status
Simulation time 108270420 ps
CPU time 3.95 seconds
Started Jun 02 03:08:06 PM PDT 24
Finished Jun 02 03:08:10 PM PDT 24
Peak memory 248772 kb
Host smart-57809e40-8a6b-4bb1-afe6-33d198a696f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2936317250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.2936317250
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.456056071
Short name T565
Test name
Test status
Simulation time 233246874 ps
CPU time 5.64 seconds
Started Jun 02 03:08:03 PM PDT 24
Finished Jun 02 03:08:10 PM PDT 24
Peak memory 242368 kb
Host smart-cb214199-7e04-4253-be6c-1b6403a78d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456056071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.456056071
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.1934525118
Short name T1105
Test name
Test status
Simulation time 1279870611 ps
CPU time 14.95 seconds
Started Jun 02 03:08:16 PM PDT 24
Finished Jun 02 03:08:32 PM PDT 24
Peak memory 242204 kb
Host smart-57a5541a-7608-446f-baef-2d854d24b4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934525118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.1934525118
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.2456228348
Short name T473
Test name
Test status
Simulation time 173938158 ps
CPU time 4.33 seconds
Started Jun 02 03:11:00 PM PDT 24
Finished Jun 02 03:11:05 PM PDT 24
Peak memory 242332 kb
Host smart-f9063057-f265-4271-a96e-b1f3b539775a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456228348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.2456228348
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.1428884325
Short name T401
Test name
Test status
Simulation time 340434071 ps
CPU time 8.16 seconds
Started Jun 02 03:10:59 PM PDT 24
Finished Jun 02 03:11:08 PM PDT 24
Peak memory 242184 kb
Host smart-0a6f4ec8-ad59-4e5e-b526-6ef8d6657bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428884325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.1428884325
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.3816773946
Short name T197
Test name
Test status
Simulation time 183754932 ps
CPU time 3.05 seconds
Started Jun 02 03:11:03 PM PDT 24
Finished Jun 02 03:11:06 PM PDT 24
Peak memory 242668 kb
Host smart-c5468a22-f702-40fc-a68f-30aa27c43dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816773946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3816773946
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.1188279998
Short name T986
Test name
Test status
Simulation time 147761355 ps
CPU time 4.23 seconds
Started Jun 02 03:11:00 PM PDT 24
Finished Jun 02 03:11:05 PM PDT 24
Peak memory 242404 kb
Host smart-c76f0205-881d-4c99-80f0-8f1979b353b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188279998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.1188279998
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.3792560719
Short name T353
Test name
Test status
Simulation time 444400512 ps
CPU time 3.7 seconds
Started Jun 02 03:11:00 PM PDT 24
Finished Jun 02 03:11:04 PM PDT 24
Peak memory 242192 kb
Host smart-d4bc4f0d-ced6-4dc9-aca3-ef96cf21143a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792560719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.3792560719
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.1370137116
Short name T758
Test name
Test status
Simulation time 164950872 ps
CPU time 3.84 seconds
Started Jun 02 03:11:05 PM PDT 24
Finished Jun 02 03:11:09 PM PDT 24
Peak memory 242676 kb
Host smart-7cebfd0a-ecb0-40e0-9d4b-bff8c8447bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370137116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.1370137116
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.772571477
Short name T272
Test name
Test status
Simulation time 2885509430 ps
CPU time 5.61 seconds
Started Jun 02 03:11:01 PM PDT 24
Finished Jun 02 03:11:07 PM PDT 24
Peak memory 242716 kb
Host smart-99746fe2-5797-44a5-a957-101d8fc0cbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772571477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.772571477
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.3474675230
Short name T885
Test name
Test status
Simulation time 3265320138 ps
CPU time 8.34 seconds
Started Jun 02 03:11:02 PM PDT 24
Finished Jun 02 03:11:10 PM PDT 24
Peak memory 242240 kb
Host smart-f4d5e187-dfac-48ba-9ee0-5c295760f9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474675230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.3474675230
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.31905548
Short name T754
Test name
Test status
Simulation time 198790046 ps
CPU time 3.73 seconds
Started Jun 02 03:11:00 PM PDT 24
Finished Jun 02 03:11:05 PM PDT 24
Peak memory 242516 kb
Host smart-c7dfb2e0-c70a-41f6-9144-bb06ecebd8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31905548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.31905548
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.1361376204
Short name T613
Test name
Test status
Simulation time 342663547 ps
CPU time 5.47 seconds
Started Jun 02 03:10:59 PM PDT 24
Finished Jun 02 03:11:06 PM PDT 24
Peak memory 242272 kb
Host smart-44a7ea16-0dac-4fbf-b20f-89f6cc82c694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361376204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.1361376204
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.2493377163
Short name T910
Test name
Test status
Simulation time 1377766246 ps
CPU time 5.43 seconds
Started Jun 02 03:11:01 PM PDT 24
Finished Jun 02 03:11:07 PM PDT 24
Peak memory 242296 kb
Host smart-3f9861b6-5428-412c-af1d-c2d9664b7ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493377163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.2493377163
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.2909150488
Short name T739
Test name
Test status
Simulation time 3082984597 ps
CPU time 10.97 seconds
Started Jun 02 03:11:00 PM PDT 24
Finished Jun 02 03:11:11 PM PDT 24
Peak memory 242528 kb
Host smart-32e5c5e2-bad7-43cf-a81c-0389b4255470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909150488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.2909150488
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.1364739668
Short name T129
Test name
Test status
Simulation time 165444968 ps
CPU time 4.86 seconds
Started Jun 02 03:11:02 PM PDT 24
Finished Jun 02 03:11:07 PM PDT 24
Peak memory 242476 kb
Host smart-63832063-29be-4709-8a9f-7b79d679e3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364739668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.1364739668
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.2294181442
Short name T113
Test name
Test status
Simulation time 528274837 ps
CPU time 6.24 seconds
Started Jun 02 03:11:00 PM PDT 24
Finished Jun 02 03:11:07 PM PDT 24
Peak memory 242512 kb
Host smart-43cc849d-de3a-433e-a959-cb1fed8611c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294181442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.2294181442
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.2118131577
Short name T199
Test name
Test status
Simulation time 456500086 ps
CPU time 3.65 seconds
Started Jun 02 03:11:03 PM PDT 24
Finished Jun 02 03:11:07 PM PDT 24
Peak memory 242344 kb
Host smart-cb271fe1-8745-41ce-83f9-91f18bec4c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118131577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.2118131577
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.1203483660
Short name T91
Test name
Test status
Simulation time 2171232717 ps
CPU time 8.8 seconds
Started Jun 02 03:10:59 PM PDT 24
Finished Jun 02 03:11:09 PM PDT 24
Peak memory 242288 kb
Host smart-5d5d1124-9546-4762-8090-ed00adb68acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203483660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.1203483660
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.3933937672
Short name T521
Test name
Test status
Simulation time 114872027 ps
CPU time 3.55 seconds
Started Jun 02 03:11:00 PM PDT 24
Finished Jun 02 03:11:04 PM PDT 24
Peak memory 242700 kb
Host smart-784a2851-0340-4f42-81b9-f355e24dde6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933937672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.3933937672
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.4133845961
Short name T1056
Test name
Test status
Simulation time 1023062374 ps
CPU time 8.33 seconds
Started Jun 02 03:11:00 PM PDT 24
Finished Jun 02 03:11:09 PM PDT 24
Peak memory 242156 kb
Host smart-6d1ac629-a0af-4ace-8192-8ba9e2ec781f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133845961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.4133845961
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.193187720
Short name T1166
Test name
Test status
Simulation time 119272668 ps
CPU time 1.98 seconds
Started Jun 02 03:08:15 PM PDT 24
Finished Jun 02 03:08:19 PM PDT 24
Peak memory 240200 kb
Host smart-2b96f683-911b-4850-8831-78b9a89c6296
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193187720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.193187720
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.3406324335
Short name T68
Test name
Test status
Simulation time 1326233155 ps
CPU time 20.37 seconds
Started Jun 02 03:08:08 PM PDT 24
Finished Jun 02 03:08:29 PM PDT 24
Peak memory 242596 kb
Host smart-a6f5453a-8ed5-485a-808e-8193ef890c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406324335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.3406324335
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.3553347458
Short name T457
Test name
Test status
Simulation time 1306198375 ps
CPU time 36.09 seconds
Started Jun 02 03:08:03 PM PDT 24
Finished Jun 02 03:08:40 PM PDT 24
Peak memory 246608 kb
Host smart-d396c038-9de0-4f93-bfdc-9a5c9c95174d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553347458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.3553347458
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.1274890123
Short name T1111
Test name
Test status
Simulation time 5559744683 ps
CPU time 42.83 seconds
Started Jun 02 03:08:05 PM PDT 24
Finished Jun 02 03:08:49 PM PDT 24
Peak memory 243396 kb
Host smart-b9d43a26-1ff6-4a27-b0ac-d89cb11d5df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274890123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.1274890123
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.2008598104
Short name T571
Test name
Test status
Simulation time 248177324 ps
CPU time 5.19 seconds
Started Jun 02 03:08:09 PM PDT 24
Finished Jun 02 03:08:15 PM PDT 24
Peak memory 242688 kb
Host smart-36c46baf-0fe2-4d76-902d-d5299e66addd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008598104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.2008598104
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.2136572500
Short name T796
Test name
Test status
Simulation time 206156009 ps
CPU time 5.62 seconds
Started Jun 02 03:08:08 PM PDT 24
Finished Jun 02 03:08:14 PM PDT 24
Peak memory 242348 kb
Host smart-5ec155ff-7fd5-4da4-9b85-b77ace5ff0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136572500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.2136572500
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.4213139113
Short name T1134
Test name
Test status
Simulation time 297192757 ps
CPU time 4.32 seconds
Started Jun 02 03:08:04 PM PDT 24
Finished Jun 02 03:08:09 PM PDT 24
Peak memory 242224 kb
Host smart-60cea498-ff10-4916-9175-53bd6d9f1c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213139113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.4213139113
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.56712367
Short name T638
Test name
Test status
Simulation time 736053102 ps
CPU time 6.99 seconds
Started Jun 02 03:08:08 PM PDT 24
Finished Jun 02 03:08:16 PM PDT 24
Peak memory 242404 kb
Host smart-7517d984-67f7-4543-9634-ef71459b0bfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56712367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.56712367
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.2566562294
Short name T369
Test name
Test status
Simulation time 721657434 ps
CPU time 10.03 seconds
Started Jun 02 03:08:04 PM PDT 24
Finished Jun 02 03:08:15 PM PDT 24
Peak memory 242524 kb
Host smart-062163de-0eec-4d91-9ff8-8c4cbbb097c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2566562294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2566562294
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.3261668313
Short name T1058
Test name
Test status
Simulation time 532406451 ps
CPU time 5.98 seconds
Started Jun 02 03:08:03 PM PDT 24
Finished Jun 02 03:08:10 PM PDT 24
Peak memory 242124 kb
Host smart-134a0b78-5c3d-45a0-bba8-79ec43ee50c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261668313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.3261668313
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.2096200299
Short name T1025
Test name
Test status
Simulation time 25257860229 ps
CPU time 152.87 seconds
Started Jun 02 03:08:03 PM PDT 24
Finished Jun 02 03:10:36 PM PDT 24
Peak memory 248980 kb
Host smart-34a4f5d3-704c-403c-8560-b8ef85c373d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096200299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all
.2096200299
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.4133922949
Short name T288
Test name
Test status
Simulation time 72146645809 ps
CPU time 702.07 seconds
Started Jun 02 03:08:08 PM PDT 24
Finished Jun 02 03:19:50 PM PDT 24
Peak memory 335224 kb
Host smart-b77d5df6-4444-44b5-af85-f6abd8046610
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133922949 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.4133922949
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.741848617
Short name T936
Test name
Test status
Simulation time 4707112846 ps
CPU time 31.81 seconds
Started Jun 02 03:08:08 PM PDT 24
Finished Jun 02 03:08:40 PM PDT 24
Peak memory 243768 kb
Host smart-b03da6da-162c-4d7b-8282-b21e2da320df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741848617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.741848617
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.3008343558
Short name T439
Test name
Test status
Simulation time 2782397500 ps
CPU time 5.78 seconds
Started Jun 02 03:11:00 PM PDT 24
Finished Jun 02 03:11:07 PM PDT 24
Peak memory 242436 kb
Host smart-0532035b-6b3b-4c6c-8ada-55fe0bdcf5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008343558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.3008343558
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.2069749889
Short name T1123
Test name
Test status
Simulation time 377634035 ps
CPU time 8.72 seconds
Started Jun 02 03:11:05 PM PDT 24
Finished Jun 02 03:11:14 PM PDT 24
Peak memory 242540 kb
Host smart-1341f0f4-d4e4-4b65-9a3d-1a464f223ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069749889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.2069749889
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.1524253203
Short name T196
Test name
Test status
Simulation time 515141885 ps
CPU time 4.52 seconds
Started Jun 02 03:11:07 PM PDT 24
Finished Jun 02 03:11:12 PM PDT 24
Peak memory 242364 kb
Host smart-42baa30a-9828-4420-b040-609749df189f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524253203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.1524253203
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.3937709374
Short name T526
Test name
Test status
Simulation time 451214577 ps
CPU time 12.26 seconds
Started Jun 02 03:11:06 PM PDT 24
Finished Jun 02 03:11:18 PM PDT 24
Peak memory 242188 kb
Host smart-3da5e481-30f3-448b-b4fd-ca6e6a3f79c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937709374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.3937709374
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.1435789825
Short name T84
Test name
Test status
Simulation time 386872773 ps
CPU time 4.55 seconds
Started Jun 02 03:11:08 PM PDT 24
Finished Jun 02 03:11:13 PM PDT 24
Peak memory 242604 kb
Host smart-c15f3463-4925-46b2-8ef9-cb4c762d8b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435789825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.1435789825
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.294585655
Short name T1053
Test name
Test status
Simulation time 300006705 ps
CPU time 4.71 seconds
Started Jun 02 03:11:04 PM PDT 24
Finished Jun 02 03:11:09 PM PDT 24
Peak memory 242368 kb
Host smart-6e2bef43-27d0-4272-a4ce-216143b6a819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294585655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.294585655
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.1800558944
Short name T397
Test name
Test status
Simulation time 247682080 ps
CPU time 4.32 seconds
Started Jun 02 03:11:05 PM PDT 24
Finished Jun 02 03:11:10 PM PDT 24
Peak memory 242368 kb
Host smart-69c0e7bd-656b-420c-adbb-892aa7b2de75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800558944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.1800558944
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.3231860166
Short name T1150
Test name
Test status
Simulation time 2811104587 ps
CPU time 8.32 seconds
Started Jun 02 03:11:08 PM PDT 24
Finished Jun 02 03:11:17 PM PDT 24
Peak memory 242236 kb
Host smart-0a03d0e1-4667-4802-9c68-c369e50b047e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231860166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.3231860166
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.1136648391
Short name T722
Test name
Test status
Simulation time 110985638 ps
CPU time 3.91 seconds
Started Jun 02 03:11:05 PM PDT 24
Finished Jun 02 03:11:09 PM PDT 24
Peak memory 242400 kb
Host smart-debd1ea8-9983-46bd-b5bb-81cb970fe8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136648391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.1136648391
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.2980723980
Short name T1078
Test name
Test status
Simulation time 234678315 ps
CPU time 11.43 seconds
Started Jun 02 03:11:04 PM PDT 24
Finished Jun 02 03:11:16 PM PDT 24
Peak memory 242468 kb
Host smart-9ad3ced0-6cee-4a32-81d0-61559c09edf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980723980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.2980723980
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.72548267
Short name T409
Test name
Test status
Simulation time 132345368 ps
CPU time 4.05 seconds
Started Jun 02 03:11:03 PM PDT 24
Finished Jun 02 03:11:07 PM PDT 24
Peak memory 242728 kb
Host smart-f35472e6-8108-4471-b7ec-01a1f6380d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72548267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.72548267
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.4054611723
Short name T183
Test name
Test status
Simulation time 861248358 ps
CPU time 6.22 seconds
Started Jun 02 03:11:08 PM PDT 24
Finished Jun 02 03:11:15 PM PDT 24
Peak memory 242568 kb
Host smart-84030ef6-f376-4166-800a-f90341b5029f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054611723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.4054611723
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.3390671684
Short name T190
Test name
Test status
Simulation time 2382557777 ps
CPU time 6.18 seconds
Started Jun 02 03:11:09 PM PDT 24
Finished Jun 02 03:11:16 PM PDT 24
Peak memory 242344 kb
Host smart-26edf0cb-f30c-49db-a10b-a6d42c5a2f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390671684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.3390671684
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.685268565
Short name T143
Test name
Test status
Simulation time 1377594594 ps
CPU time 11.14 seconds
Started Jun 02 03:11:04 PM PDT 24
Finished Jun 02 03:11:16 PM PDT 24
Peak memory 242588 kb
Host smart-93ee7c4a-945e-484c-98a3-72f16ea21a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685268565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.685268565
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.959449932
Short name T1139
Test name
Test status
Simulation time 204208828 ps
CPU time 4.34 seconds
Started Jun 02 03:11:10 PM PDT 24
Finished Jun 02 03:11:15 PM PDT 24
Peak memory 242372 kb
Host smart-b7a8275d-d7d0-4d86-86d2-0d756a638cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959449932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.959449932
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.3928190690
Short name T182
Test name
Test status
Simulation time 133433775 ps
CPU time 3.29 seconds
Started Jun 02 03:11:11 PM PDT 24
Finished Jun 02 03:11:15 PM PDT 24
Peak memory 242736 kb
Host smart-4743a139-4342-41ee-9bcd-b4570ea28c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928190690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.3928190690
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.2102254533
Short name T819
Test name
Test status
Simulation time 481623448 ps
CPU time 3.77 seconds
Started Jun 02 03:11:09 PM PDT 24
Finished Jun 02 03:11:13 PM PDT 24
Peak memory 242584 kb
Host smart-cc426daf-7ddc-4d59-8f4c-a4d4b61a59d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102254533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.2102254533
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.3550018458
Short name T498
Test name
Test status
Simulation time 156233007 ps
CPU time 3.42 seconds
Started Jun 02 03:11:10 PM PDT 24
Finished Jun 02 03:11:14 PM PDT 24
Peak memory 242344 kb
Host smart-bf4dd9a7-bd37-4bdb-ac5f-1e542444e12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550018458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.3550018458
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.2755253652
Short name T576
Test name
Test status
Simulation time 1026795367 ps
CPU time 8.04 seconds
Started Jun 02 03:11:11 PM PDT 24
Finished Jun 02 03:11:20 PM PDT 24
Peak memory 242204 kb
Host smart-b42e447f-8b08-4298-803e-cd550994dbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755253652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.2755253652
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.3107898165
Short name T542
Test name
Test status
Simulation time 268413802 ps
CPU time 2.17 seconds
Started Jun 02 03:08:08 PM PDT 24
Finished Jun 02 03:08:11 PM PDT 24
Peak memory 240680 kb
Host smart-c3d6f93b-9d31-4ec2-96c9-c45f5066d1a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107898165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.3107898165
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.2736461569
Short name T856
Test name
Test status
Simulation time 7519096116 ps
CPU time 40 seconds
Started Jun 02 03:08:11 PM PDT 24
Finished Jun 02 03:08:51 PM PDT 24
Peak memory 242552 kb
Host smart-4f5ab341-31cf-459b-aab3-3f45f9b136b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736461569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.2736461569
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.1075562730
Short name T6
Test name
Test status
Simulation time 688085233 ps
CPU time 18.8 seconds
Started Jun 02 03:08:09 PM PDT 24
Finished Jun 02 03:08:28 PM PDT 24
Peak memory 242476 kb
Host smart-5fc8bcce-de36-455e-98ea-4a07c4c660c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075562730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.1075562730
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.3777942582
Short name T971
Test name
Test status
Simulation time 1112160573 ps
CPU time 22.87 seconds
Started Jun 02 03:08:07 PM PDT 24
Finished Jun 02 03:08:30 PM PDT 24
Peak memory 242580 kb
Host smart-59b9b9b2-1e0c-4d9c-ad85-43f1b68b6615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777942582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.3777942582
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.238123465
Short name T225
Test name
Test status
Simulation time 120790998 ps
CPU time 4.3 seconds
Started Jun 02 03:08:05 PM PDT 24
Finished Jun 02 03:08:10 PM PDT 24
Peak memory 242384 kb
Host smart-a754f562-66dd-4c22-b22a-9637602a927d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238123465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.238123465
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.3280374485
Short name T1124
Test name
Test status
Simulation time 908619513 ps
CPU time 9.68 seconds
Started Jun 02 03:08:14 PM PDT 24
Finished Jun 02 03:08:25 PM PDT 24
Peak memory 242356 kb
Host smart-40d9d180-c065-4e23-b10a-1fc1b2f0d9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280374485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.3280374485
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.1276654158
Short name T415
Test name
Test status
Simulation time 491785502 ps
CPU time 4.54 seconds
Started Jun 02 03:08:08 PM PDT 24
Finished Jun 02 03:08:13 PM PDT 24
Peak memory 242220 kb
Host smart-3afc83fd-69f9-4d3d-bc45-79cbe70479c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276654158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.1276654158
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.2422494910
Short name T517
Test name
Test status
Simulation time 3646704735 ps
CPU time 25.26 seconds
Started Jun 02 03:08:04 PM PDT 24
Finished Jun 02 03:08:30 PM PDT 24
Peak memory 242628 kb
Host smart-30ebb01a-ad7e-484c-84e4-8ff354178b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422494910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.2422494910
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.686639641
Short name T511
Test name
Test status
Simulation time 1402629086 ps
CPU time 22.79 seconds
Started Jun 02 03:08:05 PM PDT 24
Finished Jun 02 03:08:28 PM PDT 24
Peak memory 248852 kb
Host smart-187bb4df-0172-4ec0-95ef-82d6b9c13d4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=686639641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.686639641
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.229242211
Short name T1174
Test name
Test status
Simulation time 135880559 ps
CPU time 4.43 seconds
Started Jun 02 03:08:10 PM PDT 24
Finished Jun 02 03:08:15 PM PDT 24
Peak memory 242564 kb
Host smart-a2b9fbc4-8619-4720-8db5-25be0fefb1b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=229242211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.229242211
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.1184448844
Short name T532
Test name
Test status
Simulation time 784041740 ps
CPU time 9.9 seconds
Started Jun 02 03:08:15 PM PDT 24
Finished Jun 02 03:08:26 PM PDT 24
Peak memory 248792 kb
Host smart-52e69c2e-0ea8-4d90-bd9a-71b7b87242b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184448844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.1184448844
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.4133312807
Short name T1163
Test name
Test status
Simulation time 194887840773 ps
CPU time 284.74 seconds
Started Jun 02 03:08:09 PM PDT 24
Finished Jun 02 03:12:54 PM PDT 24
Peak memory 283684 kb
Host smart-e1dc2135-5a9b-4c7d-99f2-8256b02fc9ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133312807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all
.4133312807
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.1565234550
Short name T620
Test name
Test status
Simulation time 384836032015 ps
CPU time 1084.19 seconds
Started Jun 02 03:08:09 PM PDT 24
Finished Jun 02 03:26:14 PM PDT 24
Peak memory 275836 kb
Host smart-1525edf4-c84f-482e-96a5-9684f5177d09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565234550 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.1565234550
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.687789271
Short name T544
Test name
Test status
Simulation time 3663810135 ps
CPU time 36.6 seconds
Started Jun 02 03:08:09 PM PDT 24
Finished Jun 02 03:08:47 PM PDT 24
Peak memory 242968 kb
Host smart-43cd1470-29d2-4eb1-8c46-d94db3246a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687789271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.687789271
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.3704707669
Short name T1089
Test name
Test status
Simulation time 1649386823 ps
CPU time 4.57 seconds
Started Jun 02 03:11:11 PM PDT 24
Finished Jun 02 03:11:16 PM PDT 24
Peak memory 242336 kb
Host smart-2ec09460-3ce8-4d45-904c-26ac2e25293c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704707669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.3704707669
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.1658704782
Short name T520
Test name
Test status
Simulation time 332040447 ps
CPU time 4.29 seconds
Started Jun 02 03:11:10 PM PDT 24
Finished Jun 02 03:11:15 PM PDT 24
Peak memory 242460 kb
Host smart-4d55fcf0-1253-4c42-9dde-b12a0e2748cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658704782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.1658704782
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.1006960769
Short name T162
Test name
Test status
Simulation time 416342696 ps
CPU time 4.78 seconds
Started Jun 02 03:11:11 PM PDT 24
Finished Jun 02 03:11:17 PM PDT 24
Peak memory 242400 kb
Host smart-b588e6b6-b399-432d-adef-2ef0ab52959d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006960769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.1006960769
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.1991326583
Short name T668
Test name
Test status
Simulation time 1940120122 ps
CPU time 8.12 seconds
Started Jun 02 03:11:14 PM PDT 24
Finished Jun 02 03:11:23 PM PDT 24
Peak memory 242200 kb
Host smart-bcb64396-eefe-4024-b563-96f6e565a9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991326583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.1991326583
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.3376779145
Short name T50
Test name
Test status
Simulation time 191619062 ps
CPU time 4.37 seconds
Started Jun 02 03:11:10 PM PDT 24
Finished Jun 02 03:11:15 PM PDT 24
Peak memory 242452 kb
Host smart-c9fc2880-d3d9-4d2f-94ae-fae4fd818975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376779145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.3376779145
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.3423414004
Short name T1038
Test name
Test status
Simulation time 3102123732 ps
CPU time 7.7 seconds
Started Jun 02 03:11:10 PM PDT 24
Finished Jun 02 03:11:19 PM PDT 24
Peak memory 242280 kb
Host smart-3a2fc580-72ce-489d-ab0f-78ebb8af343f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423414004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.3423414004
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.866863812
Short name T533
Test name
Test status
Simulation time 241939070 ps
CPU time 4.68 seconds
Started Jun 02 03:11:12 PM PDT 24
Finished Jun 02 03:11:17 PM PDT 24
Peak memory 242500 kb
Host smart-e2d25806-1c13-43d5-b0a7-3f2f6b54c655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866863812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.866863812
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.3148313119
Short name T873
Test name
Test status
Simulation time 299786767 ps
CPU time 8.43 seconds
Started Jun 02 03:11:12 PM PDT 24
Finished Jun 02 03:11:21 PM PDT 24
Peak memory 242600 kb
Host smart-72b6e8fa-a21d-418e-b1a5-986c9e95917c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148313119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.3148313119
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.456018774
Short name T881
Test name
Test status
Simulation time 584177020 ps
CPU time 6.13 seconds
Started Jun 02 03:11:17 PM PDT 24
Finished Jun 02 03:11:23 PM PDT 24
Peak memory 242668 kb
Host smart-c1d5665d-58f1-47af-b3ff-2f78e27eea35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456018774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.456018774
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.4113016421
Short name T1164
Test name
Test status
Simulation time 608088830 ps
CPU time 9.45 seconds
Started Jun 02 03:11:16 PM PDT 24
Finished Jun 02 03:11:26 PM PDT 24
Peak memory 242276 kb
Host smart-14ea26ca-2dbb-4b69-beb8-d9e290e4464f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113016421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.4113016421
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.1932082753
Short name T169
Test name
Test status
Simulation time 211626747 ps
CPU time 3.79 seconds
Started Jun 02 03:11:18 PM PDT 24
Finished Jun 02 03:11:22 PM PDT 24
Peak memory 242280 kb
Host smart-e1894b8b-3592-4b1b-8090-fab3905e237a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932082753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.1932082753
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.3084538712
Short name T349
Test name
Test status
Simulation time 1104987948 ps
CPU time 17.39 seconds
Started Jun 02 03:11:16 PM PDT 24
Finished Jun 02 03:11:34 PM PDT 24
Peak memory 242208 kb
Host smart-3bbd35a2-e024-477d-bef5-54a82bd583c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084538712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.3084538712
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.2243484452
Short name T911
Test name
Test status
Simulation time 1437216463 ps
CPU time 4.61 seconds
Started Jun 02 03:11:15 PM PDT 24
Finished Jun 02 03:11:20 PM PDT 24
Peak memory 242388 kb
Host smart-47140c47-3ea7-46ad-bad5-2b528b80c002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243484452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.2243484452
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.3170935734
Short name T771
Test name
Test status
Simulation time 243228036 ps
CPU time 5.76 seconds
Started Jun 02 03:11:16 PM PDT 24
Finished Jun 02 03:11:22 PM PDT 24
Peak memory 242488 kb
Host smart-e459ac4c-b59c-4a31-a8b1-554aabe3c6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170935734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.3170935734
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.2337293585
Short name T181
Test name
Test status
Simulation time 131546665 ps
CPU time 4.16 seconds
Started Jun 02 03:11:20 PM PDT 24
Finished Jun 02 03:11:24 PM PDT 24
Peak memory 242408 kb
Host smart-28309b05-3120-4d96-878b-dfd9cca4cc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337293585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.2337293585
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.1799168985
Short name T1131
Test name
Test status
Simulation time 218545911 ps
CPU time 3.09 seconds
Started Jun 02 03:11:17 PM PDT 24
Finished Jun 02 03:11:21 PM PDT 24
Peak memory 242640 kb
Host smart-2927ffea-361a-4591-b694-4d6804aad484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799168985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.1799168985
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.2311186082
Short name T591
Test name
Test status
Simulation time 218538581 ps
CPU time 11.09 seconds
Started Jun 02 03:11:18 PM PDT 24
Finished Jun 02 03:11:30 PM PDT 24
Peak memory 242384 kb
Host smart-5d1298e9-b584-46b1-bfca-d2da69d2f6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311186082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.2311186082
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.2951857323
Short name T965
Test name
Test status
Simulation time 368030385 ps
CPU time 4.23 seconds
Started Jun 02 03:11:14 PM PDT 24
Finished Jun 02 03:11:19 PM PDT 24
Peak memory 242332 kb
Host smart-4ed949d8-24b4-4b9d-ac91-e328ec8690fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951857323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2951857323
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.346645657
Short name T382
Test name
Test status
Simulation time 322817919 ps
CPU time 8.7 seconds
Started Jun 02 03:11:16 PM PDT 24
Finished Jun 02 03:11:25 PM PDT 24
Peak memory 248168 kb
Host smart-2020150d-ab5b-4c27-9274-b9522544d00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346645657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.346645657
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.4047571912
Short name T637
Test name
Test status
Simulation time 883015376 ps
CPU time 2.71 seconds
Started Jun 02 03:08:11 PM PDT 24
Finished Jun 02 03:08:14 PM PDT 24
Peak memory 240804 kb
Host smart-e97148dd-08dc-412c-81a4-1dbb6b622165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047571912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.4047571912
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.2087526761
Short name T77
Test name
Test status
Simulation time 10891900026 ps
CPU time 21.01 seconds
Started Jun 02 03:08:10 PM PDT 24
Finished Jun 02 03:08:32 PM PDT 24
Peak memory 249024 kb
Host smart-e6980309-62b0-4960-b851-d2d6d62e581d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087526761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.2087526761
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.51408547
Short name T1021
Test name
Test status
Simulation time 433923142 ps
CPU time 15.14 seconds
Started Jun 02 03:08:12 PM PDT 24
Finished Jun 02 03:08:28 PM PDT 24
Peak memory 242244 kb
Host smart-cc840968-c993-4fe3-8a81-f67a89baceea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51408547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.51408547
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.223465868
Short name T912
Test name
Test status
Simulation time 1000517646 ps
CPU time 24.59 seconds
Started Jun 02 03:08:19 PM PDT 24
Finished Jun 02 03:08:44 PM PDT 24
Peak memory 248908 kb
Host smart-7017852a-0ce5-4b03-8580-cdd47e2a6492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223465868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.223465868
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.2401356271
Short name T39
Test name
Test status
Simulation time 191049440 ps
CPU time 4.56 seconds
Started Jun 02 03:08:09 PM PDT 24
Finished Jun 02 03:08:15 PM PDT 24
Peak memory 242272 kb
Host smart-2ae90479-084b-4b3c-b8cb-4c4110f5bd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401356271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.2401356271
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.1915293601
Short name T429
Test name
Test status
Simulation time 348694809 ps
CPU time 7.15 seconds
Started Jun 02 03:08:09 PM PDT 24
Finished Jun 02 03:08:17 PM PDT 24
Peak memory 242256 kb
Host smart-f7c0f330-903d-41ce-9066-2d98e9d2b1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915293601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.1915293601
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.1944328029
Short name T944
Test name
Test status
Simulation time 1274596660 ps
CPU time 19.91 seconds
Started Jun 02 03:08:08 PM PDT 24
Finished Jun 02 03:08:29 PM PDT 24
Peak memory 242380 kb
Host smart-39f5074d-f554-4341-96a0-b8901044c52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944328029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.1944328029
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.1406537803
Short name T899
Test name
Test status
Simulation time 13563643465 ps
CPU time 33.69 seconds
Started Jun 02 03:08:13 PM PDT 24
Finished Jun 02 03:08:47 PM PDT 24
Peak memory 242296 kb
Host smart-c0d24f0c-0f55-4e8c-bc90-5a95be4a7ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406537803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.1406537803
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.3935326914
Short name T861
Test name
Test status
Simulation time 1729482070 ps
CPU time 17.92 seconds
Started Jun 02 03:08:08 PM PDT 24
Finished Jun 02 03:08:27 PM PDT 24
Peak memory 242532 kb
Host smart-d6f7887f-ec4f-4e7f-8100-3a0c129b96a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3935326914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.3935326914
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.2182923343
Short name T371
Test name
Test status
Simulation time 382661113 ps
CPU time 7.3 seconds
Started Jun 02 03:08:09 PM PDT 24
Finished Jun 02 03:08:17 PM PDT 24
Peak memory 242276 kb
Host smart-5d108dd7-2c7b-4f32-92c2-09b3033d23c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2182923343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.2182923343
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.3801363494
Short name T106
Test name
Test status
Simulation time 299875728 ps
CPU time 5.02 seconds
Started Jun 02 03:08:08 PM PDT 24
Finished Jun 02 03:08:14 PM PDT 24
Peak memory 242272 kb
Host smart-819e01d6-9432-4506-bba3-ddcb10e69579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801363494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.3801363494
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.591575067
Short name T18
Test name
Test status
Simulation time 323980295288 ps
CPU time 984.44 seconds
Started Jun 02 03:08:11 PM PDT 24
Finished Jun 02 03:24:36 PM PDT 24
Peak memory 313368 kb
Host smart-ea3afeb8-9047-4bec-ab2d-a77a3711678c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591575067 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.591575067
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.3030006862
Short name T570
Test name
Test status
Simulation time 372567667 ps
CPU time 11.8 seconds
Started Jun 02 03:08:08 PM PDT 24
Finished Jun 02 03:08:21 PM PDT 24
Peak memory 242132 kb
Host smart-bd988eb9-87ce-4546-8e85-af0f22ae9667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030006862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.3030006862
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.3856772284
Short name T463
Test name
Test status
Simulation time 135920513 ps
CPU time 3.99 seconds
Started Jun 02 03:11:20 PM PDT 24
Finished Jun 02 03:11:25 PM PDT 24
Peak memory 242632 kb
Host smart-54874e58-00a9-4324-92c5-a99bbd0f5586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856772284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.3856772284
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.583934385
Short name T1176
Test name
Test status
Simulation time 653757586 ps
CPU time 8.1 seconds
Started Jun 02 03:11:17 PM PDT 24
Finished Jun 02 03:11:25 PM PDT 24
Peak memory 242572 kb
Host smart-0637784f-ccd5-4af1-9f75-4087eaff447a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583934385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.583934385
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.3534382760
Short name T83
Test name
Test status
Simulation time 376766964 ps
CPU time 3.25 seconds
Started Jun 02 03:11:18 PM PDT 24
Finished Jun 02 03:11:22 PM PDT 24
Peak memory 242560 kb
Host smart-c45701a4-2e3f-461b-92d6-1a2c41824573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534382760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.3534382760
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.2732214224
Short name T957
Test name
Test status
Simulation time 223131788 ps
CPU time 3.36 seconds
Started Jun 02 03:11:20 PM PDT 24
Finished Jun 02 03:11:24 PM PDT 24
Peak memory 242620 kb
Host smart-3a4ab819-a01c-4734-9d4d-c7ca96b3e1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732214224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.2732214224
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.2711695497
Short name T1144
Test name
Test status
Simulation time 466650038 ps
CPU time 7.06 seconds
Started Jun 02 03:11:17 PM PDT 24
Finished Jun 02 03:11:24 PM PDT 24
Peak memory 242400 kb
Host smart-f6531038-9ec4-4f04-bf09-997f8cc4b434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711695497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.2711695497
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.4238623554
Short name T427
Test name
Test status
Simulation time 1765422763 ps
CPU time 4.27 seconds
Started Jun 02 03:11:20 PM PDT 24
Finished Jun 02 03:11:25 PM PDT 24
Peak memory 242380 kb
Host smart-1fb3c99a-64a1-4f40-bb6e-ec49e55e630a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238623554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.4238623554
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.2979015415
Short name T135
Test name
Test status
Simulation time 1259660982 ps
CPU time 21.63 seconds
Started Jun 02 03:11:16 PM PDT 24
Finished Jun 02 03:11:38 PM PDT 24
Peak memory 242184 kb
Host smart-dad6785f-5c44-4652-b19b-db58cf61b5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979015415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.2979015415
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.567788651
Short name T1116
Test name
Test status
Simulation time 121913622 ps
CPU time 3.64 seconds
Started Jun 02 03:11:15 PM PDT 24
Finished Jun 02 03:11:19 PM PDT 24
Peak memory 242616 kb
Host smart-2ae82c8d-daca-47af-b611-f950dd2b5a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567788651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.567788651
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.1225577266
Short name T261
Test name
Test status
Simulation time 412901147 ps
CPU time 12.51 seconds
Started Jun 02 03:11:20 PM PDT 24
Finished Jun 02 03:11:33 PM PDT 24
Peak memory 242396 kb
Host smart-8e3250ee-3c8d-4460-adc1-4a34836572ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225577266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.1225577266
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.4187921348
Short name T1153
Test name
Test status
Simulation time 233174157 ps
CPU time 4.77 seconds
Started Jun 02 03:11:20 PM PDT 24
Finished Jun 02 03:11:25 PM PDT 24
Peak memory 242312 kb
Host smart-b591aba6-a9b8-42fa-b8a0-78cdb95ff495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187921348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.4187921348
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.3888126016
Short name T381
Test name
Test status
Simulation time 5883138734 ps
CPU time 10.8 seconds
Started Jun 02 03:11:19 PM PDT 24
Finished Jun 02 03:11:31 PM PDT 24
Peak memory 242684 kb
Host smart-1657ab11-d978-4336-a2a1-f20e87f4a1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888126016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.3888126016
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.1196353533
Short name T466
Test name
Test status
Simulation time 1698591390 ps
CPU time 5.69 seconds
Started Jun 02 03:11:20 PM PDT 24
Finished Jun 02 03:11:26 PM PDT 24
Peak memory 242408 kb
Host smart-1c8cb9fc-e7ca-4e4e-b565-778a39069962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196353533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.1196353533
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.1580494321
Short name T352
Test name
Test status
Simulation time 195699283 ps
CPU time 7.89 seconds
Started Jun 02 03:11:19 PM PDT 24
Finished Jun 02 03:11:28 PM PDT 24
Peak memory 242292 kb
Host smart-30e7c656-188d-428e-bd2e-8b072b61ef62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580494321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.1580494321
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.734643246
Short name T1094
Test name
Test status
Simulation time 116909034 ps
CPU time 3.79 seconds
Started Jun 02 03:11:20 PM PDT 24
Finished Jun 02 03:11:24 PM PDT 24
Peak memory 242400 kb
Host smart-9e39939f-c61b-494a-8d77-5a7c57662849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734643246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.734643246
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.1699183106
Short name T314
Test name
Test status
Simulation time 406372485 ps
CPU time 12.28 seconds
Started Jun 02 03:11:20 PM PDT 24
Finished Jun 02 03:11:33 PM PDT 24
Peak memory 242628 kb
Host smart-e6beef23-3912-4ac8-802d-96493183d9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699183106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.1699183106
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.4279835912
Short name T744
Test name
Test status
Simulation time 479897554 ps
CPU time 4.57 seconds
Started Jun 02 03:11:19 PM PDT 24
Finished Jun 02 03:11:24 PM PDT 24
Peak memory 242700 kb
Host smart-efb31ba1-aa43-40ac-b9fd-e28cd6b4aa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279835912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.4279835912
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.2087913030
Short name T779
Test name
Test status
Simulation time 4663833373 ps
CPU time 8.6 seconds
Started Jun 02 03:11:21 PM PDT 24
Finished Jun 02 03:11:31 PM PDT 24
Peak memory 242364 kb
Host smart-4eec72da-e80d-482e-970e-620a94ae6785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087913030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.2087913030
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.2833977221
Short name T773
Test name
Test status
Simulation time 121131660 ps
CPU time 3.35 seconds
Started Jun 02 03:11:21 PM PDT 24
Finished Jun 02 03:11:25 PM PDT 24
Peak memory 242368 kb
Host smart-5094f82b-e4fe-4e83-b579-b5046660231c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833977221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.2833977221
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.809895387
Short name T496
Test name
Test status
Simulation time 222998334 ps
CPU time 6.08 seconds
Started Jun 02 03:11:21 PM PDT 24
Finished Jun 02 03:11:28 PM PDT 24
Peak memory 242512 kb
Host smart-6d794214-e631-4215-bbc9-98f008c22402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809895387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.809895387
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.905145374
Short name T693
Test name
Test status
Simulation time 911577463 ps
CPU time 2.9 seconds
Started Jun 02 03:08:16 PM PDT 24
Finished Jun 02 03:08:20 PM PDT 24
Peak memory 240920 kb
Host smart-bbdf8a78-c5a8-423b-a4d7-cc9c926dd592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905145374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.905145374
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.3828089989
Short name T546
Test name
Test status
Simulation time 2586283498 ps
CPU time 25.73 seconds
Started Jun 02 03:08:09 PM PDT 24
Finished Jun 02 03:08:35 PM PDT 24
Peak memory 243528 kb
Host smart-9c6c0265-371d-4054-a790-ad4d6dd4e7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828089989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.3828089989
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.2756237743
Short name T949
Test name
Test status
Simulation time 4460793702 ps
CPU time 37.83 seconds
Started Jun 02 03:08:14 PM PDT 24
Finished Jun 02 03:08:53 PM PDT 24
Peak memory 248564 kb
Host smart-ff0d20a6-7418-41ea-8418-1aa5e105209c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756237743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.2756237743
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.407884163
Short name T176
Test name
Test status
Simulation time 1740325945 ps
CPU time 14.71 seconds
Started Jun 02 03:08:09 PM PDT 24
Finished Jun 02 03:08:25 PM PDT 24
Peak memory 242312 kb
Host smart-72affa18-8d97-4006-820d-4749c23254d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407884163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.407884163
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.156507827
Short name T111
Test name
Test status
Simulation time 2302788344 ps
CPU time 7.92 seconds
Started Jun 02 03:08:13 PM PDT 24
Finished Jun 02 03:08:21 PM PDT 24
Peak memory 242676 kb
Host smart-77131a85-f820-4969-bd04-6ec67ff2c7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156507827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.156507827
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.1574289828
Short name T154
Test name
Test status
Simulation time 800407681 ps
CPU time 23.11 seconds
Started Jun 02 03:08:10 PM PDT 24
Finished Jun 02 03:08:34 PM PDT 24
Peak memory 242676 kb
Host smart-e445272f-f419-4b19-8e28-60723afdcecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574289828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.1574289828
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.1923580033
Short name T1068
Test name
Test status
Simulation time 1381006508 ps
CPU time 24.01 seconds
Started Jun 02 03:08:15 PM PDT 24
Finished Jun 02 03:08:41 PM PDT 24
Peak memory 242216 kb
Host smart-868b7a53-2e15-49fa-ba3b-d18d1d256560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923580033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.1923580033
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.1093700197
Short name T1108
Test name
Test status
Simulation time 380469699 ps
CPU time 10.45 seconds
Started Jun 02 03:08:12 PM PDT 24
Finished Jun 02 03:08:23 PM PDT 24
Peak memory 242560 kb
Host smart-b85359a6-9d2f-46c3-82d6-7caa9951c74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093700197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.1093700197
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.1664854320
Short name T772
Test name
Test status
Simulation time 2274948011 ps
CPU time 17.35 seconds
Started Jun 02 03:08:12 PM PDT 24
Finished Jun 02 03:08:30 PM PDT 24
Peak memory 242304 kb
Host smart-d1e1785d-b049-48d0-ba02-0be6c5395d45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1664854320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.1664854320
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.2082236404
Short name T374
Test name
Test status
Simulation time 861823734 ps
CPU time 9.76 seconds
Started Jun 02 03:08:14 PM PDT 24
Finished Jun 02 03:08:25 PM PDT 24
Peak memory 242276 kb
Host smart-100ed730-24f0-4fa8-bbe2-87e91717bfcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2082236404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.2082236404
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.2508345086
Short name T449
Test name
Test status
Simulation time 1180872794 ps
CPU time 15.34 seconds
Started Jun 02 03:08:13 PM PDT 24
Finished Jun 02 03:08:29 PM PDT 24
Peak memory 242196 kb
Host smart-0749ccc9-4a96-4660-bd27-7f03e2eff81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508345086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.2508345086
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.651626379
Short name T992
Test name
Test status
Simulation time 9747138421 ps
CPU time 222.34 seconds
Started Jun 02 03:08:16 PM PDT 24
Finished Jun 02 03:11:59 PM PDT 24
Peak memory 275684 kb
Host smart-8166a492-d518-4244-8f66-33e9b5295b2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651626379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.
651626379
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.1767711591
Short name T756
Test name
Test status
Simulation time 2280804190 ps
CPU time 15.59 seconds
Started Jun 02 03:08:08 PM PDT 24
Finished Jun 02 03:08:24 PM PDT 24
Peak memory 242532 kb
Host smart-6301444c-939e-4149-88e4-784f9526d2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767711591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.1767711591
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.110302500
Short name T82
Test name
Test status
Simulation time 2384696578 ps
CPU time 7.7 seconds
Started Jun 02 03:11:21 PM PDT 24
Finished Jun 02 03:11:30 PM PDT 24
Peak memory 242460 kb
Host smart-712ea0e9-6e24-4752-8d09-2654527eb6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110302500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.110302500
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.1334792536
Short name T212
Test name
Test status
Simulation time 342801719 ps
CPU time 11.64 seconds
Started Jun 02 03:11:22 PM PDT 24
Finished Jun 02 03:11:34 PM PDT 24
Peak memory 242400 kb
Host smart-37b58f72-2b6c-4322-a7b9-b00f233b6eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334792536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.1334792536
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.97166983
Short name T164
Test name
Test status
Simulation time 3520955068 ps
CPU time 8.52 seconds
Started Jun 02 03:11:22 PM PDT 24
Finished Jun 02 03:11:31 PM PDT 24
Peak memory 242272 kb
Host smart-c0418a07-9bb1-465a-b360-9c4bf6a52659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97166983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.97166983
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.3888188828
Short name T501
Test name
Test status
Simulation time 153234458 ps
CPU time 3.94 seconds
Started Jun 02 03:11:22 PM PDT 24
Finished Jun 02 03:11:26 PM PDT 24
Peak memory 242284 kb
Host smart-ded3b49c-fbbd-489d-86db-4c62412f737c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888188828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.3888188828
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.1129470883
Short name T816
Test name
Test status
Simulation time 2769775872 ps
CPU time 20.88 seconds
Started Jun 02 03:11:20 PM PDT 24
Finished Jun 02 03:11:42 PM PDT 24
Peak memory 242304 kb
Host smart-c615b5c6-3c04-4ecc-9513-29d3cabd41ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129470883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.1129470883
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.1556556610
Short name T187
Test name
Test status
Simulation time 178747122 ps
CPU time 2.99 seconds
Started Jun 02 03:11:21 PM PDT 24
Finished Jun 02 03:11:25 PM PDT 24
Peak memory 242332 kb
Host smart-f49c9d0b-8c56-470b-bceb-37d0e2a005a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556556610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.1556556610
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.3051115027
Short name T436
Test name
Test status
Simulation time 2368373976 ps
CPU time 8.54 seconds
Started Jun 02 03:11:20 PM PDT 24
Finished Jun 02 03:11:29 PM PDT 24
Peak memory 242584 kb
Host smart-2772dd7c-93ff-48ab-a4f3-db03a18c0efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051115027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.3051115027
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.3338451262
Short name T762
Test name
Test status
Simulation time 683556984 ps
CPU time 5.48 seconds
Started Jun 02 03:11:22 PM PDT 24
Finished Jun 02 03:11:28 PM PDT 24
Peak memory 242668 kb
Host smart-483a18e4-3dff-40ce-9af7-2d739f330c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338451262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.3338451262
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.2868933277
Short name T724
Test name
Test status
Simulation time 800568801 ps
CPU time 6.64 seconds
Started Jun 02 03:11:21 PM PDT 24
Finished Jun 02 03:11:28 PM PDT 24
Peak memory 242592 kb
Host smart-2063282c-2d2c-4586-a3db-543c489c2f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868933277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.2868933277
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.704007549
Short name T1067
Test name
Test status
Simulation time 195278937 ps
CPU time 4.89 seconds
Started Jun 02 03:11:22 PM PDT 24
Finished Jun 02 03:11:28 PM PDT 24
Peak memory 242596 kb
Host smart-4c1c8b8d-2aea-4463-8c21-493b9399d3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704007549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.704007549
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.2284884475
Short name T941
Test name
Test status
Simulation time 1314387428 ps
CPU time 22.7 seconds
Started Jun 02 03:11:20 PM PDT 24
Finished Jun 02 03:11:43 PM PDT 24
Peak memory 242560 kb
Host smart-c75b0621-f583-48e2-aaf7-783140a39576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284884475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.2284884475
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.2103514006
Short name T1171
Test name
Test status
Simulation time 1491046098 ps
CPU time 6.14 seconds
Started Jun 02 03:11:23 PM PDT 24
Finished Jun 02 03:11:29 PM PDT 24
Peak memory 242468 kb
Host smart-c6e12807-1246-4b5a-be8e-44f03996862d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103514006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.2103514006
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.2181151004
Short name T593
Test name
Test status
Simulation time 831390632 ps
CPU time 12.3 seconds
Started Jun 02 03:11:20 PM PDT 24
Finished Jun 02 03:11:33 PM PDT 24
Peak memory 242640 kb
Host smart-0a9700fb-d1a9-4b51-9cf5-1868d1f38d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181151004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.2181151004
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.1733937153
Short name T504
Test name
Test status
Simulation time 165306879 ps
CPU time 4.38 seconds
Started Jun 02 03:11:22 PM PDT 24
Finished Jun 02 03:11:27 PM PDT 24
Peak memory 242328 kb
Host smart-c5e79279-ae70-41c2-9704-575a0a337262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733937153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.1733937153
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.3406218355
Short name T273
Test name
Test status
Simulation time 295905878 ps
CPU time 7.28 seconds
Started Jun 02 03:11:21 PM PDT 24
Finished Jun 02 03:11:29 PM PDT 24
Peak memory 242180 kb
Host smart-45ad58c4-cf9c-4f52-a27c-cf7c8cc34986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406218355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.3406218355
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.4076726205
Short name T1044
Test name
Test status
Simulation time 88633341 ps
CPU time 3.19 seconds
Started Jun 02 03:11:20 PM PDT 24
Finished Jun 02 03:11:24 PM PDT 24
Peak memory 242624 kb
Host smart-dae5aeec-5d03-49a6-a366-1f21c50cc0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076726205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.4076726205
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.1006770467
Short name T900
Test name
Test status
Simulation time 134136260 ps
CPU time 3.64 seconds
Started Jun 02 03:11:21 PM PDT 24
Finished Jun 02 03:11:25 PM PDT 24
Peak memory 242440 kb
Host smart-fba36c71-2f62-4abf-b4e8-77b7b800dc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006770467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.1006770467
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.2635722532
Short name T506
Test name
Test status
Simulation time 342441803 ps
CPU time 4.84 seconds
Started Jun 02 03:11:20 PM PDT 24
Finished Jun 02 03:11:26 PM PDT 24
Peak memory 242436 kb
Host smart-9504e75f-f418-47a4-beeb-5ee5d1e5db77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635722532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.2635722532
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.2598421101
Short name T598
Test name
Test status
Simulation time 416184121 ps
CPU time 7.34 seconds
Started Jun 02 03:11:21 PM PDT 24
Finished Jun 02 03:11:29 PM PDT 24
Peak memory 242180 kb
Host smart-7dda6966-0328-4d20-97ef-acf856729321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598421101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.2598421101
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.3109984451
Short name T1162
Test name
Test status
Simulation time 60083296 ps
CPU time 1.77 seconds
Started Jun 02 03:08:17 PM PDT 24
Finished Jun 02 03:08:20 PM PDT 24
Peak memory 240752 kb
Host smart-8f290e57-7e5b-4d33-b416-59b220c43b26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109984451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.3109984451
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.3829326512
Short name T480
Test name
Test status
Simulation time 423825199 ps
CPU time 11.15 seconds
Started Jun 02 03:08:15 PM PDT 24
Finished Jun 02 03:08:28 PM PDT 24
Peak memory 242368 kb
Host smart-da1e4ee5-f3e5-4f01-9623-dbf511a60aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829326512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.3829326512
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.3401751031
Short name T1193
Test name
Test status
Simulation time 3033347077 ps
CPU time 31.1 seconds
Started Jun 02 03:08:21 PM PDT 24
Finished Jun 02 03:08:52 PM PDT 24
Peak memory 242444 kb
Host smart-92c327c4-bc02-4ace-ad31-ece6e2cc480c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401751031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.3401751031
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.2877935010
Short name T226
Test name
Test status
Simulation time 174769756 ps
CPU time 3.1 seconds
Started Jun 02 03:08:23 PM PDT 24
Finished Jun 02 03:08:27 PM PDT 24
Peak memory 242660 kb
Host smart-27e36759-a301-40ae-be50-928cd0ed227b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877935010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.2877935010
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.449548748
Short name T354
Test name
Test status
Simulation time 7580298269 ps
CPU time 46.41 seconds
Started Jun 02 03:08:21 PM PDT 24
Finished Jun 02 03:09:08 PM PDT 24
Peak memory 244792 kb
Host smart-627189cc-ee40-4784-9474-48a2fa1fe469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449548748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.449548748
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.2395902913
Short name T205
Test name
Test status
Simulation time 1237362354 ps
CPU time 15.59 seconds
Started Jun 02 03:08:17 PM PDT 24
Finished Jun 02 03:08:34 PM PDT 24
Peak memory 242564 kb
Host smart-0c34e256-c847-46fa-941c-58f6f864b68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395902913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.2395902913
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.3031186211
Short name T664
Test name
Test status
Simulation time 118534253 ps
CPU time 5.29 seconds
Started Jun 02 03:08:17 PM PDT 24
Finished Jun 02 03:08:23 PM PDT 24
Peak memory 242100 kb
Host smart-c8ab231e-059c-417f-8f50-87e6166c0fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031186211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.3031186211
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.2118617791
Short name T997
Test name
Test status
Simulation time 1601730675 ps
CPU time 12.25 seconds
Started Jun 02 03:08:15 PM PDT 24
Finished Jun 02 03:08:28 PM PDT 24
Peak memory 242272 kb
Host smart-ec4a5f00-c5a8-43eb-b8cb-fb98b3430180
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2118617791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.2118617791
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.3047099480
Short name T636
Test name
Test status
Simulation time 972069972 ps
CPU time 8.13 seconds
Started Jun 02 03:08:13 PM PDT 24
Finished Jun 02 03:08:22 PM PDT 24
Peak memory 242452 kb
Host smart-6bdfa450-06a3-4765-bbb1-429b2f2c3050
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3047099480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.3047099480
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.1111799234
Short name T407
Test name
Test status
Simulation time 887733695 ps
CPU time 6.17 seconds
Started Jun 02 03:08:16 PM PDT 24
Finished Jun 02 03:08:23 PM PDT 24
Peak memory 242156 kb
Host smart-e33c89d1-c9bc-4543-9042-60af1c13e4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111799234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.1111799234
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.1805694322
Short name T479
Test name
Test status
Simulation time 48949623701 ps
CPU time 171.6 seconds
Started Jun 02 03:08:16 PM PDT 24
Finished Jun 02 03:11:08 PM PDT 24
Peak memory 257200 kb
Host smart-1125b6b5-6304-4f84-b01e-7b9adfe871bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805694322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all
.1805694322
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.2734976103
Short name T343
Test name
Test status
Simulation time 100041449311 ps
CPU time 2332.28 seconds
Started Jun 02 03:08:17 PM PDT 24
Finished Jun 02 03:47:11 PM PDT 24
Peak memory 598364 kb
Host smart-364f1d3e-714a-4511-8f52-eb02856bbd61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734976103 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.2734976103
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.2534555868
Short name T585
Test name
Test status
Simulation time 700676455 ps
CPU time 11.01 seconds
Started Jun 02 03:08:21 PM PDT 24
Finished Jun 02 03:08:32 PM PDT 24
Peak memory 242376 kb
Host smart-6465fd85-606c-41ae-a4f3-a5548e0e8bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534555868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.2534555868
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.4197854719
Short name T833
Test name
Test status
Simulation time 199679348 ps
CPU time 2.95 seconds
Started Jun 02 03:11:21 PM PDT 24
Finished Jun 02 03:11:24 PM PDT 24
Peak memory 242404 kb
Host smart-65c47fe6-eb3d-4bc8-a3a8-acfe196e63ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197854719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.4197854719
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.3305213326
Short name T653
Test name
Test status
Simulation time 267081135 ps
CPU time 9.98 seconds
Started Jun 02 03:11:23 PM PDT 24
Finished Jun 02 03:11:33 PM PDT 24
Peak memory 242156 kb
Host smart-e4e13d9f-c0b7-4a52-9119-f1e35849cf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305213326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.3305213326
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.1438540872
Short name T581
Test name
Test status
Simulation time 443714195 ps
CPU time 3.58 seconds
Started Jun 02 03:11:21 PM PDT 24
Finished Jun 02 03:11:25 PM PDT 24
Peak memory 242488 kb
Host smart-af717176-04d1-45ea-b490-56278b2d63f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438540872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.1438540872
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.3171395110
Short name T549
Test name
Test status
Simulation time 782859784 ps
CPU time 20.47 seconds
Started Jun 02 03:11:18 PM PDT 24
Finished Jun 02 03:11:39 PM PDT 24
Peak memory 242592 kb
Host smart-eccd26d4-dea6-4645-9b59-68fae8ca9dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171395110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.3171395110
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.3759381928
Short name T892
Test name
Test status
Simulation time 246833252 ps
CPU time 3.71 seconds
Started Jun 02 03:11:27 PM PDT 24
Finished Jun 02 03:11:31 PM PDT 24
Peak memory 242688 kb
Host smart-8d29a818-3f26-4dab-abde-3f60e7e81238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759381928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.3759381928
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.322750073
Short name T1079
Test name
Test status
Simulation time 198946074 ps
CPU time 9.16 seconds
Started Jun 02 03:11:27 PM PDT 24
Finished Jun 02 03:11:37 PM PDT 24
Peak memory 242304 kb
Host smart-f78310a4-f662-42a6-a61b-9c3c4f5d2b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322750073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.322750073
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.2399373153
Short name T234
Test name
Test status
Simulation time 2193742503 ps
CPU time 5.95 seconds
Started Jun 02 03:11:27 PM PDT 24
Finished Jun 02 03:11:33 PM PDT 24
Peak memory 242428 kb
Host smart-996c8d59-5080-4a84-8612-03160fa3eeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399373153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.2399373153
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.3068199427
Short name T88
Test name
Test status
Simulation time 389785883 ps
CPU time 8.8 seconds
Started Jun 02 03:11:26 PM PDT 24
Finished Jun 02 03:11:35 PM PDT 24
Peak memory 242336 kb
Host smart-bac5037c-8baa-439a-8198-341c58e90ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068199427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.3068199427
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.1832523691
Short name T788
Test name
Test status
Simulation time 1679816977 ps
CPU time 6.35 seconds
Started Jun 02 03:11:23 PM PDT 24
Finished Jun 02 03:11:30 PM PDT 24
Peak memory 242388 kb
Host smart-2e10e31f-9b0e-49ca-bec4-4ab4fcb693a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832523691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.1832523691
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.580917766
Short name T256
Test name
Test status
Simulation time 1601747201 ps
CPU time 5.5 seconds
Started Jun 02 03:11:25 PM PDT 24
Finished Jun 02 03:11:31 PM PDT 24
Peak memory 242180 kb
Host smart-82961948-27a1-4cf3-9eae-261984e9f567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580917766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.580917766
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.3617816521
Short name T1041
Test name
Test status
Simulation time 1580169786 ps
CPU time 4.32 seconds
Started Jun 02 03:11:24 PM PDT 24
Finished Jun 02 03:11:28 PM PDT 24
Peak memory 242396 kb
Host smart-5846cc31-67a3-4cd6-80f2-5cf5d77ab3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617816521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.3617816521
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.421116643
Short name T1047
Test name
Test status
Simulation time 673323379 ps
CPU time 7.71 seconds
Started Jun 02 03:11:24 PM PDT 24
Finished Jun 02 03:11:32 PM PDT 24
Peak memory 242108 kb
Host smart-ef394145-1e37-4252-b42e-bdbd4b716375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421116643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.421116643
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.2626110215
Short name T1070
Test name
Test status
Simulation time 146282790 ps
CPU time 5.66 seconds
Started Jun 02 03:11:26 PM PDT 24
Finished Jun 02 03:11:32 PM PDT 24
Peak memory 242288 kb
Host smart-40245c7b-96cd-48d5-97a8-674145876548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626110215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.2626110215
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.1917307892
Short name T380
Test name
Test status
Simulation time 542019783 ps
CPU time 15.36 seconds
Started Jun 02 03:11:23 PM PDT 24
Finished Jun 02 03:11:39 PM PDT 24
Peak memory 242500 kb
Host smart-94257e03-d267-4786-aaa3-973823ce0c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917307892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.1917307892
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.2405212184
Short name T1135
Test name
Test status
Simulation time 514599508 ps
CPU time 5.54 seconds
Started Jun 02 03:11:24 PM PDT 24
Finished Jun 02 03:11:30 PM PDT 24
Peak memory 242492 kb
Host smart-54fae767-5f56-49d3-b87d-a128a45bf2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405212184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.2405212184
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.2448879566
Short name T126
Test name
Test status
Simulation time 180876764 ps
CPU time 4.95 seconds
Started Jun 02 03:11:25 PM PDT 24
Finished Jun 02 03:11:31 PM PDT 24
Peak memory 242384 kb
Host smart-ad3c0668-6d4e-4bb4-96f8-138748e012b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448879566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.2448879566
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.3318876250
Short name T923
Test name
Test status
Simulation time 1629084051 ps
CPU time 5.77 seconds
Started Jun 02 03:11:28 PM PDT 24
Finished Jun 02 03:11:34 PM PDT 24
Peak memory 242364 kb
Host smart-016883b7-5068-49f0-a369-a3da49ae9d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318876250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.3318876250
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.3113030662
Short name T868
Test name
Test status
Simulation time 1867089827 ps
CPU time 6.87 seconds
Started Jun 02 03:11:24 PM PDT 24
Finished Jun 02 03:11:31 PM PDT 24
Peak memory 242556 kb
Host smart-49738080-424e-4c76-8649-e45489eb83b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113030662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.3113030662
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.2997025673
Short name T539
Test name
Test status
Simulation time 380900128 ps
CPU time 4.22 seconds
Started Jun 02 03:11:30 PM PDT 24
Finished Jun 02 03:11:34 PM PDT 24
Peak memory 242424 kb
Host smart-e2487a76-8eb2-4a8b-8078-7d42d5a69058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997025673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.2997025673
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.485169202
Short name T842
Test name
Test status
Simulation time 1757336278 ps
CPU time 5.22 seconds
Started Jun 02 03:11:33 PM PDT 24
Finished Jun 02 03:11:38 PM PDT 24
Peak memory 242572 kb
Host smart-126a8dc1-45c9-4a1a-8edb-215ec14915f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485169202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.485169202
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.1973503136
Short name T629
Test name
Test status
Simulation time 57226849 ps
CPU time 1.74 seconds
Started Jun 02 03:08:31 PM PDT 24
Finished Jun 02 03:08:33 PM PDT 24
Peak memory 240864 kb
Host smart-79bf1143-a041-4063-a806-e65daa58d3ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973503136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.1973503136
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.3829613973
Short name T942
Test name
Test status
Simulation time 133715643 ps
CPU time 3.67 seconds
Started Jun 02 03:08:21 PM PDT 24
Finished Jun 02 03:08:26 PM PDT 24
Peak memory 242560 kb
Host smart-560d8b5c-b82c-4dd1-b81a-4d8ee918fbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829613973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.3829613973
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.661849869
Short name T86
Test name
Test status
Simulation time 2431703068 ps
CPU time 15.81 seconds
Started Jun 02 03:08:15 PM PDT 24
Finished Jun 02 03:08:32 PM PDT 24
Peak memory 242376 kb
Host smart-b00cfeef-639b-4e26-aa06-e56a7c0fef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661849869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.661849869
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.1141417725
Short name T1018
Test name
Test status
Simulation time 1996805707 ps
CPU time 18.31 seconds
Started Jun 02 03:08:15 PM PDT 24
Finished Jun 02 03:08:35 PM PDT 24
Peak memory 242572 kb
Host smart-b6b57944-2a4a-4ea4-b2b7-1ee1e12d7604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141417725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.1141417725
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.3130226223
Short name T853
Test name
Test status
Simulation time 171820646 ps
CPU time 4.61 seconds
Started Jun 02 03:08:17 PM PDT 24
Finished Jun 02 03:08:23 PM PDT 24
Peak memory 242400 kb
Host smart-3262e2f8-7086-42da-aafe-a4d7489a7b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130226223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.3130226223
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.1368431251
Short name T216
Test name
Test status
Simulation time 1322322500 ps
CPU time 13.82 seconds
Started Jun 02 03:08:22 PM PDT 24
Finished Jun 02 03:08:36 PM PDT 24
Peak memory 242984 kb
Host smart-b290566d-7802-44f1-80a3-227dec38465d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368431251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.1368431251
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.1673765217
Short name T1031
Test name
Test status
Simulation time 4740309024 ps
CPU time 10.95 seconds
Started Jun 02 03:08:31 PM PDT 24
Finished Jun 02 03:08:43 PM PDT 24
Peak memory 243364 kb
Host smart-a8a8323d-ed5a-4b25-9f41-1878b0b91d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673765217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.1673765217
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.3768831189
Short name T761
Test name
Test status
Simulation time 3890179303 ps
CPU time 6.82 seconds
Started Jun 02 03:08:21 PM PDT 24
Finished Jun 02 03:08:28 PM PDT 24
Peak memory 242280 kb
Host smart-6269dd2a-a0b4-485f-ac1f-7169be7344ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768831189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.3768831189
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.237876284
Short name T835
Test name
Test status
Simulation time 581423064 ps
CPU time 10.71 seconds
Started Jun 02 03:08:14 PM PDT 24
Finished Jun 02 03:08:26 PM PDT 24
Peak memory 248900 kb
Host smart-428f39eb-5dbc-4570-a647-6deb82e2a512
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=237876284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.237876284
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.2523080548
Short name T372
Test name
Test status
Simulation time 251152159 ps
CPU time 7.77 seconds
Started Jun 02 03:08:21 PM PDT 24
Finished Jun 02 03:08:30 PM PDT 24
Peak memory 248828 kb
Host smart-37cee523-130a-4960-ba48-d96c8fdab299
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2523080548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.2523080548
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.1726418401
Short name T452
Test name
Test status
Simulation time 755778641 ps
CPU time 9.17 seconds
Started Jun 02 03:08:14 PM PDT 24
Finished Jun 02 03:08:25 PM PDT 24
Peak memory 242252 kb
Host smart-05022d8d-9484-435b-b055-72da74631a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726418401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.1726418401
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.484314340
Short name T808
Test name
Test status
Simulation time 60049551710 ps
CPU time 291.49 seconds
Started Jun 02 03:08:31 PM PDT 24
Finished Jun 02 03:13:23 PM PDT 24
Peak memory 257100 kb
Host smart-b0877238-7132-4dd1-bcb7-c94cf5f23989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484314340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.
484314340
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.36566094
Short name T718
Test name
Test status
Simulation time 114253772332 ps
CPU time 2073.8 seconds
Started Jun 02 03:08:31 PM PDT 24
Finished Jun 02 03:43:06 PM PDT 24
Peak memory 503380 kb
Host smart-a84700b8-cb87-4105-ac48-caff42e8ded4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36566094 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.36566094
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.984394798
Short name T978
Test name
Test status
Simulation time 579142615 ps
CPU time 11.66 seconds
Started Jun 02 03:08:22 PM PDT 24
Finished Jun 02 03:08:34 PM PDT 24
Peak memory 242252 kb
Host smart-d15dfc95-b0fa-406c-a6a1-fbe1576eaf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984394798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.984394798
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.469324752
Short name T860
Test name
Test status
Simulation time 2411497789 ps
CPU time 5.43 seconds
Started Jun 02 03:11:32 PM PDT 24
Finished Jun 02 03:11:38 PM PDT 24
Peak memory 242476 kb
Host smart-e7ab8426-e937-433a-bc5f-737023221973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469324752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.469324752
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.108930871
Short name T695
Test name
Test status
Simulation time 216461485 ps
CPU time 4.89 seconds
Started Jun 02 03:11:33 PM PDT 24
Finished Jun 02 03:11:38 PM PDT 24
Peak memory 242508 kb
Host smart-79eee77c-1354-4103-982e-05140b565ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108930871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.108930871
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.672481025
Short name T239
Test name
Test status
Simulation time 1565823473 ps
CPU time 5.87 seconds
Started Jun 02 03:11:31 PM PDT 24
Finished Jun 02 03:11:38 PM PDT 24
Peak memory 242512 kb
Host smart-6de81e2f-00c3-462c-aa92-94a236a8ee55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672481025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.672481025
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.3699406505
Short name T640
Test name
Test status
Simulation time 235815891 ps
CPU time 3.63 seconds
Started Jun 02 03:11:34 PM PDT 24
Finished Jun 02 03:11:38 PM PDT 24
Peak memory 242204 kb
Host smart-bf3a60d3-f62c-4b0f-9db0-9af0fca1e7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699406505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.3699406505
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.634055260
Short name T903
Test name
Test status
Simulation time 165686698 ps
CPU time 3.67 seconds
Started Jun 02 03:11:32 PM PDT 24
Finished Jun 02 03:11:36 PM PDT 24
Peak memory 242436 kb
Host smart-34f86e93-7e6e-4d94-ad93-676eada35fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634055260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.634055260
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.1942668372
Short name T301
Test name
Test status
Simulation time 331815352 ps
CPU time 5.22 seconds
Started Jun 02 03:11:33 PM PDT 24
Finished Jun 02 03:11:39 PM PDT 24
Peak memory 242244 kb
Host smart-460c35a5-1bfe-431a-b79d-6db9b7cd9489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942668372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.1942668372
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.3413641813
Short name T114
Test name
Test status
Simulation time 230872658 ps
CPU time 4.62 seconds
Started Jun 02 03:11:37 PM PDT 24
Finished Jun 02 03:11:42 PM PDT 24
Peak memory 242620 kb
Host smart-68d360fc-409d-4fea-bbcd-610bd8fd7246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413641813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.3413641813
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.1140561486
Short name T649
Test name
Test status
Simulation time 777673453 ps
CPU time 8.05 seconds
Started Jun 02 03:11:31 PM PDT 24
Finished Jun 02 03:11:40 PM PDT 24
Peak memory 242212 kb
Host smart-67d73220-86d5-4b4b-8b18-69b2a7472639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140561486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.1140561486
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.2336349928
Short name T726
Test name
Test status
Simulation time 148158409 ps
CPU time 3.71 seconds
Started Jun 02 03:11:31 PM PDT 24
Finished Jun 02 03:11:35 PM PDT 24
Peak memory 242340 kb
Host smart-42aeaaf1-0943-408c-b6db-744c7a2bfe43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336349928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.2336349928
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.1628083618
Short name T865
Test name
Test status
Simulation time 2333489715 ps
CPU time 17.09 seconds
Started Jun 02 03:11:31 PM PDT 24
Finished Jun 02 03:11:49 PM PDT 24
Peak memory 242648 kb
Host smart-52771b5a-13e5-4382-adad-d69e954bd7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628083618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.1628083618
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.4166613526
Short name T49
Test name
Test status
Simulation time 283992150 ps
CPU time 5.07 seconds
Started Jun 02 03:11:33 PM PDT 24
Finished Jun 02 03:11:38 PM PDT 24
Peak memory 242700 kb
Host smart-0658b07f-23c9-4c8f-b00c-13d3d6accf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166613526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.4166613526
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.705074260
Short name T679
Test name
Test status
Simulation time 2553922378 ps
CPU time 5.77 seconds
Started Jun 02 03:11:32 PM PDT 24
Finished Jun 02 03:11:39 PM PDT 24
Peak memory 242592 kb
Host smart-549b12c3-488d-4f53-bc51-15cd94e59ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705074260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.705074260
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.283171590
Short name T599
Test name
Test status
Simulation time 242926831 ps
CPU time 3.74 seconds
Started Jun 02 03:11:32 PM PDT 24
Finished Jun 02 03:11:36 PM PDT 24
Peak memory 242628 kb
Host smart-e523f28d-3ebd-4c7e-a2e7-c50f8210c2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283171590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.283171590
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.218186904
Short name T1082
Test name
Test status
Simulation time 224869704 ps
CPU time 4.22 seconds
Started Jun 02 03:11:37 PM PDT 24
Finished Jun 02 03:11:41 PM PDT 24
Peak memory 242252 kb
Host smart-5bbc0cfd-1248-4ec2-8fae-797c12edec18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218186904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.218186904
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.4192557238
Short name T59
Test name
Test status
Simulation time 313033005 ps
CPU time 4.52 seconds
Started Jun 02 03:11:36 PM PDT 24
Finished Jun 02 03:11:41 PM PDT 24
Peak memory 242464 kb
Host smart-dd12ac22-30e1-44e0-8575-f198f6152453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192557238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.4192557238
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.2820209578
Short name T925
Test name
Test status
Simulation time 234751471 ps
CPU time 6.4 seconds
Started Jun 02 03:11:31 PM PDT 24
Finished Jun 02 03:11:38 PM PDT 24
Peak memory 242152 kb
Host smart-95f7898e-dbce-4452-874a-52d7e6656c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820209578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.2820209578
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.3414788456
Short name T101
Test name
Test status
Simulation time 299445938 ps
CPU time 4.27 seconds
Started Jun 02 03:11:30 PM PDT 24
Finished Jun 02 03:11:35 PM PDT 24
Peak memory 242736 kb
Host smart-d4b00f6f-d6e3-49c8-85c3-267831e163ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414788456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.3414788456
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.3790604614
Short name T262
Test name
Test status
Simulation time 261656686 ps
CPU time 7.26 seconds
Started Jun 02 03:11:33 PM PDT 24
Finished Jun 02 03:11:41 PM PDT 24
Peak memory 242396 kb
Host smart-1b28fdeb-2ea3-44fb-ac13-20987985ec0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790604614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.3790604614
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.3324195725
Short name T523
Test name
Test status
Simulation time 508912670 ps
CPU time 5.41 seconds
Started Jun 02 03:11:29 PM PDT 24
Finished Jun 02 03:11:35 PM PDT 24
Peak memory 242700 kb
Host smart-be04ceb2-3258-4c44-99d8-364c46d2b399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324195725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.3324195725
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.471039180
Short name T889
Test name
Test status
Simulation time 262824030 ps
CPU time 5.67 seconds
Started Jun 02 03:11:35 PM PDT 24
Finished Jun 02 03:11:42 PM PDT 24
Peak memory 242572 kb
Host smart-09f4f1f2-4fd8-4a44-90a6-c3b6511a419e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471039180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.471039180
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.1398201507
Short name T907
Test name
Test status
Simulation time 238822512 ps
CPU time 2.24 seconds
Started Jun 02 03:08:31 PM PDT 24
Finished Jun 02 03:08:34 PM PDT 24
Peak memory 240920 kb
Host smart-780004d8-5e6d-4ecb-ac38-3154cf749161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398201507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.1398201507
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.1991552766
Short name T35
Test name
Test status
Simulation time 8818845852 ps
CPU time 21.4 seconds
Started Jun 02 03:08:31 PM PDT 24
Finished Jun 02 03:08:53 PM PDT 24
Peak memory 248668 kb
Host smart-89b726aa-73e1-4e03-82b3-b992013bc9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991552766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.1991552766
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.1397018434
Short name T355
Test name
Test status
Simulation time 325803408 ps
CPU time 9.71 seconds
Started Jun 02 03:08:21 PM PDT 24
Finished Jun 02 03:08:32 PM PDT 24
Peak memory 242608 kb
Host smart-597f5881-577e-43a8-85bd-c16750da0363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397018434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.1397018434
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.1252665018
Short name T561
Test name
Test status
Simulation time 3345442710 ps
CPU time 18.43 seconds
Started Jun 02 03:08:24 PM PDT 24
Finished Jun 02 03:08:43 PM PDT 24
Peak memory 242300 kb
Host smart-075560f9-9323-4f49-9422-1c791183d2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252665018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.1252665018
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.463852348
Short name T229
Test name
Test status
Simulation time 204037845 ps
CPU time 4.47 seconds
Started Jun 02 03:08:24 PM PDT 24
Finished Jun 02 03:08:29 PM PDT 24
Peak memory 242212 kb
Host smart-1e7dfad6-1e18-41b3-b976-85374c86289f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463852348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.463852348
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.1647018577
Short name T356
Test name
Test status
Simulation time 1715841111 ps
CPU time 6.88 seconds
Started Jun 02 03:08:23 PM PDT 24
Finished Jun 02 03:08:30 PM PDT 24
Peak memory 242300 kb
Host smart-9bbbf3dc-a041-4859-95cd-b55afb5a25d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647018577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.1647018577
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.3147564026
Short name T412
Test name
Test status
Simulation time 1366518399 ps
CPU time 10.69 seconds
Started Jun 02 03:08:24 PM PDT 24
Finished Jun 02 03:08:35 PM PDT 24
Peak memory 242228 kb
Host smart-7ef6ad45-88e8-4a05-bb5c-f87fa18b0a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147564026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.3147564026
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.399446956
Short name T1155
Test name
Test status
Simulation time 377277283 ps
CPU time 9.52 seconds
Started Jun 02 03:08:31 PM PDT 24
Finished Jun 02 03:08:42 PM PDT 24
Peak memory 242248 kb
Host smart-17cb0b60-a905-4436-9148-7b1f653030bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399446956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.399446956
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.3918436559
Short name T625
Test name
Test status
Simulation time 918906938 ps
CPU time 24.39 seconds
Started Jun 02 03:08:21 PM PDT 24
Finished Jun 02 03:08:46 PM PDT 24
Peak memory 248820 kb
Host smart-3481a5f7-9ada-44fe-8ee6-a26a39c870f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3918436559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.3918436559
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.1366580551
Short name T832
Test name
Test status
Simulation time 1888626876 ps
CPU time 6.16 seconds
Started Jun 02 03:08:21 PM PDT 24
Finished Jun 02 03:08:28 PM PDT 24
Peak memory 242196 kb
Host smart-b41f6e55-4763-49fc-8a09-34a0f3927e60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1366580551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.1366580551
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.1719039405
Short name T448
Test name
Test status
Simulation time 332003068 ps
CPU time 4.49 seconds
Started Jun 02 03:08:31 PM PDT 24
Finished Jun 02 03:08:36 PM PDT 24
Peak memory 248876 kb
Host smart-ea52bf91-09bc-4bc3-9848-14ecab0b0a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719039405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.1719039405
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.2581637674
Short name T283
Test name
Test status
Simulation time 216777646571 ps
CPU time 1361 seconds
Started Jun 02 03:08:26 PM PDT 24
Finished Jun 02 03:31:08 PM PDT 24
Peak memory 441028 kb
Host smart-f10acbdf-8c55-438d-939e-228ce59998d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581637674 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.2581637674
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.1969080734
Short name T648
Test name
Test status
Simulation time 13090735645 ps
CPU time 30.89 seconds
Started Jun 02 03:08:25 PM PDT 24
Finished Jun 02 03:08:57 PM PDT 24
Peak memory 242644 kb
Host smart-7116a5fe-ab92-4d1c-87dc-dc596b456404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969080734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.1969080734
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.2424260144
Short name T870
Test name
Test status
Simulation time 1409533985 ps
CPU time 4.76 seconds
Started Jun 02 03:11:36 PM PDT 24
Finished Jun 02 03:11:41 PM PDT 24
Peak memory 242404 kb
Host smart-24ca3a9d-75a0-4809-a27f-72ade0006be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424260144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.2424260144
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.3597440658
Short name T1184
Test name
Test status
Simulation time 458792485 ps
CPU time 4.51 seconds
Started Jun 02 03:11:30 PM PDT 24
Finished Jun 02 03:11:35 PM PDT 24
Peak memory 242244 kb
Host smart-21cf5dd3-3f32-4cc4-a899-bcb0a8ed4921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597440658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.3597440658
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.2955678482
Short name T1034
Test name
Test status
Simulation time 265830020 ps
CPU time 5.11 seconds
Started Jun 02 03:11:31 PM PDT 24
Finished Jun 02 03:11:37 PM PDT 24
Peak memory 242696 kb
Host smart-3ad26a18-afb5-40ca-bb40-67fdc1d602ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955678482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.2955678482
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.3431976977
Short name T743
Test name
Test status
Simulation time 171440435 ps
CPU time 4.96 seconds
Started Jun 02 03:11:35 PM PDT 24
Finished Jun 02 03:11:40 PM PDT 24
Peak memory 242200 kb
Host smart-9b29a15f-be05-4668-9d35-a070c5c018ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431976977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.3431976977
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.3205880444
Short name T1152
Test name
Test status
Simulation time 243231382 ps
CPU time 3.35 seconds
Started Jun 02 03:11:36 PM PDT 24
Finished Jun 02 03:11:40 PM PDT 24
Peak memory 242368 kb
Host smart-77571fdb-eaf0-4066-b14c-b70430ff2c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205880444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.3205880444
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.1192560913
Short name T817
Test name
Test status
Simulation time 1106104964 ps
CPU time 26.39 seconds
Started Jun 02 03:11:38 PM PDT 24
Finished Jun 02 03:12:05 PM PDT 24
Peak memory 242400 kb
Host smart-254deb02-0555-43b9-b4ca-956d845a11fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192560913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.1192560913
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.3824406733
Short name T1092
Test name
Test status
Simulation time 230009549 ps
CPU time 3.92 seconds
Started Jun 02 03:11:33 PM PDT 24
Finished Jun 02 03:11:38 PM PDT 24
Peak memory 242284 kb
Host smart-0efba8be-6b27-4bad-9b1c-a8eeab0c6804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824406733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.3824406733
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.637657132
Short name T534
Test name
Test status
Simulation time 1005256528 ps
CPU time 15.48 seconds
Started Jun 02 03:11:36 PM PDT 24
Finished Jun 02 03:11:52 PM PDT 24
Peak memory 242596 kb
Host smart-ee46b7fc-371d-47a5-a016-27cea7e76741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637657132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.637657132
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.4220292317
Short name T914
Test name
Test status
Simulation time 110346961 ps
CPU time 3.81 seconds
Started Jun 02 03:11:36 PM PDT 24
Finished Jun 02 03:11:40 PM PDT 24
Peak memory 242276 kb
Host smart-bcbbbc99-e9f0-4232-8967-e8586d0de504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220292317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.4220292317
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.2104297299
Short name T698
Test name
Test status
Simulation time 765297387 ps
CPU time 11.15 seconds
Started Jun 02 03:11:37 PM PDT 24
Finished Jun 02 03:11:49 PM PDT 24
Peak memory 242364 kb
Host smart-2c0dbff0-7d33-46f2-9308-5fcc75231cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104297299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.2104297299
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.732408021
Short name T538
Test name
Test status
Simulation time 107192031 ps
CPU time 4.26 seconds
Started Jun 02 03:11:37 PM PDT 24
Finished Jun 02 03:11:41 PM PDT 24
Peak memory 242480 kb
Host smart-f184a7b2-b8e2-4d19-866c-7c95dc29a38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732408021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.732408021
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.1617416792
Short name T433
Test name
Test status
Simulation time 533411592 ps
CPU time 15.83 seconds
Started Jun 02 03:11:37 PM PDT 24
Finished Jun 02 03:11:53 PM PDT 24
Peak memory 242220 kb
Host smart-15796276-c2d7-4e4b-8ae6-3f553aba8b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617416792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.1617416792
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.1651810540
Short name T200
Test name
Test status
Simulation time 315197983 ps
CPU time 3.69 seconds
Started Jun 02 03:11:36 PM PDT 24
Finished Jun 02 03:11:40 PM PDT 24
Peak memory 242648 kb
Host smart-f4ea0554-8c20-4999-8ac3-e90c4285a9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651810540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.1651810540
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.2658085359
Short name T1137
Test name
Test status
Simulation time 167611225 ps
CPU time 3.44 seconds
Started Jun 02 03:11:35 PM PDT 24
Finished Jun 02 03:11:39 PM PDT 24
Peak memory 242260 kb
Host smart-37e14f59-249d-448e-b7ce-cc3f8d62d5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658085359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.2658085359
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.1247191719
Short name T29
Test name
Test status
Simulation time 2131502187 ps
CPU time 5.77 seconds
Started Jun 02 03:11:40 PM PDT 24
Finished Jun 02 03:11:46 PM PDT 24
Peak memory 242584 kb
Host smart-0dff17b5-2852-48a8-88bf-42d1cec5006a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247191719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.1247191719
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.2248937363
Short name T968
Test name
Test status
Simulation time 425506791 ps
CPU time 5.8 seconds
Started Jun 02 03:11:36 PM PDT 24
Finished Jun 02 03:11:43 PM PDT 24
Peak memory 242116 kb
Host smart-c78729b1-a721-45b7-8a6a-3dbf6a3747b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248937363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.2248937363
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.2311046927
Short name T947
Test name
Test status
Simulation time 352569804 ps
CPU time 4.79 seconds
Started Jun 02 03:11:35 PM PDT 24
Finished Jun 02 03:11:40 PM PDT 24
Peak memory 242364 kb
Host smart-c925a0af-8b2d-4460-8afd-9ad10f6a2377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311046927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.2311046927
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.2752726390
Short name T144
Test name
Test status
Simulation time 299806066 ps
CPU time 5.15 seconds
Started Jun 02 03:11:34 PM PDT 24
Finished Jun 02 03:11:40 PM PDT 24
Peak memory 242232 kb
Host smart-87f75e50-95ad-451c-97ff-25a73691444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752726390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.2752726390
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.230974981
Short name T115
Test name
Test status
Simulation time 2543161106 ps
CPU time 7.62 seconds
Started Jun 02 03:11:38 PM PDT 24
Finished Jun 02 03:11:47 PM PDT 24
Peak memory 242392 kb
Host smart-0575c54d-0c8a-41c8-ab5b-46f0238eea81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230974981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.230974981
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.3006148567
Short name T74
Test name
Test status
Simulation time 4681026463 ps
CPU time 10.67 seconds
Started Jun 02 03:11:36 PM PDT 24
Finished Jun 02 03:11:47 PM PDT 24
Peak memory 242624 kb
Host smart-ada075b3-e6db-43a1-bf09-9f2f66ac8a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006148567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.3006148567
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.4048891548
Short name T946
Test name
Test status
Simulation time 590009763 ps
CPU time 2.16 seconds
Started Jun 02 03:08:29 PM PDT 24
Finished Jun 02 03:08:31 PM PDT 24
Peak memory 241200 kb
Host smart-688023eb-3e59-4203-8fbb-1cce06ae4554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048891548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.4048891548
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.3819282324
Short name T81
Test name
Test status
Simulation time 1284807731 ps
CPU time 10.42 seconds
Started Jun 02 03:08:30 PM PDT 24
Finished Jun 02 03:08:41 PM PDT 24
Peak memory 242336 kb
Host smart-03cd9af5-e48a-4739-93ce-28531021cb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819282324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.3819282324
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.611928963
Short name T672
Test name
Test status
Simulation time 873592799 ps
CPU time 12.67 seconds
Started Jun 02 03:08:30 PM PDT 24
Finished Jun 02 03:08:43 PM PDT 24
Peak memory 242260 kb
Host smart-ae2a9937-2cae-4e90-bca6-2bc298b36d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611928963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.611928963
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.3959024083
Short name T384
Test name
Test status
Simulation time 5821255554 ps
CPU time 30.29 seconds
Started Jun 02 03:08:25 PM PDT 24
Finished Jun 02 03:08:55 PM PDT 24
Peak memory 243160 kb
Host smart-f8e49828-90c7-4450-93b9-9483c88a832f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959024083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.3959024083
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.1066191636
Short name T1195
Test name
Test status
Simulation time 3000772318 ps
CPU time 16.84 seconds
Started Jun 02 03:08:32 PM PDT 24
Finished Jun 02 03:08:49 PM PDT 24
Peak memory 244112 kb
Host smart-33d51063-e255-4b22-85b2-9c0786929992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066191636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.1066191636
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.259608028
Short name T87
Test name
Test status
Simulation time 1025572997 ps
CPU time 15.39 seconds
Started Jun 02 03:08:31 PM PDT 24
Finished Jun 02 03:08:47 PM PDT 24
Peak memory 248772 kb
Host smart-68745088-3c75-4884-84fd-208acf42cb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259608028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.259608028
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.316752113
Short name T147
Test name
Test status
Simulation time 2843007127 ps
CPU time 9.1 seconds
Started Jun 02 03:08:27 PM PDT 24
Finished Jun 02 03:08:36 PM PDT 24
Peak memory 242256 kb
Host smart-abfbb558-6931-4c96-880c-8aa70b670a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316752113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.316752113
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.2724364753
Short name T252
Test name
Test status
Simulation time 905331674 ps
CPU time 13.41 seconds
Started Jun 02 03:08:25 PM PDT 24
Finished Jun 02 03:08:39 PM PDT 24
Peak memory 248848 kb
Host smart-cd5e16da-8d31-4808-a241-0c151b2755cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2724364753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.2724364753
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.431086517
Short name T484
Test name
Test status
Simulation time 157386445 ps
CPU time 6.35 seconds
Started Jun 02 03:08:25 PM PDT 24
Finished Jun 02 03:08:32 PM PDT 24
Peak memory 242456 kb
Host smart-fee0ce4c-c966-4fee-8cbc-6bdd52afdcd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=431086517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.431086517
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.2737298667
Short name T622
Test name
Test status
Simulation time 136670715 ps
CPU time 3.19 seconds
Started Jun 02 03:08:30 PM PDT 24
Finished Jun 02 03:08:34 PM PDT 24
Peak memory 242168 kb
Host smart-9cab225b-f7a6-4209-9eb8-c4bd2385f63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737298667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.2737298667
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.3779659724
Short name T740
Test name
Test status
Simulation time 13129251801 ps
CPU time 144.37 seconds
Started Jun 02 03:08:29 PM PDT 24
Finished Jun 02 03:10:53 PM PDT 24
Peak memory 257788 kb
Host smart-78587f90-f111-42b6-9b98-b774e23c7434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779659724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.3779659724
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.1141597214
Short name T350
Test name
Test status
Simulation time 10639773260 ps
CPU time 289.17 seconds
Started Jun 02 03:08:26 PM PDT 24
Finished Jun 02 03:13:16 PM PDT 24
Peak memory 265560 kb
Host smart-dc248400-86f4-4254-a8e1-4a2c9887bdb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141597214 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.1141597214
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.3945193402
Short name T450
Test name
Test status
Simulation time 2651645291 ps
CPU time 16.25 seconds
Started Jun 02 03:08:25 PM PDT 24
Finished Jun 02 03:08:42 PM PDT 24
Peak memory 242312 kb
Host smart-7b2b3f42-b845-4be1-99e2-f1da46a9f950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945193402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.3945193402
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.4054246126
Short name T551
Test name
Test status
Simulation time 513787227 ps
CPU time 6.09 seconds
Started Jun 02 03:11:36 PM PDT 24
Finished Jun 02 03:11:43 PM PDT 24
Peak memory 242348 kb
Host smart-d3f83225-6d37-406d-b570-3314e4e93dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054246126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.4054246126
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.1327607243
Short name T727
Test name
Test status
Simulation time 174028200 ps
CPU time 4.8 seconds
Started Jun 02 03:11:35 PM PDT 24
Finished Jun 02 03:11:40 PM PDT 24
Peak memory 242368 kb
Host smart-29441b6a-d1aa-4d0d-a423-e0afbca70633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327607243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.1327607243
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.2755075617
Short name T948
Test name
Test status
Simulation time 512671919 ps
CPU time 13.61 seconds
Started Jun 02 03:11:37 PM PDT 24
Finished Jun 02 03:11:51 PM PDT 24
Peak memory 242400 kb
Host smart-afaa4dfb-9e25-4ec1-a1ca-cd79bbb55fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755075617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.2755075617
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.587199306
Short name T655
Test name
Test status
Simulation time 2399306636 ps
CPU time 5.62 seconds
Started Jun 02 03:11:37 PM PDT 24
Finished Jun 02 03:11:43 PM PDT 24
Peak memory 242324 kb
Host smart-64300658-c452-4903-be44-2141493f702b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587199306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.587199306
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.1203214783
Short name T218
Test name
Test status
Simulation time 3019615177 ps
CPU time 6.11 seconds
Started Jun 02 03:11:40 PM PDT 24
Finished Jun 02 03:11:47 PM PDT 24
Peak memory 242428 kb
Host smart-b8654882-ddd2-48d1-b41b-cb4047bd16ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203214783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.1203214783
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.2420896780
Short name T1125
Test name
Test status
Simulation time 123604544 ps
CPU time 4.05 seconds
Started Jun 02 03:11:41 PM PDT 24
Finished Jun 02 03:11:46 PM PDT 24
Peak memory 242420 kb
Host smart-121fb570-de67-4ec9-88ab-60341805e25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420896780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.2420896780
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.200038366
Short name T624
Test name
Test status
Simulation time 2071127170 ps
CPU time 6.58 seconds
Started Jun 02 03:11:40 PM PDT 24
Finished Jun 02 03:11:47 PM PDT 24
Peak memory 242176 kb
Host smart-b71a697e-dbce-4860-bc4b-115f6ca227ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200038366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.200038366
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.4170652193
Short name T1008
Test name
Test status
Simulation time 95400028 ps
CPU time 3.46 seconds
Started Jun 02 03:11:44 PM PDT 24
Finished Jun 02 03:11:48 PM PDT 24
Peak memory 242264 kb
Host smart-85f7c120-0644-437e-b1f5-1e127c18ba0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170652193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.4170652193
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.185169818
Short name T841
Test name
Test status
Simulation time 8731771034 ps
CPU time 20.33 seconds
Started Jun 02 03:11:45 PM PDT 24
Finished Jun 02 03:12:05 PM PDT 24
Peak memory 242680 kb
Host smart-408241a1-c944-4446-9211-798e36f393ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185169818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.185169818
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.3086603013
Short name T123
Test name
Test status
Simulation time 199237891 ps
CPU time 6.57 seconds
Started Jun 02 03:11:41 PM PDT 24
Finished Jun 02 03:11:48 PM PDT 24
Peak memory 242852 kb
Host smart-96460fcd-bb19-40b5-9398-1395350b337b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086603013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.3086603013
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.2520135781
Short name T678
Test name
Test status
Simulation time 120093652 ps
CPU time 3.52 seconds
Started Jun 02 03:11:45 PM PDT 24
Finished Jun 02 03:11:49 PM PDT 24
Peak memory 242416 kb
Host smart-717ac7e2-957b-416b-815c-7db8b761c19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520135781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.2520135781
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.716438829
Short name T710
Test name
Test status
Simulation time 12014019846 ps
CPU time 28.27 seconds
Started Jun 02 03:11:40 PM PDT 24
Finished Jun 02 03:12:09 PM PDT 24
Peak memory 242644 kb
Host smart-04e17562-8e3f-4fe6-b813-51a3c5dec0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716438829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.716438829
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.205939999
Short name T1003
Test name
Test status
Simulation time 128567340 ps
CPU time 4.11 seconds
Started Jun 02 03:11:40 PM PDT 24
Finished Jun 02 03:11:45 PM PDT 24
Peak memory 242228 kb
Host smart-0e6f7a63-a055-4fbd-ae5e-4914d3754a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205939999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.205939999
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.2581235951
Short name T454
Test name
Test status
Simulation time 326461289 ps
CPU time 8.33 seconds
Started Jun 02 03:11:40 PM PDT 24
Finished Jun 02 03:11:49 PM PDT 24
Peak memory 242248 kb
Host smart-4bd6107d-571a-47bd-91b7-71563ef70879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581235951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.2581235951
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.3563673572
Short name T929
Test name
Test status
Simulation time 162442791 ps
CPU time 3.52 seconds
Started Jun 02 03:11:43 PM PDT 24
Finished Jun 02 03:11:47 PM PDT 24
Peak memory 242392 kb
Host smart-04a203a0-3fb8-4c47-b73f-274b8a6edb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563673572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.3563673572
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.2655999506
Short name T493
Test name
Test status
Simulation time 362770575 ps
CPU time 7.85 seconds
Started Jun 02 03:11:44 PM PDT 24
Finished Jun 02 03:11:53 PM PDT 24
Peak memory 242544 kb
Host smart-f28ab9fe-71f0-4f48-adb6-2c64d32e23f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655999506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2655999506
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.3088309907
Short name T297
Test name
Test status
Simulation time 153496386 ps
CPU time 3.96 seconds
Started Jun 02 03:11:40 PM PDT 24
Finished Jun 02 03:11:44 PM PDT 24
Peak memory 242408 kb
Host smart-fcb655c6-331e-4c58-8685-6ca897e71a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088309907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.3088309907
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.3866234087
Short name T406
Test name
Test status
Simulation time 735454093 ps
CPU time 18.16 seconds
Started Jun 02 03:11:43 PM PDT 24
Finished Jun 02 03:12:02 PM PDT 24
Peak memory 242580 kb
Host smart-16620442-044c-46c4-a3c0-14d2bffd3631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866234087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.3866234087
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.4255272123
Short name T634
Test name
Test status
Simulation time 508338529 ps
CPU time 9.01 seconds
Started Jun 02 03:07:30 PM PDT 24
Finished Jun 02 03:07:40 PM PDT 24
Peak memory 248924 kb
Host smart-9f6f1fba-c7b1-4665-8a7b-8f5d7c4052e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255272123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.4255272123
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.503430880
Short name T232
Test name
Test status
Simulation time 5676015903 ps
CPU time 51.6 seconds
Started Jun 02 03:07:34 PM PDT 24
Finished Jun 02 03:08:26 PM PDT 24
Peak memory 253828 kb
Host smart-54bf0939-f5e1-4b42-b9bd-20a3c8fd7f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503430880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.503430880
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.3995386951
Short name T543
Test name
Test status
Simulation time 1492218903 ps
CPU time 13.8 seconds
Started Jun 02 03:07:34 PM PDT 24
Finished Jun 02 03:07:49 PM PDT 24
Peak memory 242244 kb
Host smart-de19b7c7-f8d4-440f-ba74-628e5f6d0a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995386951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.3995386951
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.3108556204
Short name T804
Test name
Test status
Simulation time 2319875701 ps
CPU time 19.48 seconds
Started Jun 02 03:07:38 PM PDT 24
Finished Jun 02 03:07:58 PM PDT 24
Peak memory 248920 kb
Host smart-0d32d6d0-6ebd-470c-a37f-b90bf3f23ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108556204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.3108556204
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.3778187677
Short name T93
Test name
Test status
Simulation time 734040625 ps
CPU time 30.32 seconds
Started Jun 02 03:07:35 PM PDT 24
Finished Jun 02 03:08:06 PM PDT 24
Peak memory 242540 kb
Host smart-924b87ec-0a51-42ac-8f4a-ed05f3f9433c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778187677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.3778187677
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.1079347918
Short name T815
Test name
Test status
Simulation time 815682365 ps
CPU time 10.69 seconds
Started Jun 02 03:07:33 PM PDT 24
Finished Jun 02 03:07:45 PM PDT 24
Peak memory 242548 kb
Host smart-d9b84fd3-2b5a-4783-8732-a7738b8a08eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079347918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.1079347918
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.3920167229
Short name T1179
Test name
Test status
Simulation time 1214241803 ps
CPU time 19.21 seconds
Started Jun 02 03:07:32 PM PDT 24
Finished Jun 02 03:07:52 PM PDT 24
Peak memory 242248 kb
Host smart-a000e804-ac1b-47ea-bcab-e38a7484bf2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3920167229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.3920167229
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.946487793
Short name T100
Test name
Test status
Simulation time 466890832 ps
CPU time 8.1 seconds
Started Jun 02 03:07:35 PM PDT 24
Finished Jun 02 03:07:44 PM PDT 24
Peak memory 242244 kb
Host smart-685d7e30-47a2-48fd-8eb8-f8a548971eb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=946487793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.946487793
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.164799447
Short name T524
Test name
Test status
Simulation time 881548891 ps
CPU time 8.12 seconds
Started Jun 02 03:07:27 PM PDT 24
Finished Jun 02 03:07:36 PM PDT 24
Peak memory 242072 kb
Host smart-dc22c05a-b6c9-4e4e-a3e6-6c748ae8b057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164799447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.164799447
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.2056520060
Short name T258
Test name
Test status
Simulation time 10775200235 ps
CPU time 144.49 seconds
Started Jun 02 03:07:36 PM PDT 24
Finished Jun 02 03:10:01 PM PDT 24
Peak memory 265452 kb
Host smart-8745731d-cbd3-4366-8b9f-f0dc8c0a3f16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056520060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.
2056520060
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.2924136618
Short name T729
Test name
Test status
Simulation time 236313553805 ps
CPU time 1323.19 seconds
Started Jun 02 03:07:34 PM PDT 24
Finished Jun 02 03:29:38 PM PDT 24
Peak memory 261792 kb
Host smart-4e142cab-5fc4-4aee-b103-de517d5693cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924136618 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.2924136618
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.2822316229
Short name T207
Test name
Test status
Simulation time 709615658 ps
CPU time 26.83 seconds
Started Jun 02 03:07:35 PM PDT 24
Finished Jun 02 03:08:02 PM PDT 24
Peak memory 242596 kb
Host smart-eeb3181b-77e2-46d9-a28b-06e3913a2cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822316229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.2822316229
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.2941920493
Short name T1132
Test name
Test status
Simulation time 576243872 ps
CPU time 1.66 seconds
Started Jun 02 03:08:33 PM PDT 24
Finished Jun 02 03:08:35 PM PDT 24
Peak memory 240788 kb
Host smart-820bb15f-a9c0-4551-a24a-d3817da4a901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941920493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.2941920493
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.4207395025
Short name T988
Test name
Test status
Simulation time 376999590 ps
CPU time 12.16 seconds
Started Jun 02 03:08:35 PM PDT 24
Finished Jun 02 03:08:48 PM PDT 24
Peak memory 242332 kb
Host smart-fb636bd4-1afd-466d-9d53-0bf564836149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207395025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.4207395025
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.3019952013
Short name T1096
Test name
Test status
Simulation time 535107382 ps
CPU time 14.81 seconds
Started Jun 02 03:08:32 PM PDT 24
Finished Jun 02 03:08:48 PM PDT 24
Peak memory 242276 kb
Host smart-d0c3a76f-372b-4674-8771-6acdf7548977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019952013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.3019952013
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.1827279594
Short name T913
Test name
Test status
Simulation time 1777644807 ps
CPU time 34 seconds
Started Jun 02 03:08:35 PM PDT 24
Finished Jun 02 03:09:10 PM PDT 24
Peak memory 242232 kb
Host smart-187ceade-6135-4026-9005-36f84694cde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827279594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.1827279594
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.603217676
Short name T1033
Test name
Test status
Simulation time 401575569 ps
CPU time 4.28 seconds
Started Jun 02 03:08:25 PM PDT 24
Finished Jun 02 03:08:30 PM PDT 24
Peak memory 242632 kb
Host smart-417b57ef-063d-4133-88cf-27cf14e88b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603217676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.603217676
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.2550256169
Short name T1035
Test name
Test status
Simulation time 923068728 ps
CPU time 19.27 seconds
Started Jun 02 03:08:32 PM PDT 24
Finished Jun 02 03:08:52 PM PDT 24
Peak memory 242320 kb
Host smart-ce4f73d4-b548-4aa4-9feb-2cdae0cd22fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550256169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.2550256169
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.2327658555
Short name T503
Test name
Test status
Simulation time 793183705 ps
CPU time 14.65 seconds
Started Jun 02 03:08:34 PM PDT 24
Finished Jun 02 03:08:49 PM PDT 24
Peak memory 242332 kb
Host smart-6f68d5b3-ff8e-4bac-8ff5-e17044808f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327658555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.2327658555
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.2394565736
Short name T247
Test name
Test status
Simulation time 289074477 ps
CPU time 16.13 seconds
Started Jun 02 03:08:33 PM PDT 24
Finished Jun 02 03:08:49 PM PDT 24
Peak memory 242584 kb
Host smart-315fdffb-84ac-4507-b2b4-eff5a8c9cc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394565736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.2394565736
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.552395729
Short name T998
Test name
Test status
Simulation time 857598897 ps
CPU time 8.23 seconds
Started Jun 02 03:08:25 PM PDT 24
Finished Jun 02 03:08:34 PM PDT 24
Peak memory 242300 kb
Host smart-9a398dee-7e91-491b-988f-b5754c3e83d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552395729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.552395729
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.1011787445
Short name T821
Test name
Test status
Simulation time 152658372 ps
CPU time 4.34 seconds
Started Jun 02 03:08:25 PM PDT 24
Finished Jun 02 03:08:30 PM PDT 24
Peak memory 242456 kb
Host smart-88315863-fbe1-4a4f-804a-1489dfb98adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011787445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.1011787445
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.3614156304
Short name T604
Test name
Test status
Simulation time 31359647110 ps
CPU time 170.77 seconds
Started Jun 02 03:08:33 PM PDT 24
Finished Jun 02 03:11:24 PM PDT 24
Peak memory 257248 kb
Host smart-b012e5b1-90fe-4d82-a06b-40fb2b1e56ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614156304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all
.3614156304
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.3860685077
Short name T838
Test name
Test status
Simulation time 70357204766 ps
CPU time 382.25 seconds
Started Jun 02 03:08:30 PM PDT 24
Finished Jun 02 03:14:53 PM PDT 24
Peak memory 258772 kb
Host smart-675f4e85-f2df-4ee4-beb7-9914a17ed7f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860685077 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.3860685077
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.1541320461
Short name T1020
Test name
Test status
Simulation time 24475833756 ps
CPU time 52.93 seconds
Started Jun 02 03:08:34 PM PDT 24
Finished Jun 02 03:09:28 PM PDT 24
Peak memory 243024 kb
Host smart-6da69556-dadc-4269-95cd-7570b7b51f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541320461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.1541320461
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.2405492344
Short name T826
Test name
Test status
Simulation time 181227246 ps
CPU time 3.86 seconds
Started Jun 02 03:11:44 PM PDT 24
Finished Jun 02 03:11:48 PM PDT 24
Peak memory 242644 kb
Host smart-e6af77d4-dabe-49bb-a963-93765a309efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405492344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.2405492344
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.4248700867
Short name T931
Test name
Test status
Simulation time 409967720 ps
CPU time 4.17 seconds
Started Jun 02 03:11:43 PM PDT 24
Finished Jun 02 03:11:48 PM PDT 24
Peak memory 242408 kb
Host smart-158a27d9-274b-4026-ac28-c5c1bb2718b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248700867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.4248700867
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.4004542175
Short name T954
Test name
Test status
Simulation time 1907415595 ps
CPU time 4.84 seconds
Started Jun 02 03:11:40 PM PDT 24
Finished Jun 02 03:11:46 PM PDT 24
Peak memory 242336 kb
Host smart-6fdf32d2-ca6b-4951-96ff-8cb174ba14eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004542175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.4004542175
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.3600033285
Short name T236
Test name
Test status
Simulation time 393613058 ps
CPU time 3.68 seconds
Started Jun 02 03:11:40 PM PDT 24
Finished Jun 02 03:11:45 PM PDT 24
Peak memory 242808 kb
Host smart-861c722d-c8e0-4fd9-86c9-af034edbfa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600033285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.3600033285
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.3658673719
Short name T863
Test name
Test status
Simulation time 229046342 ps
CPU time 3.13 seconds
Started Jun 02 03:11:40 PM PDT 24
Finished Jun 02 03:11:44 PM PDT 24
Peak memory 242356 kb
Host smart-d04fb79b-0a45-49b4-98f3-8249e2864a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658673719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.3658673719
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.3577452316
Short name T614
Test name
Test status
Simulation time 252457621 ps
CPU time 3.94 seconds
Started Jun 02 03:11:42 PM PDT 24
Finished Jun 02 03:11:47 PM PDT 24
Peak memory 242340 kb
Host smart-04243d99-8075-427e-a3b4-7afc9c04574e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577452316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.3577452316
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.264502196
Short name T612
Test name
Test status
Simulation time 137490719 ps
CPU time 3.93 seconds
Started Jun 02 03:11:42 PM PDT 24
Finished Jun 02 03:11:47 PM PDT 24
Peak memory 242592 kb
Host smart-d3607bb7-ea48-4459-99b0-b040ac4a608a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264502196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.264502196
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.2183618307
Short name T163
Test name
Test status
Simulation time 2651170672 ps
CPU time 7.3 seconds
Started Jun 02 03:11:43 PM PDT 24
Finished Jun 02 03:11:51 PM PDT 24
Peak memory 242404 kb
Host smart-5a53f398-1206-4a4a-85da-9695f14f1bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183618307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.2183618307
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.3795445693
Short name T807
Test name
Test status
Simulation time 160279369 ps
CPU time 4.05 seconds
Started Jun 02 03:11:44 PM PDT 24
Finished Jun 02 03:11:48 PM PDT 24
Peak memory 242656 kb
Host smart-f759a5ae-51e5-4df2-a8ac-1769b17c9a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795445693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.3795445693
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.2449644510
Short name T746
Test name
Test status
Simulation time 95286228 ps
CPU time 1.93 seconds
Started Jun 02 03:08:40 PM PDT 24
Finished Jun 02 03:08:42 PM PDT 24
Peak memory 240892 kb
Host smart-e5767762-f914-4874-990c-19ccf60bf354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449644510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.2449644510
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.1704346699
Short name T928
Test name
Test status
Simulation time 2510124972 ps
CPU time 8.69 seconds
Started Jun 02 03:08:41 PM PDT 24
Finished Jun 02 03:08:51 PM PDT 24
Peak memory 248964 kb
Host smart-0a1a333b-4da2-43a5-990a-7aca3e14a5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704346699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.1704346699
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.3548835816
Short name T601
Test name
Test status
Simulation time 907771780 ps
CPU time 15.52 seconds
Started Jun 02 03:08:40 PM PDT 24
Finished Jun 02 03:08:56 PM PDT 24
Peak memory 242760 kb
Host smart-17e9775b-1850-49ff-b2ed-7c4e18d4ee81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548835816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.3548835816
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.2345119845
Short name T735
Test name
Test status
Simulation time 1638797621 ps
CPU time 34.15 seconds
Started Jun 02 03:08:40 PM PDT 24
Finished Jun 02 03:09:14 PM PDT 24
Peak memory 242316 kb
Host smart-09cbf063-e060-4f2f-b1d0-ae6d0194775d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345119845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.2345119845
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.79637387
Short name T1095
Test name
Test status
Simulation time 193285079 ps
CPU time 4.59 seconds
Started Jun 02 03:08:40 PM PDT 24
Finished Jun 02 03:08:46 PM PDT 24
Peak memory 242352 kb
Host smart-a420244b-728b-4282-b6d9-b6b4bbe6c341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79637387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.79637387
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.1253556443
Short name T186
Test name
Test status
Simulation time 15999866051 ps
CPU time 32.51 seconds
Started Jun 02 03:08:38 PM PDT 24
Finished Jun 02 03:09:11 PM PDT 24
Peak memory 242636 kb
Host smart-f0680d7e-74aa-4793-95a6-409958e758d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253556443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.1253556443
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.442114620
Short name T760
Test name
Test status
Simulation time 883640465 ps
CPU time 11.47 seconds
Started Jun 02 03:08:42 PM PDT 24
Finished Jun 02 03:08:54 PM PDT 24
Peak memory 242296 kb
Host smart-a2e839f5-c23c-4fba-8fe7-e94cafa283d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442114620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.442114620
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.2961229872
Short name T393
Test name
Test status
Simulation time 426537172 ps
CPU time 11.94 seconds
Started Jun 02 03:08:39 PM PDT 24
Finished Jun 02 03:08:51 PM PDT 24
Peak memory 242384 kb
Host smart-566dd844-2020-4bb3-83c1-6aec7262b450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961229872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.2961229872
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.1920342422
Short name T1104
Test name
Test status
Simulation time 9405342789 ps
CPU time 28.1 seconds
Started Jun 02 03:08:41 PM PDT 24
Finished Jun 02 03:09:10 PM PDT 24
Peak memory 242560 kb
Host smart-d789ecb2-6bac-4b4b-9fe2-d5a2c482bf37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1920342422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.1920342422
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.267513396
Short name T1158
Test name
Test status
Simulation time 275030193 ps
CPU time 4.92 seconds
Started Jun 02 03:08:40 PM PDT 24
Finished Jun 02 03:08:46 PM PDT 24
Peak memory 242452 kb
Host smart-468e97ab-6cf6-45c2-b5e9-dd0a8f8bf4d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=267513396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.267513396
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.1416324097
Short name T398
Test name
Test status
Simulation time 760923061 ps
CPU time 9.49 seconds
Started Jun 02 03:08:39 PM PDT 24
Finished Jun 02 03:08:49 PM PDT 24
Peak memory 248844 kb
Host smart-57fa8494-d139-4de3-9b49-4adda12f004d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416324097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.1416324097
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.3581865754
Short name T563
Test name
Test status
Simulation time 2859963915 ps
CPU time 72.99 seconds
Started Jun 02 03:08:42 PM PDT 24
Finished Jun 02 03:09:55 PM PDT 24
Peak memory 248992 kb
Host smart-a551fdce-5a38-4cec-b9bf-cc0e6225c56d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581865754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all
.3581865754
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.1069183092
Short name T287
Test name
Test status
Simulation time 89849249052 ps
CPU time 817.72 seconds
Started Jun 02 03:08:40 PM PDT 24
Finished Jun 02 03:22:19 PM PDT 24
Peak memory 275820 kb
Host smart-d09d6ee5-3711-49d5-9a99-c72f92d7fc72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069183092 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.1069183092
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.1606947129
Short name T705
Test name
Test status
Simulation time 1913711040 ps
CPU time 24.01 seconds
Started Jun 02 03:08:41 PM PDT 24
Finished Jun 02 03:09:06 PM PDT 24
Peak memory 248872 kb
Host smart-3e679964-ec25-4e2c-a583-3ffe7b48a0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606947129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.1606947129
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.2413395165
Short name T696
Test name
Test status
Simulation time 476185612 ps
CPU time 4.55 seconds
Started Jun 02 03:11:42 PM PDT 24
Finished Jun 02 03:11:47 PM PDT 24
Peak memory 242644 kb
Host smart-3af6131e-53d0-4d9b-b487-b29f75e45528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413395165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.2413395165
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.2226560166
Short name T166
Test name
Test status
Simulation time 283934066 ps
CPU time 4.4 seconds
Started Jun 02 03:11:48 PM PDT 24
Finished Jun 02 03:11:53 PM PDT 24
Peak memory 242488 kb
Host smart-6858fa7e-4862-45d3-893f-56856e10679d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226560166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.2226560166
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.1865435116
Short name T1101
Test name
Test status
Simulation time 168599346 ps
CPU time 4.32 seconds
Started Jun 02 03:11:47 PM PDT 24
Finished Jun 02 03:11:52 PM PDT 24
Peak memory 242684 kb
Host smart-456cc6ad-6a87-4942-bdde-cab4315c7fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865435116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.1865435116
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.291842499
Short name T1107
Test name
Test status
Simulation time 236107063 ps
CPU time 5.19 seconds
Started Jun 02 03:11:45 PM PDT 24
Finished Jun 02 03:11:51 PM PDT 24
Peak memory 242304 kb
Host smart-1a34ad8a-6b84-4301-9205-45b92781da1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291842499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.291842499
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.3241037540
Short name T588
Test name
Test status
Simulation time 104996271 ps
CPU time 3.94 seconds
Started Jun 02 03:11:47 PM PDT 24
Finished Jun 02 03:11:52 PM PDT 24
Peak memory 242280 kb
Host smart-24419939-1dea-4452-9e96-0088201d730a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241037540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.3241037540
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.402458939
Short name T1130
Test name
Test status
Simulation time 679836136 ps
CPU time 4.69 seconds
Started Jun 02 03:11:47 PM PDT 24
Finished Jun 02 03:11:52 PM PDT 24
Peak memory 242640 kb
Host smart-f0265cee-492c-4316-89f8-458aa7c49fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402458939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.402458939
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.3322666904
Short name T168
Test name
Test status
Simulation time 369187052 ps
CPU time 3.4 seconds
Started Jun 02 03:11:46 PM PDT 24
Finished Jun 02 03:11:50 PM PDT 24
Peak memory 242968 kb
Host smart-bd1441f7-81a3-46d7-8bce-cabc9a6aa6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322666904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.3322666904
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.1319521042
Short name T1037
Test name
Test status
Simulation time 242155980 ps
CPU time 3.32 seconds
Started Jun 02 03:11:51 PM PDT 24
Finished Jun 02 03:11:54 PM PDT 24
Peak memory 242644 kb
Host smart-44509291-96c9-4b60-8922-f4d96580af9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319521042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.1319521042
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.227977556
Short name T781
Test name
Test status
Simulation time 564944441 ps
CPU time 4.92 seconds
Started Jun 02 03:11:47 PM PDT 24
Finished Jun 02 03:11:52 PM PDT 24
Peak memory 242396 kb
Host smart-129b2e42-b4b4-4fcd-9430-5e18b8193483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227977556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.227977556
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.4143239115
Short name T839
Test name
Test status
Simulation time 213227133 ps
CPU time 4.38 seconds
Started Jun 02 03:11:48 PM PDT 24
Finished Jun 02 03:11:53 PM PDT 24
Peak memory 242400 kb
Host smart-6618c11e-27c1-4e53-b6d8-4efd4f0742f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143239115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.4143239115
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.3537841543
Short name T102
Test name
Test status
Simulation time 110350163 ps
CPU time 1.94 seconds
Started Jun 02 03:08:40 PM PDT 24
Finished Jun 02 03:08:43 PM PDT 24
Peak memory 240768 kb
Host smart-aed910b9-b285-4799-b2ec-21aa13f4b681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537841543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.3537841543
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.99524790
Short name T52
Test name
Test status
Simulation time 746483289 ps
CPU time 21.61 seconds
Started Jun 02 03:08:41 PM PDT 24
Finished Jun 02 03:09:03 PM PDT 24
Peak memory 248956 kb
Host smart-46f7905b-8791-48cb-8c44-82732fa74537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99524790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.99524790
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.3393437186
Short name T1160
Test name
Test status
Simulation time 288976322 ps
CPU time 7.71 seconds
Started Jun 02 03:08:41 PM PDT 24
Finished Jun 02 03:08:49 PM PDT 24
Peak memory 242512 kb
Host smart-595c656c-2984-4bde-91f8-2c7f9fa370a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393437186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.3393437186
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.1108607035
Short name T535
Test name
Test status
Simulation time 2025315421 ps
CPU time 5.37 seconds
Started Jun 02 03:08:39 PM PDT 24
Finished Jun 02 03:08:45 PM PDT 24
Peak memory 242164 kb
Host smart-ae68b429-ccae-4f3d-ad19-9ccfee2a5433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108607035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.1108607035
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.3594507044
Short name T1142
Test name
Test status
Simulation time 153782566 ps
CPU time 3.96 seconds
Started Jun 02 03:08:37 PM PDT 24
Finished Jun 02 03:08:42 PM PDT 24
Peak memory 242636 kb
Host smart-ca3465b8-da15-48c3-804d-284219e84dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594507044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.3594507044
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.3492119521
Short name T357
Test name
Test status
Simulation time 396557446 ps
CPU time 14.56 seconds
Started Jun 02 03:08:39 PM PDT 24
Finished Jun 02 03:08:54 PM PDT 24
Peak memory 242624 kb
Host smart-5171014b-8f51-4dab-8fc4-13b93f9de511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492119521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.3492119521
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.1297689764
Short name T794
Test name
Test status
Simulation time 888951767 ps
CPU time 22.43 seconds
Started Jun 02 03:08:42 PM PDT 24
Finished Jun 02 03:09:05 PM PDT 24
Peak memory 242636 kb
Host smart-b497b5be-8717-4704-bdfc-17baf27644b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297689764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.1297689764
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.3571540478
Short name T652
Test name
Test status
Simulation time 212234602 ps
CPU time 5.9 seconds
Started Jun 02 03:08:38 PM PDT 24
Finished Jun 02 03:08:45 PM PDT 24
Peak memory 242336 kb
Host smart-b65f1f0a-8771-4612-87f1-764d01addaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571540478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.3571540478
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.851974683
Short name T711
Test name
Test status
Simulation time 246934083 ps
CPU time 4.04 seconds
Started Jun 02 03:08:38 PM PDT 24
Finished Jun 02 03:08:42 PM PDT 24
Peak memory 242296 kb
Host smart-9f4247de-5a6d-4706-b147-68366d763c08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=851974683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.851974683
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.3618470505
Short name T1016
Test name
Test status
Simulation time 1028143218 ps
CPU time 9.76 seconds
Started Jun 02 03:08:37 PM PDT 24
Finished Jun 02 03:08:47 PM PDT 24
Peak memory 248836 kb
Host smart-7594ed92-0d7d-4c8a-bc56-e36bb077108d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3618470505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.3618470505
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.3279697539
Short name T405
Test name
Test status
Simulation time 568853512 ps
CPU time 9.1 seconds
Started Jun 02 03:08:40 PM PDT 24
Finished Jun 02 03:08:50 PM PDT 24
Peak memory 248928 kb
Host smart-b1155f49-8780-4cb1-94f3-ae2f48d68a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279697539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.3279697539
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.1081298158
Short name T1110
Test name
Test status
Simulation time 9527626903 ps
CPU time 151.52 seconds
Started Jun 02 03:08:41 PM PDT 24
Finished Jun 02 03:11:13 PM PDT 24
Peak memory 250108 kb
Host smart-e05ce60f-b7b2-4303-89a5-4960bbd1cf25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081298158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all
.1081298158
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.3568492744
Short name T512
Test name
Test status
Simulation time 30547001670 ps
CPU time 470.14 seconds
Started Jun 02 03:08:40 PM PDT 24
Finished Jun 02 03:16:31 PM PDT 24
Peak memory 307440 kb
Host smart-82b9cf58-a37b-4bfd-b6be-3ec62cdbf2fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568492744 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.3568492744
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.637570268
Short name T172
Test name
Test status
Simulation time 1115092333 ps
CPU time 18.69 seconds
Started Jun 02 03:08:39 PM PDT 24
Finished Jun 02 03:08:58 PM PDT 24
Peak memory 242488 kb
Host smart-62754d4c-6473-4e4b-a5e1-ddf904806069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637570268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.637570268
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.4152322371
Short name T956
Test name
Test status
Simulation time 2111088213 ps
CPU time 4.59 seconds
Started Jun 02 03:11:50 PM PDT 24
Finished Jun 02 03:11:55 PM PDT 24
Peak memory 242728 kb
Host smart-dd7599a5-a6f2-4a10-ade3-e263243b169e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152322371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.4152322371
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.96140280
Short name T854
Test name
Test status
Simulation time 109197925 ps
CPU time 4.03 seconds
Started Jun 02 03:11:47 PM PDT 24
Finished Jun 02 03:11:52 PM PDT 24
Peak memory 242380 kb
Host smart-176dd01d-aed5-41f9-8b52-ad5354be4419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96140280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.96140280
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.1555383586
Short name T786
Test name
Test status
Simulation time 550215700 ps
CPU time 4.48 seconds
Started Jun 02 03:11:47 PM PDT 24
Finished Jun 02 03:11:52 PM PDT 24
Peak memory 242404 kb
Host smart-e73ca923-ddb7-47cc-8fb7-6b6caa3f63aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555383586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.1555383586
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.1513410625
Short name T770
Test name
Test status
Simulation time 543543125 ps
CPU time 4.09 seconds
Started Jun 02 03:11:46 PM PDT 24
Finished Jun 02 03:11:51 PM PDT 24
Peak memory 242276 kb
Host smart-89fa2dcb-8f7f-4484-9ffd-e57f400d78c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513410625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.1513410625
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.2938627469
Short name T603
Test name
Test status
Simulation time 438220206 ps
CPU time 4.05 seconds
Started Jun 02 03:11:45 PM PDT 24
Finished Jun 02 03:11:49 PM PDT 24
Peak memory 242464 kb
Host smart-a0766e9a-3465-4962-ad6d-d3f9f54a36d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938627469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.2938627469
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.4173145567
Short name T117
Test name
Test status
Simulation time 177231352 ps
CPU time 4.61 seconds
Started Jun 02 03:11:47 PM PDT 24
Finished Jun 02 03:11:53 PM PDT 24
Peak memory 242640 kb
Host smart-729ca266-8dee-4a00-993d-221acbd8fc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173145567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.4173145567
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.1449163117
Short name T607
Test name
Test status
Simulation time 127027962 ps
CPU time 3.82 seconds
Started Jun 02 03:11:48 PM PDT 24
Finished Jun 02 03:11:52 PM PDT 24
Peak memory 242380 kb
Host smart-d97c3f9e-ba4b-4462-ae67-ae403914589a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449163117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.1449163117
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.3263375426
Short name T1115
Test name
Test status
Simulation time 204559333 ps
CPU time 4.23 seconds
Started Jun 02 03:11:51 PM PDT 24
Finished Jun 02 03:11:56 PM PDT 24
Peak memory 242356 kb
Host smart-c06ba954-c8ee-4c3a-8254-27453f9996a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263375426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.3263375426
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.4062487766
Short name T89
Test name
Test status
Simulation time 59188958 ps
CPU time 1.81 seconds
Started Jun 02 03:08:51 PM PDT 24
Finished Jun 02 03:08:53 PM PDT 24
Peak memory 240712 kb
Host smart-57a65748-db87-46d3-bb6d-609ecd2542b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062487766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.4062487766
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.1776600871
Short name T657
Test name
Test status
Simulation time 1164713735 ps
CPU time 20.42 seconds
Started Jun 02 03:08:43 PM PDT 24
Finished Jun 02 03:09:04 PM PDT 24
Peak memory 242348 kb
Host smart-7e2300b7-4240-4cdb-ab9b-00c3b32df3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776600871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.1776600871
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.2310255857
Short name T435
Test name
Test status
Simulation time 1404863055 ps
CPU time 23.67 seconds
Started Jun 02 03:08:50 PM PDT 24
Finished Jun 02 03:09:15 PM PDT 24
Peak memory 242268 kb
Host smart-63f92a3c-3755-43d0-804f-3bed4948d9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310255857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.2310255857
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.1312261688
Short name T844
Test name
Test status
Simulation time 1842820768 ps
CPU time 14.96 seconds
Started Jun 02 03:08:43 PM PDT 24
Finished Jun 02 03:08:59 PM PDT 24
Peak memory 242560 kb
Host smart-fa006a52-0fe0-4647-a6d3-7ea7e8bce36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312261688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.1312261688
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.3802659171
Short name T219
Test name
Test status
Simulation time 107834279 ps
CPU time 3.12 seconds
Started Jun 02 03:08:47 PM PDT 24
Finished Jun 02 03:08:51 PM PDT 24
Peak memory 242284 kb
Host smart-c556a8b0-2a60-4fd3-b5a3-3b22e31163d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802659171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.3802659171
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.1839665857
Short name T818
Test name
Test status
Simulation time 2024210357 ps
CPU time 32.72 seconds
Started Jun 02 03:08:49 PM PDT 24
Finished Jun 02 03:09:23 PM PDT 24
Peak memory 245032 kb
Host smart-3e031566-2e8f-4da8-bb2a-0d57caa5b2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839665857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.1839665857
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.432331805
Short name T94
Test name
Test status
Simulation time 14981629884 ps
CPU time 44.31 seconds
Started Jun 02 03:08:50 PM PDT 24
Finished Jun 02 03:09:35 PM PDT 24
Peak memory 242252 kb
Host smart-0945f8ec-7cef-4dc4-87b9-f639997a2067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432331805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.432331805
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.524051461
Short name T231
Test name
Test status
Simulation time 3002482702 ps
CPU time 7.67 seconds
Started Jun 02 03:08:50 PM PDT 24
Finished Jun 02 03:08:58 PM PDT 24
Peak memory 242852 kb
Host smart-20bc9230-5003-4cb4-b33f-bcbad9a984f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524051461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.524051461
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.1746073016
Short name T237
Test name
Test status
Simulation time 693479759 ps
CPU time 18.96 seconds
Started Jun 02 03:08:45 PM PDT 24
Finished Jun 02 03:09:05 PM PDT 24
Peak memory 242216 kb
Host smart-6d23b977-77dc-4169-b4e9-e5a510f9cd44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1746073016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.1746073016
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.1506536288
Short name T1023
Test name
Test status
Simulation time 900554771 ps
CPU time 8.24 seconds
Started Jun 02 03:08:47 PM PDT 24
Finished Jun 02 03:08:56 PM PDT 24
Peak memory 242280 kb
Host smart-a61eca7a-4b57-4fef-bca4-747755efc0ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1506536288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.1506536288
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.3979377716
Short name T656
Test name
Test status
Simulation time 345383662 ps
CPU time 5.63 seconds
Started Jun 02 03:08:46 PM PDT 24
Finished Jun 02 03:08:52 PM PDT 24
Peak memory 242188 kb
Host smart-72f87a4a-4369-4f07-8792-510fbadcc863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979377716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.3979377716
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.775641825
Short name T346
Test name
Test status
Simulation time 68803089542 ps
CPU time 882.44 seconds
Started Jun 02 03:08:44 PM PDT 24
Finished Jun 02 03:23:27 PM PDT 24
Peak memory 328704 kb
Host smart-e92de87b-1327-4c8b-b8cd-a6cbcb41efe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775641825 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.775641825
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.3152703650
Short name T1055
Test name
Test status
Simulation time 1592339502 ps
CPU time 19.47 seconds
Started Jun 02 03:08:45 PM PDT 24
Finished Jun 02 03:09:05 PM PDT 24
Peak memory 248828 kb
Host smart-b0c0325c-051f-4c21-922c-111ef8c3d905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152703650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.3152703650
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.768007077
Short name T495
Test name
Test status
Simulation time 103069382 ps
CPU time 2.7 seconds
Started Jun 02 03:11:52 PM PDT 24
Finished Jun 02 03:11:55 PM PDT 24
Peak memory 242584 kb
Host smart-9507f100-635f-4882-99df-010a904e8c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768007077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.768007077
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.1469996685
Short name T189
Test name
Test status
Simulation time 570169531 ps
CPU time 3.61 seconds
Started Jun 02 03:11:53 PM PDT 24
Finished Jun 02 03:11:57 PM PDT 24
Peak memory 242340 kb
Host smart-d14bea36-9d1b-4ae5-b972-60feca24f08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469996685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.1469996685
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.3983416359
Short name T1
Test name
Test status
Simulation time 160853392 ps
CPU time 4.47 seconds
Started Jun 02 03:11:51 PM PDT 24
Finished Jun 02 03:11:57 PM PDT 24
Peak memory 242284 kb
Host smart-fe5f1ea3-d311-44d7-9bcb-0fd5c239eec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983416359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.3983416359
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.867548169
Short name T502
Test name
Test status
Simulation time 1565965990 ps
CPU time 3.18 seconds
Started Jun 02 03:11:56 PM PDT 24
Finished Jun 02 03:12:00 PM PDT 24
Peak memory 242748 kb
Host smart-93cdf659-076e-41bc-b868-823b479d686f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867548169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.867548169
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.1467059087
Short name T1169
Test name
Test status
Simulation time 1863227796 ps
CPU time 4.89 seconds
Started Jun 02 03:11:53 PM PDT 24
Finished Jun 02 03:11:59 PM PDT 24
Peak memory 242328 kb
Host smart-ab0eec48-de33-482f-92b2-7846b5d3d21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467059087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.1467059087
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.1996125356
Short name T79
Test name
Test status
Simulation time 362522966 ps
CPU time 4.12 seconds
Started Jun 02 03:11:52 PM PDT 24
Finished Jun 02 03:11:57 PM PDT 24
Peak memory 242468 kb
Host smart-ea1585ca-7be4-4751-8c9e-68c388377feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996125356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.1996125356
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.2696562313
Short name T1122
Test name
Test status
Simulation time 175729610 ps
CPU time 4.51 seconds
Started Jun 02 03:11:51 PM PDT 24
Finished Jun 02 03:11:56 PM PDT 24
Peak memory 242424 kb
Host smart-d61f2da6-c7df-45d7-9ce8-f56d14c8138a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696562313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.2696562313
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.4005973457
Short name T996
Test name
Test status
Simulation time 1531475912 ps
CPU time 3.95 seconds
Started Jun 02 03:11:52 PM PDT 24
Finished Jun 02 03:11:57 PM PDT 24
Peak memory 242272 kb
Host smart-70854bcc-f3e5-40fe-b850-9cc478ae3179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005973457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.4005973457
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.4103281961
Short name T128
Test name
Test status
Simulation time 351949058 ps
CPU time 3.64 seconds
Started Jun 02 03:11:52 PM PDT 24
Finished Jun 02 03:11:56 PM PDT 24
Peak memory 242584 kb
Host smart-0089a03d-2f67-4ae7-9ec2-ed042250f876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103281961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.4103281961
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.2383551076
Short name T437
Test name
Test status
Simulation time 232268542 ps
CPU time 2.19 seconds
Started Jun 02 03:08:48 PM PDT 24
Finished Jun 02 03:08:51 PM PDT 24
Peak memory 241140 kb
Host smart-2e03c2bb-ca6e-4d8e-8878-6d1ff775c679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383551076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.2383551076
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.2711604335
Short name T54
Test name
Test status
Simulation time 1606319725 ps
CPU time 35.1 seconds
Started Jun 02 03:08:49 PM PDT 24
Finished Jun 02 03:09:26 PM PDT 24
Peak memory 248956 kb
Host smart-2a71b9e2-2af1-488c-a1b5-7d36943dafcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711604335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.2711604335
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.4038171528
Short name T650
Test name
Test status
Simulation time 1608406075 ps
CPU time 18.64 seconds
Started Jun 02 03:08:47 PM PDT 24
Finished Jun 02 03:09:06 PM PDT 24
Peak memory 242688 kb
Host smart-c9b5def7-470c-4321-a8fe-8c10510cae48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038171528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.4038171528
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.4274220165
Short name T888
Test name
Test status
Simulation time 412761999 ps
CPU time 11.21 seconds
Started Jun 02 03:08:50 PM PDT 24
Finished Jun 02 03:09:02 PM PDT 24
Peak memory 242520 kb
Host smart-9b7e5e0d-1a4f-4749-afde-fc6b96f68fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274220165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.4274220165
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.657788893
Short name T515
Test name
Test status
Simulation time 248996483 ps
CPU time 5.11 seconds
Started Jun 02 03:08:51 PM PDT 24
Finished Jun 02 03:08:57 PM PDT 24
Peak memory 242268 kb
Host smart-3a325382-7e7f-4fa4-a85b-88033ff885cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657788893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.657788893
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.2569965707
Short name T155
Test name
Test status
Simulation time 877603790 ps
CPU time 11.08 seconds
Started Jun 02 03:08:50 PM PDT 24
Finished Jun 02 03:09:02 PM PDT 24
Peak memory 242220 kb
Host smart-71732c6a-f34c-4eb3-8b68-08f345879ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569965707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.2569965707
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.2765260739
Short name T738
Test name
Test status
Simulation time 414918035 ps
CPU time 11.43 seconds
Started Jun 02 03:08:49 PM PDT 24
Finished Jun 02 03:09:01 PM PDT 24
Peak memory 242380 kb
Host smart-e36b6d0a-5d3c-44f4-af70-6e1ec7d3bff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765260739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.2765260739
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.2431691774
Short name T1052
Test name
Test status
Simulation time 268060702 ps
CPU time 6.42 seconds
Started Jun 02 03:08:46 PM PDT 24
Finished Jun 02 03:08:53 PM PDT 24
Peak memory 242228 kb
Host smart-d88953b3-b181-43d3-b3fa-893707c235ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431691774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.2431691774
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.1959248825
Short name T869
Test name
Test status
Simulation time 1260009373 ps
CPU time 20.4 seconds
Started Jun 02 03:08:45 PM PDT 24
Finished Jun 02 03:09:06 PM PDT 24
Peak memory 248868 kb
Host smart-a6e9a067-ce8c-4b0a-9093-46b9d1009160
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1959248825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.1959248825
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.356552827
Short name T545
Test name
Test status
Simulation time 2419511274 ps
CPU time 9.19 seconds
Started Jun 02 03:08:47 PM PDT 24
Finished Jun 02 03:08:57 PM PDT 24
Peak memory 242304 kb
Host smart-4ef7a6d4-251d-4af8-baf8-1a28569d594f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=356552827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.356552827
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.3251271288
Short name T469
Test name
Test status
Simulation time 492147453 ps
CPU time 10.59 seconds
Started Jun 02 03:08:45 PM PDT 24
Finished Jun 02 03:08:56 PM PDT 24
Peak memory 242236 kb
Host smart-de73e714-3447-4b77-bf69-5676f48efc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251271288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.3251271288
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.2372457702
Short name T766
Test name
Test status
Simulation time 35623424315 ps
CPU time 213.63 seconds
Started Jun 02 03:08:48 PM PDT 24
Finished Jun 02 03:12:22 PM PDT 24
Peak memory 259340 kb
Host smart-03cdb971-90f3-4f06-b88e-987a4b2a8722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372457702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.2372457702
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.1167774383
Short name T293
Test name
Test status
Simulation time 335486481628 ps
CPU time 2662.18 seconds
Started Jun 02 03:08:49 PM PDT 24
Finished Jun 02 03:53:13 PM PDT 24
Peak memory 547516 kb
Host smart-a38313a6-d634-42a8-90d5-95da5642fd67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167774383 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.1167774383
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.364131003
Short name T609
Test name
Test status
Simulation time 309955369 ps
CPU time 10.13 seconds
Started Jun 02 03:08:49 PM PDT 24
Finished Jun 02 03:09:01 PM PDT 24
Peak memory 248976 kb
Host smart-5204d4cb-5736-4732-815f-1c8f257bde5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364131003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.364131003
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.1624428349
Short name T981
Test name
Test status
Simulation time 448003354 ps
CPU time 4.45 seconds
Started Jun 02 03:11:54 PM PDT 24
Finished Jun 02 03:11:59 PM PDT 24
Peak memory 242460 kb
Host smart-845298cb-2ab7-4751-b6b6-c4fc7b87626a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624428349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.1624428349
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.2267764039
Short name T1128
Test name
Test status
Simulation time 392226192 ps
CPU time 4.36 seconds
Started Jun 02 03:11:56 PM PDT 24
Finished Jun 02 03:12:00 PM PDT 24
Peak memory 242360 kb
Host smart-877f0b74-3cee-46b4-b0b5-0a1cd8e61d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267764039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.2267764039
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.2598654661
Short name T809
Test name
Test status
Simulation time 429534152 ps
CPU time 4.92 seconds
Started Jun 02 03:11:56 PM PDT 24
Finished Jun 02 03:12:01 PM PDT 24
Peak memory 242364 kb
Host smart-915e90f1-21a7-420d-8ea7-99ab3c92300c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598654661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.2598654661
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.4069069355
Short name T494
Test name
Test status
Simulation time 121049486 ps
CPU time 3.77 seconds
Started Jun 02 03:11:52 PM PDT 24
Finished Jun 02 03:11:57 PM PDT 24
Peak memory 242264 kb
Host smart-e3dff9bc-0a24-4df8-a543-9cdfb2aeafc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069069355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.4069069355
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.2446956303
Short name T934
Test name
Test status
Simulation time 1866447503 ps
CPU time 5.15 seconds
Started Jun 02 03:11:51 PM PDT 24
Finished Jun 02 03:11:57 PM PDT 24
Peak memory 242632 kb
Host smart-f136123d-5c4b-42df-aa4c-7e06c120ef95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446956303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.2446956303
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.424637587
Short name T1154
Test name
Test status
Simulation time 250138288 ps
CPU time 4.59 seconds
Started Jun 02 03:11:54 PM PDT 24
Finished Jun 02 03:11:59 PM PDT 24
Peak memory 242424 kb
Host smart-7516624b-c0ab-4f28-a4da-65fc20e1e692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424637587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.424637587
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.2443750599
Short name T985
Test name
Test status
Simulation time 152473825 ps
CPU time 4 seconds
Started Jun 02 03:11:53 PM PDT 24
Finished Jun 02 03:11:57 PM PDT 24
Peak memory 242608 kb
Host smart-1e99dea0-9b8c-4df1-b74b-e132b814af8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443750599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.2443750599
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.3705430641
Short name T627
Test name
Test status
Simulation time 554144350 ps
CPU time 5.44 seconds
Started Jun 02 03:11:53 PM PDT 24
Finished Jun 02 03:11:59 PM PDT 24
Peak memory 242432 kb
Host smart-e70fce3f-a908-4a5f-a5eb-58a780555a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705430641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.3705430641
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.2319374553
Short name T864
Test name
Test status
Simulation time 157742380 ps
CPU time 4.03 seconds
Started Jun 02 03:11:52 PM PDT 24
Finished Jun 02 03:11:57 PM PDT 24
Peak memory 242448 kb
Host smart-9a1cb4fb-b7ea-4a95-b077-a0246e7a77be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319374553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.2319374553
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.3942782641
Short name T1080
Test name
Test status
Simulation time 1912247713 ps
CPU time 5.15 seconds
Started Jun 02 03:11:51 PM PDT 24
Finished Jun 02 03:11:56 PM PDT 24
Peak memory 242588 kb
Host smart-7149c983-f04f-44c8-9972-76756a05ccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942782641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.3942782641
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.2833996979
Short name T242
Test name
Test status
Simulation time 305101895 ps
CPU time 2.38 seconds
Started Jun 02 03:08:49 PM PDT 24
Finished Jun 02 03:08:52 PM PDT 24
Peak memory 241144 kb
Host smart-743030ae-9f90-48d0-8019-7f59bade7cd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833996979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.2833996979
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.2219886636
Short name T70
Test name
Test status
Simulation time 1853537979 ps
CPU time 15.12 seconds
Started Jun 02 03:08:47 PM PDT 24
Finished Jun 02 03:09:03 PM PDT 24
Peak memory 248952 kb
Host smart-8fa865fa-17d8-40e8-8745-8e1f2b47bea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219886636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.2219886636
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.2026583709
Short name T204
Test name
Test status
Simulation time 219380062 ps
CPU time 8.09 seconds
Started Jun 02 03:08:49 PM PDT 24
Finished Jun 02 03:08:57 PM PDT 24
Peak memory 242568 kb
Host smart-de0472e1-c97d-4065-8356-2aceb00ea60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026583709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.2026583709
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.4007753538
Short name T383
Test name
Test status
Simulation time 3629175587 ps
CPU time 42.85 seconds
Started Jun 02 03:08:49 PM PDT 24
Finished Jun 02 03:09:32 PM PDT 24
Peak memory 242268 kb
Host smart-e1c4c04a-95de-4961-99cd-d0e5fbac8298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007753538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.4007753538
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.2698470329
Short name T635
Test name
Test status
Simulation time 106696236 ps
CPU time 3.4 seconds
Started Jun 02 03:08:47 PM PDT 24
Finished Jun 02 03:08:51 PM PDT 24
Peak memory 242248 kb
Host smart-2a6081e5-0a35-4873-9eec-bc9370e7f88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698470329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.2698470329
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.3369527327
Short name T918
Test name
Test status
Simulation time 281433314 ps
CPU time 3.82 seconds
Started Jun 02 03:08:49 PM PDT 24
Finished Jun 02 03:08:54 PM PDT 24
Peak memory 242272 kb
Host smart-f31ef72d-7dbb-44a4-9951-ca79ec41542c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369527327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.3369527327
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.544250041
Short name T284
Test name
Test status
Simulation time 111076760 ps
CPU time 4.25 seconds
Started Jun 02 03:08:49 PM PDT 24
Finished Jun 02 03:08:54 PM PDT 24
Peak memory 242464 kb
Host smart-75553a74-2300-4a37-8d53-3b7930023acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544250041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.544250041
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.729478534
Short name T908
Test name
Test status
Simulation time 198665006 ps
CPU time 3.2 seconds
Started Jun 02 03:08:48 PM PDT 24
Finished Jun 02 03:08:52 PM PDT 24
Peak memory 242636 kb
Host smart-c2a36dc3-4184-4d95-bc1d-d7ef8df8a6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729478534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.729478534
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.900372735
Short name T644
Test name
Test status
Simulation time 355958647 ps
CPU time 12.29 seconds
Started Jun 02 03:08:52 PM PDT 24
Finished Jun 02 03:09:04 PM PDT 24
Peak memory 242252 kb
Host smart-162c68d6-2589-4139-a9e6-c4a66dd484bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=900372735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.900372735
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.1216002542
Short name T798
Test name
Test status
Simulation time 526425343 ps
CPU time 8.31 seconds
Started Jun 02 03:08:51 PM PDT 24
Finished Jun 02 03:09:00 PM PDT 24
Peak memory 242220 kb
Host smart-22b16704-f551-46c8-962d-109a014037f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1216002542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.1216002542
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.2987804745
Short name T222
Test name
Test status
Simulation time 502749551 ps
CPU time 5.53 seconds
Started Jun 02 03:08:49 PM PDT 24
Finished Jun 02 03:08:56 PM PDT 24
Peak memory 242140 kb
Host smart-04cb7edd-3c8e-41bb-880e-22c6ec2f80a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987804745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.2987804745
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.29091432
Short name T775
Test name
Test status
Simulation time 196540194034 ps
CPU time 1457.85 seconds
Started Jun 02 03:08:48 PM PDT 24
Finished Jun 02 03:33:06 PM PDT 24
Peak memory 342680 kb
Host smart-04812340-b1ca-4d4e-8cf0-e3e3ca17b50e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29091432 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.29091432
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.1044390069
Short name T1109
Test name
Test status
Simulation time 99128891 ps
CPU time 3.88 seconds
Started Jun 02 03:12:00 PM PDT 24
Finished Jun 02 03:12:05 PM PDT 24
Peak memory 242344 kb
Host smart-8cab3e7c-9c39-4fd5-bc84-94834dcbf77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044390069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.1044390069
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.963828173
Short name T194
Test name
Test status
Simulation time 2358585407 ps
CPU time 5.95 seconds
Started Jun 02 03:12:04 PM PDT 24
Finished Jun 02 03:12:10 PM PDT 24
Peak memory 242404 kb
Host smart-8f936b48-3398-4911-8847-3949813cb7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963828173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.963828173
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.1903797263
Short name T898
Test name
Test status
Simulation time 177254780 ps
CPU time 3.16 seconds
Started Jun 02 03:11:57 PM PDT 24
Finished Jun 02 03:12:01 PM PDT 24
Peak memory 242336 kb
Host smart-aeb88a3d-db3d-4d58-98ca-7f98ac06fb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903797263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.1903797263
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.3978815395
Short name T195
Test name
Test status
Simulation time 320900849 ps
CPU time 3.84 seconds
Started Jun 02 03:11:56 PM PDT 24
Finished Jun 02 03:12:00 PM PDT 24
Peak memory 242428 kb
Host smart-f6dd4e6d-27e1-4e19-a6a2-79bd382d714b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978815395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.3978815395
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.2012451887
Short name T1120
Test name
Test status
Simulation time 166158821 ps
CPU time 3.73 seconds
Started Jun 02 03:11:58 PM PDT 24
Finished Jun 02 03:12:03 PM PDT 24
Peak memory 242332 kb
Host smart-2bb97001-1f02-4181-9c62-73d7e1093cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012451887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.2012451887
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.99396191
Short name T670
Test name
Test status
Simulation time 156491133 ps
CPU time 4.2 seconds
Started Jun 02 03:12:00 PM PDT 24
Finished Jun 02 03:12:05 PM PDT 24
Peak memory 242672 kb
Host smart-e9d886a6-8e36-4580-a817-498d456c4ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99396191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.99396191
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.2556347884
Short name T977
Test name
Test status
Simulation time 2164488380 ps
CPU time 5.27 seconds
Started Jun 02 03:11:58 PM PDT 24
Finished Jun 02 03:12:04 PM PDT 24
Peak memory 242804 kb
Host smart-6003a0b5-c9de-4f93-b6c4-733c62e374e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556347884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.2556347884
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.2928154494
Short name T191
Test name
Test status
Simulation time 93028468 ps
CPU time 3.38 seconds
Started Jun 02 03:11:56 PM PDT 24
Finished Jun 02 03:12:00 PM PDT 24
Peak memory 242416 kb
Host smart-4d19106c-489e-4376-a55a-a92d9d73fabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928154494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.2928154494
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.3362107182
Short name T663
Test name
Test status
Simulation time 221863262 ps
CPU time 1.96 seconds
Started Jun 02 03:08:52 PM PDT 24
Finished Jun 02 03:08:55 PM PDT 24
Peak memory 241040 kb
Host smart-4dcf15d4-b2b6-4821-a88b-57cbd9ab4c29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362107182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.3362107182
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.4144303692
Short name T467
Test name
Test status
Simulation time 388909977 ps
CPU time 5.76 seconds
Started Jun 02 03:08:54 PM PDT 24
Finished Jun 02 03:09:00 PM PDT 24
Peak memory 247316 kb
Host smart-1954599e-7a92-4b50-8b9f-e0810f1cbdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144303692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.4144303692
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.2890391516
Short name T778
Test name
Test status
Simulation time 1476918338 ps
CPU time 34.67 seconds
Started Jun 02 03:08:53 PM PDT 24
Finished Jun 02 03:09:28 PM PDT 24
Peak memory 242588 kb
Host smart-cbdc98d4-86eb-4d6d-8db0-eb21c522b326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890391516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.2890391516
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.441015693
Short name T784
Test name
Test status
Simulation time 3132142268 ps
CPU time 20.31 seconds
Started Jun 02 03:08:54 PM PDT 24
Finished Jun 02 03:09:15 PM PDT 24
Peak memory 242564 kb
Host smart-b8aa86dd-6801-4a66-acfe-7c9222b7e311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441015693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.441015693
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.4079688544
Short name T240
Test name
Test status
Simulation time 235458165 ps
CPU time 4.15 seconds
Started Jun 02 03:08:53 PM PDT 24
Finished Jun 02 03:08:57 PM PDT 24
Peak memory 242372 kb
Host smart-442ed8bd-301e-4773-9025-a165e060afe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079688544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.4079688544
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.4129401381
Short name T1036
Test name
Test status
Simulation time 155370633 ps
CPU time 4.55 seconds
Started Jun 02 03:08:53 PM PDT 24
Finished Jun 02 03:08:58 PM PDT 24
Peak memory 242252 kb
Host smart-29dd15a6-3f60-4cec-aceb-8f144657ae22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129401381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.4129401381
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.2795794436
Short name T984
Test name
Test status
Simulation time 747560695 ps
CPU time 31.59 seconds
Started Jun 02 03:08:54 PM PDT 24
Finished Jun 02 03:09:26 PM PDT 24
Peak memory 242332 kb
Host smart-96b6abd5-7cdf-467d-8ee2-26e5bb01d43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795794436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.2795794436
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.3373523755
Short name T572
Test name
Test status
Simulation time 3048536073 ps
CPU time 12.11 seconds
Started Jun 02 03:08:53 PM PDT 24
Finished Jun 02 03:09:05 PM PDT 24
Peak memory 242340 kb
Host smart-d69464a7-958f-4cef-a9b4-1508f97108bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373523755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.3373523755
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.2635853907
Short name T1040
Test name
Test status
Simulation time 763308025 ps
CPU time 8.12 seconds
Started Jun 02 03:08:52 PM PDT 24
Finished Jun 02 03:09:01 PM PDT 24
Peak memory 242192 kb
Host smart-da483f95-1968-4f19-bde1-3ab363f9ec66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2635853907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.2635853907
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.1226510210
Short name T1173
Test name
Test status
Simulation time 3828207701 ps
CPU time 9.65 seconds
Started Jun 02 03:08:51 PM PDT 24
Finished Jun 02 03:09:02 PM PDT 24
Peak memory 242396 kb
Host smart-8462bb87-e4e8-4cea-b162-4d4e34f17081
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1226510210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.1226510210
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.2346003801
Short name T266
Test name
Test status
Simulation time 404509354 ps
CPU time 9.43 seconds
Started Jun 02 03:08:53 PM PDT 24
Finished Jun 02 03:09:03 PM PDT 24
Peak memory 248800 kb
Host smart-0151ea6e-1740-4784-a382-adbb1e87b5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346003801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.2346003801
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.204851457
Short name T426
Test name
Test status
Simulation time 158003950974 ps
CPU time 382.61 seconds
Started Jun 02 03:08:54 PM PDT 24
Finished Jun 02 03:15:17 PM PDT 24
Peak memory 265572 kb
Host smart-65b6e155-61c5-4d77-9995-1cc21a9472e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204851457 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.204851457
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.3790969764
Short name T600
Test name
Test status
Simulation time 593157982 ps
CPU time 18.67 seconds
Started Jun 02 03:08:53 PM PDT 24
Finished Jun 02 03:09:13 PM PDT 24
Peak memory 242580 kb
Host smart-6189e173-0563-49d8-94e9-959f3bf21821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790969764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.3790969764
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.999731038
Short name T558
Test name
Test status
Simulation time 561276154 ps
CPU time 4.53 seconds
Started Jun 02 03:11:58 PM PDT 24
Finished Jun 02 03:12:02 PM PDT 24
Peak memory 242444 kb
Host smart-c458801a-3748-4335-8c2e-982d42614f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999731038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.999731038
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.2160872885
Short name T8
Test name
Test status
Simulation time 143608156 ps
CPU time 4.18 seconds
Started Jun 02 03:12:00 PM PDT 24
Finished Jun 02 03:12:05 PM PDT 24
Peak memory 242700 kb
Host smart-6899a45b-55cc-4c63-a6f5-4c67e3d75a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160872885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.2160872885
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.3238358734
Short name T755
Test name
Test status
Simulation time 113004523 ps
CPU time 4.6 seconds
Started Jun 02 03:11:56 PM PDT 24
Finished Jun 02 03:12:01 PM PDT 24
Peak memory 242748 kb
Host smart-21008b99-4556-4d48-8c9f-7de881de4609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238358734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.3238358734
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.2241134733
Short name T750
Test name
Test status
Simulation time 309314109 ps
CPU time 4.46 seconds
Started Jun 02 03:12:00 PM PDT 24
Finished Jun 02 03:12:05 PM PDT 24
Peak memory 242412 kb
Host smart-82e20c38-a0e6-4c93-96dd-edab90212a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241134733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.2241134733
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.2000306568
Short name T976
Test name
Test status
Simulation time 176128377 ps
CPU time 4.2 seconds
Started Jun 02 03:11:57 PM PDT 24
Finished Jun 02 03:12:02 PM PDT 24
Peak memory 242408 kb
Host smart-437b12f6-4ab0-484f-96f1-7e60faffb9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000306568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.2000306568
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.2722686668
Short name T836
Test name
Test status
Simulation time 265281089 ps
CPU time 4.17 seconds
Started Jun 02 03:12:01 PM PDT 24
Finished Jun 02 03:12:06 PM PDT 24
Peak memory 242388 kb
Host smart-541a4138-2001-4150-b94e-f8fd0c0d9f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722686668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.2722686668
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.2477747630
Short name T1191
Test name
Test status
Simulation time 563948016 ps
CPU time 4.19 seconds
Started Jun 02 03:11:58 PM PDT 24
Finished Jun 02 03:12:03 PM PDT 24
Peak memory 242380 kb
Host smart-9cec8dd4-ae84-4743-b695-0595825f4fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477747630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.2477747630
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.3708008560
Short name T932
Test name
Test status
Simulation time 447597601 ps
CPU time 4.57 seconds
Started Jun 02 03:11:59 PM PDT 24
Finished Jun 02 03:12:04 PM PDT 24
Peak memory 242452 kb
Host smart-9caee906-eab7-4fc2-9c38-9cf9d26032d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708008560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.3708008560
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.3217853402
Short name T1074
Test name
Test status
Simulation time 585162531 ps
CPU time 4.82 seconds
Started Jun 02 03:11:57 PM PDT 24
Finished Jun 02 03:12:02 PM PDT 24
Peak memory 242440 kb
Host smart-b793f820-c8aa-4d32-8b42-cb265b5c8822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217853402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.3217853402
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.124796504
Short name T33
Test name
Test status
Simulation time 2153163452 ps
CPU time 3.68 seconds
Started Jun 02 03:11:59 PM PDT 24
Finished Jun 02 03:12:03 PM PDT 24
Peak memory 242456 kb
Host smart-2fb06e82-99a9-4a9a-9e23-4d01ece69ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124796504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.124796504
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.2579969133
Short name T1083
Test name
Test status
Simulation time 72187119 ps
CPU time 1.88 seconds
Started Jun 02 03:08:57 PM PDT 24
Finished Jun 02 03:09:00 PM PDT 24
Peak memory 240836 kb
Host smart-8bccdf07-02fc-40fd-9ff6-458343336fb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579969133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.2579969133
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.1930122372
Short name T58
Test name
Test status
Simulation time 544502557 ps
CPU time 15.03 seconds
Started Jun 02 03:09:01 PM PDT 24
Finished Jun 02 03:09:16 PM PDT 24
Peak memory 242336 kb
Host smart-40a52bcf-16a3-4141-943a-d6d9c61baa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930122372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.1930122372
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.1812825443
Short name T1194
Test name
Test status
Simulation time 1287931298 ps
CPU time 39.72 seconds
Started Jun 02 03:09:00 PM PDT 24
Finished Jun 02 03:09:40 PM PDT 24
Peak memory 249212 kb
Host smart-844b8cb9-2fb1-495a-b7c0-821eaf458dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812825443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.1812825443
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.232483889
Short name T92
Test name
Test status
Simulation time 14155013874 ps
CPU time 45.61 seconds
Started Jun 02 03:08:57 PM PDT 24
Finished Jun 02 03:09:43 PM PDT 24
Peak memory 243276 kb
Host smart-f3e7dd88-1980-40da-a525-4dc49f95fd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232483889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.232483889
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.3728057590
Short name T159
Test name
Test status
Simulation time 2286989460 ps
CPU time 4.11 seconds
Started Jun 02 03:08:55 PM PDT 24
Finished Jun 02 03:08:59 PM PDT 24
Peak memory 242732 kb
Host smart-8db30340-5a3b-4f05-b05d-e8273f3bd079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728057590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.3728057590
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.1865434828
Short name T822
Test name
Test status
Simulation time 658518121 ps
CPU time 7.89 seconds
Started Jun 02 03:08:58 PM PDT 24
Finished Jun 02 03:09:06 PM PDT 24
Peak memory 247524 kb
Host smart-b1f95b18-d6c6-4060-b7b9-cd9d32e6ad54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865434828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.1865434828
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.302679817
Short name T1017
Test name
Test status
Simulation time 12021928367 ps
CPU time 40.62 seconds
Started Jun 02 03:08:58 PM PDT 24
Finished Jun 02 03:09:39 PM PDT 24
Peak memory 243424 kb
Host smart-91711bb1-9368-4da0-8278-44154f2e7c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302679817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.302679817
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.791447803
Short name T1151
Test name
Test status
Simulation time 1097566906 ps
CPU time 6.9 seconds
Started Jun 02 03:08:59 PM PDT 24
Finished Jun 02 03:09:06 PM PDT 24
Peak memory 242216 kb
Host smart-1e9d0215-7e51-480e-86ee-71ee7499a683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791447803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.791447803
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.4078252209
Short name T690
Test name
Test status
Simulation time 1323534331 ps
CPU time 11.91 seconds
Started Jun 02 03:08:52 PM PDT 24
Finished Jun 02 03:09:05 PM PDT 24
Peak memory 248788 kb
Host smart-97c28ab3-3da7-4178-a11e-5e1ccd588172
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4078252209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.4078252209
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.3642292027
Short name T878
Test name
Test status
Simulation time 122224311 ps
CPU time 5.27 seconds
Started Jun 02 03:08:56 PM PDT 24
Finished Jun 02 03:09:02 PM PDT 24
Peak memory 242508 kb
Host smart-a1278b0b-628b-4380-978d-a28ffb51138d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3642292027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.3642292027
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.264832013
Short name T1076
Test name
Test status
Simulation time 401927312 ps
CPU time 5.68 seconds
Started Jun 02 03:08:52 PM PDT 24
Finished Jun 02 03:08:58 PM PDT 24
Peak memory 248736 kb
Host smart-8c8293e8-9529-4f94-80ba-c2c14c04d3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264832013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.264832013
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.176032743
Short name T1062
Test name
Test status
Simulation time 27821694952 ps
CPU time 54.23 seconds
Started Jun 02 03:08:57 PM PDT 24
Finished Jun 02 03:09:52 PM PDT 24
Peak memory 242720 kb
Host smart-7c4d7a96-c040-492a-b30d-ff7e04d8713f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176032743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.176032743
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.4210586901
Short name T241
Test name
Test status
Simulation time 117228043 ps
CPU time 3.52 seconds
Started Jun 02 03:12:01 PM PDT 24
Finished Jun 02 03:12:05 PM PDT 24
Peak memory 242588 kb
Host smart-f7863fbb-57ea-45ef-ab60-99a7369a19ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210586901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.4210586901
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.3338318943
Short name T170
Test name
Test status
Simulation time 101018815 ps
CPU time 3.54 seconds
Started Jun 02 03:12:04 PM PDT 24
Finished Jun 02 03:12:08 PM PDT 24
Peak memory 242380 kb
Host smart-3338210b-fdfd-43e1-afed-d74c986bb7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338318943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.3338318943
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.2313008571
Short name T1126
Test name
Test status
Simulation time 131134731 ps
CPU time 3.21 seconds
Started Jun 02 03:12:06 PM PDT 24
Finished Jun 02 03:12:10 PM PDT 24
Peak memory 242360 kb
Host smart-41494914-57d1-4cc1-8b83-c2002cdac618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313008571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.2313008571
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.2691925499
Short name T482
Test name
Test status
Simulation time 135281912 ps
CPU time 3.91 seconds
Started Jun 02 03:12:05 PM PDT 24
Finished Jun 02 03:12:09 PM PDT 24
Peak memory 242768 kb
Host smart-27409c14-34f1-48bb-b37e-72aa13371caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691925499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.2691925499
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.1203318534
Short name T1022
Test name
Test status
Simulation time 266233105 ps
CPU time 3.77 seconds
Started Jun 02 03:12:02 PM PDT 24
Finished Jun 02 03:12:06 PM PDT 24
Peak memory 242392 kb
Host smart-15d5557b-d2e2-4ab9-bb6e-6957ac10cc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203318534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.1203318534
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.2313510759
Short name T41
Test name
Test status
Simulation time 143197163 ps
CPU time 3.42 seconds
Started Jun 02 03:12:02 PM PDT 24
Finished Jun 02 03:12:06 PM PDT 24
Peak memory 242676 kb
Host smart-e575223b-c544-47ec-8dbb-6bea252ba34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313510759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.2313510759
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.864679478
Short name T700
Test name
Test status
Simulation time 1751197992 ps
CPU time 6.65 seconds
Started Jun 02 03:12:03 PM PDT 24
Finished Jun 02 03:12:10 PM PDT 24
Peak memory 242552 kb
Host smart-073f3a23-ccb9-4267-b631-fc60f08ae61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864679478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.864679478
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.2468882503
Short name T1013
Test name
Test status
Simulation time 259493132 ps
CPU time 4.8 seconds
Started Jun 02 03:12:05 PM PDT 24
Finished Jun 02 03:12:11 PM PDT 24
Peak memory 242408 kb
Host smart-081595b1-fb1f-48c7-8993-7ab681dc045b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468882503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.2468882503
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.872119850
Short name T736
Test name
Test status
Simulation time 1804290421 ps
CPU time 4.42 seconds
Started Jun 02 03:12:05 PM PDT 24
Finished Jun 02 03:12:10 PM PDT 24
Peak memory 242436 kb
Host smart-35e942b6-b14d-4f9c-90cf-0becfa3e40e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872119850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.872119850
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.1932181329
Short name T855
Test name
Test status
Simulation time 238726265 ps
CPU time 3.74 seconds
Started Jun 02 03:12:04 PM PDT 24
Finished Jun 02 03:12:09 PM PDT 24
Peak memory 242436 kb
Host smart-49ba25af-0ca2-49f6-9f67-58ca4e0f7489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932181329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.1932181329
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.3551579155
Short name T402
Test name
Test status
Simulation time 742184476 ps
CPU time 2.55 seconds
Started Jun 02 03:09:03 PM PDT 24
Finished Jun 02 03:09:06 PM PDT 24
Peak memory 240828 kb
Host smart-2aeebbd6-fb11-45c9-86ce-c945a7ba377a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551579155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.3551579155
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.617995947
Short name T987
Test name
Test status
Simulation time 849947055 ps
CPU time 21.96 seconds
Started Jun 02 03:08:57 PM PDT 24
Finished Jun 02 03:09:20 PM PDT 24
Peak memory 242340 kb
Host smart-25b8a178-11f2-46cc-bd5d-0adeed5affa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617995947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.617995947
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.922297430
Short name T642
Test name
Test status
Simulation time 1259127788 ps
CPU time 30.52 seconds
Started Jun 02 03:09:00 PM PDT 24
Finished Jun 02 03:09:31 PM PDT 24
Peak memory 243800 kb
Host smart-52a8b066-20a0-40a5-ac0f-9575725a0c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922297430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.922297430
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.1407608161
Short name T1127
Test name
Test status
Simulation time 1489045698 ps
CPU time 6.11 seconds
Started Jun 02 03:08:59 PM PDT 24
Finished Jun 02 03:09:05 PM PDT 24
Peak memory 242228 kb
Host smart-9d94e127-4039-4ed7-8dac-a4796e026972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407608161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.1407608161
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.2967041956
Short name T921
Test name
Test status
Simulation time 310184165 ps
CPU time 4.69 seconds
Started Jun 02 03:09:00 PM PDT 24
Finished Jun 02 03:09:05 PM PDT 24
Peak memory 242340 kb
Host smart-d6b0051c-dffa-4131-911f-a3f8ab7d1614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967041956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.2967041956
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.1330506589
Short name T1156
Test name
Test status
Simulation time 2585543453 ps
CPU time 16.08 seconds
Started Jun 02 03:09:02 PM PDT 24
Finished Jun 02 03:09:18 PM PDT 24
Peak memory 242384 kb
Host smart-816b5432-e4f5-46c1-9982-335d17472bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330506589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.1330506589
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.1292990236
Short name T26
Test name
Test status
Simulation time 857891951 ps
CPU time 24.45 seconds
Started Jun 02 03:09:01 PM PDT 24
Finished Jun 02 03:09:26 PM PDT 24
Peak memory 248820 kb
Host smart-86f2731b-45f8-4daa-a1dc-5ca0d64d1661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292990236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.1292990236
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.3048156624
Short name T787
Test name
Test status
Simulation time 314465390 ps
CPU time 6.22 seconds
Started Jun 02 03:09:03 PM PDT 24
Finished Jun 02 03:09:09 PM PDT 24
Peak memory 247828 kb
Host smart-f8ea26d1-19ec-4290-81b4-04a31647bcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048156624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.3048156624
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.852180526
Short name T877
Test name
Test status
Simulation time 919593323 ps
CPU time 24.66 seconds
Started Jun 02 03:09:01 PM PDT 24
Finished Jun 02 03:09:27 PM PDT 24
Peak memory 248892 kb
Host smart-098f4c0b-06b2-43df-aefb-0402b5449007
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=852180526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.852180526
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.2596694863
Short name T774
Test name
Test status
Simulation time 1293869378 ps
CPU time 4.49 seconds
Started Jun 02 03:08:56 PM PDT 24
Finished Jun 02 03:09:01 PM PDT 24
Peak memory 242268 kb
Host smart-d0a89529-98df-472e-b1dc-f1f0a66e4c20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2596694863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.2596694863
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.35842897
Short name T171
Test name
Test status
Simulation time 330543827 ps
CPU time 6.07 seconds
Started Jun 02 03:09:00 PM PDT 24
Finished Jun 02 03:09:06 PM PDT 24
Peak memory 242152 kb
Host smart-7a50e953-9a4d-4d8b-9c3c-d8461f698aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35842897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.35842897
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.89101942
Short name T1006
Test name
Test status
Simulation time 1017223700 ps
CPU time 15.56 seconds
Started Jun 02 03:09:03 PM PDT 24
Finished Jun 02 03:09:19 PM PDT 24
Peak memory 241916 kb
Host smart-1179217d-c7dd-47cc-a961-cd454b817577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89101942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.89101942
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.1750109243
Short name T1048
Test name
Test status
Simulation time 917707161 ps
CPU time 11.81 seconds
Started Jun 02 03:08:57 PM PDT 24
Finished Jun 02 03:09:10 PM PDT 24
Peak memory 248808 kb
Host smart-9f7e8b43-c108-4abd-ba8d-52d602d174fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750109243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.1750109243
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.3619377553
Short name T238
Test name
Test status
Simulation time 341825747 ps
CPU time 5.17 seconds
Started Jun 02 03:12:04 PM PDT 24
Finished Jun 02 03:12:09 PM PDT 24
Peak memory 242784 kb
Host smart-8192161e-2a8a-4cde-88f4-4a121462c844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619377553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.3619377553
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.2005614914
Short name T651
Test name
Test status
Simulation time 2168967001 ps
CPU time 6.87 seconds
Started Jun 02 03:12:06 PM PDT 24
Finished Jun 02 03:12:13 PM PDT 24
Peak memory 242784 kb
Host smart-0385187f-9311-4a77-bb28-267f1968c19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005614914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.2005614914
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.1794246416
Short name T801
Test name
Test status
Simulation time 1738698237 ps
CPU time 4.48 seconds
Started Jun 02 03:12:03 PM PDT 24
Finished Jun 02 03:12:08 PM PDT 24
Peak memory 242644 kb
Host smart-47b97cfd-ee40-4fee-ae92-1cc476712b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794246416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.1794246416
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.3879790090
Short name T522
Test name
Test status
Simulation time 199474983 ps
CPU time 4.25 seconds
Started Jun 02 03:12:04 PM PDT 24
Finished Jun 02 03:12:08 PM PDT 24
Peak memory 242348 kb
Host smart-49f8c197-6d62-42f9-9dad-7f81413666cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879790090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.3879790090
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.3303903020
Short name T959
Test name
Test status
Simulation time 127266001 ps
CPU time 4.14 seconds
Started Jun 02 03:12:02 PM PDT 24
Finished Jun 02 03:12:07 PM PDT 24
Peak memory 242236 kb
Host smart-02a2c6a2-f069-450b-bdc1-f3f354ac46bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303903020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.3303903020
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.1062634443
Short name T1077
Test name
Test status
Simulation time 118380408 ps
CPU time 4.4 seconds
Started Jun 02 03:12:06 PM PDT 24
Finished Jun 02 03:12:11 PM PDT 24
Peak memory 242472 kb
Host smart-6f93f36c-db00-4ab8-bf45-2121f314d4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062634443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.1062634443
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.2962853278
Short name T40
Test name
Test status
Simulation time 396600031 ps
CPU time 3.88 seconds
Started Jun 02 03:12:03 PM PDT 24
Finished Jun 02 03:12:07 PM PDT 24
Peak memory 242752 kb
Host smart-850462b6-1dca-43f6-ae31-8be37431e57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962853278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.2962853278
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.3852580299
Short name T824
Test name
Test status
Simulation time 2207438565 ps
CPU time 5.8 seconds
Started Jun 02 03:12:04 PM PDT 24
Finished Jun 02 03:12:10 PM PDT 24
Peak memory 242512 kb
Host smart-9bc850e2-c69a-4fe1-ac37-2a9b220493d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852580299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.3852580299
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.264764423
Short name T1091
Test name
Test status
Simulation time 140624138 ps
CPU time 4.48 seconds
Started Jun 02 03:12:02 PM PDT 24
Finished Jun 02 03:12:08 PM PDT 24
Peak memory 242364 kb
Host smart-97916af2-0531-4a31-aa64-16e60bf510ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264764423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.264764423
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.2602271681
Short name T768
Test name
Test status
Simulation time 207152473 ps
CPU time 2.04 seconds
Started Jun 02 03:09:03 PM PDT 24
Finished Jun 02 03:09:05 PM PDT 24
Peak memory 240828 kb
Host smart-5c5cdc84-376b-4d43-b98c-440ffe715603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602271681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.2602271681
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.3456666405
Short name T298
Test name
Test status
Simulation time 1827444806 ps
CPU time 13.61 seconds
Started Jun 02 03:09:04 PM PDT 24
Finished Jun 02 03:09:18 PM PDT 24
Peak memory 248876 kb
Host smart-aa45bf93-dd2d-4ddb-9164-980b813707fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456666405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.3456666405
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.2783214388
Short name T485
Test name
Test status
Simulation time 640260909 ps
CPU time 20.84 seconds
Started Jun 02 03:09:06 PM PDT 24
Finished Jun 02 03:09:27 PM PDT 24
Peak memory 242444 kb
Host smart-5c5d967b-8813-4ad9-9449-489c7b120dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783214388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.2783214388
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.4046245860
Short name T487
Test name
Test status
Simulation time 300499464 ps
CPU time 5.38 seconds
Started Jun 02 03:09:05 PM PDT 24
Finished Jun 02 03:09:11 PM PDT 24
Peak memory 242504 kb
Host smart-d90871b0-eb96-4533-b501-2adf816c6aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046245860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.4046245860
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.2737090286
Short name T30
Test name
Test status
Simulation time 296473715 ps
CPU time 4.35 seconds
Started Jun 02 03:09:05 PM PDT 24
Finished Jun 02 03:09:10 PM PDT 24
Peak memory 242648 kb
Host smart-2d963203-1fe6-42b0-b0a4-f76ab526c8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737090286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.2737090286
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.1974983301
Short name T897
Test name
Test status
Simulation time 18930951788 ps
CPU time 100.48 seconds
Started Jun 02 03:09:03 PM PDT 24
Finished Jun 02 03:10:44 PM PDT 24
Peak memory 257648 kb
Host smart-e070986e-2907-4b9e-815a-1980a415f280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974983301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.1974983301
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.3918907211
Short name T847
Test name
Test status
Simulation time 1377687683 ps
CPU time 33.26 seconds
Started Jun 02 03:09:05 PM PDT 24
Finished Jun 02 03:09:39 PM PDT 24
Peak memory 242464 kb
Host smart-4fea2762-deeb-430b-8131-5c0649cd5b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918907211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.3918907211
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.338646838
Short name T394
Test name
Test status
Simulation time 180527020 ps
CPU time 4.16 seconds
Started Jun 02 03:09:04 PM PDT 24
Finished Jun 02 03:09:09 PM PDT 24
Peak memory 242344 kb
Host smart-dd751558-1c9c-49fc-8f7f-8f645e4e880b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338646838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.338646838
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.74234184
Short name T610
Test name
Test status
Simulation time 1156282867 ps
CPU time 18.78 seconds
Started Jun 02 03:09:09 PM PDT 24
Finished Jun 02 03:09:29 PM PDT 24
Peak memory 242264 kb
Host smart-e4dc8877-38c6-4348-8d4c-d9491005defa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74234184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.74234184
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.2205448273
Short name T958
Test name
Test status
Simulation time 121277448 ps
CPU time 2.88 seconds
Started Jun 02 03:09:03 PM PDT 24
Finished Jun 02 03:09:07 PM PDT 24
Peak memory 242168 kb
Host smart-9319f09e-9165-4dff-b20f-0b0c65b29839
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2205448273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.2205448273
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.3877814700
Short name T753
Test name
Test status
Simulation time 543918867 ps
CPU time 5.9 seconds
Started Jun 02 03:09:03 PM PDT 24
Finished Jun 02 03:09:09 PM PDT 24
Peak memory 242184 kb
Host smart-93232776-2a0e-4ef1-9b2b-dbfae5c4ce2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877814700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.3877814700
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.3813561538
Short name T444
Test name
Test status
Simulation time 16315572781 ps
CPU time 162.85 seconds
Started Jun 02 03:09:04 PM PDT 24
Finished Jun 02 03:11:47 PM PDT 24
Peak memory 275708 kb
Host smart-fcaedee8-db12-4df8-8b06-9eb4c9c1a7b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813561538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.3813561538
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.12094147
Short name T303
Test name
Test status
Simulation time 285197635935 ps
CPU time 2374.69 seconds
Started Jun 02 03:09:05 PM PDT 24
Finished Jun 02 03:48:40 PM PDT 24
Peak memory 281944 kb
Host smart-92f041aa-0d5e-4cac-8c2e-a500458052b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12094147 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.12094147
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.861940504
Short name T528
Test name
Test status
Simulation time 1232592767 ps
CPU time 11.57 seconds
Started Jun 02 03:09:03 PM PDT 24
Finished Jun 02 03:09:15 PM PDT 24
Peak memory 242504 kb
Host smart-c1bd916b-176d-4886-bb9b-ae41bf85b68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861940504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.861940504
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.2560047962
Short name T975
Test name
Test status
Simulation time 2322174982 ps
CPU time 4.68 seconds
Started Jun 02 03:12:06 PM PDT 24
Finished Jun 02 03:12:12 PM PDT 24
Peak memory 242772 kb
Host smart-dcaf6fff-668f-4a4d-be74-2f8ff9214bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560047962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.2560047962
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.2053336478
Short name T1028
Test name
Test status
Simulation time 578557041 ps
CPU time 4.79 seconds
Started Jun 02 03:12:03 PM PDT 24
Finished Jun 02 03:12:08 PM PDT 24
Peak memory 242384 kb
Host smart-cdc8c027-5ba3-4ee4-ba80-f8df48cd8e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053336478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.2053336478
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.2328793507
Short name T44
Test name
Test status
Simulation time 247173166 ps
CPU time 3.88 seconds
Started Jun 02 03:12:01 PM PDT 24
Finished Jun 02 03:12:06 PM PDT 24
Peak memory 242464 kb
Host smart-2a9c0c58-1658-462d-9d84-3c463208ecd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328793507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.2328793507
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.1766533631
Short name T440
Test name
Test status
Simulation time 109061223 ps
CPU time 4.1 seconds
Started Jun 02 03:12:02 PM PDT 24
Finished Jun 02 03:12:07 PM PDT 24
Peak memory 242412 kb
Host smart-c9a5f50c-83b4-4fea-aaa0-15f8c14470e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766533631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.1766533631
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.1947785091
Short name T1140
Test name
Test status
Simulation time 238735040 ps
CPU time 3.8 seconds
Started Jun 02 03:12:06 PM PDT 24
Finished Jun 02 03:12:11 PM PDT 24
Peak memory 242680 kb
Host smart-e8fc7a89-3ef6-4faf-95e2-ab70277b9419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947785091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.1947785091
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.272137822
Short name T785
Test name
Test status
Simulation time 222362793 ps
CPU time 3.83 seconds
Started Jun 02 03:12:04 PM PDT 24
Finished Jun 02 03:12:09 PM PDT 24
Peak memory 242360 kb
Host smart-ec76ffba-87b5-4544-a1f1-7822e5d4ed4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272137822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.272137822
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.3573089243
Short name T667
Test name
Test status
Simulation time 235522897 ps
CPU time 4.31 seconds
Started Jun 02 03:12:05 PM PDT 24
Finished Jun 02 03:12:10 PM PDT 24
Peak memory 242340 kb
Host smart-c0d78827-4cfe-4acc-a322-966165fb9e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573089243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.3573089243
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.1454745903
Short name T60
Test name
Test status
Simulation time 448977120 ps
CPU time 4.96 seconds
Started Jun 02 03:12:06 PM PDT 24
Finished Jun 02 03:12:11 PM PDT 24
Peak memory 242396 kb
Host smart-25506314-5f43-41ab-ad29-9d93174b8814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454745903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.1454745903
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.792900891
Short name T707
Test name
Test status
Simulation time 488311835 ps
CPU time 5.64 seconds
Started Jun 02 03:12:06 PM PDT 24
Finished Jun 02 03:12:12 PM PDT 24
Peak memory 242320 kb
Host smart-d87e0cfe-d8ad-46e0-8c1d-12a27e556e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792900891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.792900891
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.4097251298
Short name T789
Test name
Test status
Simulation time 2358049426 ps
CPU time 7.8 seconds
Started Jun 02 03:12:03 PM PDT 24
Finished Jun 02 03:12:11 PM PDT 24
Peak memory 242352 kb
Host smart-3de55911-1ee7-476c-8b93-3cb908b317fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097251298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.4097251298
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.2829270848
Short name T1007
Test name
Test status
Simulation time 151470062 ps
CPU time 2.52 seconds
Started Jun 02 03:07:41 PM PDT 24
Finished Jun 02 03:07:44 PM PDT 24
Peak memory 241204 kb
Host smart-34579a00-f394-40b8-b2fb-67744771e2f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829270848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.2829270848
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.3846575553
Short name T1117
Test name
Test status
Simulation time 11983115070 ps
CPU time 26.01 seconds
Started Jun 02 03:07:37 PM PDT 24
Finished Jun 02 03:08:04 PM PDT 24
Peak memory 243004 kb
Host smart-5145bd76-d0fa-459a-a919-c87554bd8bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846575553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.3846575553
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.3600221334
Short name T1005
Test name
Test status
Simulation time 2121062295 ps
CPU time 12.8 seconds
Started Jun 02 03:07:39 PM PDT 24
Finished Jun 02 03:07:53 PM PDT 24
Peak memory 242652 kb
Host smart-c3182fd8-cb46-4c1c-9099-4d8563e0253a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600221334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.3600221334
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.917367822
Short name T403
Test name
Test status
Simulation time 1001517541 ps
CPU time 17.5 seconds
Started Jun 02 03:07:37 PM PDT 24
Finished Jun 02 03:07:55 PM PDT 24
Peak memory 242364 kb
Host smart-d0494766-3484-4dd9-aaee-47c67ed327e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917367822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.917367822
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.1605162104
Short name T846
Test name
Test status
Simulation time 2990908734 ps
CPU time 26.38 seconds
Started Jun 02 03:07:35 PM PDT 24
Finished Jun 02 03:08:02 PM PDT 24
Peak memory 243052 kb
Host smart-5a52c70f-b53d-412a-b1b9-275590cedad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605162104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.1605162104
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.1193383197
Short name T745
Test name
Test status
Simulation time 140465742 ps
CPU time 3.55 seconds
Started Jun 02 03:07:34 PM PDT 24
Finished Jun 02 03:07:38 PM PDT 24
Peak memory 242412 kb
Host smart-a2306d65-a8cc-418c-b030-54d322582c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193383197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.1193383197
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.1350993146
Short name T553
Test name
Test status
Simulation time 135578931 ps
CPU time 5.48 seconds
Started Jun 02 03:07:40 PM PDT 24
Finished Jun 02 03:07:46 PM PDT 24
Peak memory 242324 kb
Host smart-83e27976-aef2-4398-9352-7a3d70df4c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350993146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.1350993146
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.1166121910
Short name T643
Test name
Test status
Simulation time 607290011 ps
CPU time 15.07 seconds
Started Jun 02 03:07:46 PM PDT 24
Finished Jun 02 03:08:02 PM PDT 24
Peak memory 242440 kb
Host smart-e588a744-077e-4c40-ae4f-8e40440a34aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166121910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.1166121910
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.3068694369
Short name T752
Test name
Test status
Simulation time 1479951683 ps
CPU time 14.05 seconds
Started Jun 02 03:07:35 PM PDT 24
Finished Jun 02 03:07:50 PM PDT 24
Peak memory 242228 kb
Host smart-b277633f-a0ba-4717-b414-128277e48ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068694369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.3068694369
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.3161671454
Short name T399
Test name
Test status
Simulation time 286894157 ps
CPU time 4.71 seconds
Started Jun 02 03:07:37 PM PDT 24
Finished Jun 02 03:07:42 PM PDT 24
Peak memory 248004 kb
Host smart-cddbbbd3-e1fa-40bb-af94-747e0029ce05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3161671454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.3161671454
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.2627621231
Short name T580
Test name
Test status
Simulation time 122548990 ps
CPU time 5.32 seconds
Started Jun 02 03:07:42 PM PDT 24
Finished Jun 02 03:07:48 PM PDT 24
Peak memory 242488 kb
Host smart-1191c29c-a280-4542-8da6-30eda15cd083
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627621231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.2627621231
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.2172748875
Short name T246
Test name
Test status
Simulation time 156229206937 ps
CPU time 204.46 seconds
Started Jun 02 03:07:44 PM PDT 24
Finished Jun 02 03:11:10 PM PDT 24
Peak memory 266700 kb
Host smart-27473853-579c-470f-8aa9-a87dcafbebcd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172748875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.2172748875
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.2495579724
Short name T811
Test name
Test status
Simulation time 441208490 ps
CPU time 7.76 seconds
Started Jun 02 03:07:35 PM PDT 24
Finished Jun 02 03:07:44 PM PDT 24
Peak memory 242396 kb
Host smart-f968f812-637b-43ac-b26e-6bff71733e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495579724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.2495579724
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.4181393737
Short name T1106
Test name
Test status
Simulation time 8270976145 ps
CPU time 77.27 seconds
Started Jun 02 03:07:43 PM PDT 24
Finished Jun 02 03:09:01 PM PDT 24
Peak memory 245316 kb
Host smart-ff46ddd3-742c-4b2f-9d6a-4f7259c3c677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181393737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.
4181393737
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.3712359195
Short name T1148
Test name
Test status
Simulation time 177598321628 ps
CPU time 1253.05 seconds
Started Jun 02 03:07:44 PM PDT 24
Finished Jun 02 03:28:37 PM PDT 24
Peak memory 303716 kb
Host smart-d7fdd7ef-4959-4c8a-9446-f1a742d54cd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712359195 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.3712359195
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.2282275953
Short name T104
Test name
Test status
Simulation time 1653809944 ps
CPU time 38.99 seconds
Started Jun 02 03:07:42 PM PDT 24
Finished Jun 02 03:08:22 PM PDT 24
Peak memory 248856 kb
Host smart-38f4cb09-9869-47dc-8b2c-aac6302be2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282275953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.2282275953
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.2276884314
Short name T684
Test name
Test status
Simulation time 1010281152 ps
CPU time 2.07 seconds
Started Jun 02 03:09:09 PM PDT 24
Finished Jun 02 03:09:12 PM PDT 24
Peak memory 241036 kb
Host smart-7e242422-0421-4301-8cab-28af528a1fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276884314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.2276884314
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.4249549350
Short name T477
Test name
Test status
Simulation time 1019266988 ps
CPU time 20.54 seconds
Started Jun 02 03:09:05 PM PDT 24
Finished Jun 02 03:09:26 PM PDT 24
Peak memory 243044 kb
Host smart-99880634-048c-4ab0-8518-6ba21c1981c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249549350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.4249549350
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.517432104
Short name T574
Test name
Test status
Simulation time 2995403255 ps
CPU time 40.68 seconds
Started Jun 02 03:09:03 PM PDT 24
Finished Jun 02 03:09:44 PM PDT 24
Peak memory 250040 kb
Host smart-40705c37-34bb-4cd7-bb66-b5b27f5ef23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517432104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.517432104
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.788030735
Short name T962
Test name
Test status
Simulation time 805986282 ps
CPU time 24.88 seconds
Started Jun 02 03:09:05 PM PDT 24
Finished Jun 02 03:09:31 PM PDT 24
Peak memory 242256 kb
Host smart-d4e7eb3b-33d9-4234-81c2-3992af1c9d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788030735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.788030735
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.1217732686
Short name T548
Test name
Test status
Simulation time 1753721381 ps
CPU time 5.42 seconds
Started Jun 02 03:09:03 PM PDT 24
Finished Jun 02 03:09:09 PM PDT 24
Peak memory 242692 kb
Host smart-f80098d9-68ca-40fb-8239-76da1b1fb0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217732686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.1217732686
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.3544761992
Short name T461
Test name
Test status
Simulation time 1826226794 ps
CPU time 29.95 seconds
Started Jun 02 03:09:04 PM PDT 24
Finished Jun 02 03:09:35 PM PDT 24
Peak memory 244140 kb
Host smart-efdb7ff0-232b-41ee-ac30-650d38e340d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544761992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.3544761992
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.2465971299
Short name T935
Test name
Test status
Simulation time 874262703 ps
CPU time 11.38 seconds
Started Jun 02 03:09:04 PM PDT 24
Finished Jun 02 03:09:16 PM PDT 24
Peak memory 248832 kb
Host smart-01f08efa-5a4e-4d41-ae9a-729dbf9c5fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465971299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.2465971299
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.143351188
Short name T263
Test name
Test status
Simulation time 6327472792 ps
CPU time 12.23 seconds
Started Jun 02 03:09:02 PM PDT 24
Finished Jun 02 03:09:15 PM PDT 24
Peak memory 242268 kb
Host smart-11f175b9-adb7-4f05-b2f3-728eb4311f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143351188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.143351188
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.2039936314
Short name T459
Test name
Test status
Simulation time 7374570126 ps
CPU time 23.46 seconds
Started Jun 02 03:09:09 PM PDT 24
Finished Jun 02 03:09:33 PM PDT 24
Peak memory 242388 kb
Host smart-9d3dee71-9c85-4ef5-aa13-ba6e75dc23a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2039936314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.2039936314
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.2699880341
Short name T830
Test name
Test status
Simulation time 534974525 ps
CPU time 6.62 seconds
Started Jun 02 03:09:03 PM PDT 24
Finished Jun 02 03:09:10 PM PDT 24
Peak memory 242140 kb
Host smart-70f1a108-4314-4066-bfee-b184886d0190
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2699880341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.2699880341
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.2708736281
Short name T413
Test name
Test status
Simulation time 9696388151 ps
CPU time 25.47 seconds
Started Jun 02 03:09:02 PM PDT 24
Finished Jun 02 03:09:28 PM PDT 24
Peak memory 242444 kb
Host smart-2d63cdee-1f52-4201-961f-6845f70e9b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708736281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.2708736281
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.2575878247
Short name T702
Test name
Test status
Simulation time 1152999946 ps
CPU time 21.92 seconds
Started Jun 02 03:09:10 PM PDT 24
Finished Jun 02 03:09:32 PM PDT 24
Peak memory 241908 kb
Host smart-01e44f09-9e75-4912-8170-ffd20c89824d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575878247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all
.2575878247
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.1692571063
Short name T706
Test name
Test status
Simulation time 1073569841 ps
CPU time 23.59 seconds
Started Jun 02 03:09:04 PM PDT 24
Finished Jun 02 03:09:28 PM PDT 24
Peak memory 242460 kb
Host smart-c26642b3-81d8-4c4e-974f-7df00b373331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692571063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.1692571063
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.3079900297
Short name T1098
Test name
Test status
Simulation time 77157506 ps
CPU time 1.99 seconds
Started Jun 02 03:09:09 PM PDT 24
Finished Jun 02 03:09:12 PM PDT 24
Peak memory 240812 kb
Host smart-28cdd8f0-7e25-4e6f-bdc6-35cbe40774c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079900297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.3079900297
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.469664561
Short name T960
Test name
Test status
Simulation time 1406373631 ps
CPU time 16.3 seconds
Started Jun 02 03:09:09 PM PDT 24
Finished Jun 02 03:09:26 PM PDT 24
Peak memory 248956 kb
Host smart-28722fd9-dac5-44cf-869b-f897fae4ecfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469664561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.469664561
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.1109558816
Short name T608
Test name
Test status
Simulation time 1443438346 ps
CPU time 22.31 seconds
Started Jun 02 03:09:10 PM PDT 24
Finished Jun 02 03:09:33 PM PDT 24
Peak memory 242288 kb
Host smart-50343fc8-1621-45a4-ba95-99621a5cad4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109558816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.1109558816
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.2804829470
Short name T803
Test name
Test status
Simulation time 301080885 ps
CPU time 5.08 seconds
Started Jun 02 03:09:08 PM PDT 24
Finished Jun 02 03:09:14 PM PDT 24
Peak memory 242316 kb
Host smart-60b24dbf-7705-4192-aae8-2c37535d6915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804829470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.2804829470
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.617476856
Short name T465
Test name
Test status
Simulation time 384561059 ps
CPU time 3.34 seconds
Started Jun 02 03:09:09 PM PDT 24
Finished Jun 02 03:09:13 PM PDT 24
Peak memory 242328 kb
Host smart-7f7601e4-a5e1-4411-a1fe-91e8f5ea9497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617476856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.617476856
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.1802698261
Short name T1147
Test name
Test status
Simulation time 504409161 ps
CPU time 8.75 seconds
Started Jun 02 03:09:12 PM PDT 24
Finished Jun 02 03:09:21 PM PDT 24
Peak memory 242416 kb
Host smart-f21b02e9-5694-4899-beb8-2d3499124c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802698261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.1802698261
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.4149853784
Short name T896
Test name
Test status
Simulation time 435616787 ps
CPU time 17.52 seconds
Started Jun 02 03:09:08 PM PDT 24
Finished Jun 02 03:09:26 PM PDT 24
Peak memory 248876 kb
Host smart-f9cc96be-2494-44d0-a459-4f5e9b46c2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149853784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.4149853784
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.670087942
Short name T1009
Test name
Test status
Simulation time 1739103914 ps
CPU time 7.3 seconds
Started Jun 02 03:09:09 PM PDT 24
Finished Jun 02 03:09:17 PM PDT 24
Peak memory 242200 kb
Host smart-82395c22-2aa9-4f1d-b3ef-92a460b4151a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670087942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.670087942
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.1664327972
Short name T1059
Test name
Test status
Simulation time 1122538446 ps
CPU time 24.06 seconds
Started Jun 02 03:09:10 PM PDT 24
Finished Jun 02 03:09:35 PM PDT 24
Peak memory 242212 kb
Host smart-edf759de-499c-40f1-ae1c-8a1d394c8bed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1664327972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.1664327972
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.856658922
Short name T376
Test name
Test status
Simulation time 4741125017 ps
CPU time 13 seconds
Started Jun 02 03:09:08 PM PDT 24
Finished Jun 02 03:09:21 PM PDT 24
Peak memory 242616 kb
Host smart-0ae8b580-c54c-44ef-91aa-3bc7277a436a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=856658922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.856658922
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.3695003864
Short name T478
Test name
Test status
Simulation time 348279661 ps
CPU time 10.57 seconds
Started Jun 02 03:09:08 PM PDT 24
Finished Jun 02 03:09:19 PM PDT 24
Peak memory 242284 kb
Host smart-b5c479db-a5b9-42a6-b31b-6afe1a4b9d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695003864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.3695003864
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.4246784397
Short name T119
Test name
Test status
Simulation time 9074422448 ps
CPU time 163.19 seconds
Started Jun 02 03:09:12 PM PDT 24
Finished Jun 02 03:11:56 PM PDT 24
Peak memory 265496 kb
Host smart-4f1af083-7907-4429-9b99-f296daa584e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246784397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.4246784397
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.1960159946
Short name T1026
Test name
Test status
Simulation time 141363833309 ps
CPU time 2271.42 seconds
Started Jun 02 03:09:10 PM PDT 24
Finished Jun 02 03:47:02 PM PDT 24
Peak memory 299464 kb
Host smart-79f259f7-9235-4f14-b28a-c30917061391
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960159946 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.1960159946
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.3735230566
Short name T410
Test name
Test status
Simulation time 901583973 ps
CPU time 6.75 seconds
Started Jun 02 03:09:07 PM PDT 24
Finished Jun 02 03:09:14 PM PDT 24
Peak memory 242568 kb
Host smart-ddce689b-46f4-43a8-b8a8-890aa63952c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735230566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.3735230566
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.169236845
Short name T658
Test name
Test status
Simulation time 70945168 ps
CPU time 1.79 seconds
Started Jun 02 03:09:14 PM PDT 24
Finished Jun 02 03:09:16 PM PDT 24
Peak memory 240804 kb
Host smart-e057b280-3289-4241-8fba-0c6bccca614e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169236845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.169236845
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.1838166143
Short name T12
Test name
Test status
Simulation time 3162495067 ps
CPU time 18.51 seconds
Started Jun 02 03:09:08 PM PDT 24
Finished Jun 02 03:09:27 PM PDT 24
Peak memory 248948 kb
Host smart-4cfe6c2e-d77a-4797-9b35-9e84e418248a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838166143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.1838166143
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.4065273060
Short name T519
Test name
Test status
Simulation time 1482748838 ps
CPU time 21.18 seconds
Started Jun 02 03:09:08 PM PDT 24
Finished Jun 02 03:09:30 PM PDT 24
Peak memory 242716 kb
Host smart-d2b05d73-7a9b-41dd-a8ba-75b30f656a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065273060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.4065273060
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.4254389089
Short name T1196
Test name
Test status
Simulation time 6190339160 ps
CPU time 33.95 seconds
Started Jun 02 03:09:08 PM PDT 24
Finished Jun 02 03:09:43 PM PDT 24
Peak memory 242244 kb
Host smart-5856c8ae-30f9-4a31-8e0d-11cb5cea0b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254389089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.4254389089
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.226692480
Short name T879
Test name
Test status
Simulation time 2202979095 ps
CPU time 5.12 seconds
Started Jun 02 03:09:14 PM PDT 24
Finished Jun 02 03:09:19 PM PDT 24
Peak memory 242508 kb
Host smart-5d762d55-fee3-4b66-9bdd-cd3f76e40217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226692480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.226692480
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.4250079733
Short name T315
Test name
Test status
Simulation time 2093992193 ps
CPU time 31.48 seconds
Started Jun 02 03:09:08 PM PDT 24
Finished Jun 02 03:09:41 PM PDT 24
Peak memory 242512 kb
Host smart-30474842-4c0b-4991-a7f9-1d288ecdf0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250079733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.4250079733
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.2699732522
Short name T568
Test name
Test status
Simulation time 428736779 ps
CPU time 13 seconds
Started Jun 02 03:09:10 PM PDT 24
Finished Jun 02 03:09:24 PM PDT 24
Peak memory 242392 kb
Host smart-540e4767-ea74-486d-93a6-9dba410e48f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699732522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.2699732522
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.131617917
Short name T955
Test name
Test status
Simulation time 900277341 ps
CPU time 10.69 seconds
Started Jun 02 03:09:08 PM PDT 24
Finished Jun 02 03:09:19 PM PDT 24
Peak memory 242268 kb
Host smart-6303c72b-2547-43e7-accf-fc54806fddcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=131617917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.131617917
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.2257066817
Short name T370
Test name
Test status
Simulation time 359827064 ps
CPU time 9.65 seconds
Started Jun 02 03:09:08 PM PDT 24
Finished Jun 02 03:09:19 PM PDT 24
Peak memory 242212 kb
Host smart-9e0b6ab6-8e31-4f64-89b6-f4f31cf7fea7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2257066817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.2257066817
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.2089000926
Short name T783
Test name
Test status
Simulation time 2479912146 ps
CPU time 7.37 seconds
Started Jun 02 03:09:12 PM PDT 24
Finished Jun 02 03:09:20 PM PDT 24
Peak memory 242364 kb
Host smart-7c8c051e-ed8d-40ee-9f24-55d811dbc18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089000926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.2089000926
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.4226607681
Short name T596
Test name
Test status
Simulation time 6711101480 ps
CPU time 61.16 seconds
Started Jun 02 03:09:17 PM PDT 24
Finished Jun 02 03:10:19 PM PDT 24
Peak memory 244536 kb
Host smart-5b40e266-8290-43ea-a130-dcfea45dd341
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226607681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all
.4226607681
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.2540398496
Short name T243
Test name
Test status
Simulation time 252563404592 ps
CPU time 1422.69 seconds
Started Jun 02 03:09:12 PM PDT 24
Finished Jun 02 03:32:56 PM PDT 24
Peak memory 281472 kb
Host smart-7f761853-7bb1-40cf-9acc-0aebf28caedf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540398496 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.2540398496
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.803542703
Short name T939
Test name
Test status
Simulation time 6898905763 ps
CPU time 11.79 seconds
Started Jun 02 03:09:10 PM PDT 24
Finished Jun 02 03:09:23 PM PDT 24
Peak memory 248948 kb
Host smart-f471bd1e-5cbc-46cb-a4c0-02bb19a791da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803542703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.803542703
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.2522494612
Short name T90
Test name
Test status
Simulation time 50722234 ps
CPU time 1.71 seconds
Started Jun 02 03:09:20 PM PDT 24
Finished Jun 02 03:09:23 PM PDT 24
Peak memory 240840 kb
Host smart-f7cc0940-d7c4-4d6d-91cb-ae49f6ccd7be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522494612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.2522494612
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.751282849
Short name T715
Test name
Test status
Simulation time 3194938284 ps
CPU time 33.47 seconds
Started Jun 02 03:09:16 PM PDT 24
Finished Jun 02 03:09:50 PM PDT 24
Peak memory 242732 kb
Host smart-1f65039a-1854-47fd-8d2e-27f1b7917537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751282849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.751282849
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.3742968727
Short name T475
Test name
Test status
Simulation time 1086805228 ps
CPU time 32.16 seconds
Started Jun 02 03:09:19 PM PDT 24
Finished Jun 02 03:09:52 PM PDT 24
Peak memory 242844 kb
Host smart-fba5818b-9793-4543-8c36-b08fd619577b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742968727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.3742968727
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.544306983
Short name T508
Test name
Test status
Simulation time 4163343651 ps
CPU time 57.92 seconds
Started Jun 02 03:09:18 PM PDT 24
Finished Jun 02 03:10:16 PM PDT 24
Peak memory 243220 kb
Host smart-0cf579b0-5ff5-4e29-a1f0-d5ad2f73b54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544306983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.544306983
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.1138352561
Short name T24
Test name
Test status
Simulation time 166376668 ps
CPU time 4.65 seconds
Started Jun 02 03:09:13 PM PDT 24
Finished Jun 02 03:09:18 PM PDT 24
Peak memory 242684 kb
Host smart-a54fbdef-160d-4d09-bbc6-bbda10ed56fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138352561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.1138352561
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.290279845
Short name T973
Test name
Test status
Simulation time 1304258217 ps
CPU time 12.89 seconds
Started Jun 02 03:09:19 PM PDT 24
Finished Jun 02 03:09:32 PM PDT 24
Peak memory 244824 kb
Host smart-bf1741cf-973e-4a62-abb9-3e79ccf1dce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290279845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.290279845
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.3277182510
Short name T814
Test name
Test status
Simulation time 432742814 ps
CPU time 13.19 seconds
Started Jun 02 03:09:22 PM PDT 24
Finished Jun 02 03:09:36 PM PDT 24
Peak memory 242276 kb
Host smart-7ce57cce-d0fb-4dc8-9df8-0e6e7b8aecb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277182510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.3277182510
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.3266625029
Short name T1071
Test name
Test status
Simulation time 267840122 ps
CPU time 7.95 seconds
Started Jun 02 03:09:15 PM PDT 24
Finished Jun 02 03:09:23 PM PDT 24
Peak memory 242396 kb
Host smart-cafe03b4-9f47-44cb-b919-5a91f62d60c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266625029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.3266625029
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.1823033106
Short name T460
Test name
Test status
Simulation time 1295162596 ps
CPU time 16.55 seconds
Started Jun 02 03:09:13 PM PDT 24
Finished Jun 02 03:09:30 PM PDT 24
Peak memory 242232 kb
Host smart-909f68e2-9b07-4ae2-b5f3-1f52751350f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1823033106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.1823033106
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.3418248149
Short name T1002
Test name
Test status
Simulation time 979136892 ps
CPU time 7.89 seconds
Started Jun 02 03:09:19 PM PDT 24
Finished Jun 02 03:09:28 PM PDT 24
Peak memory 242292 kb
Host smart-18882637-93f9-4a04-b795-6d59e5933095
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3418248149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.3418248149
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.2019060373
Short name T583
Test name
Test status
Simulation time 252913162 ps
CPU time 5.06 seconds
Started Jun 02 03:09:13 PM PDT 24
Finished Jun 02 03:09:18 PM PDT 24
Peak memory 242600 kb
Host smart-22688c05-746f-4335-a6d4-644d31f76ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019060373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.2019060373
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.3039763093
Short name T132
Test name
Test status
Simulation time 49397279641 ps
CPU time 532.4 seconds
Started Jun 02 03:09:17 PM PDT 24
Finished Jun 02 03:18:10 PM PDT 24
Peak memory 322716 kb
Host smart-a56b6ead-2ff2-4814-a96f-da18a4d56781
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039763093 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.3039763093
Directory /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.1034249583
Short name T1029
Test name
Test status
Simulation time 438431143 ps
CPU time 10.46 seconds
Started Jun 02 03:09:21 PM PDT 24
Finished Jun 02 03:09:32 PM PDT 24
Peak memory 242256 kb
Host smart-3dbed0e2-34a3-43dd-9d48-167d04ea6010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034249583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.1034249583
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.3439317428
Short name T296
Test name
Test status
Simulation time 605161163 ps
CPU time 1.84 seconds
Started Jun 02 03:09:18 PM PDT 24
Finished Jun 02 03:09:20 PM PDT 24
Peak memory 240756 kb
Host smart-a2ed6d2f-df9d-48f9-aa13-f523191acbbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439317428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.3439317428
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.1510972311
Short name T980
Test name
Test status
Simulation time 1884048420 ps
CPU time 18.19 seconds
Started Jun 02 03:09:18 PM PDT 24
Finished Jun 02 03:09:37 PM PDT 24
Peak memory 242888 kb
Host smart-b2fc0983-56f0-419b-b2bf-a1405e3da84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510972311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.1510972311
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.2172733534
Short name T1069
Test name
Test status
Simulation time 5009816191 ps
CPU time 23.48 seconds
Started Jun 02 03:09:21 PM PDT 24
Finished Jun 02 03:09:45 PM PDT 24
Peak memory 242780 kb
Host smart-64420c71-4341-41db-b4ae-2677f1f21227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172733534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.2172733534
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.3196545274
Short name T1057
Test name
Test status
Simulation time 12296927531 ps
CPU time 26.91 seconds
Started Jun 02 03:09:23 PM PDT 24
Finished Jun 02 03:09:50 PM PDT 24
Peak memory 243648 kb
Host smart-136f7ddf-95b9-4b33-b070-4ee75d16a2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196545274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.3196545274
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.94990782
Short name T731
Test name
Test status
Simulation time 102917784 ps
CPU time 4.06 seconds
Started Jun 02 03:09:20 PM PDT 24
Finished Jun 02 03:09:24 PM PDT 24
Peak memory 242660 kb
Host smart-f590ffb1-9040-4576-9ba6-705f2ad54a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94990782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.94990782
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.94016679
Short name T767
Test name
Test status
Simulation time 149289466 ps
CPU time 4.23 seconds
Started Jun 02 03:09:22 PM PDT 24
Finished Jun 02 03:09:27 PM PDT 24
Peak memory 248888 kb
Host smart-f9b6edf8-672c-4f04-bdd3-ce74c90b3d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94016679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.94016679
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.836602822
Short name T712
Test name
Test status
Simulation time 4450169741 ps
CPU time 13.02 seconds
Started Jun 02 03:09:22 PM PDT 24
Finished Jun 02 03:09:36 PM PDT 24
Peak memory 242992 kb
Host smart-7b1d9396-0570-4184-9241-e03f3554d47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836602822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.836602822
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.11400099
Short name T116
Test name
Test status
Simulation time 346177278 ps
CPU time 5.25 seconds
Started Jun 02 03:09:19 PM PDT 24
Finished Jun 02 03:09:25 PM PDT 24
Peak memory 242472 kb
Host smart-9e7b12ca-548c-4220-90f3-3548ac12b35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11400099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.11400099
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.2701920
Short name T661
Test name
Test status
Simulation time 658815348 ps
CPU time 5.98 seconds
Started Jun 02 03:09:21 PM PDT 24
Finished Jun 02 03:09:28 PM PDT 24
Peak memory 242320 kb
Host smart-73d3c4d2-59f3-42dc-b066-a61ec06a31a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2701920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.2701920
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.118750197
Short name T748
Test name
Test status
Simulation time 1514570541 ps
CPU time 4.26 seconds
Started Jun 02 03:09:17 PM PDT 24
Finished Jun 02 03:09:22 PM PDT 24
Peak memory 242176 kb
Host smart-020c399a-ef9e-4f03-bf2a-7ae2c5698395
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=118750197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.118750197
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.1662155053
Short name T721
Test name
Test status
Simulation time 485599332 ps
CPU time 6.08 seconds
Started Jun 02 03:09:22 PM PDT 24
Finished Jun 02 03:09:28 PM PDT 24
Peak memory 242232 kb
Host smart-4d6f97d1-c852-46f6-9bf0-4bd9976b1b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662155053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.1662155053
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.1299629957
Short name T63
Test name
Test status
Simulation time 3456019152 ps
CPU time 39.12 seconds
Started Jun 02 03:09:19 PM PDT 24
Finished Jun 02 03:09:58 PM PDT 24
Peak memory 243492 kb
Host smart-effa6858-b1e4-48b8-ba3e-d7b748bbbe6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299629957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.1299629957
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.4174125917
Short name T969
Test name
Test status
Simulation time 75533628339 ps
CPU time 475.34 seconds
Started Jun 02 03:09:21 PM PDT 24
Finished Jun 02 03:17:17 PM PDT 24
Peak memory 257368 kb
Host smart-dfff3ec6-2c18-4c8f-a6f5-620c34a72b4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174125917 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.4174125917
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.2774751046
Short name T587
Test name
Test status
Simulation time 1034754227 ps
CPU time 2.93 seconds
Started Jun 02 03:09:28 PM PDT 24
Finished Jun 02 03:09:32 PM PDT 24
Peak memory 240976 kb
Host smart-4ed32669-d071-49c2-b67d-b9776980f897
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774751046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.2774751046
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.343738207
Short name T1046
Test name
Test status
Simulation time 299194437 ps
CPU time 18.04 seconds
Started Jun 02 03:09:24 PM PDT 24
Finished Jun 02 03:09:42 PM PDT 24
Peak memory 242548 kb
Host smart-b27b01b5-c741-4e9e-b58f-0b9c04241ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343738207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.343738207
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.3960315479
Short name T930
Test name
Test status
Simulation time 929352839 ps
CPU time 35.56 seconds
Started Jun 02 03:09:25 PM PDT 24
Finished Jun 02 03:10:01 PM PDT 24
Peak memory 242264 kb
Host smart-306731b6-5483-4de8-9223-bc435f553cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960315479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.3960315479
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.2723456030
Short name T970
Test name
Test status
Simulation time 201799723 ps
CPU time 3.98 seconds
Started Jun 02 03:09:23 PM PDT 24
Finished Jun 02 03:09:27 PM PDT 24
Peak memory 242552 kb
Host smart-2c04528b-0a8d-4b7a-8ec7-372333ec3642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723456030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.2723456030
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.3105289030
Short name T223
Test name
Test status
Simulation time 449215973 ps
CPU time 8.64 seconds
Started Jun 02 03:09:25 PM PDT 24
Finished Jun 02 03:09:34 PM PDT 24
Peak memory 242260 kb
Host smart-a141adbc-478f-4515-a3df-7abc13ca8196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105289030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.3105289030
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.3356485943
Short name T1027
Test name
Test status
Simulation time 974622789 ps
CPU time 14.42 seconds
Started Jun 02 03:09:23 PM PDT 24
Finished Jun 02 03:09:38 PM PDT 24
Peak memory 242448 kb
Host smart-a912f6e5-fe08-4778-bb5f-9d2a09d99fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356485943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.3356485943
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.4199543897
Short name T142
Test name
Test status
Simulation time 4382821790 ps
CPU time 10.54 seconds
Started Jun 02 03:09:26 PM PDT 24
Finished Jun 02 03:09:37 PM PDT 24
Peak memory 242672 kb
Host smart-5fca3758-b336-46e0-99a9-18c724f77b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199543897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.4199543897
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.2943710453
Short name T326
Test name
Test status
Simulation time 256047884 ps
CPU time 8.34 seconds
Started Jun 02 03:09:27 PM PDT 24
Finished Jun 02 03:09:36 PM PDT 24
Peak memory 248864 kb
Host smart-06979a1d-ac52-4dc2-9756-c7000ead4b8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2943710453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.2943710453
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.4074568112
Short name T1149
Test name
Test status
Simulation time 1869186185 ps
CPU time 5.42 seconds
Started Jun 02 03:09:28 PM PDT 24
Finished Jun 02 03:09:34 PM PDT 24
Peak memory 242168 kb
Host smart-8c8e72ad-468f-46d8-a828-1022e7bc5587
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074568112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.4074568112
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.1388039739
Short name T1185
Test name
Test status
Simulation time 709291839 ps
CPU time 7.45 seconds
Started Jun 02 03:09:27 PM PDT 24
Finished Jun 02 03:09:36 PM PDT 24
Peak memory 248556 kb
Host smart-33f6f915-13fe-4c4c-a81d-73a3e38eaeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388039739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.1388039739
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.3907369662
Short name T16
Test name
Test status
Simulation time 75997917689 ps
CPU time 290.72 seconds
Started Jun 02 03:09:24 PM PDT 24
Finished Jun 02 03:14:15 PM PDT 24
Peak memory 249260 kb
Host smart-2f827e3d-9382-4730-a3ab-4b41b4a710bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907369662 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.3907369662
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.620423124
Short name T531
Test name
Test status
Simulation time 3744383405 ps
CPU time 37.35 seconds
Started Jun 02 03:09:25 PM PDT 24
Finished Jun 02 03:10:03 PM PDT 24
Peak memory 243372 kb
Host smart-0b55bfd0-0947-4eee-ba65-b009a8397c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620423124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.620423124
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.4194716386
Short name T688
Test name
Test status
Simulation time 48645363 ps
CPU time 1.82 seconds
Started Jun 02 03:09:30 PM PDT 24
Finished Jun 02 03:09:33 PM PDT 24
Peak memory 240904 kb
Host smart-7efa4774-2db3-41ff-b26a-47e32c7bff9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194716386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.4194716386
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.979653833
Short name T122
Test name
Test status
Simulation time 10505778191 ps
CPU time 21.31 seconds
Started Jun 02 03:09:28 PM PDT 24
Finished Jun 02 03:09:50 PM PDT 24
Peak memory 242864 kb
Host smart-56f96b63-b467-44c7-b9a2-e1f3ce6c3fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979653833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.979653833
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.2325673144
Short name T749
Test name
Test status
Simulation time 388699779 ps
CPU time 10.56 seconds
Started Jun 02 03:09:27 PM PDT 24
Finished Jun 02 03:09:39 PM PDT 24
Peak memory 242412 kb
Host smart-6f63d763-bf74-4208-82f0-0519e871f261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325673144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.2325673144
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.2243392901
Short name T577
Test name
Test status
Simulation time 3172771412 ps
CPU time 33.07 seconds
Started Jun 02 03:09:25 PM PDT 24
Finished Jun 02 03:09:59 PM PDT 24
Peak memory 242804 kb
Host smart-72875ca9-8f8a-4e9e-8793-7a1cc62a9be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243392901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.2243392901
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.3246501220
Short name T507
Test name
Test status
Simulation time 649382931 ps
CPU time 5.22 seconds
Started Jun 02 03:09:24 PM PDT 24
Finished Jun 02 03:09:30 PM PDT 24
Peak memory 242408 kb
Host smart-7c674c12-085a-4051-a152-e9c77fee1677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246501220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.3246501220
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.1424697677
Short name T843
Test name
Test status
Simulation time 504814173 ps
CPU time 5.84 seconds
Started Jun 02 03:09:28 PM PDT 24
Finished Jun 02 03:09:35 PM PDT 24
Peak memory 242164 kb
Host smart-63eaa8a1-693a-4896-8fe8-b1e93ce7cc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424697677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.1424697677
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.1959277359
Short name T617
Test name
Test status
Simulation time 298821889 ps
CPU time 4.6 seconds
Started Jun 02 03:09:26 PM PDT 24
Finished Jun 02 03:09:31 PM PDT 24
Peak memory 242184 kb
Host smart-dd7c40d5-9de7-437c-909e-d2b449c76652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959277359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.1959277359
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.3986593794
Short name T98
Test name
Test status
Simulation time 494484730 ps
CPU time 15.6 seconds
Started Jun 02 03:09:23 PM PDT 24
Finished Jun 02 03:09:39 PM PDT 24
Peak memory 248904 kb
Host smart-7f1f36f8-4f84-4354-be95-659432e306fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3986593794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.3986593794
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.3738827411
Short name T938
Test name
Test status
Simulation time 156833857 ps
CPU time 4.02 seconds
Started Jun 02 03:09:25 PM PDT 24
Finished Jun 02 03:09:30 PM PDT 24
Peak memory 242124 kb
Host smart-623f3fe9-bb0d-4fe4-b751-f41405103baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738827411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.3738827411
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.4238143273
Short name T926
Test name
Test status
Simulation time 11564025432 ps
CPU time 26.62 seconds
Started Jun 02 03:09:30 PM PDT 24
Finished Jun 02 03:09:57 PM PDT 24
Peak memory 243244 kb
Host smart-b29729d0-74c1-496e-a60a-fd8916154181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238143273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all
.4238143273
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.122660631
Short name T902
Test name
Test status
Simulation time 142731591802 ps
CPU time 1203.56 seconds
Started Jun 02 03:09:29 PM PDT 24
Finished Jun 02 03:29:33 PM PDT 24
Peak memory 313812 kb
Host smart-c0062f6f-3349-4987-a889-af11ba4cae32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122660631 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.122660631
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.2326889522
Short name T790
Test name
Test status
Simulation time 2831313637 ps
CPU time 26.68 seconds
Started Jun 02 03:09:28 PM PDT 24
Finished Jun 02 03:09:56 PM PDT 24
Peak memory 243124 kb
Host smart-d40b5571-d82f-4640-8215-3474df49a305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326889522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.2326889522
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.2197999389
Short name T673
Test name
Test status
Simulation time 156856191 ps
CPU time 1.75 seconds
Started Jun 02 03:09:30 PM PDT 24
Finished Jun 02 03:09:33 PM PDT 24
Peak memory 241168 kb
Host smart-1a4aeb3b-71c5-402d-afcd-483c196f94bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197999389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.2197999389
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.786151124
Short name T27
Test name
Test status
Simulation time 4867276139 ps
CPU time 30.64 seconds
Started Jun 02 03:09:29 PM PDT 24
Finished Jun 02 03:10:00 PM PDT 24
Peak memory 248968 kb
Host smart-b8325cd3-2d6b-40d4-9cac-55cad9b10146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786151124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.786151124
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.365294593
Short name T491
Test name
Test status
Simulation time 177378872 ps
CPU time 7.1 seconds
Started Jun 02 03:09:30 PM PDT 24
Finished Jun 02 03:09:37 PM PDT 24
Peak memory 242220 kb
Host smart-e3d38c69-258c-458c-a2e1-3786c4d1a5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365294593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.365294593
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.3988715097
Short name T392
Test name
Test status
Simulation time 2447019535 ps
CPU time 27.85 seconds
Started Jun 02 03:09:33 PM PDT 24
Finished Jun 02 03:10:02 PM PDT 24
Peak memory 242364 kb
Host smart-001c0a0a-5672-4e70-bd6d-28f5b86f375e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988715097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.3988715097
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.1688710857
Short name T516
Test name
Test status
Simulation time 370635282 ps
CPU time 4.99 seconds
Started Jun 02 03:09:28 PM PDT 24
Finished Jun 02 03:09:33 PM PDT 24
Peak memory 242688 kb
Host smart-24c3fc99-c8d0-47ae-9d8c-a977a924536e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688710857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.1688710857
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.2842843813
Short name T1054
Test name
Test status
Simulation time 2616989629 ps
CPU time 19.5 seconds
Started Jun 02 03:09:28 PM PDT 24
Finished Jun 02 03:09:48 PM PDT 24
Peak memory 244488 kb
Host smart-c7491891-4213-4f50-a525-b706d1358211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842843813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.2842843813
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.553376900
Short name T529
Test name
Test status
Simulation time 1247145507 ps
CPU time 37.71 seconds
Started Jun 02 03:09:27 PM PDT 24
Finished Jun 02 03:10:06 PM PDT 24
Peak memory 242504 kb
Host smart-841a8232-9894-449d-b165-3ba7a0cbd1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553376900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.553376900
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.1835113860
Short name T699
Test name
Test status
Simulation time 106980404 ps
CPU time 4.84 seconds
Started Jun 02 03:09:31 PM PDT 24
Finished Jun 02 03:09:36 PM PDT 24
Peak memory 242184 kb
Host smart-23e0f802-f9ed-4f56-842d-665ee6071e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835113860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.1835113860
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.2197883367
Short name T800
Test name
Test status
Simulation time 374026900 ps
CPU time 13.09 seconds
Started Jun 02 03:09:33 PM PDT 24
Finished Jun 02 03:09:47 PM PDT 24
Peak memory 242584 kb
Host smart-5f0c8650-6bcf-49e8-a810-5eb37081d4c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2197883367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.2197883367
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.120134202
Short name T175
Test name
Test status
Simulation time 432585166 ps
CPU time 4.17 seconds
Started Jun 02 03:09:29 PM PDT 24
Finished Jun 02 03:09:33 PM PDT 24
Peak memory 242592 kb
Host smart-e59b1acb-2214-4159-9c7b-7c863d58a5d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=120134202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.120134202
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.853712137
Short name T615
Test name
Test status
Simulation time 2246285748 ps
CPU time 12.4 seconds
Started Jun 02 03:09:28 PM PDT 24
Finished Jun 02 03:09:41 PM PDT 24
Peak memory 248872 kb
Host smart-ea3d8caf-9e89-449a-97b7-0e9c65c192df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853712137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.853712137
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.3731541751
Short name T13
Test name
Test status
Simulation time 182853336865 ps
CPU time 905.1 seconds
Started Jun 02 03:09:31 PM PDT 24
Finished Jun 02 03:24:36 PM PDT 24
Peak memory 281592 kb
Host smart-88fd9ab3-b081-48ee-a44a-038ccd35183e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731541751 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.3731541751
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.1050052571
Short name T905
Test name
Test status
Simulation time 2192625994 ps
CPU time 19.11 seconds
Started Jun 02 03:09:31 PM PDT 24
Finished Jun 02 03:09:51 PM PDT 24
Peak memory 242388 kb
Host smart-53e2eff3-9dca-48aa-9e3d-cc04e70f4f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050052571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.1050052571
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.2864470264
Short name T1114
Test name
Test status
Simulation time 76067849 ps
CPU time 1.56 seconds
Started Jun 02 03:09:35 PM PDT 24
Finished Jun 02 03:09:37 PM PDT 24
Peak memory 240804 kb
Host smart-22ae8663-9940-47f9-adfd-853f682d28f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864470264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.2864470264
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.1046245344
Short name T47
Test name
Test status
Simulation time 1061272546 ps
CPU time 27.78 seconds
Started Jun 02 03:09:38 PM PDT 24
Finished Jun 02 03:10:07 PM PDT 24
Peak memory 249064 kb
Host smart-9b16cae8-9a9d-4122-ade3-84e8f7060c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046245344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.1046245344
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.3823813123
Short name T723
Test name
Test status
Simulation time 6089571101 ps
CPU time 26.16 seconds
Started Jun 02 03:09:47 PM PDT 24
Finished Jun 02 03:10:14 PM PDT 24
Peak memory 242640 kb
Host smart-fbaaff30-742e-43bf-bf29-5679bb65353e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823813123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.3823813123
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.855708845
Short name T505
Test name
Test status
Simulation time 991574994 ps
CPU time 21.75 seconds
Started Jun 02 03:09:34 PM PDT 24
Finished Jun 02 03:09:56 PM PDT 24
Peak memory 242644 kb
Host smart-75ce02be-9fa4-4fb9-afa7-5c97ed54005e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855708845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.855708845
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.787025634
Short name T489
Test name
Test status
Simulation time 237264033 ps
CPU time 4.2 seconds
Started Jun 02 03:09:47 PM PDT 24
Finished Jun 02 03:09:52 PM PDT 24
Peak memory 242416 kb
Host smart-d1b1f64b-cae6-40d0-9941-d89d47311475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787025634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.787025634
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.3609604867
Short name T161
Test name
Test status
Simulation time 3291873065 ps
CPU time 20.67 seconds
Started Jun 02 03:09:37 PM PDT 24
Finished Jun 02 03:09:58 PM PDT 24
Peak memory 248968 kb
Host smart-1447d1d3-ac34-429d-ae7f-c45968228784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609604867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.3609604867
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.247212564
Short name T1072
Test name
Test status
Simulation time 360729858 ps
CPU time 14.13 seconds
Started Jun 02 03:09:35 PM PDT 24
Finished Jun 02 03:09:49 PM PDT 24
Peak memory 242348 kb
Host smart-d3da2b4f-f24e-4976-b50c-c69a66b2998c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247212564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.247212564
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.193965307
Short name T1063
Test name
Test status
Simulation time 1854581507 ps
CPU time 14.85 seconds
Started Jun 02 03:09:35 PM PDT 24
Finished Jun 02 03:09:50 PM PDT 24
Peak memory 242164 kb
Host smart-fc75b694-7d98-444e-b721-c76a32dd8094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193965307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.193965307
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.1673825649
Short name T530
Test name
Test status
Simulation time 1772489901 ps
CPU time 15.24 seconds
Started Jun 02 03:09:34 PM PDT 24
Finished Jun 02 03:09:50 PM PDT 24
Peak memory 242496 kb
Host smart-d752cca2-fdb7-4546-9c3e-9ea8d7e84dab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1673825649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.1673825649
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.1408890171
Short name T991
Test name
Test status
Simulation time 450102108 ps
CPU time 6.52 seconds
Started Jun 02 03:09:35 PM PDT 24
Finished Jun 02 03:09:42 PM PDT 24
Peak memory 242456 kb
Host smart-00626fb3-72d1-4a5d-b691-70a30ddf3aa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1408890171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.1408890171
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.203797426
Short name T203
Test name
Test status
Simulation time 182463891 ps
CPU time 4.76 seconds
Started Jun 02 03:09:29 PM PDT 24
Finished Jun 02 03:09:34 PM PDT 24
Peak memory 242280 kb
Host smart-42db1e99-2abe-44ef-b70f-e2d09db2d744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203797426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.203797426
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.3420564628
Short name T311
Test name
Test status
Simulation time 8859559812 ps
CPU time 67.64 seconds
Started Jun 02 03:09:47 PM PDT 24
Finished Jun 02 03:10:55 PM PDT 24
Peak memory 248344 kb
Host smart-4a71fbbc-5f9c-4c07-84e8-ff4423ccada5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420564628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.3420564628
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.3026884286
Short name T206
Test name
Test status
Simulation time 27423993452 ps
CPU time 793.97 seconds
Started Jun 02 03:09:32 PM PDT 24
Finished Jun 02 03:22:47 PM PDT 24
Peak memory 304836 kb
Host smart-4af7ea11-5679-4cc4-8a51-4ffa57cb4daf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026884286 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.3026884286
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.1784193002
Short name T97
Test name
Test status
Simulation time 2934208201 ps
CPU time 26.77 seconds
Started Jun 02 03:09:35 PM PDT 24
Finished Jun 02 03:10:02 PM PDT 24
Peak memory 242628 kb
Host smart-506f4124-d7c8-41b5-b10c-254eb2897795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784193002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.1784193002
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.166183621
Short name T1189
Test name
Test status
Simulation time 184796117 ps
CPU time 1.98 seconds
Started Jun 02 03:09:41 PM PDT 24
Finished Jun 02 03:09:44 PM PDT 24
Peak memory 240748 kb
Host smart-433df6d7-1c9a-4ccb-8ad4-73789da5dd7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166183621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.166183621
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.1196517319
Short name T834
Test name
Test status
Simulation time 1874401908 ps
CPU time 32.88 seconds
Started Jun 02 03:09:35 PM PDT 24
Finished Jun 02 03:10:08 PM PDT 24
Peak memory 242336 kb
Host smart-591e81d6-c867-4f50-95ac-25d25840ae0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196517319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.1196517319
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.4046222525
Short name T575
Test name
Test status
Simulation time 2953614028 ps
CPU time 12.24 seconds
Started Jun 02 03:09:34 PM PDT 24
Finished Jun 02 03:09:47 PM PDT 24
Peak memory 242404 kb
Host smart-04fba3b5-0212-4b51-a29c-85283908b8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046222525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.4046222525
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.2787781822
Short name T683
Test name
Test status
Simulation time 1102522788 ps
CPU time 14.8 seconds
Started Jun 02 03:09:34 PM PDT 24
Finished Jun 02 03:09:50 PM PDT 24
Peak memory 242320 kb
Host smart-17a46c48-58da-40dd-a9ae-b887507b53b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787781822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.2787781822
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.3110390622
Short name T192
Test name
Test status
Simulation time 285626493 ps
CPU time 2.83 seconds
Started Jun 02 03:09:35 PM PDT 24
Finished Jun 02 03:09:38 PM PDT 24
Peak memory 242388 kb
Host smart-d968b916-8eee-4f5f-ade2-ac68d96d88c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110390622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.3110390622
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.1487250292
Short name T1182
Test name
Test status
Simulation time 316276692 ps
CPU time 3.37 seconds
Started Jun 02 03:09:34 PM PDT 24
Finished Jun 02 03:09:38 PM PDT 24
Peak memory 242596 kb
Host smart-ef43b750-1f0b-467d-8dce-095e016f6d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487250292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.1487250292
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.2800132657
Short name T621
Test name
Test status
Simulation time 2056245405 ps
CPU time 28.02 seconds
Started Jun 02 03:09:36 PM PDT 24
Finished Jun 02 03:10:04 PM PDT 24
Peak memory 242276 kb
Host smart-6669d3c4-fcc5-43e3-a92e-2579dd9615f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800132657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.2800132657
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.168431321
Short name T547
Test name
Test status
Simulation time 637740109 ps
CPU time 8.7 seconds
Started Jun 02 03:09:35 PM PDT 24
Finished Jun 02 03:09:44 PM PDT 24
Peak memory 242504 kb
Host smart-76c30fd1-7b5d-4b69-8ea8-29461ffb2b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168431321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.168431321
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.2784949930
Short name T559
Test name
Test status
Simulation time 331493140 ps
CPU time 9.08 seconds
Started Jun 02 03:09:47 PM PDT 24
Finished Jun 02 03:09:57 PM PDT 24
Peak memory 242204 kb
Host smart-5f4d3221-956a-408f-8859-24d6e20402e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2784949930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.2784949930
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.1679001557
Short name T917
Test name
Test status
Simulation time 248343226 ps
CPU time 5.23 seconds
Started Jun 02 03:09:34 PM PDT 24
Finished Jun 02 03:09:39 PM PDT 24
Peak memory 242136 kb
Host smart-71978448-2c0d-49fb-816d-36bdf22f3e99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679001557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.1679001557
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.1544133936
Short name T979
Test name
Test status
Simulation time 476309730 ps
CPU time 12.87 seconds
Started Jun 02 03:09:35 PM PDT 24
Finished Jun 02 03:09:48 PM PDT 24
Peak memory 242332 kb
Host smart-66e1458d-d620-441f-ba68-8e986873f89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544133936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.1544133936
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.1619530954
Short name T901
Test name
Test status
Simulation time 69642582877 ps
CPU time 122.23 seconds
Started Jun 02 03:09:40 PM PDT 24
Finished Jun 02 03:11:42 PM PDT 24
Peak memory 259148 kb
Host smart-f1210065-5c15-41a1-af14-4342e9484236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619530954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.1619530954
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.1925885321
Short name T265
Test name
Test status
Simulation time 115517492122 ps
CPU time 1491.92 seconds
Started Jun 02 03:09:37 PM PDT 24
Finished Jun 02 03:34:30 PM PDT 24
Peak memory 265520 kb
Host smart-44767226-e325-4185-ad94-99708d34692f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925885321 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.1925885321
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.4289670575
Short name T486
Test name
Test status
Simulation time 8877687684 ps
CPU time 23.47 seconds
Started Jun 02 03:09:41 PM PDT 24
Finished Jun 02 03:10:06 PM PDT 24
Peak memory 243016 kb
Host smart-f79ed4d2-e0ee-4870-9274-c7edf18aee96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289670575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.4289670575
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.2056581239
Short name T468
Test name
Test status
Simulation time 549599649 ps
CPU time 2.19 seconds
Started Jun 02 03:07:44 PM PDT 24
Finished Jun 02 03:07:47 PM PDT 24
Peak memory 241276 kb
Host smart-d091ca02-c600-4691-95aa-11cc68fc357c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056581239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.2056581239
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.2762748531
Short name T886
Test name
Test status
Simulation time 1904655279 ps
CPU time 23.76 seconds
Started Jun 02 03:07:41 PM PDT 24
Finished Jun 02 03:08:06 PM PDT 24
Peak memory 242648 kb
Host smart-021fa2de-5ae0-4698-842f-f453501bcd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762748531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.2762748531
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.2424888092
Short name T85
Test name
Test status
Simulation time 1276849911 ps
CPU time 19.84 seconds
Started Jun 02 03:07:44 PM PDT 24
Finished Jun 02 03:08:05 PM PDT 24
Peak memory 242924 kb
Host smart-90115d1d-7bb4-4387-8726-21ccbf74591a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424888092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.2424888092
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.1618291071
Short name T850
Test name
Test status
Simulation time 1569629872 ps
CPU time 35.12 seconds
Started Jun 02 03:07:42 PM PDT 24
Finished Jun 02 03:08:18 PM PDT 24
Peak memory 249916 kb
Host smart-7eef0216-4055-4305-9efd-dc5e2266d5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618291071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.1618291071
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.2702130371
Short name T805
Test name
Test status
Simulation time 278858443 ps
CPU time 4.63 seconds
Started Jun 02 03:07:41 PM PDT 24
Finished Jun 02 03:07:47 PM PDT 24
Peak memory 248908 kb
Host smart-a8513837-0cdb-4436-92c4-1753f1de33b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702130371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.2702130371
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.3948568349
Short name T483
Test name
Test status
Simulation time 1549510279 ps
CPU time 5.43 seconds
Started Jun 02 03:07:45 PM PDT 24
Finished Jun 02 03:07:51 PM PDT 24
Peak memory 242400 kb
Host smart-10db7734-8a00-4f82-864e-3a9996a287ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948568349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.3948568349
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.3961104762
Short name T1102
Test name
Test status
Simulation time 6800535528 ps
CPU time 26.38 seconds
Started Jun 02 03:07:42 PM PDT 24
Finished Jun 02 03:08:09 PM PDT 24
Peak memory 245960 kb
Host smart-ad9eccac-731d-41e6-be4b-1829dfd8969f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961104762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.3961104762
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.1573157968
Short name T251
Test name
Test status
Simulation time 1154752256 ps
CPU time 21.93 seconds
Started Jun 02 03:07:41 PM PDT 24
Finished Jun 02 03:08:04 PM PDT 24
Peak memory 242488 kb
Host smart-28b3f912-321c-44b3-a9ab-b33b6b2165a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573157968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.1573157968
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.817288557
Short name T734
Test name
Test status
Simulation time 211653048 ps
CPU time 4.08 seconds
Started Jun 02 03:07:43 PM PDT 24
Finished Jun 02 03:07:48 PM PDT 24
Peak memory 242508 kb
Host smart-362ea9a5-c8ad-4a03-a690-512884625692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817288557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.817288557
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.3271891467
Short name T594
Test name
Test status
Simulation time 9396614860 ps
CPU time 21.32 seconds
Started Jun 02 03:07:43 PM PDT 24
Finished Jun 02 03:08:05 PM PDT 24
Peak memory 242572 kb
Host smart-6306c207-a1ef-4b50-a90d-cb3d3ca9f8c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3271891467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.3271891467
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.1911621801
Short name T23
Test name
Test status
Simulation time 40763982597 ps
CPU time 199.3 seconds
Started Jun 02 03:07:41 PM PDT 24
Finished Jun 02 03:11:02 PM PDT 24
Peak memory 278012 kb
Host smart-45deeef8-f1b5-42e0-a4a2-0a41030550d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911621801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.1911621801
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.2756095307
Short name T1061
Test name
Test status
Simulation time 675644742 ps
CPU time 5.52 seconds
Started Jun 02 03:07:39 PM PDT 24
Finished Jun 02 03:07:45 PM PDT 24
Peak memory 242164 kb
Host smart-67016124-1f5d-40b9-9d8b-fbe06e94607e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756095307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.2756095307
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.3246485379
Short name T210
Test name
Test status
Simulation time 5301344135 ps
CPU time 121.04 seconds
Started Jun 02 03:07:41 PM PDT 24
Finished Jun 02 03:09:43 PM PDT 24
Peak memory 265488 kb
Host smart-e8cdca48-4396-4125-9396-4ef7c8862879
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246485379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.
3246485379
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.310043083
Short name T1187
Test name
Test status
Simulation time 190545775931 ps
CPU time 1356.56 seconds
Started Jun 02 03:07:42 PM PDT 24
Finished Jun 02 03:30:20 PM PDT 24
Peak memory 311228 kb
Host smart-6b997d58-c8f9-4c6c-aeee-964ec969faaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310043083 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.310043083
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.554239753
Short name T763
Test name
Test status
Simulation time 200237565 ps
CPU time 4.95 seconds
Started Jun 02 03:07:41 PM PDT 24
Finished Jun 02 03:07:47 PM PDT 24
Peak memory 242260 kb
Host smart-60d98030-1598-4f00-aec5-8e22eb0c15b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554239753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.554239753
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.901306286
Short name T1024
Test name
Test status
Simulation time 102270502 ps
CPU time 2.24 seconds
Started Jun 02 03:09:42 PM PDT 24
Finished Jun 02 03:09:45 PM PDT 24
Peak memory 241256 kb
Host smart-9a77a0c4-fa15-4d20-b13d-70a83b1a33f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901306286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.901306286
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.845387697
Short name T1032
Test name
Test status
Simulation time 3395678570 ps
CPU time 41.77 seconds
Started Jun 02 03:09:41 PM PDT 24
Finished Jun 02 03:10:24 PM PDT 24
Peak memory 249764 kb
Host smart-ff51bc27-b959-41b2-aae4-ea521aa381b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845387697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.845387697
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.719619273
Short name T641
Test name
Test status
Simulation time 3313222818 ps
CPU time 10.6 seconds
Started Jun 02 03:09:38 PM PDT 24
Finished Jun 02 03:09:50 PM PDT 24
Peak memory 242312 kb
Host smart-9fd94402-526b-4570-95d9-160fbcf5548e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719619273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.719619273
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.3393337380
Short name T227
Test name
Test status
Simulation time 169308571 ps
CPU time 4.84 seconds
Started Jun 02 03:09:41 PM PDT 24
Finished Jun 02 03:09:47 PM PDT 24
Peak memory 242404 kb
Host smart-e8b9c04e-74a0-47aa-9416-ce6176777009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393337380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.3393337380
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.1942854579
Short name T224
Test name
Test status
Simulation time 1978139338 ps
CPU time 25.97 seconds
Started Jun 02 03:09:38 PM PDT 24
Finished Jun 02 03:10:05 PM PDT 24
Peak memory 245412 kb
Host smart-d4da9be4-b4a1-4d95-b2d9-cfcf400fb731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942854579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.1942854579
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.812876059
Short name T1165
Test name
Test status
Simulation time 1641480678 ps
CPU time 13.31 seconds
Started Jun 02 03:09:41 PM PDT 24
Finished Jun 02 03:09:55 PM PDT 24
Peak memory 249100 kb
Host smart-2f3c7ec7-0174-49af-bec5-234845dee8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812876059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.812876059
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.460488762
Short name T674
Test name
Test status
Simulation time 5860024327 ps
CPU time 17.75 seconds
Started Jun 02 03:09:39 PM PDT 24
Finished Jun 02 03:09:57 PM PDT 24
Peak memory 249004 kb
Host smart-98fef0db-845b-4439-883b-07b5823a7ae0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=460488762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.460488762
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.3798423047
Short name T1043
Test name
Test status
Simulation time 2712869459 ps
CPU time 8.29 seconds
Started Jun 02 03:09:44 PM PDT 24
Finished Jun 02 03:09:53 PM PDT 24
Peak memory 242296 kb
Host smart-cfa17f5f-00db-4ee5-a654-965c33eb5b28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3798423047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.3798423047
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.3502305522
Short name T887
Test name
Test status
Simulation time 186752818 ps
CPU time 3.92 seconds
Started Jun 02 03:09:41 PM PDT 24
Finished Jun 02 03:09:45 PM PDT 24
Peak memory 242096 kb
Host smart-36cbe9c1-fc8b-47ff-8af9-e5d58b68a67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502305522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.3502305522
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.3034729559
Short name T806
Test name
Test status
Simulation time 1389363298 ps
CPU time 18.07 seconds
Started Jun 02 03:09:47 PM PDT 24
Finished Jun 02 03:10:06 PM PDT 24
Peak memory 241920 kb
Host smart-22a87168-2165-40ae-8eaf-147f6632a039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034729559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all
.3034729559
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.2781416234
Short name T972
Test name
Test status
Simulation time 43545196616 ps
CPU time 845.57 seconds
Started Jun 02 03:09:43 PM PDT 24
Finished Jun 02 03:23:49 PM PDT 24
Peak memory 281120 kb
Host smart-676b52ad-c551-4ec0-b808-f7acc3e1d2e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781416234 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.2781416234
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.2879318320
Short name T795
Test name
Test status
Simulation time 1324077846 ps
CPU time 8.43 seconds
Started Jun 02 03:09:42 PM PDT 24
Finished Jun 02 03:09:51 PM PDT 24
Peak memory 242364 kb
Host smart-a350c13e-8f51-43d8-8e52-248246f5a7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879318320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.2879318320
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.3466808293
Short name T453
Test name
Test status
Simulation time 93999047 ps
CPU time 1.63 seconds
Started Jun 02 03:09:46 PM PDT 24
Finished Jun 02 03:09:48 PM PDT 24
Peak memory 240840 kb
Host smart-26775df2-c99e-4741-867f-fc7aa66dd9f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466808293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.3466808293
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.360815084
Short name T327
Test name
Test status
Simulation time 3831627723 ps
CPU time 17.02 seconds
Started Jun 02 03:09:41 PM PDT 24
Finished Jun 02 03:09:59 PM PDT 24
Peak memory 248964 kb
Host smart-8d697a5e-15c7-4778-9ac4-2cf680cf4060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360815084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.360815084
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.2971878519
Short name T1030
Test name
Test status
Simulation time 476340112 ps
CPU time 14.16 seconds
Started Jun 02 03:09:44 PM PDT 24
Finished Jun 02 03:09:58 PM PDT 24
Peak memory 242352 kb
Host smart-273ff021-5cfc-42c9-b293-ed806f3320ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971878519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.2971878519
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.1836972793
Short name T514
Test name
Test status
Simulation time 4955382624 ps
CPU time 26.7 seconds
Started Jun 02 03:09:42 PM PDT 24
Finished Jun 02 03:10:09 PM PDT 24
Peak memory 243104 kb
Host smart-1bb2a77e-0be1-4a97-8534-edefc76f2377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836972793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.1836972793
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.446715896
Short name T1136
Test name
Test status
Simulation time 175984921 ps
CPU time 5.06 seconds
Started Jun 02 03:09:44 PM PDT 24
Finished Jun 02 03:09:49 PM PDT 24
Peak memory 242636 kb
Host smart-6572b535-5724-4ac5-a95c-94d17fbda353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446715896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.446715896
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.3405444235
Short name T153
Test name
Test status
Simulation time 1220856750 ps
CPU time 25.49 seconds
Started Jun 02 03:09:41 PM PDT 24
Finished Jun 02 03:10:08 PM PDT 24
Peak memory 245492 kb
Host smart-28d2e80c-6751-407c-8ab7-cc0b283e239a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405444235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.3405444235
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.1372105104
Short name T103
Test name
Test status
Simulation time 4248555203 ps
CPU time 28.36 seconds
Started Jun 02 03:09:42 PM PDT 24
Finished Jun 02 03:10:11 PM PDT 24
Peak memory 243536 kb
Host smart-514f1859-6094-4a17-97a0-f3cee1d0ce54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372105104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.1372105104
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.1775352454
Short name T874
Test name
Test status
Simulation time 261767098 ps
CPU time 14.09 seconds
Started Jun 02 03:09:37 PM PDT 24
Finished Jun 02 03:09:52 PM PDT 24
Peak memory 242404 kb
Host smart-3bccdb5e-4957-4e06-8a7b-b66207ede4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775352454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.1775352454
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.1509460778
Short name T812
Test name
Test status
Simulation time 608663796 ps
CPU time 16.09 seconds
Started Jun 02 03:09:40 PM PDT 24
Finished Jun 02 03:09:57 PM PDT 24
Peak memory 248860 kb
Host smart-04282954-b8ce-4487-89d5-cd2db0849ddc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1509460778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.1509460778
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.3561513192
Short name T967
Test name
Test status
Simulation time 215787801 ps
CPU time 5.38 seconds
Started Jun 02 03:09:42 PM PDT 24
Finished Jun 02 03:09:48 PM PDT 24
Peak memory 242228 kb
Host smart-c0e89795-ed86-4fbd-8214-75a6d564355d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561513192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.3561513192
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.731162935
Short name T497
Test name
Test status
Simulation time 1153197528 ps
CPU time 8.63 seconds
Started Jun 02 03:09:39 PM PDT 24
Finished Jun 02 03:09:48 PM PDT 24
Peak memory 242184 kb
Host smart-e8b4582b-a3c8-46ab-a493-8eaa928ba13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731162935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.731162935
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.2868660424
Short name T177
Test name
Test status
Simulation time 36848279477 ps
CPU time 96.04 seconds
Started Jun 02 03:09:47 PM PDT 24
Finished Jun 02 03:11:23 PM PDT 24
Peak memory 249012 kb
Host smart-baf99081-b59e-40f9-b86e-68f5f9147cd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868660424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.2868660424
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.1222009451
Short name T432
Test name
Test status
Simulation time 298997076 ps
CPU time 9.22 seconds
Started Jun 02 03:09:41 PM PDT 24
Finished Jun 02 03:09:50 PM PDT 24
Peak memory 242592 kb
Host smart-932d928a-ccda-49aa-9bae-9caa6c43fb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222009451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.1222009451
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.2670793202
Short name T562
Test name
Test status
Simulation time 147753126 ps
CPU time 2.54 seconds
Started Jun 02 03:09:53 PM PDT 24
Finished Jun 02 03:09:56 PM PDT 24
Peak memory 241032 kb
Host smart-cecbed8e-2dfd-488a-beea-2fd6d8b1f9f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670793202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.2670793202
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.3960207402
Short name T924
Test name
Test status
Simulation time 2113643404 ps
CPU time 23.28 seconds
Started Jun 02 03:09:50 PM PDT 24
Finished Jun 02 03:10:14 PM PDT 24
Peak memory 242352 kb
Host smart-8b0ee6e9-31cc-42f9-b269-bc310adf442c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960207402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.3960207402
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.3930111979
Short name T995
Test name
Test status
Simulation time 808656873 ps
CPU time 22.21 seconds
Started Jun 02 03:09:45 PM PDT 24
Finished Jun 02 03:10:08 PM PDT 24
Peak memory 242316 kb
Host smart-bf7b07db-ecd5-413b-9c22-9c2c9e4444e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930111979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.3930111979
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.4276121601
Short name T1133
Test name
Test status
Simulation time 169633786 ps
CPU time 3.19 seconds
Started Jun 02 03:09:45 PM PDT 24
Finished Jun 02 03:09:48 PM PDT 24
Peak memory 242352 kb
Host smart-6b600052-adf5-403f-976e-25cf619e4894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276121601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.4276121601
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.1151463126
Short name T420
Test name
Test status
Simulation time 1191082658 ps
CPU time 21.57 seconds
Started Jun 02 03:09:45 PM PDT 24
Finished Jun 02 03:10:07 PM PDT 24
Peak memory 249528 kb
Host smart-5fabfc49-afad-430f-ba14-ba5ef2ad11ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151463126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.1151463126
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.2248241092
Short name T557
Test name
Test status
Simulation time 535390826 ps
CPU time 4.25 seconds
Started Jun 02 03:09:46 PM PDT 24
Finished Jun 02 03:09:51 PM PDT 24
Peak memory 242436 kb
Host smart-96d366d1-5132-4b3e-a1cc-15ce0b40033e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248241092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.2248241092
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.4121327072
Short name T592
Test name
Test status
Simulation time 122719131 ps
CPU time 3.15 seconds
Started Jun 02 03:09:46 PM PDT 24
Finished Jun 02 03:09:50 PM PDT 24
Peak memory 242264 kb
Host smart-58b2915c-149b-48de-bd00-370edbc3e3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121327072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.4121327072
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.1641343078
Short name T441
Test name
Test status
Simulation time 536063175 ps
CPU time 14.63 seconds
Started Jun 02 03:09:46 PM PDT 24
Finished Jun 02 03:10:01 PM PDT 24
Peak memory 248880 kb
Host smart-b3bd9785-1ffb-46ee-9ca0-1eeedd4f2d27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1641343078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.1641343078
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.609528962
Short name T373
Test name
Test status
Simulation time 300117417 ps
CPU time 7.89 seconds
Started Jun 02 03:09:47 PM PDT 24
Finished Jun 02 03:09:55 PM PDT 24
Peak memory 242292 kb
Host smart-15de5ad2-2852-4866-a2de-2fd0309b9b69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=609528962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.609528962
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.2310376935
Short name T675
Test name
Test status
Simulation time 600225865 ps
CPU time 8.42 seconds
Started Jun 02 03:09:46 PM PDT 24
Finished Jun 02 03:09:55 PM PDT 24
Peak memory 242216 kb
Host smart-ce6339ca-84b9-411e-b1fd-c9020ee0cbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310376935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.2310376935
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.843519240
Short name T125
Test name
Test status
Simulation time 154014325060 ps
CPU time 1595.6 seconds
Started Jun 02 03:09:51 PM PDT 24
Finished Jun 02 03:36:28 PM PDT 24
Peak memory 479504 kb
Host smart-6d3a5ade-3627-4fdf-94a1-e4ef20894848
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843519240 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.843519240
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.3782268051
Short name T639
Test name
Test status
Simulation time 1392212183 ps
CPU time 19.6 seconds
Started Jun 02 03:09:44 PM PDT 24
Finished Jun 02 03:10:04 PM PDT 24
Peak memory 242508 kb
Host smart-e163c54a-5bce-428c-858f-946a4dd37606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782268051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.3782268051
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.2669858837
Short name T725
Test name
Test status
Simulation time 887925854 ps
CPU time 2.61 seconds
Started Jun 02 03:09:52 PM PDT 24
Finished Jun 02 03:09:55 PM PDT 24
Peak memory 240792 kb
Host smart-db6ddf7d-a2cd-4888-9c65-d1363a748cd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669858837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.2669858837
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.1006552542
Short name T872
Test name
Test status
Simulation time 864300533 ps
CPU time 5.93 seconds
Started Jun 02 03:09:51 PM PDT 24
Finished Jun 02 03:09:57 PM PDT 24
Peak memory 242316 kb
Host smart-40aa1dd7-7775-4209-a2e8-f1ecd90bd9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006552542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.1006552542
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.538242373
Short name T447
Test name
Test status
Simulation time 1975331518 ps
CPU time 15.94 seconds
Started Jun 02 03:09:50 PM PDT 24
Finished Jun 02 03:10:07 PM PDT 24
Peak memory 242320 kb
Host smart-c07fb182-e754-41d7-85ad-fb429b9eb5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538242373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.538242373
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.666395472
Short name T1088
Test name
Test status
Simulation time 1196583761 ps
CPU time 25.3 seconds
Started Jun 02 03:09:50 PM PDT 24
Finished Jun 02 03:10:16 PM PDT 24
Peak memory 242252 kb
Host smart-b5d1966d-f3b8-4472-b5f3-f530bdd9ab80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666395472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.666395472
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.1106183014
Short name T1119
Test name
Test status
Simulation time 240269254 ps
CPU time 3.99 seconds
Started Jun 02 03:09:50 PM PDT 24
Finished Jun 02 03:09:54 PM PDT 24
Peak memory 242304 kb
Host smart-6073d238-cede-42b3-83a8-bad8c13de2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106183014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.1106183014
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.2802224172
Short name T434
Test name
Test status
Simulation time 445483242 ps
CPU time 10.84 seconds
Started Jun 02 03:09:51 PM PDT 24
Finished Jun 02 03:10:02 PM PDT 24
Peak memory 242720 kb
Host smart-433b822a-c4fa-4ca5-93cd-71151a0f2434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802224172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.2802224172
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.2500145043
Short name T518
Test name
Test status
Simulation time 14081279810 ps
CPU time 39.4 seconds
Started Jun 02 03:09:50 PM PDT 24
Finished Jun 02 03:10:30 PM PDT 24
Peak memory 243628 kb
Host smart-1512349c-b025-433d-8184-59e5121f407e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500145043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.2500145043
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.1006356376
Short name T1145
Test name
Test status
Simulation time 514945804 ps
CPU time 7.1 seconds
Started Jun 02 03:09:51 PM PDT 24
Finished Jun 02 03:09:59 PM PDT 24
Peak memory 242244 kb
Host smart-f0c39b25-0e94-4131-a596-57d2791fbaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006356376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.1006356376
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.2293688920
Short name T687
Test name
Test status
Simulation time 1460391050 ps
CPU time 22.14 seconds
Started Jun 02 03:09:51 PM PDT 24
Finished Jun 02 03:10:14 PM PDT 24
Peak memory 248876 kb
Host smart-626f4aa2-0651-4a64-b0cf-7cae13356f1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293688920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.2293688920
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.643891480
Short name T378
Test name
Test status
Simulation time 1062241414 ps
CPU time 9.14 seconds
Started Jun 02 03:09:51 PM PDT 24
Finished Jun 02 03:10:00 PM PDT 24
Peak memory 242548 kb
Host smart-6c465120-2b49-4cee-a3f9-749cc5ad42fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=643891480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.643891480
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.2815783971
Short name T425
Test name
Test status
Simulation time 195322513 ps
CPU time 4.77 seconds
Started Jun 02 03:09:50 PM PDT 24
Finished Jun 02 03:09:56 PM PDT 24
Peak memory 242436 kb
Host smart-ce3ca2f8-be2b-4d3a-899a-1236d5ad4b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815783971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.2815783971
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.2949752838
Short name T1146
Test name
Test status
Simulation time 95572387033 ps
CPU time 1862.96 seconds
Started Jun 02 03:09:52 PM PDT 24
Finished Jun 02 03:40:56 PM PDT 24
Peak memory 352312 kb
Host smart-3174d4a1-8baf-4c82-bc7e-5e441cb4ae60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949752838 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.2949752838
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.1203920460
Short name T2
Test name
Test status
Simulation time 722482013 ps
CPU time 24.07 seconds
Started Jun 02 03:09:50 PM PDT 24
Finished Jun 02 03:10:15 PM PDT 24
Peak memory 248868 kb
Host smart-29fa86bc-c2b8-44f3-bd35-6d7ae5a198e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203920460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.1203920460
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.2605632407
Short name T730
Test name
Test status
Simulation time 180560731 ps
CPU time 1.67 seconds
Started Jun 02 03:09:56 PM PDT 24
Finished Jun 02 03:09:58 PM PDT 24
Peak memory 240904 kb
Host smart-73db1018-c228-4f29-b4b0-9e9ae45f16b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605632407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.2605632407
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.3052528192
Short name T527
Test name
Test status
Simulation time 4514382559 ps
CPU time 12.5 seconds
Started Jun 02 03:10:00 PM PDT 24
Finished Jun 02 03:10:13 PM PDT 24
Peak memory 243528 kb
Host smart-b453f66e-9a9e-4c62-ba09-419d05b5f10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052528192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.3052528192
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.2386994742
Short name T1066
Test name
Test status
Simulation time 6384852973 ps
CPU time 53.8 seconds
Started Jun 02 03:09:57 PM PDT 24
Finished Jun 02 03:10:51 PM PDT 24
Peak memory 257668 kb
Host smart-11cc3bd5-2e1e-46d8-87c2-9927de26ba98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386994742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.2386994742
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.1640027261
Short name T430
Test name
Test status
Simulation time 2572728691 ps
CPU time 24.14 seconds
Started Jun 02 03:09:56 PM PDT 24
Finished Jun 02 03:10:20 PM PDT 24
Peak memory 248916 kb
Host smart-1d0bfe98-2c6b-4182-9e2b-08f4d8679d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640027261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.1640027261
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.1300420005
Short name T75
Test name
Test status
Simulation time 211453587 ps
CPU time 3.66 seconds
Started Jun 02 03:09:57 PM PDT 24
Finished Jun 02 03:10:02 PM PDT 24
Peak memory 242404 kb
Host smart-0d9786e1-9230-4e40-8976-77187e086b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300420005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.1300420005
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.1235024009
Short name T891
Test name
Test status
Simulation time 2429055351 ps
CPU time 42.6 seconds
Started Jun 02 03:09:58 PM PDT 24
Finished Jun 02 03:10:42 PM PDT 24
Peak memory 245996 kb
Host smart-e732f478-75c0-404e-83d2-7fa84145e139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235024009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.1235024009
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.55552512
Short name T813
Test name
Test status
Simulation time 25295515546 ps
CPU time 55.26 seconds
Started Jun 02 03:09:57 PM PDT 24
Finished Jun 02 03:10:53 PM PDT 24
Peak memory 242812 kb
Host smart-df70c843-0a24-40ea-8b9e-2abed0d566f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55552512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.55552512
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.407421556
Short name T1177
Test name
Test status
Simulation time 1041736146 ps
CPU time 9.41 seconds
Started Jun 02 03:09:59 PM PDT 24
Finished Jun 02 03:10:09 PM PDT 24
Peak memory 242392 kb
Host smart-4e5c70d4-9394-45cc-b7e6-c769cffb79c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407421556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.407421556
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.795357627
Short name T737
Test name
Test status
Simulation time 1567345671 ps
CPU time 16.73 seconds
Started Jun 02 03:09:56 PM PDT 24
Finished Jun 02 03:10:13 PM PDT 24
Peak memory 242148 kb
Host smart-20ff1465-a500-4021-b686-05dca72d8766
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=795357627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.795357627
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.3441860848
Short name T943
Test name
Test status
Simulation time 154870468 ps
CPU time 4.59 seconds
Started Jun 02 03:09:57 PM PDT 24
Finished Jun 02 03:10:02 PM PDT 24
Peak memory 248892 kb
Host smart-4447a9ec-2b00-4184-bb19-8eb1d083bfab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3441860848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.3441860848
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.3445184791
Short name T267
Test name
Test status
Simulation time 1381677742 ps
CPU time 3.3 seconds
Started Jun 02 03:09:58 PM PDT 24
Finished Jun 02 03:10:02 PM PDT 24
Peak memory 246888 kb
Host smart-fa6db8d3-b8c6-4baa-8846-205729bda444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445184791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.3445184791
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.4130745023
Short name T19
Test name
Test status
Simulation time 463408997766 ps
CPU time 1196.59 seconds
Started Jun 02 03:09:58 PM PDT 24
Finished Jun 02 03:29:56 PM PDT 24
Peak memory 362324 kb
Host smart-3454c22e-ce57-45fc-ac86-0a454baa5d5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130745023 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.4130745023
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.3928973407
Short name T555
Test name
Test status
Simulation time 9790046283 ps
CPU time 70.74 seconds
Started Jun 02 03:09:57 PM PDT 24
Finished Jun 02 03:11:08 PM PDT 24
Peak memory 242248 kb
Host smart-45407a51-153e-4565-89a5-6c10e3b7a32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928973407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.3928973407
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.2733026744
Short name T764
Test name
Test status
Simulation time 194061180 ps
CPU time 1.63 seconds
Started Jun 02 03:10:05 PM PDT 24
Finished Jun 02 03:10:07 PM PDT 24
Peak memory 240956 kb
Host smart-21ea0481-327e-4665-953a-e7b5c8e14764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733026744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.2733026744
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.671362150
Short name T1090
Test name
Test status
Simulation time 5513123196 ps
CPU time 27.83 seconds
Started Jun 02 03:09:57 PM PDT 24
Finished Jun 02 03:10:26 PM PDT 24
Peak memory 247720 kb
Host smart-dec4a15d-47f4-47ce-a5bb-21a476750f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671362150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.671362150
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.83438316
Short name T201
Test name
Test status
Simulation time 1562746268 ps
CPU time 45.55 seconds
Started Jun 02 03:09:58 PM PDT 24
Finished Jun 02 03:10:44 PM PDT 24
Peak memory 248796 kb
Host smart-4318b548-da03-4ca1-beee-6dd8fcefdec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83438316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.83438316
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.938853199
Short name T564
Test name
Test status
Simulation time 486678847 ps
CPU time 11.76 seconds
Started Jun 02 03:10:00 PM PDT 24
Finished Jun 02 03:10:12 PM PDT 24
Peak memory 242360 kb
Host smart-e3619210-83e0-490e-9c13-03cf36b1d3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938853199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.938853199
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.2451282124
Short name T109
Test name
Test status
Simulation time 158074223 ps
CPU time 4.57 seconds
Started Jun 02 03:10:02 PM PDT 24
Finished Jun 02 03:10:07 PM PDT 24
Peak memory 242340 kb
Host smart-9ef8f217-a1bb-43d7-a6d6-43d9d6dcc45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451282124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.2451282124
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.3504185752
Short name T823
Test name
Test status
Simulation time 673553742 ps
CPU time 22.2 seconds
Started Jun 02 03:09:59 PM PDT 24
Finished Jun 02 03:10:22 PM PDT 24
Peak memory 243816 kb
Host smart-854c480a-6a13-494b-aae2-b2feb64b31a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504185752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.3504185752
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.1632981625
Short name T217
Test name
Test status
Simulation time 2673689769 ps
CPU time 25.67 seconds
Started Jun 02 03:10:08 PM PDT 24
Finished Jun 02 03:10:35 PM PDT 24
Peak memory 242588 kb
Host smart-708d7ec5-e566-4776-854f-4d7c96150634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632981625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.1632981625
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.1334374893
Short name T716
Test name
Test status
Simulation time 499299686 ps
CPU time 6.04 seconds
Started Jun 02 03:09:59 PM PDT 24
Finished Jun 02 03:10:06 PM PDT 24
Peak memory 241948 kb
Host smart-a346e96c-6131-4580-842b-164f3dfade84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334374893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.1334374893
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.3391709023
Short name T704
Test name
Test status
Simulation time 802491328 ps
CPU time 23.21 seconds
Started Jun 02 03:10:00 PM PDT 24
Finished Jun 02 03:10:23 PM PDT 24
Peak memory 242572 kb
Host smart-2bf10a1d-40f4-4d49-b21f-6404d5927c86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3391709023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.3391709023
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.3649010100
Short name T462
Test name
Test status
Simulation time 3312403711 ps
CPU time 8.12 seconds
Started Jun 02 03:10:00 PM PDT 24
Finished Jun 02 03:10:09 PM PDT 24
Peak memory 248952 kb
Host smart-734169a2-19c9-426d-a653-d0790f43fd08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3649010100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.3649010100
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.1130150864
Short name T268
Test name
Test status
Simulation time 119501314 ps
CPU time 3.3 seconds
Started Jun 02 03:09:57 PM PDT 24
Finished Jun 02 03:10:01 PM PDT 24
Peak memory 242212 kb
Host smart-285dc58d-3e55-4a3f-87a5-fcddf00e7ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130150864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.1130150864
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.1129904358
Short name T882
Test name
Test status
Simulation time 2122837056 ps
CPU time 67.93 seconds
Started Jun 02 03:10:03 PM PDT 24
Finished Jun 02 03:11:12 PM PDT 24
Peak memory 244276 kb
Host smart-5e47bb81-7b79-4022-89cc-37526994dd91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129904358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all
.1129904358
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.981826473
Short name T291
Test name
Test status
Simulation time 181875086852 ps
CPU time 1494.84 seconds
Started Jun 02 03:10:03 PM PDT 24
Finished Jun 02 03:34:59 PM PDT 24
Peak memory 265576 kb
Host smart-10c269c5-fb7c-42e6-b35c-077031fba2ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981826473 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.981826473
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.3393164238
Short name T1073
Test name
Test status
Simulation time 4496802436 ps
CPU time 8.41 seconds
Started Jun 02 03:10:09 PM PDT 24
Finished Jun 02 03:10:18 PM PDT 24
Peak memory 243040 kb
Host smart-684e2766-9114-4a3c-807a-a1578822d664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393164238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.3393164238
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.1270014584
Short name T1161
Test name
Test status
Simulation time 695595696 ps
CPU time 2.05 seconds
Started Jun 02 03:10:09 PM PDT 24
Finished Jun 02 03:10:12 PM PDT 24
Peak memory 241176 kb
Host smart-234239ef-af9b-40ef-aeb9-781d6ecc7478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270014584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.1270014584
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.796309385
Short name T417
Test name
Test status
Simulation time 611403018 ps
CPU time 8.11 seconds
Started Jun 02 03:10:02 PM PDT 24
Finished Jun 02 03:10:11 PM PDT 24
Peak memory 242432 kb
Host smart-60366858-c433-4e37-83ab-cea848c051ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796309385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.796309385
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.3961397740
Short name T1042
Test name
Test status
Simulation time 844708028 ps
CPU time 11.5 seconds
Started Jun 02 03:10:03 PM PDT 24
Finished Jun 02 03:10:15 PM PDT 24
Peak memory 242180 kb
Host smart-3783a946-207e-48b3-bb9c-c0814a121df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961397740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.3961397740
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.1140270876
Short name T703
Test name
Test status
Simulation time 1065228027 ps
CPU time 20.1 seconds
Started Jun 02 03:10:01 PM PDT 24
Finished Jun 02 03:10:22 PM PDT 24
Peak memory 242572 kb
Host smart-dd4a12fa-37d3-4dea-b274-c4d60597dc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140270876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.1140270876
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.1149028814
Short name T665
Test name
Test status
Simulation time 2445248816 ps
CPU time 5.97 seconds
Started Jun 02 03:10:03 PM PDT 24
Finished Jun 02 03:10:09 PM PDT 24
Peak memory 242504 kb
Host smart-b6e84c8b-3c34-40c6-91f8-2d69bcefb995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149028814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.1149028814
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.2428158464
Short name T550
Test name
Test status
Simulation time 661504981 ps
CPU time 13.37 seconds
Started Jun 02 03:10:04 PM PDT 24
Finished Jun 02 03:10:18 PM PDT 24
Peak memory 242300 kb
Host smart-7ba71e2a-844e-44eb-a138-8dbef8c5efb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428158464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.2428158464
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.753991816
Short name T385
Test name
Test status
Simulation time 1123081904 ps
CPU time 29.44 seconds
Started Jun 02 03:10:06 PM PDT 24
Finished Jun 02 03:10:36 PM PDT 24
Peak memory 242420 kb
Host smart-2056c536-7ee6-4565-a685-96925dcd2fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753991816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.753991816
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.2708475960
Short name T791
Test name
Test status
Simulation time 1963755398 ps
CPU time 6.39 seconds
Started Jun 02 03:10:02 PM PDT 24
Finished Jun 02 03:10:09 PM PDT 24
Peak memory 242180 kb
Host smart-9278328e-36dd-4d0a-9669-895857932e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708475960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.2708475960
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.3319090576
Short name T720
Test name
Test status
Simulation time 641285753 ps
CPU time 16.12 seconds
Started Jun 02 03:10:05 PM PDT 24
Finished Jun 02 03:10:22 PM PDT 24
Peak memory 242252 kb
Host smart-7d8c2fb6-0fd9-4cc2-b1a5-1db09f1aeeaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3319090576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.3319090576
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.3718637753
Short name T105
Test name
Test status
Simulation time 243581760 ps
CPU time 4.74 seconds
Started Jun 02 03:10:03 PM PDT 24
Finished Jun 02 03:10:09 PM PDT 24
Peak memory 242232 kb
Host smart-7b011500-bd1b-42e8-86c9-85f713e86a04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3718637753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.3718637753
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.175476152
Short name T269
Test name
Test status
Simulation time 1656413064 ps
CPU time 8.39 seconds
Started Jun 02 03:10:01 PM PDT 24
Finished Jun 02 03:10:10 PM PDT 24
Peak memory 242220 kb
Host smart-6eedaede-cf82-48bf-9544-91360899dd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175476152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.175476152
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.3245792488
Short name T859
Test name
Test status
Simulation time 926663031 ps
CPU time 6.9 seconds
Started Jun 02 03:10:04 PM PDT 24
Finished Jun 02 03:10:11 PM PDT 24
Peak memory 241768 kb
Host smart-9ab31bc9-6322-45bf-9f18-62e64fe20655
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245792488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all
.3245792488
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.1292195266
Short name T827
Test name
Test status
Simulation time 79468008330 ps
CPU time 2072.99 seconds
Started Jun 02 03:10:02 PM PDT 24
Finished Jun 02 03:44:36 PM PDT 24
Peak memory 483260 kb
Host smart-5a5533de-4b05-4037-aada-58e789150a5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292195266 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.1292195266
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.3265514985
Short name T1192
Test name
Test status
Simulation time 1847040525 ps
CPU time 21.15 seconds
Started Jun 02 03:10:01 PM PDT 24
Finished Jun 02 03:10:23 PM PDT 24
Peak memory 242584 kb
Host smart-2854831a-ae85-476d-9c12-31fc46928ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265514985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.3265514985
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.4241048789
Short name T757
Test name
Test status
Simulation time 59781736 ps
CPU time 2.05 seconds
Started Jun 02 03:10:09 PM PDT 24
Finished Jun 02 03:10:12 PM PDT 24
Peak memory 240776 kb
Host smart-20b719f6-a9a2-4c15-86d4-805a85228007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241048789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.4241048789
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.3271059377
Short name T37
Test name
Test status
Simulation time 1745182321 ps
CPU time 31.47 seconds
Started Jun 02 03:10:07 PM PDT 24
Finished Jun 02 03:10:40 PM PDT 24
Peak memory 244292 kb
Host smart-ed323fab-aab6-4a8e-84ec-2a0d4d8d914f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271059377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.3271059377
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.2613591185
Short name T895
Test name
Test status
Simulation time 551009827 ps
CPU time 25.86 seconds
Started Jun 02 03:10:04 PM PDT 24
Finished Jun 02 03:10:30 PM PDT 24
Peak memory 242796 kb
Host smart-7709eb8c-7516-4b1c-8dc1-5dc173bd2ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613591185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.2613591185
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.1981380189
Short name T235
Test name
Test status
Simulation time 6631353350 ps
CPU time 18.72 seconds
Started Jun 02 03:10:06 PM PDT 24
Finished Jun 02 03:10:25 PM PDT 24
Peak memory 242908 kb
Host smart-146507e9-624c-4e2c-9538-61a45b4c9daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981380189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.1981380189
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.1246952556
Short name T1050
Test name
Test status
Simulation time 323209023 ps
CPU time 4.4 seconds
Started Jun 02 03:10:09 PM PDT 24
Finished Jun 02 03:10:14 PM PDT 24
Peak memory 242460 kb
Host smart-05d3f281-6860-4734-bf4f-56552c3d3d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246952556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.1246952556
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.357575239
Short name T151
Test name
Test status
Simulation time 716315838 ps
CPU time 19.78 seconds
Started Jun 02 03:10:06 PM PDT 24
Finished Jun 02 03:10:26 PM PDT 24
Peak memory 243048 kb
Host smart-e38c76bf-75ff-4335-9f5c-6fcbe77f4104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357575239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.357575239
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.2276756511
Short name T586
Test name
Test status
Simulation time 529295960 ps
CPU time 5.99 seconds
Started Jun 02 03:10:09 PM PDT 24
Finished Jun 02 03:10:16 PM PDT 24
Peak memory 242252 kb
Host smart-2421494e-2daf-468a-ac85-3a7567b68a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276756511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.2276756511
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.1604096824
Short name T341
Test name
Test status
Simulation time 6639441173 ps
CPU time 14.45 seconds
Started Jun 02 03:10:04 PM PDT 24
Finished Jun 02 03:10:19 PM PDT 24
Peak memory 242172 kb
Host smart-dd80a546-7304-4dcd-b859-8dd6def400e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604096824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.1604096824
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.1901640451
Short name T797
Test name
Test status
Simulation time 470447282 ps
CPU time 8.44 seconds
Started Jun 02 03:10:07 PM PDT 24
Finished Jun 02 03:10:16 PM PDT 24
Peak memory 248788 kb
Host smart-1b39b913-4106-42dc-b2c8-872b7ffeaa87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1901640451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.1901640451
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.972419963
Short name T1060
Test name
Test status
Simulation time 424523180 ps
CPU time 9.55 seconds
Started Jun 02 03:10:08 PM PDT 24
Finished Jun 02 03:10:19 PM PDT 24
Peak memory 242248 kb
Host smart-3a6bbc55-6606-4a66-9006-88be88d0a7f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=972419963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.972419963
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.1264004685
Short name T983
Test name
Test status
Simulation time 132141498 ps
CPU time 5.03 seconds
Started Jun 02 03:10:02 PM PDT 24
Finished Jun 02 03:10:08 PM PDT 24
Peak memory 242216 kb
Host smart-54788da8-2c82-473b-99dc-0c285bc7612b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264004685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.1264004685
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.1112895169
Short name T1015
Test name
Test status
Simulation time 2315911688 ps
CPU time 26.09 seconds
Started Jun 02 03:10:07 PM PDT 24
Finished Jun 02 03:10:34 PM PDT 24
Peak memory 242896 kb
Host smart-2d16adc2-6a1e-42d2-a886-d59e9ed8d5b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112895169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all
.1112895169
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.1089080841
Short name T759
Test name
Test status
Simulation time 251921555199 ps
CPU time 1637.44 seconds
Started Jun 02 03:10:08 PM PDT 24
Finished Jun 02 03:37:27 PM PDT 24
Peak memory 374748 kb
Host smart-14892c5b-01ca-4575-8599-bd9c02893260
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089080841 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.1089080841
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.4191261075
Short name T765
Test name
Test status
Simulation time 1494132528 ps
CPU time 31.62 seconds
Started Jun 02 03:10:07 PM PDT 24
Finished Jun 02 03:10:39 PM PDT 24
Peak memory 242516 kb
Host smart-e993fa19-6992-4d79-8111-e5277f046645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191261075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.4191261075
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.2363595601
Short name T799
Test name
Test status
Simulation time 86183807 ps
CPU time 1.81 seconds
Started Jun 02 03:10:07 PM PDT 24
Finished Jun 02 03:10:10 PM PDT 24
Peak memory 240912 kb
Host smart-86465f9c-de19-43c2-b754-a797e6a8d647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363595601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.2363595601
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.2180664473
Short name T820
Test name
Test status
Simulation time 3911093228 ps
CPU time 35.29 seconds
Started Jun 02 03:10:07 PM PDT 24
Finished Jun 02 03:10:43 PM PDT 24
Peak memory 247372 kb
Host smart-69961c61-a904-4bff-8da4-62b2f5b7ec8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180664473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.2180664473
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.5394774
Short name T295
Test name
Test status
Simulation time 1061973097 ps
CPU time 22.72 seconds
Started Jun 02 03:10:08 PM PDT 24
Finished Jun 02 03:10:31 PM PDT 24
Peak memory 242208 kb
Host smart-5ba356b1-63b4-42ba-83b8-592a9e56a007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5394774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.5394774
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.3190872806
Short name T606
Test name
Test status
Simulation time 169092433 ps
CPU time 5.33 seconds
Started Jun 02 03:10:08 PM PDT 24
Finished Jun 02 03:10:15 PM PDT 24
Peak memory 242404 kb
Host smart-6c59c4c1-1ac4-4c15-8017-b34f89933b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190872806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.3190872806
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.2263016920
Short name T165
Test name
Test status
Simulation time 3729309161 ps
CPU time 35.27 seconds
Started Jun 02 03:10:09 PM PDT 24
Finished Jun 02 03:10:45 PM PDT 24
Peak memory 245604 kb
Host smart-4dc8c010-43a3-4f6c-a447-a8d64cf42fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263016920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.2263016920
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.605746847
Short name T312
Test name
Test status
Simulation time 902878127 ps
CPU time 22.99 seconds
Started Jun 02 03:10:15 PM PDT 24
Finished Jun 02 03:10:39 PM PDT 24
Peak memory 242192 kb
Host smart-7b5e271a-b2da-4b28-b63c-9f6fc15acdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605746847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.605746847
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.2902364364
Short name T140
Test name
Test status
Simulation time 128914305 ps
CPU time 3.38 seconds
Started Jun 02 03:10:08 PM PDT 24
Finished Jun 02 03:10:13 PM PDT 24
Peak memory 242248 kb
Host smart-1a219328-ca48-466c-bcee-0d0fddb7a314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902364364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.2902364364
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.2634835233
Short name T1175
Test name
Test status
Simulation time 1667640872 ps
CPU time 27.8 seconds
Started Jun 02 03:10:06 PM PDT 24
Finished Jun 02 03:10:34 PM PDT 24
Peak memory 242228 kb
Host smart-c4e231e7-94fa-48ca-960a-d6ea778e3775
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2634835233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.2634835233
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.2511487427
Short name T367
Test name
Test status
Simulation time 824851210 ps
CPU time 6.1 seconds
Started Jun 02 03:10:15 PM PDT 24
Finished Jun 02 03:10:22 PM PDT 24
Peak memory 248864 kb
Host smart-08fbe484-ecdd-4439-802b-16a831a9967d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2511487427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.2511487427
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.3232722966
Short name T849
Test name
Test status
Simulation time 505356382 ps
CPU time 8.68 seconds
Started Jun 02 03:10:08 PM PDT 24
Finished Jun 02 03:10:18 PM PDT 24
Peak memory 248848 kb
Host smart-85c03836-8dd3-4692-b85b-90126f1818ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232722966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.3232722966
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.202050450
Short name T112
Test name
Test status
Simulation time 44183809506 ps
CPU time 228.32 seconds
Started Jun 02 03:10:15 PM PDT 24
Finished Jun 02 03:14:04 PM PDT 24
Peak memory 263228 kb
Host smart-b4801a09-ec59-4757-8846-1c8573703e11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202050450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.
202050450
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.2609468722
Short name T290
Test name
Test status
Simulation time 1380141601778 ps
CPU time 3370.11 seconds
Started Jun 02 03:10:08 PM PDT 24
Finished Jun 02 04:06:20 PM PDT 24
Peak memory 432724 kb
Host smart-c8c5cb7b-11c3-4d64-98b9-464d5ebed60d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609468722 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.2609468722
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.2185007161
Short name T1157
Test name
Test status
Simulation time 747231172 ps
CPU time 5.2 seconds
Started Jun 02 03:10:09 PM PDT 24
Finished Jun 02 03:10:15 PM PDT 24
Peak memory 242224 kb
Host smart-628573f7-93fe-490e-8517-521f60d66b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185007161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.2185007161
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.1695110943
Short name T400
Test name
Test status
Simulation time 765609270 ps
CPU time 1.76 seconds
Started Jun 02 03:10:11 PM PDT 24
Finished Jun 02 03:10:13 PM PDT 24
Peak memory 240844 kb
Host smart-c14bd4b0-1ff2-445a-bdff-39a6bac919fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695110943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.1695110943
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.117397921
Short name T56
Test name
Test status
Simulation time 1067867646 ps
CPU time 25.47 seconds
Started Jun 02 03:10:15 PM PDT 24
Finished Jun 02 03:10:40 PM PDT 24
Peak memory 243308 kb
Host smart-6eb05a9e-b07b-4953-8c97-32628636bf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117397921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.117397921
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.255767228
Short name T1159
Test name
Test status
Simulation time 724932012 ps
CPU time 9.98 seconds
Started Jun 02 03:10:12 PM PDT 24
Finished Jun 02 03:10:22 PM PDT 24
Peak memory 242088 kb
Host smart-f90d91d4-89a2-4472-a82b-f399d835c65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255767228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.255767228
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.4160137422
Short name T602
Test name
Test status
Simulation time 1273599673 ps
CPU time 29.77 seconds
Started Jun 02 03:10:14 PM PDT 24
Finished Jun 02 03:10:44 PM PDT 24
Peak memory 242308 kb
Host smart-28e78d3c-f80b-47ee-9b57-885faadee355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160137422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.4160137422
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.2279203144
Short name T694
Test name
Test status
Simulation time 145580556 ps
CPU time 4.27 seconds
Started Jun 02 03:10:18 PM PDT 24
Finished Jun 02 03:10:23 PM PDT 24
Peak memory 242280 kb
Host smart-44ca0d88-7b94-4742-be31-da69d3a06b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279203144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.2279203144
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.2836572961
Short name T230
Test name
Test status
Simulation time 868698356 ps
CPU time 22.57 seconds
Started Jun 02 03:10:18 PM PDT 24
Finished Jun 02 03:10:41 PM PDT 24
Peak memory 243100 kb
Host smart-fb71e781-055e-4112-8e56-c17699c8fd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836572961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.2836572961
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.2384580668
Short name T845
Test name
Test status
Simulation time 10902581019 ps
CPU time 40.39 seconds
Started Jun 02 03:10:15 PM PDT 24
Finished Jun 02 03:10:55 PM PDT 24
Peak memory 243556 kb
Host smart-4b4f1b9d-0f76-48b9-9652-2056d3c6c4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384580668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.2384580668
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.3050307595
Short name T732
Test name
Test status
Simulation time 211856576 ps
CPU time 5.57 seconds
Started Jun 02 03:10:13 PM PDT 24
Finished Jun 02 03:10:19 PM PDT 24
Peak memory 242548 kb
Host smart-2d629190-ff66-4f70-8857-f63786185d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050307595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.3050307595
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.3123516666
Short name T211
Test name
Test status
Simulation time 609493232 ps
CPU time 11.77 seconds
Started Jun 02 03:10:13 PM PDT 24
Finished Jun 02 03:10:25 PM PDT 24
Peak memory 242160 kb
Host smart-68427ca9-690b-4025-a172-737a3449d601
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3123516666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.3123516666
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.2642225659
Short name T375
Test name
Test status
Simulation time 172927207 ps
CPU time 6.66 seconds
Started Jun 02 03:10:12 PM PDT 24
Finished Jun 02 03:10:20 PM PDT 24
Peak memory 242644 kb
Host smart-d0e8cb11-6849-4aea-98f9-49abc8875221
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2642225659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.2642225659
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.2920956897
Short name T966
Test name
Test status
Simulation time 309011811 ps
CPU time 5.24 seconds
Started Jun 02 03:10:13 PM PDT 24
Finished Jun 02 03:10:19 PM PDT 24
Peak memory 242232 kb
Host smart-0173ebed-4c84-488a-a030-6bda585fd352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920956897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.2920956897
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.2487962534
Short name T1100
Test name
Test status
Simulation time 2469753349 ps
CPU time 49.62 seconds
Started Jun 02 03:10:14 PM PDT 24
Finished Jun 02 03:11:04 PM PDT 24
Peak memory 253212 kb
Host smart-29ba2950-8761-4e9d-9057-434f66a79a57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487962534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all
.2487962534
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.3385345597
Short name T782
Test name
Test status
Simulation time 732624595 ps
CPU time 15.19 seconds
Started Jun 02 03:10:13 PM PDT 24
Finished Jun 02 03:10:29 PM PDT 24
Peak memory 242064 kb
Host smart-e5b1e254-4b03-4ca5-8aa9-23f5f1f368ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385345597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.3385345597
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.1774789862
Short name T418
Test name
Test status
Simulation time 87337502 ps
CPU time 1.79 seconds
Started Jun 02 03:07:45 PM PDT 24
Finished Jun 02 03:07:48 PM PDT 24
Peak memory 240896 kb
Host smart-2aa170e1-c74e-4a69-818a-7b8fe8e40624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774789862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.1774789862
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.1223837280
Short name T862
Test name
Test status
Simulation time 1875463470 ps
CPU time 15.06 seconds
Started Jun 02 03:07:42 PM PDT 24
Finished Jun 02 03:07:58 PM PDT 24
Peak memory 242340 kb
Host smart-08d54613-0e8f-4a73-99bc-acaef928f86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223837280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.1223837280
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.3306060409
Short name T857
Test name
Test status
Simulation time 1076656824 ps
CPU time 17.45 seconds
Started Jun 02 03:07:45 PM PDT 24
Finished Jun 02 03:08:03 PM PDT 24
Peak memory 242352 kb
Host smart-a16c2d55-7ac7-4d2f-86e4-788081e92893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306060409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.3306060409
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.945838353
Short name T442
Test name
Test status
Simulation time 11819125946 ps
CPU time 29.21 seconds
Started Jun 02 03:07:44 PM PDT 24
Finished Jun 02 03:08:14 PM PDT 24
Peak memory 242448 kb
Host smart-81f60ea1-c6cd-442c-a487-cd63e1a24944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945838353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.945838353
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.1777505835
Short name T488
Test name
Test status
Simulation time 1893471033 ps
CPU time 6.27 seconds
Started Jun 02 03:07:41 PM PDT 24
Finished Jun 02 03:07:49 PM PDT 24
Peak memory 242628 kb
Host smart-6d8691d3-6bff-4f8b-8029-9c6d21daca73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777505835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.1777505835
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.2267889018
Short name T993
Test name
Test status
Simulation time 20103711069 ps
CPU time 56.46 seconds
Started Jun 02 03:07:47 PM PDT 24
Finished Jun 02 03:08:44 PM PDT 24
Peak memory 249016 kb
Host smart-21b3704e-f9c2-48f2-b93d-097413d7e0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267889018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.2267889018
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.710595300
Short name T904
Test name
Test status
Simulation time 1040128855 ps
CPU time 12.11 seconds
Started Jun 02 03:07:47 PM PDT 24
Finished Jun 02 03:07:59 PM PDT 24
Peak memory 248868 kb
Host smart-78cdd6dc-6201-4a1b-ae54-cabe875bb319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710595300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.710595300
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.2159188444
Short name T660
Test name
Test status
Simulation time 1365218992 ps
CPU time 23.1 seconds
Started Jun 02 03:07:47 PM PDT 24
Finished Jun 02 03:08:11 PM PDT 24
Peak memory 242256 kb
Host smart-bc302039-7124-4d8a-af6b-4121655ddc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159188444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.2159188444
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.2135166663
Short name T537
Test name
Test status
Simulation time 484278930 ps
CPU time 8.61 seconds
Started Jun 02 03:07:45 PM PDT 24
Finished Jun 02 03:07:55 PM PDT 24
Peak memory 242224 kb
Host smart-fdcebd3e-1b63-4266-9534-8d162776174d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2135166663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.2135166663
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.2181121947
Short name T408
Test name
Test status
Simulation time 4794691309 ps
CPU time 14.03 seconds
Started Jun 02 03:07:47 PM PDT 24
Finished Jun 02 03:08:01 PM PDT 24
Peak memory 242304 kb
Host smart-7ea7af20-2fc3-4770-9e76-6e50d33e996f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181121947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.2181121947
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.1773191058
Short name T1186
Test name
Test status
Simulation time 126503907431 ps
CPU time 1032.82 seconds
Started Jun 02 03:07:44 PM PDT 24
Finished Jun 02 03:24:58 PM PDT 24
Peak memory 363868 kb
Host smart-673a3c4b-19fa-475a-83eb-2d29ac19fcd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773191058 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.1773191058
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.3375552621
Short name T248
Test name
Test status
Simulation time 24204408576 ps
CPU time 72.11 seconds
Started Jun 02 03:07:46 PM PDT 24
Finished Jun 02 03:08:59 PM PDT 24
Peak memory 243784 kb
Host smart-53d4f7ac-ac6c-446d-a4d6-b5f06bd2b7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375552621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.3375552621
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.1534425605
Short name T492
Test name
Test status
Simulation time 227688901 ps
CPU time 5.52 seconds
Started Jun 02 03:10:12 PM PDT 24
Finished Jun 02 03:10:18 PM PDT 24
Peak memory 242368 kb
Host smart-5b0ab018-0d72-4207-b5de-80ce80d82fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534425605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.1534425605
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.2672236001
Short name T719
Test name
Test status
Simulation time 679824151 ps
CPU time 10.67 seconds
Started Jun 02 03:10:12 PM PDT 24
Finished Jun 02 03:10:23 PM PDT 24
Peak memory 242724 kb
Host smart-b56fbe24-d17a-44ed-8ee9-b79ba7944197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672236001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.2672236001
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.908261525
Short name T1004
Test name
Test status
Simulation time 108740446717 ps
CPU time 3014.37 seconds
Started Jun 02 03:10:13 PM PDT 24
Finished Jun 02 04:00:29 PM PDT 24
Peak memory 553304 kb
Host smart-f590b6fa-db39-4907-80dc-5aeea1b0f747
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908261525 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.908261525
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.2036964273
Short name T72
Test name
Test status
Simulation time 110506236 ps
CPU time 3.98 seconds
Started Jun 02 03:10:15 PM PDT 24
Finished Jun 02 03:10:20 PM PDT 24
Peak memory 242404 kb
Host smart-ff59dca1-bdbb-4c0e-ab1b-d837c3ba10e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036964273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.2036964273
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.538032799
Short name T573
Test name
Test status
Simulation time 706935263 ps
CPU time 5.81 seconds
Started Jun 02 03:10:13 PM PDT 24
Finished Jun 02 03:10:19 PM PDT 24
Peak memory 242580 kb
Host smart-ae64f3ed-6d89-42f8-82ff-26cb73f8306f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538032799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.538032799
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.3294239511
Short name T1138
Test name
Test status
Simulation time 12654567249 ps
CPU time 338.64 seconds
Started Jun 02 03:10:13 PM PDT 24
Finished Jun 02 03:15:52 PM PDT 24
Peak memory 263528 kb
Host smart-61ee90ce-4e9a-4345-a058-ddddee5d0ebb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294239511 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.3294239511
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.45038299
Short name T456
Test name
Test status
Simulation time 469537551 ps
CPU time 3.89 seconds
Started Jun 02 03:10:14 PM PDT 24
Finished Jun 02 03:10:18 PM PDT 24
Peak memory 242464 kb
Host smart-25f23e05-553b-4ddc-834e-a6664e511401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45038299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.45038299
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.527467201
Short name T133
Test name
Test status
Simulation time 340864511 ps
CPU time 7.25 seconds
Started Jun 02 03:10:14 PM PDT 24
Finished Jun 02 03:10:22 PM PDT 24
Peak memory 242332 kb
Host smart-a391f1a9-845b-4d27-b394-6f4eb913a875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527467201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.527467201
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.1440789103
Short name T388
Test name
Test status
Simulation time 16098888456 ps
CPU time 446.36 seconds
Started Jun 02 03:10:14 PM PDT 24
Finished Jun 02 03:17:41 PM PDT 24
Peak memory 257272 kb
Host smart-f6872f6a-cded-4e7c-865b-ce6042cbc403
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440789103 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.1440789103
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.25712019
Short name T513
Test name
Test status
Simulation time 1997338317 ps
CPU time 3.99 seconds
Started Jun 02 03:10:20 PM PDT 24
Finished Jun 02 03:10:25 PM PDT 24
Peak memory 242616 kb
Host smart-4be893a0-f3b4-407c-a3c1-707a33ac8943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25712019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.25712019
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.828388483
Short name T633
Test name
Test status
Simulation time 658767026 ps
CPU time 22.58 seconds
Started Jun 02 03:10:17 PM PDT 24
Finished Jun 02 03:10:40 PM PDT 24
Peak memory 242540 kb
Host smart-270149fe-418a-43d0-934d-13fd1fb0fc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828388483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.828388483
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.2532911184
Short name T286
Test name
Test status
Simulation time 60798285339 ps
CPU time 1393.64 seconds
Started Jun 02 03:10:16 PM PDT 24
Finished Jun 02 03:33:31 PM PDT 24
Peak memory 270760 kb
Host smart-2d845824-7a15-44ce-ac8d-9d4aa5bb426c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532911184 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.2532911184
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.1450922313
Short name T751
Test name
Test status
Simulation time 219409647 ps
CPU time 4.82 seconds
Started Jun 02 03:10:17 PM PDT 24
Finished Jun 02 03:10:23 PM PDT 24
Peak memory 242284 kb
Host smart-28d8f7fc-8be4-4176-8f37-712b14c8b852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450922313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.1450922313
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.3411191276
Short name T202
Test name
Test status
Simulation time 227224590 ps
CPU time 2.64 seconds
Started Jun 02 03:10:19 PM PDT 24
Finished Jun 02 03:10:22 PM PDT 24
Peak memory 242180 kb
Host smart-194de97b-cf2d-42fd-a9fa-2972f9932edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411191276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.3411191276
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.3018730401
Short name T428
Test name
Test status
Simulation time 48088451524 ps
CPU time 774.99 seconds
Started Jun 02 03:10:17 PM PDT 24
Finished Jun 02 03:23:13 PM PDT 24
Peak memory 272640 kb
Host smart-38a8dfd6-c6b9-4bb9-af9b-04e1c3c82a60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018730401 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.3018730401
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.2978579980
Short name T945
Test name
Test status
Simulation time 263438727 ps
CPU time 4.52 seconds
Started Jun 02 03:10:19 PM PDT 24
Finished Jun 02 03:10:24 PM PDT 24
Peak memory 242612 kb
Host smart-0f417c40-7211-4298-80b8-ecb26baf5a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978579980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.2978579980
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.4107560091
Short name T597
Test name
Test status
Simulation time 195887045 ps
CPU time 8.91 seconds
Started Jun 02 03:10:30 PM PDT 24
Finished Jun 02 03:10:39 PM PDT 24
Peak memory 242176 kb
Host smart-d8c12650-84f0-4152-be21-bae20822442d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107560091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.4107560091
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.2229679122
Short name T131
Test name
Test status
Simulation time 523654016626 ps
CPU time 1553.99 seconds
Started Jun 02 03:10:18 PM PDT 24
Finished Jun 02 03:36:13 PM PDT 24
Peak memory 366464 kb
Host smart-f31bf291-bdea-4d8b-804b-446526e97049
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229679122 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.2229679122
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.3576556921
Short name T1141
Test name
Test status
Simulation time 89765433 ps
CPU time 3.32 seconds
Started Jun 02 03:10:17 PM PDT 24
Finished Jun 02 03:10:20 PM PDT 24
Peak memory 242628 kb
Host smart-9f9b7c32-65a5-481b-96c3-a0e581dcfc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576556921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.3576556921
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.133986511
Short name T974
Test name
Test status
Simulation time 169354833 ps
CPU time 4.34 seconds
Started Jun 02 03:10:21 PM PDT 24
Finished Jun 02 03:10:25 PM PDT 24
Peak memory 242292 kb
Host smart-6c3a9dfe-7346-440e-b01e-21e3fc781ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133986511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.133986511
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.2237529081
Short name T867
Test name
Test status
Simulation time 6939092144 ps
CPU time 19 seconds
Started Jun 02 03:10:20 PM PDT 24
Finished Jun 02 03:10:40 PM PDT 24
Peak memory 242276 kb
Host smart-4a920a21-cfa0-4946-a35f-d4618973329d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237529081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.2237529081
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.1941537941
Short name T525
Test name
Test status
Simulation time 327387926 ps
CPU time 4.59 seconds
Started Jun 02 03:10:23 PM PDT 24
Finished Jun 02 03:10:28 PM PDT 24
Peak memory 242464 kb
Host smart-aa284268-110d-441e-9ded-4f7fa5ddfdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941537941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.1941537941
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.1043255412
Short name T1181
Test name
Test status
Simulation time 230912703 ps
CPU time 9.68 seconds
Started Jun 02 03:10:24 PM PDT 24
Finished Jun 02 03:10:34 PM PDT 24
Peak memory 242404 kb
Host smart-0441fe17-e828-4f8c-9712-0c58c22bfd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043255412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.1043255412
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.2492680441
Short name T316
Test name
Test status
Simulation time 102969334930 ps
CPU time 3146.94 seconds
Started Jun 02 03:10:32 PM PDT 24
Finished Jun 02 04:03:00 PM PDT 24
Peak memory 347372 kb
Host smart-ee4ce785-ddd6-499e-95cd-21f7fc7df58d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492680441 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.2492680441
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.2672766774
Short name T741
Test name
Test status
Simulation time 244631919 ps
CPU time 4.31 seconds
Started Jun 02 03:10:32 PM PDT 24
Finished Jun 02 03:10:37 PM PDT 24
Peak memory 242524 kb
Host smart-9dd54408-5c15-4821-ad18-b1403593d6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672766774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.2672766774
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.351761292
Short name T579
Test name
Test status
Simulation time 241502628 ps
CPU time 4.23 seconds
Started Jun 02 03:10:32 PM PDT 24
Finished Jun 02 03:10:37 PM PDT 24
Peak memory 242044 kb
Host smart-457e122a-57df-4857-aa8b-e75a2a07d29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351761292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.351761292
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.1841073672
Short name T566
Test name
Test status
Simulation time 97113961 ps
CPU time 1.89 seconds
Started Jun 02 03:07:50 PM PDT 24
Finished Jun 02 03:07:52 PM PDT 24
Peak memory 240776 kb
Host smart-69f8020c-7d70-4c45-acd1-b6cb865cb183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841073672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.1841073672
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.3453171716
Short name T915
Test name
Test status
Simulation time 25287170613 ps
CPU time 44.68 seconds
Started Jun 02 03:07:45 PM PDT 24
Finished Jun 02 03:08:30 PM PDT 24
Peak memory 243868 kb
Host smart-03921466-a9d5-4cf2-9fe7-10ef3827cfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453171716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.3453171716
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.2483791388
Short name T989
Test name
Test status
Simulation time 11366132552 ps
CPU time 27.91 seconds
Started Jun 02 03:07:52 PM PDT 24
Finished Jun 02 03:08:21 PM PDT 24
Peak memory 243412 kb
Host smart-bc7dbd32-eee4-4221-a67b-7686cb95805f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483791388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.2483791388
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.3247014192
Short name T536
Test name
Test status
Simulation time 2175594398 ps
CPU time 33.01 seconds
Started Jun 02 03:07:46 PM PDT 24
Finished Jun 02 03:08:20 PM PDT 24
Peak memory 249204 kb
Host smart-676ba54a-3993-4698-973b-be459720bd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247014192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.3247014192
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.3409617081
Short name T458
Test name
Test status
Simulation time 1195959592 ps
CPU time 11.19 seconds
Started Jun 02 03:07:52 PM PDT 24
Finished Jun 02 03:08:04 PM PDT 24
Peak memory 242516 kb
Host smart-709a984c-255f-40ea-9d3e-308c91ed5c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409617081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.3409617081
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.2657760454
Short name T5
Test name
Test status
Simulation time 439022111 ps
CPU time 12.8 seconds
Started Jun 02 03:07:53 PM PDT 24
Finished Jun 02 03:08:07 PM PDT 24
Peak memory 242516 kb
Host smart-eaa700a9-36b5-402c-8ab8-45f53b6bc3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657760454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.2657760454
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.3089101134
Short name T554
Test name
Test status
Simulation time 815721938 ps
CPU time 5.57 seconds
Started Jun 02 03:07:53 PM PDT 24
Finished Jun 02 03:07:59 PM PDT 24
Peak memory 242452 kb
Host smart-dd62d918-0e91-4e73-9a13-a9ea0664796f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089101134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.3089101134
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.2335751915
Short name T709
Test name
Test status
Simulation time 462060807 ps
CPU time 11.04 seconds
Started Jun 02 03:07:48 PM PDT 24
Finished Jun 02 03:07:59 PM PDT 24
Peak memory 242584 kb
Host smart-893bb322-3bf5-4f68-8e3e-9d8a216cda98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335751915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.2335751915
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.1033889076
Short name T387
Test name
Test status
Simulation time 1200946331 ps
CPU time 11.02 seconds
Started Jun 02 03:07:47 PM PDT 24
Finished Jun 02 03:07:58 PM PDT 24
Peak memory 242460 kb
Host smart-ed1bad1b-a35c-4b18-a2e0-6705c050568e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1033889076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.1033889076
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.4104539458
Short name T876
Test name
Test status
Simulation time 145541045 ps
CPU time 4.39 seconds
Started Jun 02 03:07:52 PM PDT 24
Finished Jun 02 03:07:57 PM PDT 24
Peak memory 242300 kb
Host smart-17b8175d-5fcf-4430-b1c2-3a8c218989bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4104539458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.4104539458
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.784157215
Short name T681
Test name
Test status
Simulation time 139088074 ps
CPU time 6.09 seconds
Started Jun 02 03:07:45 PM PDT 24
Finished Jun 02 03:07:52 PM PDT 24
Peak memory 242280 kb
Host smart-eecbc6e3-c723-448e-b723-e6b5332ce6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784157215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.784157215
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.415474845
Short name T67
Test name
Test status
Simulation time 145912415186 ps
CPU time 211.04 seconds
Started Jun 02 03:07:55 PM PDT 24
Finished Jun 02 03:11:27 PM PDT 24
Peak memory 257120 kb
Host smart-9015a9a4-7893-45cf-bc6f-84d642bb3b3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415474845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.415474845
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.404899384
Short name T567
Test name
Test status
Simulation time 624324847 ps
CPU time 4.78 seconds
Started Jun 02 03:07:53 PM PDT 24
Finished Jun 02 03:07:59 PM PDT 24
Peak memory 242408 kb
Host smart-9a38d7cd-a090-47cf-8447-023710c92a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404899384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.404899384
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.3055796317
Short name T1183
Test name
Test status
Simulation time 329020962 ps
CPU time 4.08 seconds
Started Jun 02 03:10:24 PM PDT 24
Finished Jun 02 03:10:28 PM PDT 24
Peak memory 242596 kb
Host smart-58afac77-1061-4706-a202-ac10f1aee2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055796317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.3055796317
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.1646870865
Short name T906
Test name
Test status
Simulation time 226990509 ps
CPU time 5.02 seconds
Started Jun 02 03:10:23 PM PDT 24
Finished Jun 02 03:10:29 PM PDT 24
Peak memory 242156 kb
Host smart-a4ed7031-416f-4f8e-ba08-644188802071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646870865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1646870865
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.3190616710
Short name T292
Test name
Test status
Simulation time 763059429121 ps
CPU time 2293.79 seconds
Started Jun 02 03:10:25 PM PDT 24
Finished Jun 02 03:48:40 PM PDT 24
Peak memory 395892 kb
Host smart-20938286-dbef-4fdf-8c2e-fb5516c9a326
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190616710 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.3190616710
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.2080263618
Short name T828
Test name
Test status
Simulation time 163734527 ps
CPU time 4.61 seconds
Started Jun 02 03:10:32 PM PDT 24
Finished Jun 02 03:10:37 PM PDT 24
Peak memory 242632 kb
Host smart-de7aba25-8e59-496a-8e3b-b5a0857799d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080263618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.2080263618
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.1455777323
Short name T590
Test name
Test status
Simulation time 2672853318 ps
CPU time 10.61 seconds
Started Jun 02 03:10:23 PM PDT 24
Finished Jun 02 03:10:34 PM PDT 24
Peak memory 242304 kb
Host smart-fef1e531-ed7a-41f5-8230-c85bf50345e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455777323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.1455777323
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.4212929335
Short name T121
Test name
Test status
Simulation time 106420843 ps
CPU time 3.51 seconds
Started Jun 02 03:10:24 PM PDT 24
Finished Jun 02 03:10:28 PM PDT 24
Peak memory 242556 kb
Host smart-3518bb62-cce0-48d1-86ae-b525e0b56a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212929335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.4212929335
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.4070990949
Short name T619
Test name
Test status
Simulation time 2811092917 ps
CPU time 7.38 seconds
Started Jun 02 03:10:23 PM PDT 24
Finished Jun 02 03:10:31 PM PDT 24
Peak memory 242392 kb
Host smart-b54134eb-73ae-4955-8cc9-6730a0ac459d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070990949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.4070990949
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.2332065953
Short name T7
Test name
Test status
Simulation time 178751380387 ps
CPU time 583.4 seconds
Started Jun 02 03:10:22 PM PDT 24
Finished Jun 02 03:20:06 PM PDT 24
Peak memory 334864 kb
Host smart-905f0e1a-a397-40f3-995a-92d087bf434a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332065953 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.2332065953
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.1669349616
Short name T611
Test name
Test status
Simulation time 320275743 ps
CPU time 4.53 seconds
Started Jun 02 03:10:24 PM PDT 24
Finished Jun 02 03:10:29 PM PDT 24
Peak memory 242340 kb
Host smart-f4b9d03c-85cd-4d18-abca-53471f205fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669349616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.1669349616
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.1369184426
Short name T424
Test name
Test status
Simulation time 2530975114 ps
CPU time 20.4 seconds
Started Jun 02 03:10:32 PM PDT 24
Finished Jun 02 03:10:53 PM PDT 24
Peak memory 242136 kb
Host smart-f8e9bb1a-f64e-41d5-9bdd-2f590a3a5027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369184426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.1369184426
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.3840102516
Short name T250
Test name
Test status
Simulation time 450086216 ps
CPU time 4.5 seconds
Started Jun 02 03:10:35 PM PDT 24
Finished Jun 02 03:10:40 PM PDT 24
Peak memory 242636 kb
Host smart-50a663af-bae7-41c8-b77f-68fd3196fe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840102516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.3840102516
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.671467148
Short name T1019
Test name
Test status
Simulation time 1045507371 ps
CPU time 16.79 seconds
Started Jun 02 03:10:27 PM PDT 24
Finished Jun 02 03:10:45 PM PDT 24
Peak memory 242248 kb
Host smart-485e9de3-0a83-4c2a-945f-26e246197048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671467148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.671467148
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.1125963266
Short name T423
Test name
Test status
Simulation time 70682913383 ps
CPU time 2114.02 seconds
Started Jun 02 03:10:28 PM PDT 24
Finished Jun 02 03:45:43 PM PDT 24
Peak memory 373952 kb
Host smart-b045299d-5c41-4d65-8cac-31ff7d796d95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125963266 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.1125963266
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.2112279120
Short name T73
Test name
Test status
Simulation time 583986151 ps
CPU time 4.63 seconds
Started Jun 02 03:10:28 PM PDT 24
Finished Jun 02 03:10:33 PM PDT 24
Peak memory 242244 kb
Host smart-ad1978e7-abf4-4c32-83d7-8ade0704f181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112279120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.2112279120
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.3903568257
Short name T99
Test name
Test status
Simulation time 492621349 ps
CPU time 5.39 seconds
Started Jun 02 03:10:27 PM PDT 24
Finished Jun 02 03:10:32 PM PDT 24
Peak memory 242284 kb
Host smart-10bc8cea-c6ef-4c77-a6e1-a727c80f7505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903568257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.3903568257
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.2633096333
Short name T15
Test name
Test status
Simulation time 48591301700 ps
CPU time 1238.91 seconds
Started Jun 02 03:10:33 PM PDT 24
Finished Jun 02 03:31:13 PM PDT 24
Peak memory 494708 kb
Host smart-d2c5c36f-e0e9-4b0b-b080-c0099b4b7e36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633096333 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.2633096333
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.3275148143
Short name T880
Test name
Test status
Simulation time 197092985 ps
CPU time 4.18 seconds
Started Jun 02 03:10:34 PM PDT 24
Finished Jun 02 03:10:39 PM PDT 24
Peak memory 242716 kb
Host smart-c28ae806-7f40-4409-93ac-3e95c8de32b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275148143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.3275148143
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.2236169515
Short name T848
Test name
Test status
Simulation time 1353011029 ps
CPU time 18.15 seconds
Started Jun 02 03:10:32 PM PDT 24
Finished Jun 02 03:10:51 PM PDT 24
Peak memory 242232 kb
Host smart-5b0227d5-304c-4001-bef8-2a0e5cc6cff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236169515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.2236169515
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.539601609
Short name T1112
Test name
Test status
Simulation time 95977682313 ps
CPU time 2308.66 seconds
Started Jun 02 03:10:34 PM PDT 24
Finished Jun 02 03:49:04 PM PDT 24
Peak memory 600908 kb
Host smart-00b1d312-5b70-499c-b506-db7483246d39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539601609 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.539601609
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.842545928
Short name T840
Test name
Test status
Simulation time 1612796441 ps
CPU time 4.25 seconds
Started Jun 02 03:10:27 PM PDT 24
Finished Jun 02 03:10:32 PM PDT 24
Peak memory 242804 kb
Host smart-2afa4180-05a7-4774-b409-f322d258317b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842545928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.842545928
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.1451742459
Short name T299
Test name
Test status
Simulation time 148140304 ps
CPU time 4.52 seconds
Started Jun 02 03:10:34 PM PDT 24
Finished Jun 02 03:10:40 PM PDT 24
Peak memory 242568 kb
Host smart-a9540e26-48a6-485d-a612-37e708c41f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451742459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.1451742459
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.3131101993
Short name T396
Test name
Test status
Simulation time 23861682941 ps
CPU time 483.95 seconds
Started Jun 02 03:10:33 PM PDT 24
Finished Jun 02 03:18:38 PM PDT 24
Peak memory 258352 kb
Host smart-4a929ce7-502a-4910-b256-bbbf49af7e70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131101993 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.3131101993
Directory /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.3246810521
Short name T1178
Test name
Test status
Simulation time 169578747 ps
CPU time 4.24 seconds
Started Jun 02 03:10:34 PM PDT 24
Finished Jun 02 03:10:39 PM PDT 24
Peak memory 242648 kb
Host smart-c042d6bd-3c68-433c-85ad-b9f8884de92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246810521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.3246810521
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.1451503951
Short name T584
Test name
Test status
Simulation time 188806817 ps
CPU time 2.94 seconds
Started Jun 02 03:10:27 PM PDT 24
Finished Jun 02 03:10:31 PM PDT 24
Peak memory 242300 kb
Host smart-1b7f01df-0268-4c4e-9747-0f266195b04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451503951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.1451503951
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.2796155870
Short name T1075
Test name
Test status
Simulation time 140502412 ps
CPU time 4.06 seconds
Started Jun 02 03:10:34 PM PDT 24
Finished Jun 02 03:10:39 PM PDT 24
Peak memory 242304 kb
Host smart-ce665e12-1e71-4bcf-a930-56a4a2ac3483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796155870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.2796155870
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.2682330072
Short name T340
Test name
Test status
Simulation time 271882267 ps
CPU time 7.89 seconds
Started Jun 02 03:10:26 PM PDT 24
Finished Jun 02 03:10:35 PM PDT 24
Peak memory 242180 kb
Host smart-6966239c-a675-498f-b2d2-5af93df9ebc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682330072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.2682330072
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.1954957027
Short name T1049
Test name
Test status
Simulation time 199755182 ps
CPU time 2.04 seconds
Started Jun 02 03:07:51 PM PDT 24
Finished Jun 02 03:07:54 PM PDT 24
Peak memory 240944 kb
Host smart-7131ab9e-16da-4e8c-8b66-f953691b7dc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954957027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.1954957027
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.2190578110
Short name T178
Test name
Test status
Simulation time 910695000 ps
CPU time 6.82 seconds
Started Jun 02 03:07:52 PM PDT 24
Finished Jun 02 03:08:00 PM PDT 24
Peak memory 248940 kb
Host smart-dca55ecf-4612-4f9b-b864-fb62f6ae2777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190578110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.2190578110
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.3426254126
Short name T831
Test name
Test status
Simulation time 11966261878 ps
CPU time 31.6 seconds
Started Jun 02 03:07:50 PM PDT 24
Finished Jun 02 03:08:23 PM PDT 24
Peak memory 243360 kb
Host smart-183f87b5-8aa8-4b37-a579-3e09ca134829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426254126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.3426254126
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.1518215660
Short name T916
Test name
Test status
Simulation time 706421071 ps
CPU time 20.55 seconds
Started Jun 02 03:07:51 PM PDT 24
Finished Jun 02 03:08:12 PM PDT 24
Peak memory 242612 kb
Host smart-77aa2e48-e0b9-4405-9151-b908fbc08824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518215660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.1518215660
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.671822165
Short name T1065
Test name
Test status
Simulation time 13054926076 ps
CPU time 35.84 seconds
Started Jun 02 03:07:52 PM PDT 24
Finished Jun 02 03:08:29 PM PDT 24
Peak memory 242792 kb
Host smart-5270aa51-fdfe-43c6-8b49-34df27e6b526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671822165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.671822165
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.483319617
Short name T920
Test name
Test status
Simulation time 174344192 ps
CPU time 4.35 seconds
Started Jun 02 03:07:53 PM PDT 24
Finished Jun 02 03:07:58 PM PDT 24
Peak memory 242404 kb
Host smart-b82e4433-d2aa-406b-96f4-f1f020f9ae5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483319617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.483319617
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.2180568842
Short name T952
Test name
Test status
Simulation time 3190891297 ps
CPU time 31.48 seconds
Started Jun 02 03:07:50 PM PDT 24
Finished Jun 02 03:08:22 PM PDT 24
Peak memory 244668 kb
Host smart-d7d71d95-b498-4a6f-9264-000f44bfae3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180568842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.2180568842
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.527205522
Short name T671
Test name
Test status
Simulation time 503222866 ps
CPU time 22.96 seconds
Started Jun 02 03:07:52 PM PDT 24
Finished Jun 02 03:08:17 PM PDT 24
Peak memory 242436 kb
Host smart-fb1f2563-db1a-40b1-a457-a00b29467d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527205522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.527205522
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.2226656698
Short name T71
Test name
Test status
Simulation time 3068162085 ps
CPU time 11.19 seconds
Started Jun 02 03:07:52 PM PDT 24
Finished Jun 02 03:08:04 PM PDT 24
Peak memory 242316 kb
Host smart-4d2584a1-33e3-4430-8093-57126d7d7c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226656698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.2226656698
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.413531341
Short name T510
Test name
Test status
Simulation time 679523937 ps
CPU time 22.29 seconds
Started Jun 02 03:07:52 PM PDT 24
Finished Jun 02 03:08:16 PM PDT 24
Peak memory 248892 kb
Host smart-efc869f3-bfe2-4026-8381-16a1518276f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=413531341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.413531341
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.2780257124
Short name T1039
Test name
Test status
Simulation time 403103550 ps
CPU time 4.56 seconds
Started Jun 02 03:07:54 PM PDT 24
Finished Jun 02 03:07:59 PM PDT 24
Peak memory 242460 kb
Host smart-59593f36-d8da-4eb9-8f0d-7483db027791
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2780257124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.2780257124
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.3467810382
Short name T953
Test name
Test status
Simulation time 284901822 ps
CPU time 5.06 seconds
Started Jun 02 03:07:51 PM PDT 24
Finished Jun 02 03:07:57 PM PDT 24
Peak memory 242228 kb
Host smart-16d3599c-4a7c-488c-b503-c55a982cd31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467810382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.3467810382
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.697355293
Short name T685
Test name
Test status
Simulation time 546590734345 ps
CPU time 3211.32 seconds
Started Jun 02 03:07:53 PM PDT 24
Finished Jun 02 04:01:26 PM PDT 24
Peak memory 330892 kb
Host smart-8f3f471d-a655-44e1-a835-a25877736681
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697355293 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.697355293
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.1249661329
Short name T347
Test name
Test status
Simulation time 1486743016 ps
CPU time 11.95 seconds
Started Jun 02 03:07:54 PM PDT 24
Finished Jun 02 03:08:06 PM PDT 24
Peak memory 242460 kb
Host smart-8542f32f-b93d-4a3c-ae96-6adc670f67a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249661329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.1249661329
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.3713507515
Short name T158
Test name
Test status
Simulation time 635826412 ps
CPU time 4.24 seconds
Started Jun 02 03:10:28 PM PDT 24
Finished Jun 02 03:10:33 PM PDT 24
Peak memory 242684 kb
Host smart-183feefd-ec62-4d11-9228-479f2daaaa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713507515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.3713507515
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.3625103736
Short name T419
Test name
Test status
Simulation time 215046961 ps
CPU time 5.67 seconds
Started Jun 02 03:10:35 PM PDT 24
Finished Jun 02 03:10:42 PM PDT 24
Peak memory 242248 kb
Host smart-f153bc12-7121-4e23-870a-f37b37ef176b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625103736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.3625103736
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.562544422
Short name T1093
Test name
Test status
Simulation time 35859008793 ps
CPU time 991.13 seconds
Started Jun 02 03:10:33 PM PDT 24
Finished Jun 02 03:27:05 PM PDT 24
Peak memory 259072 kb
Host smart-a93098c7-49fa-46f8-9101-b5563b27a86f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562544422 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.562544422
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.1212002506
Short name T605
Test name
Test status
Simulation time 388005297 ps
CPU time 4.3 seconds
Started Jun 02 03:10:37 PM PDT 24
Finished Jun 02 03:10:42 PM PDT 24
Peak memory 242344 kb
Host smart-810369ec-7491-4eb1-a970-3a8d09307512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212002506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.1212002506
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.2243406129
Short name T909
Test name
Test status
Simulation time 8427802559 ps
CPU time 21.33 seconds
Started Jun 02 03:10:35 PM PDT 24
Finished Jun 02 03:10:57 PM PDT 24
Peak memory 242256 kb
Host smart-e71f6a99-e777-488e-9ef6-db3eede12522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243406129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.2243406129
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.2352117493
Short name T470
Test name
Test status
Simulation time 144974892 ps
CPU time 4.13 seconds
Started Jun 02 03:10:40 PM PDT 24
Finished Jun 02 03:10:45 PM PDT 24
Peak memory 242724 kb
Host smart-6c4b3102-a55d-4609-995d-5f97335d6ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352117493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.2352117493
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.4036960979
Short name T628
Test name
Test status
Simulation time 585722836 ps
CPU time 12.98 seconds
Started Jun 02 03:10:36 PM PDT 24
Finished Jun 02 03:10:50 PM PDT 24
Peak memory 242392 kb
Host smart-4fac3375-95fe-4f97-8f56-53cceec5191a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036960979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.4036960979
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.994354399
Short name T810
Test name
Test status
Simulation time 352931446618 ps
CPU time 2838.84 seconds
Started Jun 02 03:10:35 PM PDT 24
Finished Jun 02 03:57:55 PM PDT 24
Peak memory 348692 kb
Host smart-a8e8ca0f-4f5b-4763-b8c0-8d60e5627b7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994354399 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.994354399
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.1894262057
Short name T623
Test name
Test status
Simulation time 483115882 ps
CPU time 4.54 seconds
Started Jun 02 03:10:34 PM PDT 24
Finished Jun 02 03:10:40 PM PDT 24
Peak memory 242536 kb
Host smart-64b76d2b-a76c-44e7-b346-3f76b91683bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894262057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.1894262057
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.2741658682
Short name T713
Test name
Test status
Simulation time 4616276304 ps
CPU time 18.39 seconds
Started Jun 02 03:10:36 PM PDT 24
Finished Jun 02 03:10:55 PM PDT 24
Peak memory 242616 kb
Host smart-3fe2dfa9-2953-46a2-91f3-0dd0c5656713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741658682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.2741658682
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.173660578
Short name T922
Test name
Test status
Simulation time 639816866 ps
CPU time 4.58 seconds
Started Jun 02 03:10:35 PM PDT 24
Finished Jun 02 03:10:41 PM PDT 24
Peak memory 242660 kb
Host smart-f25a683b-6c4a-4a35-b8b5-f83874f538f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173660578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.173660578
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.4264442172
Short name T858
Test name
Test status
Simulation time 3387383276 ps
CPU time 23.68 seconds
Started Jun 02 03:10:35 PM PDT 24
Finished Jun 02 03:11:00 PM PDT 24
Peak memory 242472 kb
Host smart-d9a92d36-9367-4571-a19f-105237f2a08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264442172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.4264442172
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.3847947529
Short name T221
Test name
Test status
Simulation time 131092780099 ps
CPU time 1077.34 seconds
Started Jun 02 03:10:34 PM PDT 24
Finished Jun 02 03:28:33 PM PDT 24
Peak memory 265472 kb
Host smart-4e6392f3-f2fe-4067-82d1-2342ea0bb362
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847947529 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.3847947529
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.2991584835
Short name T1001
Test name
Test status
Simulation time 447875952 ps
CPU time 4.8 seconds
Started Jun 02 03:10:36 PM PDT 24
Finished Jun 02 03:10:42 PM PDT 24
Peak memory 242496 kb
Host smart-78d6b675-4542-40ce-9d5a-56d47fcb261e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991584835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.2991584835
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.1625478303
Short name T556
Test name
Test status
Simulation time 245824249 ps
CPU time 6.32 seconds
Started Jun 02 03:10:36 PM PDT 24
Finished Jun 02 03:10:43 PM PDT 24
Peak memory 242568 kb
Host smart-bdc5be37-6a6c-4c99-987e-53c996717ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625478303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.1625478303
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.1141298874
Short name T742
Test name
Test status
Simulation time 134526239487 ps
CPU time 2298.26 seconds
Started Jun 02 03:10:34 PM PDT 24
Finished Jun 02 03:48:53 PM PDT 24
Peak memory 281024 kb
Host smart-ed093897-d26a-4eef-bd65-3a377f8c6f28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141298874 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.1141298874
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.3568534433
Short name T490
Test name
Test status
Simulation time 296297235 ps
CPU time 6.7 seconds
Started Jun 02 03:10:33 PM PDT 24
Finished Jun 02 03:10:40 PM PDT 24
Peak memory 242240 kb
Host smart-f2809c25-ab19-486f-804d-896da349fc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568534433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.3568534433
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.1352036162
Short name T893
Test name
Test status
Simulation time 2609162783 ps
CPU time 5.65 seconds
Started Jun 02 03:10:38 PM PDT 24
Finished Jun 02 03:10:44 PM PDT 24
Peak memory 242488 kb
Host smart-507e8dbc-bc64-4404-b6e9-b466c0e7f0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352036162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.1352036162
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.2004778105
Short name T145
Test name
Test status
Simulation time 1004483727 ps
CPU time 15.34 seconds
Started Jun 02 03:10:41 PM PDT 24
Finished Jun 02 03:10:58 PM PDT 24
Peak memory 242572 kb
Host smart-b82880ef-36f5-47fe-9ab2-c8229cfd3367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004778105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.2004778105
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.2070720853
Short name T866
Test name
Test status
Simulation time 309418223655 ps
CPU time 1722.82 seconds
Started Jun 02 03:10:38 PM PDT 24
Finished Jun 02 03:39:22 PM PDT 24
Peak memory 350200 kb
Host smart-ceda2170-605b-4f46-95e1-17cf6fd82573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070720853 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.2070720853
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.91228957
Short name T964
Test name
Test status
Simulation time 187157529 ps
CPU time 3.97 seconds
Started Jun 02 03:10:39 PM PDT 24
Finished Jun 02 03:10:44 PM PDT 24
Peak memory 242408 kb
Host smart-39257deb-9930-49a5-ad1b-b825a2f206f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91228957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.91228957
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.3720996844
Short name T697
Test name
Test status
Simulation time 612292908 ps
CPU time 8.82 seconds
Started Jun 02 03:10:37 PM PDT 24
Finished Jun 02 03:10:47 PM PDT 24
Peak memory 242608 kb
Host smart-d25eabe3-ee8b-4ff9-adf5-06b8092ad9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720996844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.3720996844
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.1758189972
Short name T17
Test name
Test status
Simulation time 86361010960 ps
CPU time 236.08 seconds
Started Jun 02 03:10:38 PM PDT 24
Finished Jun 02 03:14:34 PM PDT 24
Peak memory 257328 kb
Host smart-5fc419ca-db8f-42f3-8674-83e1285b018f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758189972 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.1758189972
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.3500092925
Short name T193
Test name
Test status
Simulation time 380561351 ps
CPU time 3.77 seconds
Started Jun 02 03:10:39 PM PDT 24
Finished Jun 02 03:10:43 PM PDT 24
Peak memory 242712 kb
Host smart-bac536da-c409-4a2a-a46f-777d45658d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500092925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.3500092925
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.3384370101
Short name T999
Test name
Test status
Simulation time 970547059 ps
CPU time 8.46 seconds
Started Jun 02 03:10:41 PM PDT 24
Finished Jun 02 03:10:50 PM PDT 24
Peak memory 242176 kb
Host smart-f1a2b269-d5e4-4e48-9e06-7a0177ba56f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384370101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.3384370101
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.333590385
Short name T578
Test name
Test status
Simulation time 69755369 ps
CPU time 2.01 seconds
Started Jun 02 03:07:56 PM PDT 24
Finished Jun 02 03:07:59 PM PDT 24
Peak memory 240744 kb
Host smart-8a3bc30d-92dc-4b83-be21-debf9db37ab8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333590385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.333590385
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.3473063046
Short name T390
Test name
Test status
Simulation time 1808107189 ps
CPU time 14.94 seconds
Started Jun 02 03:07:53 PM PDT 24
Finished Jun 02 03:08:09 PM PDT 24
Peak memory 242496 kb
Host smart-865a9e34-4a62-4e77-9efe-d0b44193beb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473063046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.3473063046
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.688252272
Short name T662
Test name
Test status
Simulation time 328192598 ps
CPU time 11.33 seconds
Started Jun 02 03:07:58 PM PDT 24
Finished Jun 02 03:08:11 PM PDT 24
Peak memory 242668 kb
Host smart-ab53a1b1-1ef9-4963-834b-5ba12d53d3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688252272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.688252272
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.2453641428
Short name T414
Test name
Test status
Simulation time 1830706588 ps
CPU time 25.1 seconds
Started Jun 02 03:07:58 PM PDT 24
Finished Jun 02 03:08:24 PM PDT 24
Peak memory 242284 kb
Host smart-c9d67b59-4381-4cd5-8946-bb157396d62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453641428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.2453641428
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.2625888147
Short name T1188
Test name
Test status
Simulation time 479555953 ps
CPU time 11.64 seconds
Started Jun 02 03:08:01 PM PDT 24
Finished Jun 02 03:08:13 PM PDT 24
Peak memory 242264 kb
Host smart-ad6b7111-1b2b-463d-90c6-d823c9b74a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625888147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.2625888147
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.1630152447
Short name T654
Test name
Test status
Simulation time 109467446 ps
CPU time 4.17 seconds
Started Jun 02 03:07:51 PM PDT 24
Finished Jun 02 03:07:56 PM PDT 24
Peak memory 242316 kb
Host smart-9c13d97d-1051-4fe3-8e76-f3c484503954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630152447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.1630152447
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.3808844328
Short name T659
Test name
Test status
Simulation time 5513549876 ps
CPU time 46.01 seconds
Started Jun 02 03:07:56 PM PDT 24
Finished Jun 02 03:08:42 PM PDT 24
Peak memory 263256 kb
Host smart-e33bc62a-b18a-4d7b-9e97-4297f7c1d956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808844328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.3808844328
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.3506086739
Short name T208
Test name
Test status
Simulation time 867115632 ps
CPU time 16.33 seconds
Started Jun 02 03:07:57 PM PDT 24
Finished Jun 02 03:08:14 PM PDT 24
Peak memory 242176 kb
Host smart-5c1e3269-5eed-43c3-968b-abdc88d88cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506086739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.3506086739
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.1561121577
Short name T184
Test name
Test status
Simulation time 2122885199 ps
CPU time 8.75 seconds
Started Jun 02 03:07:57 PM PDT 24
Finished Jun 02 03:08:06 PM PDT 24
Peak memory 242512 kb
Host smart-b705169f-a3a2-400e-85b2-a6b7d812525c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561121577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.1561121577
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.2701047133
Short name T389
Test name
Test status
Simulation time 1389166032 ps
CPU time 11.34 seconds
Started Jun 02 03:07:58 PM PDT 24
Finished Jun 02 03:08:10 PM PDT 24
Peak memory 242528 kb
Host smart-2a4e32d4-507a-4fb9-a7a2-e39ac4cc122b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2701047133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.2701047133
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.3226813361
Short name T595
Test name
Test status
Simulation time 3847298531 ps
CPU time 12.57 seconds
Started Jun 02 03:07:57 PM PDT 24
Finished Jun 02 03:08:11 PM PDT 24
Peak memory 242636 kb
Host smart-dc577c69-334f-4cee-81ae-d297ace8f595
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3226813361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.3226813361
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.2845866414
Short name T582
Test name
Test status
Simulation time 8133745960 ps
CPU time 20.73 seconds
Started Jun 02 03:07:53 PM PDT 24
Finished Jun 02 03:08:15 PM PDT 24
Peak memory 248924 kb
Host smart-aaced06b-b785-40ef-b3b8-73a52aa326a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845866414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.2845866414
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.167626649
Short name T940
Test name
Test status
Simulation time 4828061309 ps
CPU time 126.55 seconds
Started Jun 02 03:07:56 PM PDT 24
Finished Jun 02 03:10:04 PM PDT 24
Peak memory 285452 kb
Host smart-f736ad4e-fa5f-4563-86da-801b093c24df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167626649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.167626649
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.3904054461
Short name T302
Test name
Test status
Simulation time 460541951358 ps
CPU time 881.26 seconds
Started Jun 02 03:07:57 PM PDT 24
Finished Jun 02 03:22:39 PM PDT 24
Peak memory 290120 kb
Host smart-2a3da328-609f-46d6-ac6c-03b6411bfdbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904054461 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.3904054461
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.2193716824
Short name T174
Test name
Test status
Simulation time 2604009641 ps
CPU time 5.81 seconds
Started Jun 02 03:07:57 PM PDT 24
Finished Jun 02 03:08:04 PM PDT 24
Peak memory 242280 kb
Host smart-7520e681-206c-48f7-8b7d-ef5a04c421a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193716824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.2193716824
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.2592507953
Short name T179
Test name
Test status
Simulation time 269535020 ps
CPU time 4.38 seconds
Started Jun 02 03:10:38 PM PDT 24
Finished Jun 02 03:10:44 PM PDT 24
Peak memory 242728 kb
Host smart-7f06870b-0b8d-4143-a01c-0d2af783059c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592507953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.2592507953
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.676629436
Short name T259
Test name
Test status
Simulation time 193880023 ps
CPU time 5.39 seconds
Started Jun 02 03:10:42 PM PDT 24
Finished Jun 02 03:10:48 PM PDT 24
Peak memory 242324 kb
Host smart-06e5c72f-7248-4d4d-bb21-0ac1818db669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676629436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.676629436
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.1179215300
Short name T990
Test name
Test status
Simulation time 285881322059 ps
CPU time 3899.27 seconds
Started Jun 02 03:10:40 PM PDT 24
Finished Jun 02 04:15:41 PM PDT 24
Peak memory 619416 kb
Host smart-01c16427-ab2d-41b6-9c64-47d13a28590a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179215300 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.1179215300
Directory /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.3424834264
Short name T1087
Test name
Test status
Simulation time 232595831 ps
CPU time 3.53 seconds
Started Jun 02 03:10:40 PM PDT 24
Finished Jun 02 03:10:45 PM PDT 24
Peak memory 242332 kb
Host smart-fa49239a-6ead-42a5-93e9-20ca28a875a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424834264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.3424834264
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.2852969236
Short name T540
Test name
Test status
Simulation time 313009752 ps
CPU time 8.67 seconds
Started Jun 02 03:10:38 PM PDT 24
Finished Jun 02 03:10:48 PM PDT 24
Peak memory 242244 kb
Host smart-644367d8-04f7-485e-8468-93e62f5677b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852969236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.2852969236
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.2609626048
Short name T686
Test name
Test status
Simulation time 42523088379 ps
CPU time 317.4 seconds
Started Jun 02 03:10:41 PM PDT 24
Finished Jun 02 03:15:59 PM PDT 24
Peak memory 257268 kb
Host smart-7fbd1334-99da-4508-9654-13afa02cde72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609626048 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.2609626048
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.1776547256
Short name T631
Test name
Test status
Simulation time 11813712443 ps
CPU time 25.87 seconds
Started Jun 02 03:10:37 PM PDT 24
Finished Jun 02 03:11:04 PM PDT 24
Peak memory 242300 kb
Host smart-614d6a3b-b53d-43a8-94fc-65e9005f5ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776547256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.1776547256
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.837866509
Short name T645
Test name
Test status
Simulation time 377321573302 ps
CPU time 617.2 seconds
Started Jun 02 03:10:41 PM PDT 24
Finished Jun 02 03:20:59 PM PDT 24
Peak memory 260408 kb
Host smart-71e43461-ea65-4be2-a122-fb9f966bc943
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837866509 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.837866509
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.340012629
Short name T499
Test name
Test status
Simulation time 402939332 ps
CPU time 3.49 seconds
Started Jun 02 03:10:42 PM PDT 24
Finished Jun 02 03:10:46 PM PDT 24
Peak memory 242328 kb
Host smart-ee519ce9-dbb4-4402-bf6e-9b470ff1303f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340012629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.340012629
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.4113606782
Short name T1129
Test name
Test status
Simulation time 160510078 ps
CPU time 5.85 seconds
Started Jun 02 03:10:39 PM PDT 24
Finished Jun 02 03:10:46 PM PDT 24
Peak memory 242496 kb
Host smart-f205e726-2cd1-41e5-bac9-08be0aa03c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113606782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.4113606782
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.2651153327
Short name T837
Test name
Test status
Simulation time 35474794700 ps
CPU time 464.7 seconds
Started Jun 02 03:10:41 PM PDT 24
Finished Jun 02 03:18:27 PM PDT 24
Peak memory 304608 kb
Host smart-e72c6d6e-1237-4345-a969-1638d826652b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651153327 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.2651153327
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.2825787233
Short name T1113
Test name
Test status
Simulation time 272660429 ps
CPU time 4.64 seconds
Started Jun 02 03:10:40 PM PDT 24
Finished Jun 02 03:10:46 PM PDT 24
Peak memory 242464 kb
Host smart-e207f82f-194d-48a8-be68-3bb381e5fda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825787233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.2825787233
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.2095398737
Short name T792
Test name
Test status
Simulation time 325376290 ps
CPU time 4.89 seconds
Started Jun 02 03:10:40 PM PDT 24
Finished Jun 02 03:10:45 PM PDT 24
Peak memory 242256 kb
Host smart-8d13926d-7d75-4bb9-a6c3-27101b618784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095398737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.2095398737
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.3121839580
Short name T982
Test name
Test status
Simulation time 154948005819 ps
CPU time 2329.74 seconds
Started Jun 02 03:10:44 PM PDT 24
Finished Jun 02 03:49:35 PM PDT 24
Peak memory 309720 kb
Host smart-236e2360-34ca-4633-91ca-d1e069932017
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121839580 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.3121839580
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.480481317
Short name T708
Test name
Test status
Simulation time 517989546 ps
CPU time 4.2 seconds
Started Jun 02 03:10:43 PM PDT 24
Finished Jun 02 03:10:48 PM PDT 24
Peak memory 242288 kb
Host smart-d9e185f1-7762-4e64-a1e4-a73a7488a5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480481317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.480481317
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.1709329512
Short name T1121
Test name
Test status
Simulation time 175392472 ps
CPU time 3.12 seconds
Started Jun 02 03:10:50 PM PDT 24
Finished Jun 02 03:10:53 PM PDT 24
Peak memory 242140 kb
Host smart-b546a67d-8aeb-4641-9042-0e5f3ec24762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709329512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.1709329512
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.4236553301
Short name T344
Test name
Test status
Simulation time 442952782494 ps
CPU time 2015.3 seconds
Started Jun 02 03:10:45 PM PDT 24
Finished Jun 02 03:44:21 PM PDT 24
Peak memory 299304 kb
Host smart-4fefdaa8-9ca2-427a-bc43-9f5d029b2278
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236553301 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.4236553301
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.3806018253
Short name T185
Test name
Test status
Simulation time 274305813 ps
CPU time 3.82 seconds
Started Jun 02 03:10:45 PM PDT 24
Finished Jun 02 03:10:50 PM PDT 24
Peak memory 242672 kb
Host smart-9f194091-72db-41c5-b545-d787379eeb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806018253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.3806018253
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.2480326221
Short name T404
Test name
Test status
Simulation time 341763822 ps
CPU time 3.46 seconds
Started Jun 02 03:10:45 PM PDT 24
Finished Jun 02 03:10:49 PM PDT 24
Peak memory 242324 kb
Host smart-68f2e1c0-18bc-4a92-8ee6-616ecbf96788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480326221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.2480326221
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.1726672484
Short name T682
Test name
Test status
Simulation time 9130534795 ps
CPU time 253.8 seconds
Started Jun 02 03:10:49 PM PDT 24
Finished Jun 02 03:15:04 PM PDT 24
Peak memory 249384 kb
Host smart-12a9adb2-7f87-4f7b-a990-13351fc0cbc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726672484 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.1726672484
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.2774097767
Short name T793
Test name
Test status
Simulation time 1666406200 ps
CPU time 4.2 seconds
Started Jun 02 03:10:43 PM PDT 24
Finished Jun 02 03:10:48 PM PDT 24
Peak memory 242204 kb
Host smart-2ff0e69f-5e5e-4d30-9a92-6d84139b6f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774097767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.2774097767
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.1795732803
Short name T961
Test name
Test status
Simulation time 103631823 ps
CPU time 3.07 seconds
Started Jun 02 03:10:43 PM PDT 24
Finished Jun 02 03:10:47 PM PDT 24
Peak memory 242112 kb
Host smart-98a26651-6f39-4b1b-a197-7a4bbcc5df67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795732803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.1795732803
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.2535584667
Short name T894
Test name
Test status
Simulation time 36541694841 ps
CPU time 1040.03 seconds
Started Jun 02 03:10:49 PM PDT 24
Finished Jun 02 03:28:10 PM PDT 24
Peak memory 334476 kb
Host smart-f87ba9d9-61d3-43e4-9010-663e253978ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535584667 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.2535584667
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.1799184912
Short name T148
Test name
Test status
Simulation time 1655744263 ps
CPU time 5.3 seconds
Started Jun 02 03:10:47 PM PDT 24
Finished Jun 02 03:10:53 PM PDT 24
Peak memory 242428 kb
Host smart-87657370-7eb3-4773-8db4-3d21f5f0e386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799184912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.1799184912
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.3970741448
Short name T108
Test name
Test status
Simulation time 173819732 ps
CPU time 5.07 seconds
Started Jun 02 03:10:45 PM PDT 24
Finished Jun 02 03:10:50 PM PDT 24
Peak memory 242120 kb
Host smart-a466f15a-5f1c-4191-a2e8-7110a2689a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970741448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.3970741448
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.2718848406
Short name T328
Test name
Test status
Simulation time 73725158008 ps
CPU time 1283.85 seconds
Started Jun 02 03:10:47 PM PDT 24
Finished Jun 02 03:32:12 PM PDT 24
Peak memory 273740 kb
Host smart-f06d8d23-7606-44e8-9c91-aafe98ef05cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718848406 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.2718848406
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.29129870
Short name T127
Test name
Test status
Simulation time 167200755 ps
CPU time 4.22 seconds
Started Jun 02 03:10:50 PM PDT 24
Finished Jun 02 03:10:55 PM PDT 24
Peak memory 242352 kb
Host smart-03e83516-902e-42e3-a580-6bf448fb8c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29129870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.29129870
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.3036292971
Short name T351
Test name
Test status
Simulation time 2686629431 ps
CPU time 8.64 seconds
Started Jun 02 03:10:47 PM PDT 24
Finished Jun 02 03:10:56 PM PDT 24
Peak memory 242416 kb
Host smart-5478c858-cbf5-476b-a08f-094b2256b4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036292971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.3036292971
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.4072449789
Short name T825
Test name
Test status
Simulation time 72140205 ps
CPU time 1.81 seconds
Started Jun 02 03:07:56 PM PDT 24
Finished Jun 02 03:07:58 PM PDT 24
Peak memory 240824 kb
Host smart-f929944d-6173-4d1f-aad8-abe4afe60550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072449789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.4072449789
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.4273490417
Short name T474
Test name
Test status
Simulation time 2910854532 ps
CPU time 18.7 seconds
Started Jun 02 03:07:57 PM PDT 24
Finished Jun 02 03:08:16 PM PDT 24
Peak memory 242504 kb
Host smart-f9c346bf-fd4f-4e65-936c-2b7b2fc3252b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273490417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.4273490417
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.1637978929
Short name T632
Test name
Test status
Simulation time 2411743616 ps
CPU time 37.72 seconds
Started Jun 02 03:08:01 PM PDT 24
Finished Jun 02 03:08:40 PM PDT 24
Peak memory 249028 kb
Host smart-8509ea2b-9401-4f1a-b1b3-84418391e67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637978929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.1637978929
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.3860804688
Short name T416
Test name
Test status
Simulation time 502247276 ps
CPU time 12.92 seconds
Started Jun 02 03:07:57 PM PDT 24
Finished Jun 02 03:08:11 PM PDT 24
Peak memory 242244 kb
Host smart-8b018513-4a11-41f4-96bd-9f02cca9a5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860804688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.3860804688
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.3160770210
Short name T769
Test name
Test status
Simulation time 382037653 ps
CPU time 9.79 seconds
Started Jun 02 03:07:57 PM PDT 24
Finished Jun 02 03:08:08 PM PDT 24
Peak memory 242180 kb
Host smart-10666f1d-45c7-4fa1-b2a2-38b1270e446a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160770210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.3160770210
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.2074722845
Short name T963
Test name
Test status
Simulation time 211046320 ps
CPU time 3.92 seconds
Started Jun 02 03:07:58 PM PDT 24
Finished Jun 02 03:08:03 PM PDT 24
Peak memory 242696 kb
Host smart-497d9488-416c-4aba-8c9c-f5af4087b5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074722845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.2074722845
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.3064245959
Short name T777
Test name
Test status
Simulation time 1522935736 ps
CPU time 29 seconds
Started Jun 02 03:07:58 PM PDT 24
Finished Jun 02 03:08:28 PM PDT 24
Peak memory 243920 kb
Host smart-9eba2251-acf0-4aa2-8652-b5e5e72b00b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064245959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.3064245959
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.3861443345
Short name T348
Test name
Test status
Simulation time 260727957 ps
CPU time 5.08 seconds
Started Jun 02 03:07:57 PM PDT 24
Finished Jun 02 03:08:03 PM PDT 24
Peak memory 242384 kb
Host smart-21170ac7-cea6-4b19-94c5-8f5e04587633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861443345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.3861443345
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.1121453958
Short name T1143
Test name
Test status
Simulation time 17990202449 ps
CPU time 52.83 seconds
Started Jun 02 03:08:02 PM PDT 24
Finished Jun 02 03:08:56 PM PDT 24
Peak memory 243028 kb
Host smart-34eb0a23-79e7-4e4e-92a0-e7f556fee90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121453958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.1121453958
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.3759670568
Short name T802
Test name
Test status
Simulation time 2823561346 ps
CPU time 25.08 seconds
Started Jun 02 03:07:57 PM PDT 24
Finished Jun 02 03:08:23 PM PDT 24
Peak memory 248820 kb
Host smart-f88559e5-8d6e-4087-b800-e863a13207eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3759670568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.3759670568
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.2861962177
Short name T368
Test name
Test status
Simulation time 303792986 ps
CPU time 9.46 seconds
Started Jun 02 03:07:59 PM PDT 24
Finished Jun 02 03:08:09 PM PDT 24
Peak memory 242336 kb
Host smart-38f9aaed-0162-4a46-8a2a-0cf3360ce388
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2861962177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.2861962177
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.221900921
Short name T1168
Test name
Test status
Simulation time 402372664 ps
CPU time 7.59 seconds
Started Jun 02 03:07:58 PM PDT 24
Finished Jun 02 03:08:07 PM PDT 24
Peak memory 248800 kb
Host smart-1c7b0ce6-d978-41de-896b-2bf4ea435bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221900921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.221900921
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.4239678316
Short name T647
Test name
Test status
Simulation time 9998561244 ps
CPU time 101.35 seconds
Started Jun 02 03:07:55 PM PDT 24
Finished Jun 02 03:09:37 PM PDT 24
Peak memory 245212 kb
Host smart-1128c13a-a58f-4ae2-b976-083446b36ac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239678316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.
4239678316
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.3265792432
Short name T220
Test name
Test status
Simulation time 188984785445 ps
CPU time 1517.99 seconds
Started Jun 02 03:07:59 PM PDT 24
Finished Jun 02 03:33:18 PM PDT 24
Peak memory 322756 kb
Host smart-80493ec5-bc83-415b-99c1-8ac4f465cbfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265792432 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.3265792432
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.1835416380
Short name T937
Test name
Test status
Simulation time 1019780034 ps
CPU time 17.64 seconds
Started Jun 02 03:08:00 PM PDT 24
Finished Jun 02 03:08:18 PM PDT 24
Peak memory 242184 kb
Host smart-702da667-4c55-4cd8-a10d-0abe7baf856a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835416380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.1835416380
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.63187914
Short name T156
Test name
Test status
Simulation time 1931661881 ps
CPU time 4.4 seconds
Started Jun 02 03:10:49 PM PDT 24
Finished Jun 02 03:10:55 PM PDT 24
Peak memory 242432 kb
Host smart-559a1296-7ff9-4e2d-99ed-6898e50d2db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63187914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.63187914
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.1380719205
Short name T451
Test name
Test status
Simulation time 651203258 ps
CPU time 8.56 seconds
Started Jun 02 03:10:47 PM PDT 24
Finished Jun 02 03:10:56 PM PDT 24
Peak memory 242528 kb
Host smart-afe2316e-4f09-4a97-874d-1eace6283657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380719205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.1380719205
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.1937520290
Short name T714
Test name
Test status
Simulation time 2104126599650 ps
CPU time 4707.21 seconds
Started Jun 02 03:10:46 PM PDT 24
Finished Jun 02 04:29:14 PM PDT 24
Peak memory 601132 kb
Host smart-3617ad85-eae2-4121-a45e-3db36279d62b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937520290 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.1937520290
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.3783332144
Short name T1097
Test name
Test status
Simulation time 2144567115 ps
CPU time 6.47 seconds
Started Jun 02 03:10:45 PM PDT 24
Finished Jun 02 03:10:52 PM PDT 24
Peak memory 242352 kb
Host smart-2a262a8d-92c4-4458-8c4d-e342089cf2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783332144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.3783332144
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.212660631
Short name T871
Test name
Test status
Simulation time 8212121758 ps
CPU time 20.65 seconds
Started Jun 02 03:10:44 PM PDT 24
Finished Jun 02 03:11:05 PM PDT 24
Peak memory 242668 kb
Host smart-ab2527b0-007c-4f9e-96b0-d5838d888117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212660631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.212660631
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.3802918440
Short name T455
Test name
Test status
Simulation time 54829424927 ps
CPU time 536.81 seconds
Started Jun 02 03:10:43 PM PDT 24
Finished Jun 02 03:19:41 PM PDT 24
Peak memory 257408 kb
Host smart-6d042a70-4747-4cbb-ad4f-07774bff803c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802918440 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.3802918440
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.2987093239
Short name T422
Test name
Test status
Simulation time 2014991140 ps
CPU time 4.84 seconds
Started Jun 02 03:10:46 PM PDT 24
Finished Jun 02 03:10:51 PM PDT 24
Peak memory 242364 kb
Host smart-1a8a43ad-2f9f-454e-9cc1-d6630da1e591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987093239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.2987093239
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.2121956645
Short name T476
Test name
Test status
Simulation time 12645126511 ps
CPU time 35.92 seconds
Started Jun 02 03:10:47 PM PDT 24
Finished Jun 02 03:11:23 PM PDT 24
Peak memory 242416 kb
Host smart-171b6646-aa78-44cc-8ce5-bb90b5337d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121956645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.2121956645
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.1389396494
Short name T233
Test name
Test status
Simulation time 122790495 ps
CPU time 3.47 seconds
Started Jun 02 03:10:53 PM PDT 24
Finished Jun 02 03:10:57 PM PDT 24
Peak memory 242380 kb
Host smart-c468628f-3106-4d43-a965-8b97dac2b608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389396494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.1389396494
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.2400979601
Short name T851
Test name
Test status
Simulation time 222243575 ps
CPU time 4.19 seconds
Started Jun 02 03:10:49 PM PDT 24
Finished Jun 02 03:10:54 PM PDT 24
Peak memory 242192 kb
Host smart-547917ac-84d2-4d5e-83ca-0dafcc0c95e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400979601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.2400979601
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.404151161
Short name T1051
Test name
Test status
Simulation time 1401544941309 ps
CPU time 2378.7 seconds
Started Jun 02 03:10:49 PM PDT 24
Finished Jun 02 03:50:30 PM PDT 24
Peak memory 526464 kb
Host smart-b0de180e-0de0-48dd-bde2-1b59c81bc10c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404151161 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.404151161
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.2000543250
Short name T884
Test name
Test status
Simulation time 627617189 ps
CPU time 4.2 seconds
Started Jun 02 03:10:50 PM PDT 24
Finished Jun 02 03:10:55 PM PDT 24
Peak memory 242432 kb
Host smart-b072a7fe-2918-411a-a591-a066c9cb72b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000543250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.2000543250
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.950440188
Short name T138
Test name
Test status
Simulation time 1169709508 ps
CPU time 16.73 seconds
Started Jun 02 03:10:49 PM PDT 24
Finished Jun 02 03:11:06 PM PDT 24
Peak memory 242580 kb
Host smart-69ab3c48-6e07-447e-9417-f9cfbd4c2e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950440188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.950440188
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.3011824129
Short name T1011
Test name
Test status
Simulation time 381303715 ps
CPU time 4.83 seconds
Started Jun 02 03:10:58 PM PDT 24
Finished Jun 02 03:11:03 PM PDT 24
Peak memory 242688 kb
Host smart-d9ed5754-419b-4a26-b6dd-86402b2e19a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011824129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.3011824129
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.2712963515
Short name T464
Test name
Test status
Simulation time 180963625 ps
CPU time 5.1 seconds
Started Jun 02 03:10:50 PM PDT 24
Finished Jun 02 03:10:55 PM PDT 24
Peak memory 242568 kb
Host smart-c1edf6c9-c22f-4dfe-87bd-2e3dad4a5d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712963515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.2712963515
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.4141364093
Short name T500
Test name
Test status
Simulation time 163386564 ps
CPU time 8.28 seconds
Started Jun 02 03:10:52 PM PDT 24
Finished Jun 02 03:11:00 PM PDT 24
Peak memory 242492 kb
Host smart-f6a08a02-3c30-4c8b-a072-bdf1fe2ebbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141364093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.4141364093
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.4156236034
Short name T717
Test name
Test status
Simulation time 138031528 ps
CPU time 4.69 seconds
Started Jun 02 03:10:49 PM PDT 24
Finished Jun 02 03:10:54 PM PDT 24
Peak memory 242332 kb
Host smart-80e227b1-2190-44d8-8453-465884a622ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156236034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.4156236034
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.1419639665
Short name T626
Test name
Test status
Simulation time 1557947406 ps
CPU time 12.13 seconds
Started Jun 02 03:10:57 PM PDT 24
Finished Jun 02 03:11:10 PM PDT 24
Peak memory 242528 kb
Host smart-dba21fc8-323d-4833-974b-288ae10e40ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419639665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.1419639665
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.3059668168
Short name T1014
Test name
Test status
Simulation time 319466814340 ps
CPU time 645.38 seconds
Started Jun 02 03:10:48 PM PDT 24
Finished Jun 02 03:21:34 PM PDT 24
Peak memory 264544 kb
Host smart-8b97a2c7-559b-4c79-9b0f-9b40fffe182e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059668168 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.3059668168
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.47495134
Short name T616
Test name
Test status
Simulation time 265659176 ps
CPU time 4.21 seconds
Started Jun 02 03:10:52 PM PDT 24
Finished Jun 02 03:10:56 PM PDT 24
Peak memory 242328 kb
Host smart-1d9f817d-13b6-4da6-93d6-7d9c731acd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47495134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.47495134
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.4142403411
Short name T933
Test name
Test status
Simulation time 361360135 ps
CPU time 8.96 seconds
Started Jun 02 03:10:49 PM PDT 24
Finished Jun 02 03:10:58 PM PDT 24
Peak memory 242556 kb
Host smart-50f0a149-7c0e-4a78-8989-52b3e22ed8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142403411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.4142403411
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.2643651048
Short name T472
Test name
Test status
Simulation time 121737461984 ps
CPU time 793.31 seconds
Started Jun 02 03:10:49 PM PDT 24
Finished Jun 02 03:24:04 PM PDT 24
Peak memory 301164 kb
Host smart-b482308b-5bf2-4562-91e4-3dcc2e8acf4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643651048 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.2643651048
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.546592270
Short name T1118
Test name
Test status
Simulation time 169883015 ps
CPU time 3.65 seconds
Started Jun 02 03:10:51 PM PDT 24
Finished Jun 02 03:10:55 PM PDT 24
Peak memory 242220 kb
Host smart-f28a212a-c069-4d20-aab9-17a8b067e6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546592270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.546592270
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.76576858
Short name T443
Test name
Test status
Simulation time 814253126 ps
CPU time 21.62 seconds
Started Jun 02 03:10:56 PM PDT 24
Finished Jun 02 03:11:18 PM PDT 24
Peak memory 248896 kb
Host smart-404b2b43-8af1-447c-935c-c24db622cf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76576858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.76576858
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.1006516374
Short name T342
Test name
Test status
Simulation time 662393645054 ps
CPU time 1048.11 seconds
Started Jun 02 03:10:54 PM PDT 24
Finished Jun 02 03:28:23 PM PDT 24
Peak memory 311712 kb
Host smart-4d3e109f-c7a0-43d0-8c7a-fe3d9e4f6d81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006516374 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.1006516374
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
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