Group : tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
flash_data_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
flash_data_req_during_lc_esc 2 0 2 100.00 100 1 1 0
flash_data_req_during_otbn_req 2 0 2 100.00 100 1 1 2
flash_data_req_during_otp_idle 2 0 2 100.00 100 1 1 2
flash_data_req_during_sram_0_req 2 0 2 100.00 100 1 1 2
flash_data_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable flash_data_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13914 1 T3 21 T4 48 T5 4
auto[1] 1080 1 T3 3 T11 6 T6 1



Summary for Variable flash_data_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for flash_data_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 14962 1 T3 24 T4 48 T5 4
lc_esc_on 32 1 T345 1 T121 1 T346 1



Summary for Variable flash_data_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13902 1 T3 21 T4 48 T5 4
auto[1] 1092 1 T3 3 T11 4 T6 3



Summary for Variable flash_data_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2055 1 T3 6 T4 5 T11 5
auto[1] 12939 1 T3 18 T4 43 T5 4



Summary for Variable flash_data_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12462 1 T3 21 T4 48 T5 4
auto[1] 2532 1 T3 3 T11 4 T6 6



Summary for Variable flash_data_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14490 1 T3 23 T4 48 T5 4
auto[1] 504 1 T3 1 T11 3 T6 4

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