Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	55291	1			T4	451		T63	32		T180	15
access_err	76566	1			T3	22		T4	435		T10	288
write_blank_err	528	1			T6	1		T144	5		T7	2
ecc_uncorr_err	76085	1			T6	462		T144	558		T7	1059
ecc_corr_err	1655	1			T69	32		T58	22		T13	1
no_err	108526	1			T3	42		T4	765		T5	12

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	806	1			T7	17		T13	11		T14	5
secret2	25250	1			T3	7		T4	125		T5	2
secret1	33401	1			T3	1		T4	89		T10	35
secret0	44604	1			T3	12		T4	109		T10	57
hw_cfg1	41775	1			T3	10		T4	121		T10	50
hw_cfg0	28419	1			T3	4		T4	112		T5	4
rot_creator_auth_state	28241	1			T3	5		T4	386		T5	2
rot_creator_auth_codesign	25891	1			T3	10		T4	333		T5	2
owner_sw_cfg	27550	1			T3	7		T4	116		T10	77
creator_sw_cfg	24311	1			T3	3		T4	123		T10	62
vendor_test	38403	1			T3	5		T4	137		T5	2

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3333	1			T16	67		T237	196		T344	89
fsm_err	secret1	5714	1			T345	47		T64	47		T346	290
fsm_err	secret0	4690	1			T347	555		T235	39		T266	65
fsm_err	hw_cfg1	3591	1			T180	15		T219	135		T228	45
fsm_err	hw_cfg0	3765	1			T16	253		T121	221		T260	89
fsm_err	rot_creator_auth_state	3632	1			T4	264		T136	34		T143	20
fsm_err	rot_creator_auth_codesign	3890	1			T4	187		T223	345		T122	341
fsm_err	owner_sw_cfg	5571	1			T122	292		T169	60		T189	10
fsm_err	creator_sw_cfg	3864	1			T259	44		T268	107		T171	28
fsm_err	vendor_test	17241	1			T63	32		T348	191		T69	59
access_err	life_cycle	806	1			T7	17		T13	11		T14	5
access_err	secret2	13369	1			T3	6		T4	106		T10	58
access_err	secret1	7300	1			T3	1		T10	34		T11	25
access_err	secret0	5583	1			T3	10		T4	4		T10	33
access_err	hw_cfg1	1383	1			T3	2		T4	5		T10	1
access_err	hw_cfg0	2434	1			T3	2		T11	7		T15	7
access_err	rot_creator_auth_state	7429	1			T4	73		T10	15		T11	7
access_err	rot_creator_auth_codesign	10032	1			T3	1		T4	62		T10	47
access_err	owner_sw_cfg	8908	1			T4	75		T10	47		T11	10
access_err	creator_sw_cfg	9833	1			T4	46		T10	34		T11	25
access_err	vendor_test	9489	1			T4	64		T10	19		T11	12
write_blank_err	secret2	7	1			T349	1		T350	1		T351	1
write_blank_err	secret1	24	1			T243	1		T216	1		T352	1
write_blank_err	secret0	57	1			T6	1		T14	1		T243	1
write_blank_err	hw_cfg1	83	1			T144	1		T7	2		T13	2
write_blank_err	hw_cfg0	18	1			T122	1		T333	1		T217	1
write_blank_err	rot_creator_auth_state	166	1			T187	3		T243	2		T244	3
write_blank_err	rot_creator_auth_codesign	80	1			T14	4		T187	2		T243	3
write_blank_err	owner_sw_cfg	30	1			T122	1		T217	3		T260	2
write_blank_err	creator_sw_cfg	23	1			T217	1		T265	2		T67	1
write_blank_err	vendor_test	40	1			T144	4		T13	1		T14	1
ecc_uncorr_err	secret2	2485	1			T353	68		T169	113		T171	25
ecc_uncorr_err	secret1	9306	1			T243	492		T216	437		T352	438
ecc_uncorr_err	secret0	23739	1			T6	462		T14	310		T243	432
ecc_uncorr_err	hw_cfg1	23306	1			T144	558		T7	1059		T13	188
ecc_uncorr_err	hw_cfg0	7052	1			T141	8		T333	688		T217	415
ecc_uncorr_err	rot_creator_auth_state	6803	1			T245	9		T354	273		T263	502
ecc_uncorr_err	rot_creator_auth_codesign	1041	1			T141	12		T355	5		T143	37
ecc_uncorr_err	owner_sw_cfg	1888	1			T141	22		T142	11		T143	25
ecc_uncorr_err	creator_sw_cfg	465	1			T169	60		T174	74		T356	61
ecc_corr_err	secret2	103	1			T69	1		T48	5		T357	1
ecc_corr_err	secret1	163	1			T69	3		T48	3		T141	2
ecc_corr_err	secret0	172	1			T69	1		T58	3		T48	5
ecc_corr_err	hw_cfg1	337	1			T69	3		T58	3		T13	1
ecc_corr_err	hw_cfg0	262	1			T69	4		T58	3		T48	6
ecc_corr_err	rot_creator_auth_state	152	1			T48	2		T138	3		T136	1
ecc_corr_err	rot_creator_auth_codesign	171	1			T69	1		T58	2		T48	11
ecc_corr_err	owner_sw_cfg	151	1			T69	8		T58	4		T48	5
ecc_corr_err	creator_sw_cfg	144	1			T69	11		T58	7		T48	3
no_err	secret2	5953	1			T3	1		T4	19		T5	2
no_err	secret1	10894	1			T4	89		T10	1		T11	6
no_err	secret0	10363	1			T3	2		T4	105		T10	24
no_err	hw_cfg1	13075	1			T3	8		T4	116		T10	49
no_err	hw_cfg0	14888	1			T3	2		T4	112		T5	4
no_err	rot_creator_auth_state	10059	1			T3	5		T4	49		T5	2
no_err	rot_creator_auth_codesign	10677	1			T3	9		T4	84		T5	2
no_err	owner_sw_cfg	11002	1			T3	7		T4	41		T10	30
no_err	creator_sw_cfg	9982	1			T3	3		T4	77		T10	28
no_err	vendor_test	11633	1			T3	5		T4	73		T5	2

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded