Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.81 93.84 96.17 95.48 91.65 97.00 96.26 93.28


Total test records in report: 1333
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T1263 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2883600339 Jun 04 01:19:01 PM PDT 24 Jun 04 01:19:03 PM PDT 24 71256860 ps
T1264 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.1682007031 Jun 04 01:18:59 PM PDT 24 Jun 04 01:19:01 PM PDT 24 148607364 ps
T1265 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.908542303 Jun 04 01:19:24 PM PDT 24 Jun 04 01:19:26 PM PDT 24 91989282 ps
T1266 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3234823470 Jun 04 01:18:38 PM PDT 24 Jun 04 01:18:41 PM PDT 24 46100698 ps
T1267 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.397877081 Jun 04 01:19:19 PM PDT 24 Jun 04 01:19:30 PM PDT 24 2597598937 ps
T286 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.535096172 Jun 04 01:19:09 PM PDT 24 Jun 04 01:19:31 PM PDT 24 1800287708 ps
T1268 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.269947871 Jun 04 01:18:53 PM PDT 24 Jun 04 01:18:58 PM PDT 24 203803802 ps
T1269 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2897210387 Jun 04 01:19:01 PM PDT 24 Jun 04 01:19:06 PM PDT 24 61938160 ps
T1270 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3153977968 Jun 04 01:19:18 PM PDT 24 Jun 04 01:19:22 PM PDT 24 97927645 ps
T1271 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.3831196721 Jun 04 01:18:52 PM PDT 24 Jun 04 01:18:54 PM PDT 24 38448222 ps
T1272 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.1547294564 Jun 04 01:19:22 PM PDT 24 Jun 04 01:19:24 PM PDT 24 134133074 ps
T324 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1280081350 Jun 04 01:19:06 PM PDT 24 Jun 04 01:19:09 PM PDT 24 44906675 ps
T1273 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.463939110 Jun 04 01:19:24 PM PDT 24 Jun 04 01:19:26 PM PDT 24 562891621 ps
T1274 /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.3429547434 Jun 04 01:19:24 PM PDT 24 Jun 04 01:19:27 PM PDT 24 152847682 ps
T1275 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.1466913834 Jun 04 01:18:45 PM PDT 24 Jun 04 01:18:48 PM PDT 24 132934570 ps
T1276 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1983902219 Jun 04 01:19:24 PM PDT 24 Jun 04 01:19:27 PM PDT 24 145160282 ps
T319 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1428360155 Jun 04 01:19:17 PM PDT 24 Jun 04 01:19:20 PM PDT 24 73158687 ps
T1277 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.4274936006 Jun 04 01:18:56 PM PDT 24 Jun 04 01:19:01 PM PDT 24 257069675 ps
T1278 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1589693966 Jun 04 01:18:46 PM PDT 24 Jun 04 01:18:49 PM PDT 24 159946576 ps
T1279 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1435067721 Jun 04 01:19:09 PM PDT 24 Jun 04 01:19:12 PM PDT 24 46937517 ps
T1280 /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.4026276526 Jun 04 01:19:16 PM PDT 24 Jun 04 01:19:20 PM PDT 24 1155857139 ps
T1281 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3519335912 Jun 04 01:19:07 PM PDT 24 Jun 04 01:19:10 PM PDT 24 137718690 ps
T1282 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2397260941 Jun 04 01:18:47 PM PDT 24 Jun 04 01:18:49 PM PDT 24 151035178 ps
T1283 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.317158226 Jun 04 01:18:45 PM PDT 24 Jun 04 01:18:48 PM PDT 24 81261556 ps
T1284 /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.1319525476 Jun 04 01:19:17 PM PDT 24 Jun 04 01:19:20 PM PDT 24 42213754 ps
T1285 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.3164605602 Jun 04 01:18:37 PM PDT 24 Jun 04 01:18:41 PM PDT 24 163354844 ps
T1286 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.868660981 Jun 04 01:19:02 PM PDT 24 Jun 04 01:19:05 PM PDT 24 140032755 ps
T1287 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2776094381 Jun 04 01:18:53 PM PDT 24 Jun 04 01:19:04 PM PDT 24 2557487862 ps
T358 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.4278028576 Jun 04 01:18:44 PM PDT 24 Jun 04 01:19:07 PM PDT 24 3271384113 ps
T1288 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.2871067736 Jun 04 01:18:54 PM PDT 24 Jun 04 01:18:57 PM PDT 24 87228087 ps
T362 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.693946279 Jun 04 01:18:45 PM PDT 24 Jun 04 01:19:08 PM PDT 24 10273607608 ps
T1289 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.4256083702 Jun 04 01:19:18 PM PDT 24 Jun 04 01:19:22 PM PDT 24 216231289 ps
T1290 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3541532306 Jun 04 01:18:46 PM PDT 24 Jun 04 01:18:51 PM PDT 24 345692573 ps
T1291 /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.2425618083 Jun 04 01:19:25 PM PDT 24 Jun 04 01:19:27 PM PDT 24 526647258 ps
T281 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.594293552 Jun 04 01:18:53 PM PDT 24 Jun 04 01:19:04 PM PDT 24 10271473656 ps
T1292 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.1851433569 Jun 04 01:19:10 PM PDT 24 Jun 04 01:19:13 PM PDT 24 593178850 ps
T1293 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.531744745 Jun 04 01:18:47 PM PDT 24 Jun 04 01:18:52 PM PDT 24 212313478 ps
T1294 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2673511386 Jun 04 01:18:38 PM PDT 24 Jun 04 01:18:40 PM PDT 24 72998666 ps
T320 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2051759966 Jun 04 01:19:07 PM PDT 24 Jun 04 01:19:10 PM PDT 24 73881869 ps
T1295 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.4236621930 Jun 04 01:19:01 PM PDT 24 Jun 04 01:19:05 PM PDT 24 374883814 ps
T1296 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2889268908 Jun 04 01:18:53 PM PDT 24 Jun 04 01:18:55 PM PDT 24 129235852 ps
T1297 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.2767578899 Jun 04 01:19:16 PM PDT 24 Jun 04 01:19:20 PM PDT 24 334733452 ps
T1298 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.561805 Jun 04 01:18:53 PM PDT 24 Jun 04 01:18:57 PM PDT 24 70288459 ps
T1299 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.3147011090 Jun 04 01:19:24 PM PDT 24 Jun 04 01:19:26 PM PDT 24 77618065 ps
T1300 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.3425769892 Jun 04 01:19:08 PM PDT 24 Jun 04 01:19:11 PM PDT 24 123304169 ps
T1301 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.3325144484 Jun 04 01:19:18 PM PDT 24 Jun 04 01:19:21 PM PDT 24 81917636 ps
T1302 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1536295379 Jun 04 01:19:19 PM PDT 24 Jun 04 01:19:21 PM PDT 24 41665689 ps
T1303 /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2025871571 Jun 04 01:19:03 PM PDT 24 Jun 04 01:19:06 PM PDT 24 75503661 ps
T321 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2382348257 Jun 04 01:19:08 PM PDT 24 Jun 04 01:19:11 PM PDT 24 38739549 ps
T1304 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.192153056 Jun 04 01:18:54 PM PDT 24 Jun 04 01:18:57 PM PDT 24 76776210 ps
T1305 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.2894144242 Jun 04 01:18:36 PM PDT 24 Jun 04 01:18:47 PM PDT 24 2659153129 ps
T1306 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.72238345 Jun 04 01:18:37 PM PDT 24 Jun 04 01:18:39 PM PDT 24 66623212 ps
T1307 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.3396331004 Jun 04 01:19:24 PM PDT 24 Jun 04 01:19:26 PM PDT 24 41694293 ps
T1308 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.3833144819 Jun 04 01:19:24 PM PDT 24 Jun 04 01:19:26 PM PDT 24 55396819 ps
T322 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.616427933 Jun 04 01:18:45 PM PDT 24 Jun 04 01:18:49 PM PDT 24 47083252 ps
T1309 /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.1811926414 Jun 04 01:19:18 PM PDT 24 Jun 04 01:19:20 PM PDT 24 65178922 ps
T1310 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3446486352 Jun 04 01:18:52 PM PDT 24 Jun 04 01:18:55 PM PDT 24 41131455 ps
T1311 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.1554293542 Jun 04 01:19:16 PM PDT 24 Jun 04 01:19:20 PM PDT 24 421299146 ps
T1312 /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1898647491 Jun 04 01:19:01 PM PDT 24 Jun 04 01:19:06 PM PDT 24 1443054071 ps
T1313 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2507333968 Jun 04 01:18:47 PM PDT 24 Jun 04 01:18:57 PM PDT 24 2513751771 ps
T1314 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1268573680 Jun 04 01:19:04 PM PDT 24 Jun 04 01:19:09 PM PDT 24 1626532885 ps
T1315 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1386846534 Jun 04 01:19:08 PM PDT 24 Jun 04 01:19:14 PM PDT 24 143553814 ps
T1316 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.3677034593 Jun 04 01:19:09 PM PDT 24 Jun 04 01:19:37 PM PDT 24 10326604534 ps
T1317 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1842407692 Jun 04 01:18:36 PM PDT 24 Jun 04 01:18:39 PM PDT 24 1554759413 ps
T1318 /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.1847076885 Jun 04 01:19:03 PM PDT 24 Jun 04 01:19:07 PM PDT 24 89439039 ps
T1319 /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.1294482779 Jun 04 01:19:23 PM PDT 24 Jun 04 01:19:26 PM PDT 24 74578874 ps
T1320 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.673648836 Jun 04 01:18:54 PM PDT 24 Jun 04 01:19:07 PM PDT 24 1006032838 ps
T1321 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3068758924 Jun 04 01:18:59 PM PDT 24 Jun 04 01:19:04 PM PDT 24 890882926 ps
T282 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2654200249 Jun 04 01:18:38 PM PDT 24 Jun 04 01:18:51 PM PDT 24 1329145721 ps
T1322 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.3793453745 Jun 04 01:19:17 PM PDT 24 Jun 04 01:19:19 PM PDT 24 72135153 ps
T1323 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.329895556 Jun 04 01:19:07 PM PDT 24 Jun 04 01:19:10 PM PDT 24 254343386 ps
T1324 /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.4040366028 Jun 04 01:19:09 PM PDT 24 Jun 04 01:19:12 PM PDT 24 53391056 ps
T1325 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.2608941398 Jun 04 01:19:01 PM PDT 24 Jun 04 01:19:12 PM PDT 24 1216914025 ps
T1326 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.1430888010 Jun 04 01:19:17 PM PDT 24 Jun 04 01:19:19 PM PDT 24 41562346 ps
T1327 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.216591781 Jun 04 01:19:03 PM PDT 24 Jun 04 01:19:20 PM PDT 24 9719048889 ps
T1328 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.1392141488 Jun 04 01:19:02 PM PDT 24 Jun 04 01:19:07 PM PDT 24 97000006 ps
T1329 /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1351531511 Jun 04 01:19:02 PM PDT 24 Jun 04 01:19:05 PM PDT 24 173164079 ps
T363 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.472805946 Jun 04 01:18:54 PM PDT 24 Jun 04 01:19:06 PM PDT 24 647027534 ps
T1330 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.482271143 Jun 04 01:18:47 PM PDT 24 Jun 04 01:18:51 PM PDT 24 127848577 ps
T325 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.623438303 Jun 04 01:18:45 PM PDT 24 Jun 04 01:18:49 PM PDT 24 73491915 ps
T1331 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.3308897155 Jun 04 01:19:16 PM PDT 24 Jun 04 01:19:18 PM PDT 24 75710302 ps
T1332 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.235712796 Jun 04 01:19:09 PM PDT 24 Jun 04 01:19:13 PM PDT 24 888903450 ps
T1333 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2368871817 Jun 04 01:19:26 PM PDT 24 Jun 04 01:19:29 PM PDT 24 515179267 ps

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.4003652443
Short name T4
Test name
Test status
Simulation time 38600637532 ps
CPU time 983.36 seconds
Started Jun 04 02:59:48 PM PDT 24
Finished Jun 04 03:16:12 PM PDT 24
Peak memory 297036 kb
Host smart-66e5c502-37cc-4935-a63e-e0afe7005106
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003652443 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.4003652443
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.2318540427
Short name T122
Test name
Test status
Simulation time 17739101502 ps
CPU time 282.4 seconds
Started Jun 04 03:01:01 PM PDT 24
Finished Jun 04 03:05:46 PM PDT 24
Peak memory 265348 kb
Host smart-6916dc52-ba39-4a28-aa6c-0ea418546cb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318540427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all
.2318540427
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.3167156955
Short name T11
Test name
Test status
Simulation time 1209624944 ps
CPU time 23.13 seconds
Started Jun 04 03:02:18 PM PDT 24
Finished Jun 04 03:02:43 PM PDT 24
Peak memory 242244 kb
Host smart-a53ab726-5e3f-46ad-9c79-e9a88bb572e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167156955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.3167156955
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.1877416843
Short name T121
Test name
Test status
Simulation time 24093432014 ps
CPU time 211.04 seconds
Started Jun 04 03:00:14 PM PDT 24
Finished Jun 04 03:03:47 PM PDT 24
Peak memory 247408 kb
Host smart-fdff1ccd-3ee4-4e93-956f-8c685969322d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877416843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all
.1877416843
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.408437413
Short name T66
Test name
Test status
Simulation time 40763405061 ps
CPU time 463.22 seconds
Started Jun 04 03:01:09 PM PDT 24
Finished Jun 04 03:08:56 PM PDT 24
Peak memory 281840 kb
Host smart-bda1c36b-7aa9-4456-a9f5-d57a906fe821
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408437413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.
408437413
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.211392402
Short name T20
Test name
Test status
Simulation time 21573290970 ps
CPU time 222.02 seconds
Started Jun 04 02:59:30 PM PDT 24
Finished Jun 04 03:03:12 PM PDT 24
Peak memory 283264 kb
Host smart-15e4b2a0-d2da-45ef-865c-715f3d3dfeb2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211392402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.211392402
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.1669180406
Short name T2
Test name
Test status
Simulation time 1906482632 ps
CPU time 5.59 seconds
Started Jun 04 03:04:12 PM PDT 24
Finished Jun 04 03:04:18 PM PDT 24
Peak memory 242396 kb
Host smart-b7745191-9917-4c6a-b7b1-48ffb7f1f553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669180406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.1669180406
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.391492437
Short name T91
Test name
Test status
Simulation time 1872329488 ps
CPU time 30.98 seconds
Started Jun 04 03:01:46 PM PDT 24
Finished Jun 04 03:02:18 PM PDT 24
Peak memory 242312 kb
Host smart-637c5f0b-8a03-4e88-a0f7-7fed046c8c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391492437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.391492437
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.873755102
Short name T48
Test name
Test status
Simulation time 892941053 ps
CPU time 28.99 seconds
Started Jun 04 03:02:41 PM PDT 24
Finished Jun 04 03:03:11 PM PDT 24
Peak memory 248940 kb
Host smart-7725db35-d8dd-40bf-a3e6-209af2f17d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873755102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.873755102
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.805382404
Short name T14
Test name
Test status
Simulation time 144041230122 ps
CPU time 1614.21 seconds
Started Jun 04 03:02:13 PM PDT 24
Finished Jun 04 03:29:08 PM PDT 24
Peak memory 281976 kb
Host smart-d4ff5fb8-36ff-4644-8a7c-ba8a62dfeb80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805382404 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.805382404
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1982372979
Short name T275
Test name
Test status
Simulation time 871878805 ps
CPU time 12.05 seconds
Started Jun 04 01:19:00 PM PDT 24
Finished Jun 04 01:19:13 PM PDT 24
Peak memory 242616 kb
Host smart-913e85e4-afd0-4d10-8327-45b21f624d39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982372979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.1982372979
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.99517512
Short name T132
Test name
Test status
Simulation time 1696202626 ps
CPU time 6.42 seconds
Started Jun 04 03:04:47 PM PDT 24
Finished Jun 04 03:04:54 PM PDT 24
Peak memory 242328 kb
Host smart-1828bc82-7b4a-424a-9deb-9b4364b3c460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99517512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.99517512
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.65141372
Short name T185
Test name
Test status
Simulation time 33044810953 ps
CPU time 229.4 seconds
Started Jun 04 03:01:36 PM PDT 24
Finished Jun 04 03:05:26 PM PDT 24
Peak memory 262012 kb
Host smart-6abfbb19-d507-4c1f-a892-675792f0b27a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65141372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.65141372
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.405889265
Short name T9
Test name
Test status
Simulation time 1773291023 ps
CPU time 4.31 seconds
Started Jun 04 03:00:15 PM PDT 24
Finished Jun 04 03:00:21 PM PDT 24
Peak memory 242584 kb
Host smart-af240ce0-d0a7-4edd-b27f-0ef310273d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405889265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.405889265
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.1123756120
Short name T39
Test name
Test status
Simulation time 2208614197 ps
CPU time 4.84 seconds
Started Jun 04 02:59:48 PM PDT 24
Finished Jun 04 02:59:54 PM PDT 24
Peak memory 242452 kb
Host smart-26b1e045-b168-4ea5-bc1d-1acfd384382e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123756120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.1123756120
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.3869740883
Short name T171
Test name
Test status
Simulation time 1733362892 ps
CPU time 37.18 seconds
Started Jun 04 03:01:46 PM PDT 24
Finished Jun 04 03:02:24 PM PDT 24
Peak memory 251060 kb
Host smart-66a17b6f-8497-4049-9cb5-f2aad7bec610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869740883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.3869740883
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.461646970
Short name T67
Test name
Test status
Simulation time 3937785388 ps
CPU time 101.95 seconds
Started Jun 04 03:00:49 PM PDT 24
Finished Jun 04 03:02:32 PM PDT 24
Peak memory 248576 kb
Host smart-ed37fe6f-25ad-4e54-bd67-dd570a5c8f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461646970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.
461646970
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.2221049559
Short name T44
Test name
Test status
Simulation time 480148369 ps
CPU time 5.57 seconds
Started Jun 04 03:03:48 PM PDT 24
Finished Jun 04 03:03:55 PM PDT 24
Peak memory 242364 kb
Host smart-eb03edd9-a363-4dff-bcec-6d5fcb3b09d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221049559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.2221049559
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.355678928
Short name T23
Test name
Test status
Simulation time 256943804 ps
CPU time 3.62 seconds
Started Jun 04 03:01:51 PM PDT 24
Finished Jun 04 03:01:55 PM PDT 24
Peak memory 242596 kb
Host smart-e0eb15c2-04b9-472e-8157-22216dc7bffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355678928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.355678928
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.1661585999
Short name T226
Test name
Test status
Simulation time 420207153761 ps
CPU time 1794.06 seconds
Started Jun 04 03:02:53 PM PDT 24
Finished Jun 04 03:32:48 PM PDT 24
Peak memory 401460 kb
Host smart-a355c9c0-9b92-4f76-8efd-80cf12b1c85b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661585999 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.1661585999
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.4205104088
Short name T33
Test name
Test status
Simulation time 2696289751 ps
CPU time 18.06 seconds
Started Jun 04 03:00:50 PM PDT 24
Finished Jun 04 03:01:09 PM PDT 24
Peak memory 242444 kb
Host smart-0c2d0fa7-e1e5-42e4-ad4a-10d3968e8cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205104088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.4205104088
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.3426994148
Short name T78
Test name
Test status
Simulation time 19705093692 ps
CPU time 44.32 seconds
Started Jun 04 03:01:13 PM PDT 24
Finished Jun 04 03:02:00 PM PDT 24
Peak memory 242808 kb
Host smart-fde6cc38-57c2-4a18-9c71-9605ec7d4e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426994148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.3426994148
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.2894856689
Short name T90
Test name
Test status
Simulation time 798231198 ps
CPU time 11.4 seconds
Started Jun 04 03:01:03 PM PDT 24
Finished Jun 04 03:01:16 PM PDT 24
Peak memory 242220 kb
Host smart-64aa9b53-b082-4915-a693-17b91f3d8cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894856689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.2894856689
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.1479136102
Short name T50
Test name
Test status
Simulation time 540205645 ps
CPU time 5.98 seconds
Started Jun 04 03:04:04 PM PDT 24
Finished Jun 04 03:04:12 PM PDT 24
Peak memory 242360 kb
Host smart-87fd3532-e6e1-4a60-a2b4-ea2ef7c49528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479136102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.1479136102
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.3445210257
Short name T260
Test name
Test status
Simulation time 6628990338 ps
CPU time 223.86 seconds
Started Jun 04 02:59:59 PM PDT 24
Finished Jun 04 03:03:43 PM PDT 24
Peak memory 257564 kb
Host smart-bd36833c-2488-48d8-b30d-2280fa3b224f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445210257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.
3445210257
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.309055730
Short name T62
Test name
Test status
Simulation time 163240139 ps
CPU time 4.41 seconds
Started Jun 04 03:00:50 PM PDT 24
Finished Jun 04 03:00:56 PM PDT 24
Peak memory 242672 kb
Host smart-44fdc35e-2b0b-42d3-ba59-90e9a6b1eaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309055730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.309055730
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.3818529295
Short name T131
Test name
Test status
Simulation time 2452675407 ps
CPU time 4.67 seconds
Started Jun 04 03:03:49 PM PDT 24
Finished Jun 04 03:03:55 PM PDT 24
Peak memory 242456 kb
Host smart-f87d0c4b-c8bc-4a0b-9006-3ace5df46658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818529295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.3818529295
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.3950314095
Short name T289
Test name
Test status
Simulation time 1920690814690 ps
CPU time 4523.72 seconds
Started Jun 04 03:03:01 PM PDT 24
Finished Jun 04 04:18:27 PM PDT 24
Peak memory 590216 kb
Host smart-0595a3dd-6884-4c8e-a265-a27ddac6b3d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950314095 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.3950314095
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.4069334430
Short name T189
Test name
Test status
Simulation time 1025976584 ps
CPU time 29.67 seconds
Started Jun 04 03:00:52 PM PDT 24
Finished Jun 04 03:01:22 PM PDT 24
Peak memory 243900 kb
Host smart-b48b2a40-d995-4624-8afe-cff9532525c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069334430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.4069334430
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.423954199
Short name T1003
Test name
Test status
Simulation time 147461298 ps
CPU time 4.1 seconds
Started Jun 04 03:03:36 PM PDT 24
Finished Jun 04 03:03:41 PM PDT 24
Peak memory 242264 kb
Host smart-b41970e6-2d61-4276-89e1-23cbeb1d9208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423954199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.423954199
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.1235104692
Short name T975
Test name
Test status
Simulation time 149868382 ps
CPU time 5.71 seconds
Started Jun 04 03:03:56 PM PDT 24
Finished Jun 04 03:04:03 PM PDT 24
Peak memory 242652 kb
Host smart-6efbc9ea-3a30-4c99-bf00-7de6dfc44130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235104692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.1235104692
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.573555520
Short name T235
Test name
Test status
Simulation time 9993521389 ps
CPU time 344.61 seconds
Started Jun 04 03:03:02 PM PDT 24
Finished Jun 04 03:08:48 PM PDT 24
Peak memory 258876 kb
Host smart-6f3a2d43-98f7-43b8-b037-076c2dfaffb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573555520 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.573555520
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.2149673879
Short name T54
Test name
Test status
Simulation time 264149261 ps
CPU time 4.54 seconds
Started Jun 04 03:03:03 PM PDT 24
Finished Jun 04 03:03:08 PM PDT 24
Peak memory 242280 kb
Host smart-a14fd72c-8bbe-40e2-8ab6-9e8edc0ab8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149673879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.2149673879
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.593480199
Short name T415
Test name
Test status
Simulation time 223211721 ps
CPU time 2.03 seconds
Started Jun 04 03:01:51 PM PDT 24
Finished Jun 04 03:01:54 PM PDT 24
Peak memory 241020 kb
Host smart-6dbc652f-bf2c-467c-a876-6966d5c364b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593480199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.593480199
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.1461835649
Short name T175
Test name
Test status
Simulation time 2084361370 ps
CPU time 5.6 seconds
Started Jun 04 03:04:26 PM PDT 24
Finished Jun 04 03:04:32 PM PDT 24
Peak memory 242380 kb
Host smart-7692f750-85ce-4ae7-b40b-4e44fb42afbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461835649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.1461835649
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.2092699476
Short name T219
Test name
Test status
Simulation time 669088871 ps
CPU time 11.98 seconds
Started Jun 04 02:58:58 PM PDT 24
Finished Jun 04 02:59:11 PM PDT 24
Peak memory 242204 kb
Host smart-7ec264a0-7393-47bc-ada2-176137766c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092699476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.2092699476
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.3986000511
Short name T269
Test name
Test status
Simulation time 311031801 ps
CPU time 11.03 seconds
Started Jun 04 03:02:51 PM PDT 24
Finished Jun 04 03:03:03 PM PDT 24
Peak memory 242612 kb
Host smart-7beea129-9611-4dd3-99a3-3a58200f9aba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3986000511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.3986000511
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.105201439
Short name T123
Test name
Test status
Simulation time 515544416 ps
CPU time 7.99 seconds
Started Jun 04 03:02:59 PM PDT 24
Finished Jun 04 03:03:08 PM PDT 24
Peak memory 242368 kb
Host smart-5c9e1cb7-f0b1-40c3-af2c-72352e623ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105201439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.105201439
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.3145173984
Short name T831
Test name
Test status
Simulation time 123894612493 ps
CPU time 271.96 seconds
Started Jun 04 02:59:49 PM PDT 24
Finished Jun 04 03:04:22 PM PDT 24
Peak memory 274012 kb
Host smart-387cecfc-acdf-499b-96c8-09573ba897c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145173984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
3145173984
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.3346139237
Short name T723
Test name
Test status
Simulation time 601671555 ps
CPU time 10.33 seconds
Started Jun 04 02:58:58 PM PDT 24
Finished Jun 04 02:59:09 PM PDT 24
Peak memory 248836 kb
Host smart-553a37df-24be-4e30-8c09-d0f8cd71233d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3346139237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.3346139237
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.1311557596
Short name T290
Test name
Test status
Simulation time 145877207873 ps
CPU time 1808.24 seconds
Started Jun 04 03:03:09 PM PDT 24
Finished Jun 04 03:33:19 PM PDT 24
Peak memory 281984 kb
Host smart-8ed123ad-1dc3-4109-aed2-6a2f122b4f30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311557596 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.1311557596
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.946076220
Short name T40
Test name
Test status
Simulation time 744282478 ps
CPU time 5.53 seconds
Started Jun 04 03:04:42 PM PDT 24
Finished Jun 04 03:04:49 PM PDT 24
Peak memory 242608 kb
Host smart-ee651299-e680-4d4b-b897-2ebcb38120b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946076220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.946076220
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.56722199
Short name T42
Test name
Test status
Simulation time 2825795081 ps
CPU time 26.56 seconds
Started Jun 04 03:01:13 PM PDT 24
Finished Jun 04 03:01:42 PM PDT 24
Peak memory 242836 kb
Host smart-0f863a19-3533-4bba-8a7e-ec7aef0ee33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56722199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.56722199
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.4135200265
Short name T170
Test name
Test status
Simulation time 326356286 ps
CPU time 3.71 seconds
Started Jun 04 03:03:46 PM PDT 24
Finished Jun 04 03:03:51 PM PDT 24
Peak memory 242648 kb
Host smart-a511cfeb-9328-4701-8740-97102c05c825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135200265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.4135200265
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.1162540617
Short name T68
Test name
Test status
Simulation time 266773812 ps
CPU time 4.34 seconds
Started Jun 04 03:02:59 PM PDT 24
Finished Jun 04 03:03:04 PM PDT 24
Peak memory 242420 kb
Host smart-faac10ae-baf1-46cb-9c1e-1c4052f9cadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162540617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.1162540617
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.922847926
Short name T254
Test name
Test status
Simulation time 1000131361 ps
CPU time 16.26 seconds
Started Jun 04 03:03:58 PM PDT 24
Finished Jun 04 03:04:15 PM PDT 24
Peak memory 242252 kb
Host smart-4625c012-2a15-46c5-8544-fe0a64a77fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922847926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.922847926
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.1545298399
Short name T240
Test name
Test status
Simulation time 47102810316 ps
CPU time 670.51 seconds
Started Jun 04 03:02:34 PM PDT 24
Finished Jun 04 03:13:45 PM PDT 24
Peak memory 258224 kb
Host smart-b8939f11-beb2-4ce3-898d-2defe9194981
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545298399 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.1545298399
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.4176704774
Short name T311
Test name
Test status
Simulation time 93028908 ps
CPU time 1.81 seconds
Started Jun 04 01:18:39 PM PDT 24
Finished Jun 04 01:18:41 PM PDT 24
Peak memory 239632 kb
Host smart-93595347-3e91-4586-8761-d4f6f0a29120
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176704774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.4176704774
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.3351137326
Short name T87
Test name
Test status
Simulation time 7842612133 ps
CPU time 16.73 seconds
Started Jun 04 03:01:12 PM PDT 24
Finished Jun 04 03:01:31 PM PDT 24
Peak memory 242344 kb
Host smart-3ec7e538-fa2e-4259-9837-49e1c8aab65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351137326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.3351137326
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3291155709
Short name T287
Test name
Test status
Simulation time 2683870098 ps
CPU time 21.05 seconds
Started Jun 04 01:19:17 PM PDT 24
Finished Jun 04 01:19:39 PM PDT 24
Peak memory 244964 kb
Host smart-4740cb1f-a2a0-4be5-ba9e-5b292fd6e023
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291155709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.3291155709
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.3072304331
Short name T25
Test name
Test status
Simulation time 510384063 ps
CPU time 12.88 seconds
Started Jun 04 03:00:41 PM PDT 24
Finished Jun 04 03:00:55 PM PDT 24
Peak memory 242800 kb
Host smart-341e4d26-0e25-4195-8216-bdb0e8074b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072304331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.3072304331
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.1277959762
Short name T86
Test name
Test status
Simulation time 234316383 ps
CPU time 4.21 seconds
Started Jun 04 02:58:58 PM PDT 24
Finished Jun 04 02:59:03 PM PDT 24
Peak memory 242760 kb
Host smart-b9f313ab-ce00-4216-9f32-9ae0f93a09a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277959762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.1277959762
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.738964235
Short name T102
Test name
Test status
Simulation time 2694259871 ps
CPU time 26.41 seconds
Started Jun 04 02:58:51 PM PDT 24
Finished Jun 04 02:59:19 PM PDT 24
Peak memory 248976 kb
Host smart-58854f45-5413-4842-9e70-41646d484451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738964235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.738964235
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.1810598048
Short name T73
Test name
Test status
Simulation time 5047272864 ps
CPU time 11.21 seconds
Started Jun 04 03:03:33 PM PDT 24
Finished Jun 04 03:03:45 PM PDT 24
Peak memory 242296 kb
Host smart-dadac201-fa0f-4d05-925d-e233ae2d5a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810598048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.1810598048
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.1128735312
Short name T183
Test name
Test status
Simulation time 624368945 ps
CPU time 4.97 seconds
Started Jun 04 03:00:16 PM PDT 24
Finished Jun 04 03:00:22 PM PDT 24
Peak memory 242308 kb
Host smart-69192b46-c81e-47a9-862f-f1b9a8e44c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128735312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.1128735312
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.2253128569
Short name T224
Test name
Test status
Simulation time 1659706174 ps
CPU time 27.11 seconds
Started Jun 04 03:00:49 PM PDT 24
Finished Jun 04 03:01:18 PM PDT 24
Peak memory 242200 kb
Host smart-751ac156-ce9d-4c82-aff5-a664c4dc60ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253128569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.2253128569
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.794760281
Short name T72
Test name
Test status
Simulation time 690234443 ps
CPU time 11.07 seconds
Started Jun 04 03:04:22 PM PDT 24
Finished Jun 04 03:04:34 PM PDT 24
Peak memory 242240 kb
Host smart-bf22caa2-177e-4ac7-8633-07a8e026a49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794760281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.794760281
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.3249202391
Short name T53
Test name
Test status
Simulation time 305247998 ps
CPU time 4.83 seconds
Started Jun 04 03:04:30 PM PDT 24
Finished Jun 04 03:04:35 PM PDT 24
Peak memory 242316 kb
Host smart-83d511c6-f2cb-4983-ab5f-662a6045c27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249202391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.3249202391
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.3470390840
Short name T231
Test name
Test status
Simulation time 356896590 ps
CPU time 5.32 seconds
Started Jun 04 03:03:09 PM PDT 24
Finished Jun 04 03:03:16 PM PDT 24
Peak memory 242096 kb
Host smart-4396a1db-449a-4370-9435-e13ca023d52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470390840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.3470390840
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.571003092
Short name T125
Test name
Test status
Simulation time 145994603269 ps
CPU time 316.22 seconds
Started Jun 04 03:03:28 PM PDT 24
Finished Jun 04 03:08:46 PM PDT 24
Peak memory 257344 kb
Host smart-ff848944-f644-42e1-b4eb-44eacac1a2bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571003092 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.571003092
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.1104225791
Short name T106
Test name
Test status
Simulation time 18274584128 ps
CPU time 32.65 seconds
Started Jun 04 02:59:40 PM PDT 24
Finished Jun 04 03:00:14 PM PDT 24
Peak memory 248992 kb
Host smart-e0e2e604-a48f-4542-a08c-c73b9fda61b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104225791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.1104225791
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.4278028576
Short name T358
Test name
Test status
Simulation time 3271384113 ps
CPU time 21.62 seconds
Started Jun 04 01:18:44 PM PDT 24
Finished Jun 04 01:19:07 PM PDT 24
Peak memory 244628 kb
Host smart-7ac2b3de-6ff1-4e1d-bea0-07cbfe57fd9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278028576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.4278028576
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.2240049691
Short name T356
Test name
Test status
Simulation time 17802632289 ps
CPU time 55.78 seconds
Started Jun 04 03:02:16 PM PDT 24
Finished Jun 04 03:03:12 PM PDT 24
Peak memory 248460 kb
Host smart-e9445281-3f54-4858-be89-0d589f800a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240049691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.2240049691
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2382348257
Short name T321
Test name
Test status
Simulation time 38739549 ps
CPU time 1.77 seconds
Started Jun 04 01:19:08 PM PDT 24
Finished Jun 04 01:19:11 PM PDT 24
Peak memory 239660 kb
Host smart-fc2f4e2f-9b19-44b3-939d-a4790df21386
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382348257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.2382348257
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.2185970121
Short name T5
Test name
Test status
Simulation time 3980927594 ps
CPU time 12.62 seconds
Started Jun 04 03:01:18 PM PDT 24
Finished Jun 04 03:01:32 PM PDT 24
Peak memory 242536 kb
Host smart-3fb57ba1-589c-45f7-8b49-972b3976ce85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2185970121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.2185970121
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.4064855310
Short name T83
Test name
Test status
Simulation time 2254427155 ps
CPU time 16.19 seconds
Started Jun 04 03:02:44 PM PDT 24
Finished Jun 04 03:03:01 PM PDT 24
Peak memory 242940 kb
Host smart-ddccbf26-8f7a-46e6-8d3a-44139271f586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064855310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.4064855310
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.3352973923
Short name T222
Test name
Test status
Simulation time 136897170093 ps
CPU time 1241.43 seconds
Started Jun 04 03:02:27 PM PDT 24
Finished Jun 04 03:23:10 PM PDT 24
Peak memory 267576 kb
Host smart-6dec250d-1ff5-4a9f-ab45-a92796d52fe9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352973923 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.3352973923
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.3346573918
Short name T92
Test name
Test status
Simulation time 1876633761 ps
CPU time 45.37 seconds
Started Jun 04 03:02:09 PM PDT 24
Finished Jun 04 03:02:55 PM PDT 24
Peak memory 242480 kb
Host smart-c506b9ac-c025-4a47-86d4-5b7298fa0d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346573918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.3346573918
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.3493698414
Short name T211
Test name
Test status
Simulation time 128783123 ps
CPU time 3.66 seconds
Started Jun 04 03:03:37 PM PDT 24
Finished Jun 04 03:03:41 PM PDT 24
Peak memory 242652 kb
Host smart-b0a6f306-528a-4a71-8955-7119bb1a028f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493698414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.3493698414
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.148162720
Short name T8
Test name
Test status
Simulation time 104510245 ps
CPU time 3.66 seconds
Started Jun 04 03:03:58 PM PDT 24
Finished Jun 04 03:04:02 PM PDT 24
Peak memory 242192 kb
Host smart-495e1f9a-e8b6-4d50-996c-1b88885d7ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148162720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.148162720
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2088810647
Short name T288
Test name
Test status
Simulation time 2458527397 ps
CPU time 18.79 seconds
Started Jun 04 01:19:09 PM PDT 24
Finished Jun 04 01:19:29 PM PDT 24
Peak memory 238452 kb
Host smart-812d594c-42c8-4a42-9d8b-eeaf612540dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088810647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i
ntg_err.2088810647
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.693946279
Short name T362
Test name
Test status
Simulation time 10273607608 ps
CPU time 20.88 seconds
Started Jun 04 01:18:45 PM PDT 24
Finished Jun 04 01:19:08 PM PDT 24
Peak memory 243952 kb
Host smart-e062c422-d2d0-4a1c-8e4b-b062be1ba91f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693946279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_int
g_err.693946279
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.1786475206
Short name T349
Test name
Test status
Simulation time 143890155002 ps
CPU time 924.62 seconds
Started Jun 04 03:00:23 PM PDT 24
Finished Jun 04 03:15:49 PM PDT 24
Peak memory 271792 kb
Host smart-0967eccc-013f-4085-997d-d802347e1cdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786475206 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.1786475206
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.903049527
Short name T242
Test name
Test status
Simulation time 102161503 ps
CPU time 1.83 seconds
Started Jun 04 02:58:44 PM PDT 24
Finished Jun 04 02:58:47 PM PDT 24
Peak memory 240536 kb
Host smart-ab688a19-9e9b-4973-a47d-2af5b027f1a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=903049527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.903049527
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.801211775
Short name T98
Test name
Test status
Simulation time 668386458 ps
CPU time 5.63 seconds
Started Jun 04 03:04:23 PM PDT 24
Finished Jun 04 03:04:29 PM PDT 24
Peak memory 242292 kb
Host smart-310d61fe-eb95-4a11-bec1-f4da93423512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801211775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.801211775
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2654200249
Short name T282
Test name
Test status
Simulation time 1329145721 ps
CPU time 11.89 seconds
Started Jun 04 01:18:38 PM PDT 24
Finished Jun 04 01:18:51 PM PDT 24
Peak memory 243232 kb
Host smart-14e61c3e-f13c-46a1-9634-bea45c050563
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654200249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.2654200249
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.535096172
Short name T286
Test name
Test status
Simulation time 1800287708 ps
CPU time 21.29 seconds
Started Jun 04 01:19:09 PM PDT 24
Finished Jun 04 01:19:31 PM PDT 24
Peak memory 244676 kb
Host smart-3eab1e7e-083c-4da0-a507-56d4f3621954
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535096172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_in
tg_err.535096172
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.594293552
Short name T281
Test name
Test status
Simulation time 10271473656 ps
CPU time 9.79 seconds
Started Jun 04 01:18:53 PM PDT 24
Finished Jun 04 01:19:04 PM PDT 24
Peak memory 244180 kb
Host smart-0d55e88b-8082-4e46-b4ea-ed3b3a1d319f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594293552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_int
g_err.594293552
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.2092592266
Short name T473
Test name
Test status
Simulation time 260074924 ps
CPU time 4.7 seconds
Started Jun 04 03:03:48 PM PDT 24
Finished Jun 04 03:03:55 PM PDT 24
Peak memory 242364 kb
Host smart-4f75c756-ed28-4e3f-a077-b9fb4e0a3e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092592266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.2092592266
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.2079952307
Short name T127
Test name
Test status
Simulation time 2055367787 ps
CPU time 6.45 seconds
Started Jun 04 03:03:19 PM PDT 24
Finished Jun 04 03:03:27 PM PDT 24
Peak memory 242328 kb
Host smart-7f7c8c07-42a9-41a5-b864-53d9f3cbed62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079952307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.2079952307
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.683991574
Short name T1121
Test name
Test status
Simulation time 4417018095 ps
CPU time 26.82 seconds
Started Jun 04 02:58:59 PM PDT 24
Finished Jun 04 02:59:26 PM PDT 24
Peak memory 243576 kb
Host smart-364d956c-a1b8-458d-9b52-b26cfdcd0add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683991574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.683991574
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.2786814397
Short name T724
Test name
Test status
Simulation time 32109828024 ps
CPU time 260.91 seconds
Started Jun 04 03:02:17 PM PDT 24
Finished Jun 04 03:06:38 PM PDT 24
Peak memory 257340 kb
Host smart-d4af9b00-f2fa-4a5b-965d-7e12f65eb432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786814397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.2786814397
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.3615154327
Short name T695
Test name
Test status
Simulation time 285979040655 ps
CPU time 1848.56 seconds
Started Jun 04 03:02:54 PM PDT 24
Finished Jun 04 03:33:43 PM PDT 24
Peak memory 278716 kb
Host smart-3c64db0c-3e5e-43ad-9439-f69bb77efcd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615154327 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.3615154327
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.975709577
Short name T118
Test name
Test status
Simulation time 222661622 ps
CPU time 5.51 seconds
Started Jun 04 03:04:16 PM PDT 24
Finished Jun 04 03:04:22 PM PDT 24
Peak memory 242156 kb
Host smart-30a1ecd4-4e8a-444e-89b9-7c0257b3c16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975709577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.975709577
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.1347400112
Short name T101
Test name
Test status
Simulation time 554535066 ps
CPU time 9.94 seconds
Started Jun 04 03:00:09 PM PDT 24
Finished Jun 04 03:00:20 PM PDT 24
Peak memory 242124 kb
Host smart-d9b7536b-40f6-4098-9c88-de261c18d043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347400112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.1347400112
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.457707723
Short name T315
Test name
Test status
Simulation time 75431036 ps
CPU time 5.1 seconds
Started Jun 04 01:18:37 PM PDT 24
Finished Jun 04 01:18:43 PM PDT 24
Peak memory 237572 kb
Host smart-5772628d-190d-42ca-9bb3-e57e2fc5c672
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457707723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alias
ing.457707723
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.3028564835
Short name T277
Test name
Test status
Simulation time 250514878 ps
CPU time 5.35 seconds
Started Jun 04 01:18:38 PM PDT 24
Finished Jun 04 01:18:44 PM PDT 24
Peak memory 237268 kb
Host smart-34295661-72cf-48da-862e-e85bfc6026cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028564835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.3028564835
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1842407692
Short name T1317
Test name
Test status
Simulation time 1554759413 ps
CPU time 2.94 seconds
Started Jun 04 01:18:36 PM PDT 24
Finished Jun 04 01:18:39 PM PDT 24
Peak memory 238356 kb
Host smart-edc4cd65-32e8-40ab-884d-00c3e2fb1dba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842407692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r
eset.1842407692
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3715770395
Short name T1244
Test name
Test status
Simulation time 1577786131 ps
CPU time 5.39 seconds
Started Jun 04 01:18:38 PM PDT 24
Finished Jun 04 01:18:44 PM PDT 24
Peak memory 246544 kb
Host smart-7d83d4c1-2a31-47ec-9f84-b74a555f7661
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715770395 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.3715770395
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.72238345
Short name T1306
Test name
Test status
Simulation time 66623212 ps
CPU time 1.38 seconds
Started Jun 04 01:18:37 PM PDT 24
Finished Jun 04 01:18:39 PM PDT 24
Peak memory 229156 kb
Host smart-3458a042-60ae-4a6d-975f-492547b13486
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72238345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.72238345
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3195782092
Short name T1211
Test name
Test status
Simulation time 73969952 ps
CPU time 1.34 seconds
Started Jun 04 01:18:36 PM PDT 24
Finished Jun 04 01:18:38 PM PDT 24
Peak memory 229928 kb
Host smart-eac3510f-0e81-46f8-876f-218697022cdb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195782092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.3195782092
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3527632594
Short name T1253
Test name
Test status
Simulation time 39048401 ps
CPU time 1.44 seconds
Started Jun 04 01:18:38 PM PDT 24
Finished Jun 04 01:18:40 PM PDT 24
Peak memory 228904 kb
Host smart-468219ad-b165-4d83-999c-bcf13372bc31
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527632594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.3527632594
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.3164605602
Short name T1285
Test name
Test status
Simulation time 163354844 ps
CPU time 3.11 seconds
Started Jun 04 01:18:37 PM PDT 24
Finished Jun 04 01:18:41 PM PDT 24
Peak memory 238292 kb
Host smart-de7e3aaa-905c-49a8-955f-edfb20abe19f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164605602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.3164605602
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2864855829
Short name T1224
Test name
Test status
Simulation time 100800532 ps
CPU time 4.14 seconds
Started Jun 04 01:18:36 PM PDT 24
Finished Jun 04 01:18:41 PM PDT 24
Peak memory 245404 kb
Host smart-fae4e8f3-b469-439c-9fe8-f6ed3ffd2f39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864855829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.2864855829
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.482271143
Short name T1330
Test name
Test status
Simulation time 127848577 ps
CPU time 3.89 seconds
Started Jun 04 01:18:47 PM PDT 24
Finished Jun 04 01:18:51 PM PDT 24
Peak memory 237216 kb
Host smart-e266ea0d-1766-47b6-9f3a-bb7452c7b1bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482271143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alias
ing.482271143
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2397854476
Short name T323
Test name
Test status
Simulation time 166028556 ps
CPU time 4.19 seconds
Started Jun 04 01:18:46 PM PDT 24
Finished Jun 04 01:18:52 PM PDT 24
Peak memory 237220 kb
Host smart-a5af0b91-4576-452a-89d9-22852ad92742
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397854476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_
bash.2397854476
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2614631651
Short name T314
Test name
Test status
Simulation time 70200701 ps
CPU time 1.99 seconds
Started Jun 04 01:18:38 PM PDT 24
Finished Jun 04 01:18:40 PM PDT 24
Peak memory 237456 kb
Host smart-1241f41a-99f9-4c7a-9974-6701543beeb7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614631651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.2614631651
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.317158226
Short name T1283
Test name
Test status
Simulation time 81261556 ps
CPU time 2.29 seconds
Started Jun 04 01:18:45 PM PDT 24
Finished Jun 04 01:18:48 PM PDT 24
Peak memory 245156 kb
Host smart-5729fa30-6afc-4c8e-b120-6905490d7986
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317158226 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.317158226
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3234823470
Short name T1266
Test name
Test status
Simulation time 46100698 ps
CPU time 1.75 seconds
Started Jun 04 01:18:38 PM PDT 24
Finished Jun 04 01:18:41 PM PDT 24
Peak memory 240100 kb
Host smart-7ddba155-f333-4e7a-acc2-8899d59f0c01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234823470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.3234823470
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.2705759540
Short name T1208
Test name
Test status
Simulation time 41608021 ps
CPU time 1.42 seconds
Started Jun 04 01:18:35 PM PDT 24
Finished Jun 04 01:18:37 PM PDT 24
Peak memory 230140 kb
Host smart-4bc79b34-a549-4e07-80f2-82aeaf7cad53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705759540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.2705759540
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2673511386
Short name T1294
Test name
Test status
Simulation time 72998666 ps
CPU time 1.41 seconds
Started Jun 04 01:18:38 PM PDT 24
Finished Jun 04 01:18:40 PM PDT 24
Peak memory 228812 kb
Host smart-b152dce9-a92c-4bea-817c-0dec417f3924
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673511386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.2673511386
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.1158404711
Short name T1209
Test name
Test status
Simulation time 106550111 ps
CPU time 1.29 seconds
Started Jun 04 01:18:43 PM PDT 24
Finished Jun 04 01:18:46 PM PDT 24
Peak memory 228932 kb
Host smart-6ef7b5ab-f4bb-4a36-afeb-b4caa8dd2381
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158404711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.1158404711
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.344987799
Short name T283
Test name
Test status
Simulation time 99420496 ps
CPU time 2.41 seconds
Started Jun 04 01:18:45 PM PDT 24
Finished Jun 04 01:18:49 PM PDT 24
Peak memory 238392 kb
Host smart-c2f4edb8-4c88-467a-ab32-a35cc99a1bf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344987799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ct
rl_same_csr_outstanding.344987799
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2853873736
Short name T1248
Test name
Test status
Simulation time 697909948 ps
CPU time 7.34 seconds
Started Jun 04 01:18:39 PM PDT 24
Finished Jun 04 01:18:47 PM PDT 24
Peak memory 246548 kb
Host smart-24c5181e-82e3-4aa0-88ed-40eb6ea039ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853873736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.2853873736
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.2894144242
Short name T1305
Test name
Test status
Simulation time 2659153129 ps
CPU time 9.59 seconds
Started Jun 04 01:18:36 PM PDT 24
Finished Jun 04 01:18:47 PM PDT 24
Peak memory 243788 kb
Host smart-8732be83-0fa5-4425-8319-1e109f345fe5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894144242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.2894144242
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2883600339
Short name T1263
Test name
Test status
Simulation time 71256860 ps
CPU time 1.98 seconds
Started Jun 04 01:19:01 PM PDT 24
Finished Jun 04 01:19:03 PM PDT 24
Peak memory 244908 kb
Host smart-fea18187-a581-4a2a-b0e0-aff8a5c11267
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883600339 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.2883600339
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1474484914
Short name T313
Test name
Test status
Simulation time 667946096 ps
CPU time 2.04 seconds
Started Jun 04 01:19:03 PM PDT 24
Finished Jun 04 01:19:06 PM PDT 24
Peak memory 239944 kb
Host smart-3a7f2122-393b-494c-8e19-ce278bd2093a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474484914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.1474484914
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.868660981
Short name T1286
Test name
Test status
Simulation time 140032755 ps
CPU time 1.46 seconds
Started Jun 04 01:19:02 PM PDT 24
Finished Jun 04 01:19:05 PM PDT 24
Peak memory 228904 kb
Host smart-4044d0c6-2037-4e39-aa4c-ade05fbf9823
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868660981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.868660981
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1351531511
Short name T1329
Test name
Test status
Simulation time 173164079 ps
CPU time 2.35 seconds
Started Jun 04 01:19:02 PM PDT 24
Finished Jun 04 01:19:05 PM PDT 24
Peak memory 237484 kb
Host smart-a7075cbd-54c7-4e23-bcfe-265852c27cf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351531511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.1351531511
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.1392141488
Short name T1328
Test name
Test status
Simulation time 97000006 ps
CPU time 3.57 seconds
Started Jun 04 01:19:02 PM PDT 24
Finished Jun 04 01:19:07 PM PDT 24
Peak memory 246052 kb
Host smart-8eaecd81-b4cc-4ea8-97ed-eba60508a732
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392141488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.1392141488
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.335897187
Short name T361
Test name
Test status
Simulation time 2552510334 ps
CPU time 29.74 seconds
Started Jun 04 01:19:03 PM PDT 24
Finished Jun 04 01:19:34 PM PDT 24
Peak memory 244032 kb
Host smart-5209d5b4-a828-464a-8d04-9e1f3837d216
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335897187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_in
tg_err.335897187
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.4236621930
Short name T1295
Test name
Test status
Simulation time 374883814 ps
CPU time 3.6 seconds
Started Jun 04 01:19:01 PM PDT 24
Finished Jun 04 01:19:05 PM PDT 24
Peak memory 246552 kb
Host smart-280656bf-35fb-4f8f-af9d-3128696024dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236621930 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.4236621930
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.4198142336
Short name T284
Test name
Test status
Simulation time 39925577 ps
CPU time 1.62 seconds
Started Jun 04 01:19:03 PM PDT 24
Finished Jun 04 01:19:05 PM PDT 24
Peak memory 239508 kb
Host smart-64de26e0-bc75-4a9b-8790-197405d24bef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198142336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.4198142336
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2025871571
Short name T1303
Test name
Test status
Simulation time 75503661 ps
CPU time 1.47 seconds
Started Jun 04 01:19:03 PM PDT 24
Finished Jun 04 01:19:06 PM PDT 24
Peak memory 229164 kb
Host smart-9b87b19d-f035-4236-a954-821d1b3a533f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025871571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.2025871571
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1898647491
Short name T1312
Test name
Test status
Simulation time 1443054071 ps
CPU time 4.05 seconds
Started Jun 04 01:19:01 PM PDT 24
Finished Jun 04 01:19:06 PM PDT 24
Peak memory 237360 kb
Host smart-6e7742a4-f409-44af-93e1-d0bafc6444a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898647491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.1898647491
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3068758924
Short name T1321
Test name
Test status
Simulation time 890882926 ps
CPU time 3.74 seconds
Started Jun 04 01:18:59 PM PDT 24
Finished Jun 04 01:19:04 PM PDT 24
Peak memory 238484 kb
Host smart-931cb88e-6471-40ca-91c0-5f12e8643d59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068758924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.3068758924
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.2608941398
Short name T1325
Test name
Test status
Simulation time 1216914025 ps
CPU time 9.63 seconds
Started Jun 04 01:19:01 PM PDT 24
Finished Jun 04 01:19:12 PM PDT 24
Peak memory 242640 kb
Host smart-80ca5a83-44e4-485e-b83f-03589ea2266f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608941398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.2608941398
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.3926593846
Short name T1251
Test name
Test status
Simulation time 108353620 ps
CPU time 2.96 seconds
Started Jun 04 01:18:59 PM PDT 24
Finished Jun 04 01:19:03 PM PDT 24
Peak memory 245928 kb
Host smart-fb0e3615-5d90-47fc-a1b8-bf6e65ea011b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926593846 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.3926593846
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1280081350
Short name T324
Test name
Test status
Simulation time 44906675 ps
CPU time 1.66 seconds
Started Jun 04 01:19:06 PM PDT 24
Finished Jun 04 01:19:09 PM PDT 24
Peak memory 239268 kb
Host smart-3f6b65fc-929d-42a3-9843-d645598472ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280081350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.1280081350
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.1682007031
Short name T1264
Test name
Test status
Simulation time 148607364 ps
CPU time 1.38 seconds
Started Jun 04 01:18:59 PM PDT 24
Finished Jun 04 01:19:01 PM PDT 24
Peak memory 228904 kb
Host smart-458c5df7-9c20-4fe4-9642-b1b91bfdd7bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682007031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.1682007031
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.3481495999
Short name T1262
Test name
Test status
Simulation time 1196394412 ps
CPU time 3.51 seconds
Started Jun 04 01:19:00 PM PDT 24
Finished Jun 04 01:19:04 PM PDT 24
Peak memory 237636 kb
Host smart-11736096-ab79-4a14-b750-c08afebfd31b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481495999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.3481495999
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2897210387
Short name T1269
Test name
Test status
Simulation time 61938160 ps
CPU time 3.71 seconds
Started Jun 04 01:19:01 PM PDT 24
Finished Jun 04 01:19:06 PM PDT 24
Peak memory 246124 kb
Host smart-0783e23e-354d-4f1e-952c-400970a83d2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897210387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.2897210387
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.216591781
Short name T1327
Test name
Test status
Simulation time 9719048889 ps
CPU time 16 seconds
Started Jun 04 01:19:03 PM PDT 24
Finished Jun 04 01:19:20 PM PDT 24
Peak memory 243916 kb
Host smart-3fac9ea9-2bae-49e8-9b67-ecdec44e81f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216591781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_in
tg_err.216591781
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1203347293
Short name T1247
Test name
Test status
Simulation time 1674880809 ps
CPU time 4.34 seconds
Started Jun 04 01:19:01 PM PDT 24
Finished Jun 04 01:19:07 PM PDT 24
Peak memory 246508 kb
Host smart-989b301d-4016-4be8-a9ee-5fc0ee563ac4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203347293 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.1203347293
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.2219782422
Short name T280
Test name
Test status
Simulation time 40628058 ps
CPU time 1.67 seconds
Started Jun 04 01:19:01 PM PDT 24
Finished Jun 04 01:19:04 PM PDT 24
Peak memory 239732 kb
Host smart-ba99f181-d316-4bcb-ab57-9ab94f468670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219782422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.2219782422
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.1160459300
Short name T1241
Test name
Test status
Simulation time 40327979 ps
CPU time 1.46 seconds
Started Jun 04 01:19:00 PM PDT 24
Finished Jun 04 01:19:02 PM PDT 24
Peak memory 229244 kb
Host smart-a4ebc187-84f9-4e6f-b342-18214433972f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160459300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.1160459300
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.2762444070
Short name T331
Test name
Test status
Simulation time 72410540 ps
CPU time 2.25 seconds
Started Jun 04 01:19:02 PM PDT 24
Finished Jun 04 01:19:05 PM PDT 24
Peak memory 238320 kb
Host smart-e5d7b1ad-2237-444f-ba99-00eada51de70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762444070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.2762444070
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2822618311
Short name T1234
Test name
Test status
Simulation time 99623444 ps
CPU time 3.01 seconds
Started Jun 04 01:19:02 PM PDT 24
Finished Jun 04 01:19:06 PM PDT 24
Peak memory 246044 kb
Host smart-062b00f5-2bc7-4f8a-b3d0-c3d0f2324112
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822618311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.2822618311
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.3425769892
Short name T1300
Test name
Test status
Simulation time 123304169 ps
CPU time 2.19 seconds
Started Jun 04 01:19:08 PM PDT 24
Finished Jun 04 01:19:11 PM PDT 24
Peak memory 245208 kb
Host smart-9c146bc1-2b16-45af-8201-044053423ad9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425769892 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.3425769892
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2051759966
Short name T320
Test name
Test status
Simulation time 73881869 ps
CPU time 1.7 seconds
Started Jun 04 01:19:07 PM PDT 24
Finished Jun 04 01:19:10 PM PDT 24
Peak memory 238312 kb
Host smart-45476a03-3f9d-43b9-b66e-55dfac81af7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051759966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.2051759966
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.1095076438
Short name T1230
Test name
Test status
Simulation time 149111711 ps
CPU time 1.52 seconds
Started Jun 04 01:19:10 PM PDT 24
Finished Jun 04 01:19:12 PM PDT 24
Peak memory 228924 kb
Host smart-7e6eea9c-3f44-4c21-8ce9-755d5a390da9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095076438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.1095076438
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.4040366028
Short name T1324
Test name
Test status
Simulation time 53391056 ps
CPU time 1.89 seconds
Started Jun 04 01:19:09 PM PDT 24
Finished Jun 04 01:19:12 PM PDT 24
Peak memory 238256 kb
Host smart-912a5f3b-93cc-4c9f-88b4-ae50fbbefa47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040366028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.4040366028
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.168336160
Short name T1237
Test name
Test status
Simulation time 54470144 ps
CPU time 2.56 seconds
Started Jun 04 01:18:59 PM PDT 24
Finished Jun 04 01:19:02 PM PDT 24
Peak memory 245652 kb
Host smart-fdc2497a-de42-4f88-a71e-b2abfae1e2d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168336160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.168336160
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3519335912
Short name T1281
Test name
Test status
Simulation time 137718690 ps
CPU time 2.11 seconds
Started Jun 04 01:19:07 PM PDT 24
Finished Jun 04 01:19:10 PM PDT 24
Peak memory 238368 kb
Host smart-0d556ed7-bb77-4975-b0b2-97b6fa08bca1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519335912 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.3519335912
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.2548414482
Short name T1242
Test name
Test status
Simulation time 76110896 ps
CPU time 1.53 seconds
Started Jun 04 01:19:09 PM PDT 24
Finished Jun 04 01:19:11 PM PDT 24
Peak memory 239088 kb
Host smart-7aa64bcf-18bc-4446-8400-e8e4f5cde371
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548414482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.2548414482
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.1851433569
Short name T1292
Test name
Test status
Simulation time 593178850 ps
CPU time 1.96 seconds
Started Jun 04 01:19:10 PM PDT 24
Finished Jun 04 01:19:13 PM PDT 24
Peak memory 229228 kb
Host smart-f4992fbb-25b7-4a1d-82f3-174f99773729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851433569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.1851433569
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.329895556
Short name T1323
Test name
Test status
Simulation time 254343386 ps
CPU time 2.3 seconds
Started Jun 04 01:19:07 PM PDT 24
Finished Jun 04 01:19:10 PM PDT 24
Peak memory 237468 kb
Host smart-ee5f6c85-8cb0-4688-a30a-fd131b4be281
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329895556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_c
trl_same_csr_outstanding.329895556
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1386846534
Short name T1315
Test name
Test status
Simulation time 143553814 ps
CPU time 4.9 seconds
Started Jun 04 01:19:08 PM PDT 24
Finished Jun 04 01:19:14 PM PDT 24
Peak memory 246044 kb
Host smart-7a08d67f-bd3e-4cff-b2e6-41c3097b3c86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386846534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.1386846534
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1692291619
Short name T1238
Test name
Test status
Simulation time 122222292 ps
CPU time 3.09 seconds
Started Jun 04 01:19:07 PM PDT 24
Finished Jun 04 01:19:11 PM PDT 24
Peak memory 246668 kb
Host smart-9678138b-fa56-4413-b1b7-502fb00e341a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692291619 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.1692291619
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1435067721
Short name T1279
Test name
Test status
Simulation time 46937517 ps
CPU time 1.72 seconds
Started Jun 04 01:19:09 PM PDT 24
Finished Jun 04 01:19:12 PM PDT 24
Peak memory 240000 kb
Host smart-fa1ef31c-7453-479c-853f-172eb246dc63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435067721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.1435067721
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.3066670775
Short name T1207
Test name
Test status
Simulation time 539289217 ps
CPU time 1.67 seconds
Started Jun 04 01:19:09 PM PDT 24
Finished Jun 04 01:19:12 PM PDT 24
Peak memory 229232 kb
Host smart-6bee061e-65d6-4232-b246-845f74ce5f75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066670775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.3066670775
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.4034993490
Short name T279
Test name
Test status
Simulation time 156100660 ps
CPU time 2.75 seconds
Started Jun 04 01:19:09 PM PDT 24
Finished Jun 04 01:19:13 PM PDT 24
Peak memory 238344 kb
Host smart-01d6e222-5bf4-430e-898f-a8d515a3fb22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034993490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_
ctrl_same_csr_outstanding.4034993490
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.235712796
Short name T1332
Test name
Test status
Simulation time 888903450 ps
CPU time 3.54 seconds
Started Jun 04 01:19:09 PM PDT 24
Finished Jun 04 01:19:13 PM PDT 24
Peak memory 238464 kb
Host smart-8fcb51a5-80a3-40cc-8e5c-ad9c2980d0e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235712796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.235712796
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.781740920
Short name T276
Test name
Test status
Simulation time 4749438819 ps
CPU time 19 seconds
Started Jun 04 01:19:09 PM PDT 24
Finished Jun 04 01:19:28 PM PDT 24
Peak memory 238408 kb
Host smart-515b9417-d34e-408d-ac43-7229c5456a63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781740920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_in
tg_err.781740920
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.1554293542
Short name T1311
Test name
Test status
Simulation time 421299146 ps
CPU time 3.4 seconds
Started Jun 04 01:19:16 PM PDT 24
Finished Jun 04 01:19:20 PM PDT 24
Peak memory 246528 kb
Host smart-6c078856-9724-44d5-8f9c-b1fb9e7fe1f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554293542 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.1554293542
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.3414723873
Short name T1214
Test name
Test status
Simulation time 48257243 ps
CPU time 1.46 seconds
Started Jun 04 01:19:09 PM PDT 24
Finished Jun 04 01:19:11 PM PDT 24
Peak memory 229116 kb
Host smart-dd3ec4ab-74e9-4986-a5d9-0f37f7d1ab90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414723873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.3414723873
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.4026276526
Short name T1280
Test name
Test status
Simulation time 1155857139 ps
CPU time 3.42 seconds
Started Jun 04 01:19:16 PM PDT 24
Finished Jun 04 01:19:20 PM PDT 24
Peak memory 237332 kb
Host smart-5ee4d489-4f7d-4cc3-8cb2-d218fc238425
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026276526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.4026276526
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.2769420246
Short name T1259
Test name
Test status
Simulation time 110296683 ps
CPU time 3.75 seconds
Started Jun 04 01:19:08 PM PDT 24
Finished Jun 04 01:19:13 PM PDT 24
Peak memory 245968 kb
Host smart-6bb9867e-9339-4737-a327-e9ff036570f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769420246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.2769420246
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.3677034593
Short name T1316
Test name
Test status
Simulation time 10326604534 ps
CPU time 26.46 seconds
Started Jun 04 01:19:09 PM PDT 24
Finished Jun 04 01:19:37 PM PDT 24
Peak memory 243480 kb
Host smart-5a87b2a8-745e-49d5-b9e5-991591475d27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677034593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.3677034593
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.4256083702
Short name T1289
Test name
Test status
Simulation time 216231289 ps
CPU time 2.88 seconds
Started Jun 04 01:19:18 PM PDT 24
Finished Jun 04 01:19:22 PM PDT 24
Peak memory 246672 kb
Host smart-1dc2eb60-752d-4777-b420-5a281f4d3f9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256083702 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.4256083702
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.2342229657
Short name T1257
Test name
Test status
Simulation time 89335526 ps
CPU time 1.6 seconds
Started Jun 04 01:19:17 PM PDT 24
Finished Jun 04 01:19:20 PM PDT 24
Peak memory 239372 kb
Host smart-52489b84-44e9-42f9-80fd-13db72f1537c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342229657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.2342229657
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.3308897155
Short name T1331
Test name
Test status
Simulation time 75710302 ps
CPU time 1.44 seconds
Started Jun 04 01:19:16 PM PDT 24
Finished Jun 04 01:19:18 PM PDT 24
Peak memory 228896 kb
Host smart-3ea8d33b-54f6-4b07-a7e9-8905d43725d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308897155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.3308897155
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.2767578899
Short name T1297
Test name
Test status
Simulation time 334733452 ps
CPU time 3.65 seconds
Started Jun 04 01:19:16 PM PDT 24
Finished Jun 04 01:19:20 PM PDT 24
Peak memory 238468 kb
Host smart-ff4f6bba-5bd1-40e5-be92-64463bf4880c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767578899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.2767578899
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2944045935
Short name T1212
Test name
Test status
Simulation time 163838146 ps
CPU time 3.65 seconds
Started Jun 04 01:19:17 PM PDT 24
Finished Jun 04 01:19:21 PM PDT 24
Peak memory 238448 kb
Host smart-907dffce-b765-4e03-8580-b62b66fe69d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944045935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.2944045935
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2465476259
Short name T1229
Test name
Test status
Simulation time 1700470078 ps
CPU time 3.53 seconds
Started Jun 04 01:19:17 PM PDT 24
Finished Jun 04 01:19:22 PM PDT 24
Peak memory 245880 kb
Host smart-6a779335-ebfd-4cc7-a5ea-cdfeef6f111c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465476259 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.2465476259
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1428360155
Short name T319
Test name
Test status
Simulation time 73158687 ps
CPU time 1.87 seconds
Started Jun 04 01:19:17 PM PDT 24
Finished Jun 04 01:19:20 PM PDT 24
Peak memory 239496 kb
Host smart-891584ba-e055-40d8-94f3-c5d475799020
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428360155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.1428360155
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1536295379
Short name T1302
Test name
Test status
Simulation time 41665689 ps
CPU time 1.39 seconds
Started Jun 04 01:19:19 PM PDT 24
Finished Jun 04 01:19:21 PM PDT 24
Peak memory 228888 kb
Host smart-51bbbcd4-b1a9-4935-9848-5928f10456db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536295379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.1536295379
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.2705424512
Short name T328
Test name
Test status
Simulation time 46498487 ps
CPU time 1.97 seconds
Started Jun 04 01:19:16 PM PDT 24
Finished Jun 04 01:19:19 PM PDT 24
Peak memory 237368 kb
Host smart-4df33c9a-addf-4457-913c-5426093ddce8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705424512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.2705424512
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3153977968
Short name T1270
Test name
Test status
Simulation time 97927645 ps
CPU time 2.83 seconds
Started Jun 04 01:19:18 PM PDT 24
Finished Jun 04 01:19:22 PM PDT 24
Peak memory 238372 kb
Host smart-04f0934b-aea4-4cfe-8645-168666f5150a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153977968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.3153977968
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.397877081
Short name T1267
Test name
Test status
Simulation time 2597598937 ps
CPU time 10.5 seconds
Started Jun 04 01:19:19 PM PDT 24
Finished Jun 04 01:19:30 PM PDT 24
Peak memory 242892 kb
Host smart-8a912ebd-c333-4834-94db-974e9a8de5d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397877081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_in
tg_err.397877081
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.4282873655
Short name T336
Test name
Test status
Simulation time 388962455 ps
CPU time 4.25 seconds
Started Jun 04 01:18:45 PM PDT 24
Finished Jun 04 01:18:51 PM PDT 24
Peak memory 230088 kb
Host smart-b9689cd4-1eec-4ce2-ae75-3349d271caaa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282873655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.4282873655
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.565129655
Short name T374
Test name
Test status
Simulation time 132891560 ps
CPU time 6.49 seconds
Started Jun 04 01:18:46 PM PDT 24
Finished Jun 04 01:18:54 PM PDT 24
Peak memory 237136 kb
Host smart-6d353de7-8feb-42b3-8a26-466de0359102
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565129655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_b
ash.565129655
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2768433711
Short name T317
Test name
Test status
Simulation time 83047423 ps
CPU time 2.07 seconds
Started Jun 04 01:18:45 PM PDT 24
Finished Jun 04 01:18:49 PM PDT 24
Peak memory 237124 kb
Host smart-0f51f3d9-f9a1-4462-ab63-168d77e929bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768433711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r
eset.2768433711
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.531744745
Short name T1293
Test name
Test status
Simulation time 212313478 ps
CPU time 4.39 seconds
Started Jun 04 01:18:47 PM PDT 24
Finished Jun 04 01:18:52 PM PDT 24
Peak memory 245692 kb
Host smart-8f6a9f1d-c5ef-41df-9296-e586424ac74a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531744745 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.531744745
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1143091642
Short name T1243
Test name
Test status
Simulation time 76374169 ps
CPU time 1.51 seconds
Started Jun 04 01:18:45 PM PDT 24
Finished Jun 04 01:18:48 PM PDT 24
Peak memory 239000 kb
Host smart-37b50d95-9477-429b-8334-8ca80336dca0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143091642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.1143091642
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2397260941
Short name T1282
Test name
Test status
Simulation time 151035178 ps
CPU time 1.53 seconds
Started Jun 04 01:18:47 PM PDT 24
Finished Jun 04 01:18:49 PM PDT 24
Peak memory 228860 kb
Host smart-f7faa0a6-e032-4e06-bcd6-56975adaf4bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397260941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.2397260941
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2972726141
Short name T1222
Test name
Test status
Simulation time 548191183 ps
CPU time 1.4 seconds
Started Jun 04 01:18:45 PM PDT 24
Finished Jun 04 01:18:48 PM PDT 24
Peak memory 228744 kb
Host smart-43113251-dd1a-4278-9f18-0904916156e7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972726141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.2972726141
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3780137811
Short name T1216
Test name
Test status
Simulation time 552522627 ps
CPU time 1.52 seconds
Started Jun 04 01:18:44 PM PDT 24
Finished Jun 04 01:18:46 PM PDT 24
Peak memory 230032 kb
Host smart-f660662a-3ef7-4a24-966e-4a3ec7de0744
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780137811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.3780137811
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1049809895
Short name T326
Test name
Test status
Simulation time 156566291 ps
CPU time 2.78 seconds
Started Jun 04 01:18:44 PM PDT 24
Finished Jun 04 01:18:48 PM PDT 24
Peak memory 238304 kb
Host smart-0730b385-38b4-40b4-8150-6cbcccdaaab8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049809895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.1049809895
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.998162118
Short name T1223
Test name
Test status
Simulation time 80853558 ps
CPU time 5.46 seconds
Started Jun 04 01:18:45 PM PDT 24
Finished Jun 04 01:18:52 PM PDT 24
Peak memory 245476 kb
Host smart-7799e74c-bb14-47a8-a08c-cb9948161b84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998162118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.998162118
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.3793453745
Short name T1322
Test name
Test status
Simulation time 72135153 ps
CPU time 1.41 seconds
Started Jun 04 01:19:17 PM PDT 24
Finished Jun 04 01:19:19 PM PDT 24
Peak memory 228944 kb
Host smart-840c4e60-413e-45fd-98fe-9f18a713cddf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793453745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.3793453745
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.3325144484
Short name T1301
Test name
Test status
Simulation time 81917636 ps
CPU time 1.5 seconds
Started Jun 04 01:19:18 PM PDT 24
Finished Jun 04 01:19:21 PM PDT 24
Peak memory 230168 kb
Host smart-e4ff994d-716c-4e9c-93ab-9d336d317cbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325144484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.3325144484
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.1430888010
Short name T1326
Test name
Test status
Simulation time 41562346 ps
CPU time 1.42 seconds
Started Jun 04 01:19:17 PM PDT 24
Finished Jun 04 01:19:19 PM PDT 24
Peak memory 229264 kb
Host smart-f2f9081b-a719-4ad2-899c-e42af52068fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430888010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.1430888010
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.2023848924
Short name T1260
Test name
Test status
Simulation time 89175373 ps
CPU time 1.47 seconds
Started Jun 04 01:19:17 PM PDT 24
Finished Jun 04 01:19:20 PM PDT 24
Peak memory 229228 kb
Host smart-e723878f-4b00-4c41-9d96-568ac4df1396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023848924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.2023848924
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.4127035862
Short name T1206
Test name
Test status
Simulation time 72529139 ps
CPU time 1.42 seconds
Started Jun 04 01:19:17 PM PDT 24
Finished Jun 04 01:19:19 PM PDT 24
Peak memory 228976 kb
Host smart-76bdd377-cade-4ede-aacb-ce9405e328b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127035862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.4127035862
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.1811926414
Short name T1309
Test name
Test status
Simulation time 65178922 ps
CPU time 1.38 seconds
Started Jun 04 01:19:18 PM PDT 24
Finished Jun 04 01:19:20 PM PDT 24
Peak memory 228944 kb
Host smart-9c2e1749-47db-48cb-9b91-ee87d958486e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811926414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.1811926414
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.1319525476
Short name T1284
Test name
Test status
Simulation time 42213754 ps
CPU time 1.41 seconds
Started Jun 04 01:19:17 PM PDT 24
Finished Jun 04 01:19:20 PM PDT 24
Peak memory 228960 kb
Host smart-20cb035c-a66c-4456-a49a-674b02a3ba4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319525476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.1319525476
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.3147011090
Short name T1299
Test name
Test status
Simulation time 77618065 ps
CPU time 1.34 seconds
Started Jun 04 01:19:24 PM PDT 24
Finished Jun 04 01:19:26 PM PDT 24
Peak memory 229000 kb
Host smart-c0b90aa1-b357-498d-a74e-e9d8d5412c12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147011090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.3147011090
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.3833144819
Short name T1308
Test name
Test status
Simulation time 55396819 ps
CPU time 1.53 seconds
Started Jun 04 01:19:24 PM PDT 24
Finished Jun 04 01:19:26 PM PDT 24
Peak memory 228888 kb
Host smart-a5c1d941-5c0c-40c4-965e-d7d053056430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833144819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.3833144819
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1983902219
Short name T1276
Test name
Test status
Simulation time 145160282 ps
CPU time 1.37 seconds
Started Jun 04 01:19:24 PM PDT 24
Finished Jun 04 01:19:27 PM PDT 24
Peak memory 229224 kb
Host smart-a8c06818-1e48-4022-8a64-df43a65b6298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983902219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.1983902219
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2507333968
Short name T1313
Test name
Test status
Simulation time 2513751771 ps
CPU time 8.76 seconds
Started Jun 04 01:18:47 PM PDT 24
Finished Jun 04 01:18:57 PM PDT 24
Peak memory 237280 kb
Host smart-fc6a8c5a-3ed7-466a-9cd0-c55beb5c3554
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507333968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.2507333968
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.3895498190
Short name T1232
Test name
Test status
Simulation time 1329752889 ps
CPU time 8.54 seconds
Started Jun 04 01:18:45 PM PDT 24
Finished Jun 04 01:18:55 PM PDT 24
Peak memory 237196 kb
Host smart-e7065e18-137f-42c4-ba98-8f8e8b7d5bc4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895498190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.3895498190
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.623438303
Short name T325
Test name
Test status
Simulation time 73491915 ps
CPU time 1.98 seconds
Started Jun 04 01:18:45 PM PDT 24
Finished Jun 04 01:18:49 PM PDT 24
Peak memory 237144 kb
Host smart-23f80751-8c46-473c-bfb4-44ce9c1feb22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623438303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_re
set.623438303
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.694316153
Short name T278
Test name
Test status
Simulation time 71364179 ps
CPU time 2.24 seconds
Started Jun 04 01:18:46 PM PDT 24
Finished Jun 04 01:18:50 PM PDT 24
Peak memory 244568 kb
Host smart-3123eacc-0618-47d3-9f90-cf43453fa4fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694316153 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.694316153
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.616427933
Short name T322
Test name
Test status
Simulation time 47083252 ps
CPU time 1.87 seconds
Started Jun 04 01:18:45 PM PDT 24
Finished Jun 04 01:18:49 PM PDT 24
Peak memory 238296 kb
Host smart-9d392a7f-4dfe-400b-8425-7b5f21e9aba9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616427933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.616427933
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.2998549096
Short name T1235
Test name
Test status
Simulation time 37054436 ps
CPU time 1.39 seconds
Started Jun 04 01:18:45 PM PDT 24
Finished Jun 04 01:18:48 PM PDT 24
Peak memory 228980 kb
Host smart-1accbe85-297b-43d0-88ba-dca47201bd0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998549096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.2998549096
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.657792350
Short name T1215
Test name
Test status
Simulation time 137401109 ps
CPU time 1.5 seconds
Started Jun 04 01:18:45 PM PDT 24
Finished Jun 04 01:18:48 PM PDT 24
Peak memory 229952 kb
Host smart-4649f2b0-7234-4fb0-acfe-3b845b5f2bf4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657792350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl
_mem_partial_access.657792350
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2731585693
Short name T1236
Test name
Test status
Simulation time 67787531 ps
CPU time 1.37 seconds
Started Jun 04 01:18:46 PM PDT 24
Finished Jun 04 01:18:49 PM PDT 24
Peak memory 230128 kb
Host smart-1af2ce85-508a-427b-be5a-5b0600b8a4c0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731585693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.2731585693
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.3083716369
Short name T332
Test name
Test status
Simulation time 82071643 ps
CPU time 1.86 seconds
Started Jun 04 01:18:46 PM PDT 24
Finished Jun 04 01:18:49 PM PDT 24
Peak memory 238264 kb
Host smart-6bc76121-d1a4-45c7-8ebf-b81de9cf7adc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083716369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.3083716369
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3541532306
Short name T1290
Test name
Test status
Simulation time 345692573 ps
CPU time 3.8 seconds
Started Jun 04 01:18:46 PM PDT 24
Finished Jun 04 01:18:51 PM PDT 24
Peak memory 246696 kb
Host smart-3df0d082-389e-4fc8-9292-21bd050e4220
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541532306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.3541532306
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.1069802138
Short name T1255
Test name
Test status
Simulation time 87692169 ps
CPU time 1.54 seconds
Started Jun 04 01:19:29 PM PDT 24
Finished Jun 04 01:19:31 PM PDT 24
Peak memory 228880 kb
Host smart-26856e65-28d4-47f0-a245-d18e17170910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069802138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.1069802138
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.1547294564
Short name T1272
Test name
Test status
Simulation time 134133074 ps
CPU time 1.34 seconds
Started Jun 04 01:19:22 PM PDT 24
Finished Jun 04 01:19:24 PM PDT 24
Peak memory 230212 kb
Host smart-0c5594dd-c000-41bc-bf47-4ad260fe48a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547294564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.1547294564
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.1294482779
Short name T1319
Test name
Test status
Simulation time 74578874 ps
CPU time 1.4 seconds
Started Jun 04 01:19:23 PM PDT 24
Finished Jun 04 01:19:26 PM PDT 24
Peak memory 228992 kb
Host smart-4d607635-b78b-4f05-93e8-6a7ee8ad1c18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294482779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.1294482779
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.111688703
Short name T1221
Test name
Test status
Simulation time 147833758 ps
CPU time 1.45 seconds
Started Jun 04 01:19:24 PM PDT 24
Finished Jun 04 01:19:26 PM PDT 24
Peak memory 228868 kb
Host smart-485500af-a760-42dc-86c4-584991bdb9c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111688703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.111688703
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.3429547434
Short name T1274
Test name
Test status
Simulation time 152847682 ps
CPU time 1.53 seconds
Started Jun 04 01:19:24 PM PDT 24
Finished Jun 04 01:19:27 PM PDT 24
Peak memory 228864 kb
Host smart-fe0f7265-c3e3-4b39-9288-3e9ced4676fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429547434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.3429547434
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.463939110
Short name T1273
Test name
Test status
Simulation time 562891621 ps
CPU time 1.58 seconds
Started Jun 04 01:19:24 PM PDT 24
Finished Jun 04 01:19:26 PM PDT 24
Peak memory 228948 kb
Host smart-497e96b6-ffaa-42c3-8bc4-1784f2758fa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463939110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.463939110
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.1799444902
Short name T1228
Test name
Test status
Simulation time 45845579 ps
CPU time 1.47 seconds
Started Jun 04 01:19:23 PM PDT 24
Finished Jun 04 01:19:25 PM PDT 24
Peak memory 229220 kb
Host smart-fd274ebc-dcb2-4e39-8064-8f1d93a18abb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799444902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.1799444902
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.3396331004
Short name T1307
Test name
Test status
Simulation time 41694293 ps
CPU time 1.56 seconds
Started Jun 04 01:19:24 PM PDT 24
Finished Jun 04 01:19:26 PM PDT 24
Peak memory 228896 kb
Host smart-39bb7501-669b-4e1b-8ad4-c418c3096bfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396331004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.3396331004
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.1981272152
Short name T1225
Test name
Test status
Simulation time 132365423 ps
CPU time 1.5 seconds
Started Jun 04 01:19:25 PM PDT 24
Finished Jun 04 01:19:28 PM PDT 24
Peak memory 230140 kb
Host smart-4d8030f5-1bdd-4532-a1fa-a0917793a84c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981272152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.1981272152
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.2082684350
Short name T1254
Test name
Test status
Simulation time 532665028 ps
CPU time 1.46 seconds
Started Jun 04 01:19:24 PM PDT 24
Finished Jun 04 01:19:26 PM PDT 24
Peak memory 228948 kb
Host smart-639faf00-cce4-41b6-8715-940118d051c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082684350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.2082684350
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2776094381
Short name T1287
Test name
Test status
Simulation time 2557487862 ps
CPU time 10.44 seconds
Started Jun 04 01:18:53 PM PDT 24
Finished Jun 04 01:19:04 PM PDT 24
Peak memory 237328 kb
Host smart-2b468132-92e7-4303-a5ae-252df695d45d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776094381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.2776094381
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.673648836
Short name T1320
Test name
Test status
Simulation time 1006032838 ps
CPU time 11.91 seconds
Started Jun 04 01:18:54 PM PDT 24
Finished Jun 04 01:19:07 PM PDT 24
Peak memory 230056 kb
Host smart-93583f6e-68b6-4f19-a2cf-5819269745d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673648836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_b
ash.673648836
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.3355678021
Short name T316
Test name
Test status
Simulation time 968791435 ps
CPU time 2.43 seconds
Started Jun 04 01:18:51 PM PDT 24
Finished Jun 04 01:18:54 PM PDT 24
Peak memory 238428 kb
Host smart-2d060846-91bb-4338-8a6a-9b38db0f6368
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355678021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.3355678021
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.974128021
Short name T1245
Test name
Test status
Simulation time 1079633231 ps
CPU time 3.03 seconds
Started Jun 04 01:18:53 PM PDT 24
Finished Jun 04 01:18:57 PM PDT 24
Peak memory 244740 kb
Host smart-adaee941-8cee-4646-a070-93eb31b06373
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974128021 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.974128021
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.1720947101
Short name T327
Test name
Test status
Simulation time 86118548 ps
CPU time 1.76 seconds
Started Jun 04 01:18:53 PM PDT 24
Finished Jun 04 01:18:56 PM PDT 24
Peak memory 239760 kb
Host smart-3c8e04ca-2899-4d90-bddc-842b5799b648
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720947101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.1720947101
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1589693966
Short name T1278
Test name
Test status
Simulation time 159946576 ps
CPU time 1.42 seconds
Started Jun 04 01:18:46 PM PDT 24
Finished Jun 04 01:18:49 PM PDT 24
Peak memory 228916 kb
Host smart-79eb82be-854e-4f46-8a33-de15cedb7d1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589693966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.1589693966
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.905292194
Short name T1256
Test name
Test status
Simulation time 43809073 ps
CPU time 1.45 seconds
Started Jun 04 01:18:53 PM PDT 24
Finished Jun 04 01:18:55 PM PDT 24
Peak memory 228840 kb
Host smart-d5d1d762-4a68-4232-8cca-b31a8f82755e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905292194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl
_mem_partial_access.905292194
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.1466913834
Short name T1275
Test name
Test status
Simulation time 132934570 ps
CPU time 1.34 seconds
Started Jun 04 01:18:45 PM PDT 24
Finished Jun 04 01:18:48 PM PDT 24
Peak memory 229972 kb
Host smart-db7d6810-561f-442e-86e5-cfdd965dc689
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466913834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.1466913834
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.1733632911
Short name T1249
Test name
Test status
Simulation time 105565986 ps
CPU time 2.86 seconds
Started Jun 04 01:18:53 PM PDT 24
Finished Jun 04 01:18:57 PM PDT 24
Peak memory 237372 kb
Host smart-cc671cb7-0af7-4cc7-bfd2-a4ad85232bfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733632911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.1733632911
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3762135464
Short name T1220
Test name
Test status
Simulation time 97472824 ps
CPU time 3.97 seconds
Started Jun 04 01:18:46 PM PDT 24
Finished Jun 04 01:18:51 PM PDT 24
Peak memory 245988 kb
Host smart-4ba07d13-6489-467c-b6fe-ce2a3c9e0a84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762135464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.3762135464
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3297077391
Short name T359
Test name
Test status
Simulation time 1293398753 ps
CPU time 10.69 seconds
Started Jun 04 01:18:45 PM PDT 24
Finished Jun 04 01:18:57 PM PDT 24
Peak memory 238356 kb
Host smart-2f78cd7e-c48b-42e7-982f-d8eb2908e99b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297077391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in
tg_err.3297077391
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.996867762
Short name T1252
Test name
Test status
Simulation time 71142405 ps
CPU time 1.41 seconds
Started Jun 04 01:19:24 PM PDT 24
Finished Jun 04 01:19:26 PM PDT 24
Peak memory 229192 kb
Host smart-353d2db7-15f8-4bd4-909f-95b044dbe38e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996867762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.996867762
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.1512315865
Short name T1213
Test name
Test status
Simulation time 68013099 ps
CPU time 1.46 seconds
Started Jun 04 01:19:24 PM PDT 24
Finished Jun 04 01:19:26 PM PDT 24
Peak memory 230144 kb
Host smart-5eefde96-4c24-46a6-ba4e-17eb79d99bc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512315865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.1512315865
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2877082802
Short name T1250
Test name
Test status
Simulation time 41142908 ps
CPU time 1.37 seconds
Started Jun 04 01:19:23 PM PDT 24
Finished Jun 04 01:19:25 PM PDT 24
Peak memory 229268 kb
Host smart-a56a8453-ab71-4a8d-8333-f6646efcb6b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877082802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.2877082802
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.2425618083
Short name T1291
Test name
Test status
Simulation time 526647258 ps
CPU time 1.58 seconds
Started Jun 04 01:19:25 PM PDT 24
Finished Jun 04 01:19:27 PM PDT 24
Peak memory 229236 kb
Host smart-121ae3bf-8b70-42cf-86d4-f48ff3c7e652
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425618083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.2425618083
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.679495141
Short name T1261
Test name
Test status
Simulation time 564451783 ps
CPU time 2.04 seconds
Started Jun 04 01:19:25 PM PDT 24
Finished Jun 04 01:19:28 PM PDT 24
Peak memory 229224 kb
Host smart-1b3537ee-ecba-47d7-b496-89952c55a1b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679495141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.679495141
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.983046977
Short name T1231
Test name
Test status
Simulation time 142690264 ps
CPU time 1.51 seconds
Started Jun 04 01:19:23 PM PDT 24
Finished Jun 04 01:19:25 PM PDT 24
Peak memory 228976 kb
Host smart-2a713003-c08f-4ca1-a9a4-0deda20529a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983046977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.983046977
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.1280388027
Short name T1217
Test name
Test status
Simulation time 43683560 ps
CPU time 1.51 seconds
Started Jun 04 01:19:26 PM PDT 24
Finished Jun 04 01:19:29 PM PDT 24
Peak memory 229228 kb
Host smart-cc5fb253-2f01-40a4-b12f-df193ece97bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280388027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.1280388027
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.908542303
Short name T1265
Test name
Test status
Simulation time 91989282 ps
CPU time 1.44 seconds
Started Jun 04 01:19:24 PM PDT 24
Finished Jun 04 01:19:26 PM PDT 24
Peak memory 228896 kb
Host smart-a161b89d-2c69-4f0e-8197-566292f23408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908542303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.908542303
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2368871817
Short name T1333
Test name
Test status
Simulation time 515179267 ps
CPU time 1.98 seconds
Started Jun 04 01:19:26 PM PDT 24
Finished Jun 04 01:19:29 PM PDT 24
Peak memory 228880 kb
Host smart-ed00b541-91f7-41c9-9b75-9fb1ac92565c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368871817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.2368871817
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3290868052
Short name T1219
Test name
Test status
Simulation time 74869612 ps
CPU time 1.44 seconds
Started Jun 04 01:19:32 PM PDT 24
Finished Jun 04 01:19:35 PM PDT 24
Peak memory 228920 kb
Host smart-de78d71f-e95e-49c4-b6d6-58ada77d8d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290868052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3290868052
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.192153056
Short name T1304
Test name
Test status
Simulation time 76776210 ps
CPU time 2.33 seconds
Started Jun 04 01:18:54 PM PDT 24
Finished Jun 04 01:18:57 PM PDT 24
Peak memory 238484 kb
Host smart-74035003-14fa-4f98-bf5e-92ed08c85b1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192153056 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.192153056
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.2511784208
Short name T318
Test name
Test status
Simulation time 42701078 ps
CPU time 1.63 seconds
Started Jun 04 01:18:55 PM PDT 24
Finished Jun 04 01:18:58 PM PDT 24
Peak memory 238344 kb
Host smart-95c69035-9538-4753-8df0-8467442b67e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511784208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.2511784208
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3839296201
Short name T1227
Test name
Test status
Simulation time 132920352 ps
CPU time 1.52 seconds
Started Jun 04 01:18:52 PM PDT 24
Finished Jun 04 01:18:55 PM PDT 24
Peak memory 230192 kb
Host smart-f6e9646d-3226-4f28-a79b-f42a887ff0d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839296201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.3839296201
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.2871067736
Short name T1288
Test name
Test status
Simulation time 87228087 ps
CPU time 1.97 seconds
Started Jun 04 01:18:54 PM PDT 24
Finished Jun 04 01:18:57 PM PDT 24
Peak memory 238424 kb
Host smart-bc1ed938-6bf9-4361-a66b-c3ef5fff59fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871067736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.2871067736
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.771074033
Short name T1226
Test name
Test status
Simulation time 118043133 ps
CPU time 2.84 seconds
Started Jun 04 01:18:55 PM PDT 24
Finished Jun 04 01:18:59 PM PDT 24
Peak memory 238436 kb
Host smart-fa765faf-edc7-4d1a-86d5-5c36e23911c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771074033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.771074033
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.1371650116
Short name T364
Test name
Test status
Simulation time 1286419176 ps
CPU time 11.97 seconds
Started Jun 04 01:18:53 PM PDT 24
Finished Jun 04 01:19:06 PM PDT 24
Peak memory 242640 kb
Host smart-425df3c4-b772-4046-b7e6-5141228e1901
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371650116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.1371650116
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.176270726
Short name T1239
Test name
Test status
Simulation time 178634245 ps
CPU time 2.67 seconds
Started Jun 04 01:18:52 PM PDT 24
Finished Jun 04 01:18:55 PM PDT 24
Peak memory 246592 kb
Host smart-536df19d-e2e4-47f5-ab93-30b761c9d790
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176270726 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.176270726
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.3831196721
Short name T1271
Test name
Test status
Simulation time 38448222 ps
CPU time 1.6 seconds
Started Jun 04 01:18:52 PM PDT 24
Finished Jun 04 01:18:54 PM PDT 24
Peak memory 238336 kb
Host smart-cd647cd2-7fb7-451c-a8d1-e42730dab04c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831196721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.3831196721
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2889268908
Short name T1296
Test name
Test status
Simulation time 129235852 ps
CPU time 1.53 seconds
Started Jun 04 01:18:53 PM PDT 24
Finished Jun 04 01:18:55 PM PDT 24
Peak memory 228952 kb
Host smart-4358a891-156d-4a28-9db3-2c89c3c0176c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889268908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.2889268908
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3158176609
Short name T329
Test name
Test status
Simulation time 701407878 ps
CPU time 2.49 seconds
Started Jun 04 01:18:55 PM PDT 24
Finished Jun 04 01:18:59 PM PDT 24
Peak memory 238264 kb
Host smart-ef22b16b-f89f-4156-8146-149109478ce0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158176609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.3158176609
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1794488552
Short name T1240
Test name
Test status
Simulation time 90946464 ps
CPU time 3.2 seconds
Started Jun 04 01:18:56 PM PDT 24
Finished Jun 04 01:19:00 PM PDT 24
Peak memory 238444 kb
Host smart-9240900d-dd9f-4eb1-995b-9400189ba043
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794488552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.1794488552
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.472805946
Short name T363
Test name
Test status
Simulation time 647027534 ps
CPU time 10.57 seconds
Started Jun 04 01:18:54 PM PDT 24
Finished Jun 04 01:19:06 PM PDT 24
Peak memory 238264 kb
Host smart-9c06c97d-7893-4bff-a924-05312797f303
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472805946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_int
g_err.472805946
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1974229709
Short name T375
Test name
Test status
Simulation time 106497725 ps
CPU time 1.98 seconds
Started Jun 04 01:18:56 PM PDT 24
Finished Jun 04 01:18:59 PM PDT 24
Peak memory 246264 kb
Host smart-b51b65ac-7856-41b8-bfe4-e4ecbe39b657
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974229709 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.1974229709
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.1250108048
Short name T1233
Test name
Test status
Simulation time 153044944 ps
CPU time 1.63 seconds
Started Jun 04 01:18:55 PM PDT 24
Finished Jun 04 01:18:58 PM PDT 24
Peak memory 238552 kb
Host smart-a18e3fff-421c-4afe-bc42-63f5de6d4b0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250108048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.1250108048
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.3640796849
Short name T1210
Test name
Test status
Simulation time 134304403 ps
CPU time 1.41 seconds
Started Jun 04 01:18:54 PM PDT 24
Finished Jun 04 01:18:56 PM PDT 24
Peak memory 230160 kb
Host smart-9b729c70-a16c-4db4-823f-ac3264e9a96d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640796849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.3640796849
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.561805
Short name T1298
Test name
Test status
Simulation time 70288459 ps
CPU time 2.28 seconds
Started Jun 04 01:18:53 PM PDT 24
Finished Jun 04 01:18:57 PM PDT 24
Peak memory 237520 kb
Host smart-896922ca-0d07-4568-9b8d-a7a6bdb1d12a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_
same_csr_outstanding.561805
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.269947871
Short name T1268
Test name
Test status
Simulation time 203803802 ps
CPU time 3.89 seconds
Started Jun 04 01:18:53 PM PDT 24
Finished Jun 04 01:18:58 PM PDT 24
Peak memory 246472 kb
Host smart-858ed91a-0ff9-4092-b8b7-f8c465ec46e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269947871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.269947871
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1521375671
Short name T360
Test name
Test status
Simulation time 2261313938 ps
CPU time 21.11 seconds
Started Jun 04 01:18:56 PM PDT 24
Finished Jun 04 01:19:18 PM PDT 24
Peak memory 238408 kb
Host smart-e9ce9950-eeb8-4995-9fc2-bdc5214bc97a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521375671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in
tg_err.1521375671
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2515532662
Short name T285
Test name
Test status
Simulation time 226585723 ps
CPU time 3.08 seconds
Started Jun 04 01:19:02 PM PDT 24
Finished Jun 04 01:19:06 PM PDT 24
Peak memory 238624 kb
Host smart-e0d3a19a-623f-4d8d-b0ce-38232343fa90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515532662 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.2515532662
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3446486352
Short name T1310
Test name
Test status
Simulation time 41131455 ps
CPU time 1.63 seconds
Started Jun 04 01:18:52 PM PDT 24
Finished Jun 04 01:18:55 PM PDT 24
Peak memory 239272 kb
Host smart-d1030b17-ad89-4f0f-addd-147809a74735
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446486352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.3446486352
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.253906037
Short name T1258
Test name
Test status
Simulation time 603294396 ps
CPU time 2.07 seconds
Started Jun 04 01:18:53 PM PDT 24
Finished Jun 04 01:18:56 PM PDT 24
Peak memory 230188 kb
Host smart-ee94e0a4-eef3-4819-9e4b-89471e279c29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253906037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.253906037
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2579112459
Short name T330
Test name
Test status
Simulation time 272931701 ps
CPU time 2.41 seconds
Started Jun 04 01:19:06 PM PDT 24
Finished Jun 04 01:19:08 PM PDT 24
Peak memory 237452 kb
Host smart-b211ed02-214e-4352-9671-25448f567604
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579112459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.2579112459
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.4274936006
Short name T1277
Test name
Test status
Simulation time 257069675 ps
CPU time 4 seconds
Started Jun 04 01:18:56 PM PDT 24
Finished Jun 04 01:19:01 PM PDT 24
Peak memory 245980 kb
Host smart-83c139b9-e276-4f95-8a38-d4932b921954
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274936006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.4274936006
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1268573680
Short name T1314
Test name
Test status
Simulation time 1626532885 ps
CPU time 3.85 seconds
Started Jun 04 01:19:04 PM PDT 24
Finished Jun 04 01:19:09 PM PDT 24
Peak memory 246628 kb
Host smart-2dc58d9d-1b80-4872-a0c5-bd07b9a8ec35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268573680 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.1268573680
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.257772679
Short name T312
Test name
Test status
Simulation time 46781878 ps
CPU time 1.6 seconds
Started Jun 04 01:18:59 PM PDT 24
Finished Jun 04 01:19:01 PM PDT 24
Peak memory 239500 kb
Host smart-203132dc-6c3d-4158-b6ae-183c1d9e3142
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257772679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.257772679
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.980198261
Short name T1218
Test name
Test status
Simulation time 535592358 ps
CPU time 2.11 seconds
Started Jun 04 01:19:02 PM PDT 24
Finished Jun 04 01:19:05 PM PDT 24
Peak memory 230192 kb
Host smart-990e7d42-2042-42f4-872f-6895ad09bfa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980198261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.980198261
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.1847076885
Short name T1318
Test name
Test status
Simulation time 89439039 ps
CPU time 2.51 seconds
Started Jun 04 01:19:03 PM PDT 24
Finished Jun 04 01:19:07 PM PDT 24
Peak memory 237624 kb
Host smart-8e203c3e-9ca9-43fc-86c5-3ca7e6ac2c2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847076885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.1847076885
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1890202151
Short name T1246
Test name
Test status
Simulation time 164167045 ps
CPU time 6.06 seconds
Started Jun 04 01:19:02 PM PDT 24
Finished Jun 04 01:19:09 PM PDT 24
Peak memory 246136 kb
Host smart-b2cc66ce-7741-469b-a7dc-318b6ec9c61a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890202151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.1890202151
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.3559611776
Short name T274
Test name
Test status
Simulation time 10204445290 ps
CPU time 24.1 seconds
Started Jun 04 01:19:00 PM PDT 24
Finished Jun 04 01:19:24 PM PDT 24
Peak memory 243328 kb
Host smart-1d2b1122-21d0-46b5-9f62-2a11e6e0e253
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559611776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.3559611776
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.1436325963
Short name T922
Test name
Test status
Simulation time 244176459 ps
CPU time 2.23 seconds
Started Jun 04 02:58:58 PM PDT 24
Finished Jun 04 02:59:00 PM PDT 24
Peak memory 240888 kb
Host smart-b55b45a4-f3bc-41e1-b37d-dd0e7ed9b6c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436325963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.1436325963
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.124819931
Short name T1107
Test name
Test status
Simulation time 1525182751 ps
CPU time 29.06 seconds
Started Jun 04 02:58:52 PM PDT 24
Finished Jun 04 02:59:22 PM PDT 24
Peak memory 249000 kb
Host smart-e63e5b0b-6545-4550-a0ed-2416bcb1f6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124819931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.124819931
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.2463838574
Short name T877
Test name
Test status
Simulation time 184879115 ps
CPU time 9.13 seconds
Started Jun 04 02:58:52 PM PDT 24
Finished Jun 04 02:59:02 PM PDT 24
Peak memory 242268 kb
Host smart-41305a87-1e18-4776-8269-dc39012aa854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463838574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.2463838574
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.179890185
Short name T160
Test name
Test status
Simulation time 13472109390 ps
CPU time 35.71 seconds
Started Jun 04 02:58:52 PM PDT 24
Finished Jun 04 02:59:28 PM PDT 24
Peak memory 242796 kb
Host smart-492e37a8-02ab-446f-b813-8543b0ab6e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179890185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.179890185
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.3463317323
Short name T32
Test name
Test status
Simulation time 461489711 ps
CPU time 4.19 seconds
Started Jun 04 02:58:50 PM PDT 24
Finished Jun 04 02:58:54 PM PDT 24
Peak memory 242340 kb
Host smart-27984e9f-0ec0-49ed-9f3c-b1f633ca3846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463317323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.3463317323
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.2653292856
Short name T1025
Test name
Test status
Simulation time 3078158121 ps
CPU time 12.49 seconds
Started Jun 04 02:58:50 PM PDT 24
Finished Jun 04 02:59:04 PM PDT 24
Peak memory 242244 kb
Host smart-7abc943b-8709-4257-9065-42ec18c95513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653292856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.2653292856
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.2891563171
Short name T762
Test name
Test status
Simulation time 1101250521 ps
CPU time 10.78 seconds
Started Jun 04 02:58:48 PM PDT 24
Finished Jun 04 02:59:00 PM PDT 24
Peak memory 242760 kb
Host smart-2513131c-404f-4457-8f37-017b085b12ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891563171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.2891563171
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.496657813
Short name T264
Test name
Test status
Simulation time 1416089170 ps
CPU time 34.94 seconds
Started Jun 04 02:58:51 PM PDT 24
Finished Jun 04 02:59:27 PM PDT 24
Peak memory 242592 kb
Host smart-394d5fef-7a5f-4004-bcb1-7741fafee326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496657813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.496657813
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.3341135067
Short name T967
Test name
Test status
Simulation time 3806154353 ps
CPU time 19.64 seconds
Started Jun 04 02:58:48 PM PDT 24
Finished Jun 04 02:59:09 PM PDT 24
Peak memory 242328 kb
Host smart-af829bd6-1dbc-451d-adbf-5612e9360d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341135067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.3341135067
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.3421615606
Short name T997
Test name
Test status
Simulation time 604941800 ps
CPU time 18.46 seconds
Started Jun 04 02:58:49 PM PDT 24
Finished Jun 04 02:59:08 PM PDT 24
Peak memory 248796 kb
Host smart-8f43ef23-e2bd-452c-b0c3-b815997d25a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3421615606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.3421615606
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.2000587555
Short name T759
Test name
Test status
Simulation time 640682260 ps
CPU time 18.23 seconds
Started Jun 04 02:58:44 PM PDT 24
Finished Jun 04 02:59:03 PM PDT 24
Peak memory 241588 kb
Host smart-ff92290b-298c-4393-b48c-f6c9790e07df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000587555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.2000587555
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.931878498
Short name T249
Test name
Test status
Simulation time 37160948596 ps
CPU time 187.47 seconds
Started Jun 04 02:58:57 PM PDT 24
Finished Jun 04 03:02:05 PM PDT 24
Peak memory 270148 kb
Host smart-b7c8fc83-8856-4d63-8df3-71d39343e723
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931878498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.931878498
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.920040572
Short name T443
Test name
Test status
Simulation time 941789822 ps
CPU time 7.19 seconds
Started Jun 04 02:58:41 PM PDT 24
Finished Jun 04 02:58:49 PM PDT 24
Peak memory 242056 kb
Host smart-52d21e6c-dddc-4a6d-909d-e50965c87b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920040572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.920040572
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.2981269796
Short name T617
Test name
Test status
Simulation time 104409535841 ps
CPU time 300.2 seconds
Started Jun 04 02:59:05 PM PDT 24
Finished Jun 04 03:04:05 PM PDT 24
Peak memory 265556 kb
Host smart-6fcbe737-ae95-4fc9-81d8-7c774456ebbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981269796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
2981269796
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.935757539
Short name T779
Test name
Test status
Simulation time 70047718956 ps
CPU time 1008.65 seconds
Started Jun 04 02:58:59 PM PDT 24
Finished Jun 04 03:15:48 PM PDT 24
Peak memory 274568 kb
Host smart-fa217acd-fa1f-4f0c-8d18-3f64dc2f91f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935757539 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.935757539
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.855093483
Short name T822
Test name
Test status
Simulation time 100638764 ps
CPU time 1.61 seconds
Started Jun 04 02:59:05 PM PDT 24
Finished Jun 04 02:59:07 PM PDT 24
Peak memory 240788 kb
Host smart-95a1e243-7587-4596-8687-b973ad2927ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855093483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.855093483
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.1675019312
Short name T664
Test name
Test status
Simulation time 1262657150 ps
CPU time 18.84 seconds
Started Jun 04 02:58:58 PM PDT 24
Finished Jun 04 02:59:18 PM PDT 24
Peak memory 242632 kb
Host smart-40f5188c-b414-44cb-8ac3-79f2eebbc03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675019312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.1675019312
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.1811058791
Short name T63
Test name
Test status
Simulation time 250074798 ps
CPU time 3.8 seconds
Started Jun 04 02:58:59 PM PDT 24
Finished Jun 04 02:59:03 PM PDT 24
Peak memory 246976 kb
Host smart-a9ba5e2c-828d-44ac-8450-49cab4e666ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811058791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.1811058791
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.610038139
Short name T764
Test name
Test status
Simulation time 405091912 ps
CPU time 10.1 seconds
Started Jun 04 02:59:00 PM PDT 24
Finished Jun 04 02:59:10 PM PDT 24
Peak memory 242660 kb
Host smart-5befcca8-b58c-4baf-ae65-2dc5a61f3fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610038139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.610038139
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.900298279
Short name T100
Test name
Test status
Simulation time 3912209072 ps
CPU time 10.9 seconds
Started Jun 04 02:58:59 PM PDT 24
Finished Jun 04 02:59:11 PM PDT 24
Peak memory 242332 kb
Host smart-9a88f08b-04a4-486e-b467-8b3120e2998f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900298279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.900298279
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.4164543102
Short name T141
Test name
Test status
Simulation time 1195381132 ps
CPU time 19.37 seconds
Started Jun 04 02:58:57 PM PDT 24
Finished Jun 04 02:59:17 PM PDT 24
Peak memory 243764 kb
Host smart-4e9e79cf-3486-48b1-9e2d-03c63efe2908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164543102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.4164543102
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.393464919
Short name T410
Test name
Test status
Simulation time 382059197 ps
CPU time 6.61 seconds
Started Jun 04 02:59:06 PM PDT 24
Finished Jun 04 02:59:13 PM PDT 24
Peak memory 242512 kb
Host smart-52c02dd5-5ee4-4c5e-8ef8-6ea83307a54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393464919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.393464919
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.4191028630
Short name T679
Test name
Test status
Simulation time 12864200143 ps
CPU time 35.59 seconds
Started Jun 04 02:58:59 PM PDT 24
Finished Jun 04 02:59:35 PM PDT 24
Peak memory 248980 kb
Host smart-72d1e26e-80d8-45c3-b105-e8273838291e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4191028630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.4191028630
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.2509234235
Short name T365
Test name
Test status
Simulation time 572980828 ps
CPU time 8.2 seconds
Started Jun 04 02:59:06 PM PDT 24
Finished Jun 04 02:59:14 PM PDT 24
Peak memory 242508 kb
Host smart-553358e7-9bde-407c-a6d5-41429d1de439
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2509234235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.2509234235
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.1735834368
Short name T21
Test name
Test status
Simulation time 43504911640 ps
CPU time 221.08 seconds
Started Jun 04 02:59:07 PM PDT 24
Finished Jun 04 03:02:48 PM PDT 24
Peak memory 277484 kb
Host smart-5cb161a8-a96c-4d1f-9306-6f4e319e2416
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735834368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.1735834368
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.1381482311
Short name T592
Test name
Test status
Simulation time 4988834001 ps
CPU time 7.37 seconds
Started Jun 04 02:58:57 PM PDT 24
Finished Jun 04 02:59:05 PM PDT 24
Peak memory 242204 kb
Host smart-35ef4ac2-a4bd-4a7d-913d-c8d3fe16242e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381482311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.1381482311
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.606189410
Short name T380
Test name
Test status
Simulation time 108528350017 ps
CPU time 208.54 seconds
Started Jun 04 02:59:08 PM PDT 24
Finished Jun 04 03:02:37 PM PDT 24
Peak memory 260320 kb
Host smart-f4c08bfe-a9c7-4952-b7a7-9ac37dd04d4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606189410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.606189410
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.3344741933
Short name T815
Test name
Test status
Simulation time 1533669891 ps
CPU time 23.22 seconds
Started Jun 04 02:59:07 PM PDT 24
Finished Jun 04 02:59:31 PM PDT 24
Peak memory 242288 kb
Host smart-a8ad3dda-2468-4f25-8153-6620dd8e58fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344741933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.3344741933
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.143978755
Short name T417
Test name
Test status
Simulation time 78412668 ps
CPU time 1.63 seconds
Started Jun 04 03:00:02 PM PDT 24
Finished Jun 04 03:00:04 PM PDT 24
Peak memory 241084 kb
Host smart-e8d61b30-bb39-40e8-9e73-65705525d9a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143978755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.143978755
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.147174743
Short name T1143
Test name
Test status
Simulation time 1526179503 ps
CPU time 3.03 seconds
Started Jun 04 03:00:00 PM PDT 24
Finished Jun 04 03:00:04 PM PDT 24
Peak memory 248884 kb
Host smart-4347047e-24e2-4545-9884-c767202e525a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147174743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.147174743
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.564540435
Short name T557
Test name
Test status
Simulation time 1378386518 ps
CPU time 21.87 seconds
Started Jun 04 03:00:00 PM PDT 24
Finished Jun 04 03:00:23 PM PDT 24
Peak memory 242324 kb
Host smart-f30e89c4-4d5c-4dd8-b2d8-4865fb8df815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564540435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.564540435
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.3482503550
Short name T910
Test name
Test status
Simulation time 407343220 ps
CPU time 5.09 seconds
Started Jun 04 02:59:58 PM PDT 24
Finished Jun 04 03:00:04 PM PDT 24
Peak memory 242104 kb
Host smart-f80606fd-5cd9-491e-b552-114cbe8dcd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482503550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.3482503550
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.3935289806
Short name T1074
Test name
Test status
Simulation time 446814658 ps
CPU time 3.48 seconds
Started Jun 04 03:00:00 PM PDT 24
Finished Jun 04 03:00:05 PM PDT 24
Peak memory 242744 kb
Host smart-db92c324-9256-4d17-aa27-10347bbffbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935289806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.3935289806
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.1530179860
Short name T613
Test name
Test status
Simulation time 2862939355 ps
CPU time 23.23 seconds
Started Jun 04 03:00:02 PM PDT 24
Finished Jun 04 03:00:26 PM PDT 24
Peak memory 243400 kb
Host smart-3fc922e1-dfaf-4914-a0df-70c9849baf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530179860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.1530179860
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.1040119317
Short name T157
Test name
Test status
Simulation time 1451089392 ps
CPU time 29.36 seconds
Started Jun 04 03:00:00 PM PDT 24
Finished Jun 04 03:00:31 PM PDT 24
Peak memory 242252 kb
Host smart-e0e04d81-b711-48dc-b7b3-f6532e72f31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040119317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.1040119317
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.3982970604
Short name T705
Test name
Test status
Simulation time 209482436 ps
CPU time 5.83 seconds
Started Jun 04 03:00:00 PM PDT 24
Finished Jun 04 03:00:07 PM PDT 24
Peak memory 242208 kb
Host smart-900a387b-d3d8-4ed2-9da8-5589b77b8773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982970604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.3982970604
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.3220637028
Short name T697
Test name
Test status
Simulation time 5726549610 ps
CPU time 13.05 seconds
Started Jun 04 03:00:01 PM PDT 24
Finished Jun 04 03:00:15 PM PDT 24
Peak memory 248972 kb
Host smart-93abfe34-7db6-47f9-b10e-54d98cb7bec2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3220637028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.3220637028
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.1567219828
Short name T1163
Test name
Test status
Simulation time 710041745 ps
CPU time 7.56 seconds
Started Jun 04 03:00:01 PM PDT 24
Finished Jun 04 03:00:10 PM PDT 24
Peak memory 248784 kb
Host smart-3d9171ef-003b-4918-9798-97d6b6dfed16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1567219828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.1567219828
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.3266592203
Short name T1120
Test name
Test status
Simulation time 163973212 ps
CPU time 3.94 seconds
Started Jun 04 03:00:00 PM PDT 24
Finished Jun 04 03:00:04 PM PDT 24
Peak memory 242520 kb
Host smart-389449d7-8bcf-4e5d-8842-1abc46f389cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266592203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.3266592203
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.215658351
Short name T1020
Test name
Test status
Simulation time 8426803836 ps
CPU time 102.85 seconds
Started Jun 04 03:00:06 PM PDT 24
Finished Jun 04 03:01:49 PM PDT 24
Peak memory 281820 kb
Host smart-651e634c-bb78-4710-be7b-25f1eba9b181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215658351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.
215658351
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.2035082614
Short name T221
Test name
Test status
Simulation time 707728697846 ps
CPU time 2193.68 seconds
Started Jun 04 03:00:00 PM PDT 24
Finished Jun 04 03:36:35 PM PDT 24
Peak memory 394660 kb
Host smart-01de3fb7-8556-48f2-b6fa-7400e33cebd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035082614 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.2035082614
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.1315561243
Short name T541
Test name
Test status
Simulation time 9081878384 ps
CPU time 23.32 seconds
Started Jun 04 03:00:00 PM PDT 24
Finished Jun 04 03:00:25 PM PDT 24
Peak memory 242312 kb
Host smart-8a20e9e0-18e3-413c-8985-29ce7d31df2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315561243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.1315561243
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.2346135638
Short name T161
Test name
Test status
Simulation time 162707899 ps
CPU time 4.74 seconds
Started Jun 04 03:03:27 PM PDT 24
Finished Jun 04 03:03:34 PM PDT 24
Peak memory 242388 kb
Host smart-b549b3d3-b3a7-4ab3-b2a6-9a7d74960e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346135638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.2346135638
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.2468784966
Short name T536
Test name
Test status
Simulation time 355067399 ps
CPU time 5.04 seconds
Started Jun 04 03:03:29 PM PDT 24
Finished Jun 04 03:03:35 PM PDT 24
Peak memory 242348 kb
Host smart-85649167-d9ea-414e-b40d-b68f1ec3bee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468784966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.2468784966
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.3636890435
Short name T721
Test name
Test status
Simulation time 144170519 ps
CPU time 4.38 seconds
Started Jun 04 03:03:28 PM PDT 24
Finished Jun 04 03:03:33 PM PDT 24
Peak memory 242452 kb
Host smart-533b6b65-1666-403a-8e35-2cb967f08f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636890435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.3636890435
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.948377675
Short name T147
Test name
Test status
Simulation time 257102477 ps
CPU time 3.23 seconds
Started Jun 04 03:03:29 PM PDT 24
Finished Jun 04 03:03:33 PM PDT 24
Peak memory 242412 kb
Host smart-699a4e2b-ffb2-4ff5-8a50-164515834389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948377675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.948377675
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.693142546
Short name T854
Test name
Test status
Simulation time 200198335 ps
CPU time 5.85 seconds
Started Jun 04 03:03:38 PM PDT 24
Finished Jun 04 03:03:45 PM PDT 24
Peak memory 242136 kb
Host smart-520acd5e-4f18-43e2-86ab-c93b350ac35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693142546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.693142546
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.1633533834
Short name T768
Test name
Test status
Simulation time 214156874 ps
CPU time 4.12 seconds
Started Jun 04 03:03:36 PM PDT 24
Finished Jun 04 03:03:41 PM PDT 24
Peak memory 242704 kb
Host smart-9771ae3f-1044-4c8a-8830-19dabade7bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633533834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.1633533834
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.2813001798
Short name T625
Test name
Test status
Simulation time 465645688 ps
CPU time 5.26 seconds
Started Jun 04 03:03:38 PM PDT 24
Finished Jun 04 03:03:44 PM PDT 24
Peak memory 242340 kb
Host smart-655dd1c4-097b-42ab-a023-1906114805f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813001798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.2813001798
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.2825288175
Short name T1117
Test name
Test status
Simulation time 393440728 ps
CPU time 4.69 seconds
Started Jun 04 03:03:39 PM PDT 24
Finished Jun 04 03:03:45 PM PDT 24
Peak memory 242676 kb
Host smart-6db1fce0-9812-4083-9bea-2275f5e5c87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825288175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.2825288175
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.3358110583
Short name T551
Test name
Test status
Simulation time 441480445 ps
CPU time 3.03 seconds
Started Jun 04 03:03:43 PM PDT 24
Finished Jun 04 03:03:46 PM PDT 24
Peak memory 242188 kb
Host smart-fc31e6d6-84e8-486e-afe9-486fe14f94b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358110583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.3358110583
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.1631642945
Short name T1192
Test name
Test status
Simulation time 245353938 ps
CPU time 4.85 seconds
Started Jun 04 03:03:36 PM PDT 24
Finished Jun 04 03:03:42 PM PDT 24
Peak memory 242364 kb
Host smart-65695107-fb79-4e9c-b9d0-36d547297607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631642945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.1631642945
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.35071022
Short name T1069
Test name
Test status
Simulation time 2092947252 ps
CPU time 9.61 seconds
Started Jun 04 03:03:37 PM PDT 24
Finished Jun 04 03:03:48 PM PDT 24
Peak memory 242348 kb
Host smart-37c3e868-f2dc-460b-b1de-ba9cb1bafa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35071022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.35071022
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.1170949044
Short name T1139
Test name
Test status
Simulation time 529896994 ps
CPU time 3.67 seconds
Started Jun 04 03:03:38 PM PDT 24
Finished Jun 04 03:03:42 PM PDT 24
Peak memory 242448 kb
Host smart-539a66fb-1add-4699-90e3-f70b9c10706d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170949044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.1170949044
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.2516643953
Short name T571
Test name
Test status
Simulation time 106657482 ps
CPU time 2.98 seconds
Started Jun 04 03:03:41 PM PDT 24
Finished Jun 04 03:03:45 PM PDT 24
Peak memory 242380 kb
Host smart-ff9985d7-b86f-47b9-a957-809b2160377b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516643953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.2516643953
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.678768968
Short name T1131
Test name
Test status
Simulation time 136307084 ps
CPU time 3.93 seconds
Started Jun 04 03:03:37 PM PDT 24
Finished Jun 04 03:03:41 PM PDT 24
Peak memory 242356 kb
Host smart-c1480e38-65d3-4de1-b9ca-f017db69b91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678768968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.678768968
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.1763270068
Short name T984
Test name
Test status
Simulation time 1240195719 ps
CPU time 3.63 seconds
Started Jun 04 03:03:36 PM PDT 24
Finished Jun 04 03:03:41 PM PDT 24
Peak memory 242160 kb
Host smart-05038447-a397-4411-8337-0187d679411b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763270068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.1763270068
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.3873637089
Short name T661
Test name
Test status
Simulation time 313307302 ps
CPU time 4.32 seconds
Started Jun 04 03:03:36 PM PDT 24
Finished Jun 04 03:03:41 PM PDT 24
Peak memory 242312 kb
Host smart-8ba795bd-3b71-4e57-aca2-d53883310509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873637089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.3873637089
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.1180441598
Short name T829
Test name
Test status
Simulation time 689900184 ps
CPU time 8.79 seconds
Started Jun 04 03:03:39 PM PDT 24
Finished Jun 04 03:03:49 PM PDT 24
Peak memory 242364 kb
Host smart-6e8a78f9-ea32-4934-ae23-aed27b06d82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180441598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.1180441598
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.568329709
Short name T793
Test name
Test status
Simulation time 192852629 ps
CPU time 4.58 seconds
Started Jun 04 03:03:40 PM PDT 24
Finished Jun 04 03:03:45 PM PDT 24
Peak memory 242728 kb
Host smart-76bd3a4b-5103-452c-9943-6a4cb1e63b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568329709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.568329709
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.4020717277
Short name T386
Test name
Test status
Simulation time 132154166 ps
CPU time 3.86 seconds
Started Jun 04 03:03:39 PM PDT 24
Finished Jun 04 03:03:44 PM PDT 24
Peak memory 242164 kb
Host smart-6e2883fd-40d4-45c2-8d21-db8e6e4c5a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020717277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.4020717277
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.1427844522
Short name T926
Test name
Test status
Simulation time 148962421 ps
CPU time 2.56 seconds
Started Jun 04 03:00:11 PM PDT 24
Finished Jun 04 03:00:14 PM PDT 24
Peak memory 241164 kb
Host smart-247d037d-ad25-46ad-8bbd-83bc6ff8ba95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427844522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.1427844522
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.2360820982
Short name T901
Test name
Test status
Simulation time 1790360034 ps
CPU time 12.2 seconds
Started Jun 04 03:00:10 PM PDT 24
Finished Jun 04 03:00:23 PM PDT 24
Peak memory 242776 kb
Host smart-9d51f920-4015-48e5-916f-988e1d7eca38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360820982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.2360820982
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.3226951943
Short name T144
Test name
Test status
Simulation time 5124113990 ps
CPU time 20.75 seconds
Started Jun 04 03:00:09 PM PDT 24
Finished Jun 04 03:00:32 PM PDT 24
Peak memory 242636 kb
Host smart-bba83df7-5568-4578-8e8b-2a35b09afeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226951943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.3226951943
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.1936354868
Short name T527
Test name
Test status
Simulation time 1633200084 ps
CPU time 22.43 seconds
Started Jun 04 03:00:09 PM PDT 24
Finished Jun 04 03:00:33 PM PDT 24
Peak memory 242420 kb
Host smart-9ef40734-7de0-4ab8-9e67-0be169eb044d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936354868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.1936354868
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.106960343
Short name T890
Test name
Test status
Simulation time 2375789270 ps
CPU time 5.47 seconds
Started Jun 04 03:00:06 PM PDT 24
Finished Jun 04 03:00:12 PM PDT 24
Peak memory 242336 kb
Host smart-8ef3f17f-1650-4197-95e0-57f8833632fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106960343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.106960343
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.310460285
Short name T1064
Test name
Test status
Simulation time 7338879788 ps
CPU time 47.87 seconds
Started Jun 04 03:00:08 PM PDT 24
Finished Jun 04 03:00:57 PM PDT 24
Peak memory 257288 kb
Host smart-8cd3296b-8019-4176-8f0c-70f0e49dcf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310460285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.310460285
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.2558603936
Short name T176
Test name
Test status
Simulation time 1736325047 ps
CPU time 23.56 seconds
Started Jun 04 03:00:07 PM PDT 24
Finished Jun 04 03:00:31 PM PDT 24
Peak memory 242884 kb
Host smart-3e0d22be-447c-4887-be25-fc5de6281553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558603936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.2558603936
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.68165018
Short name T225
Test name
Test status
Simulation time 436254090 ps
CPU time 6.11 seconds
Started Jun 04 03:00:08 PM PDT 24
Finished Jun 04 03:00:15 PM PDT 24
Peak memory 242604 kb
Host smart-249740fd-5ca2-4188-b015-fc1ae7ac3a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68165018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.68165018
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.2823291932
Short name T377
Test name
Test status
Simulation time 598997947 ps
CPU time 19.81 seconds
Started Jun 04 03:00:06 PM PDT 24
Finished Jun 04 03:00:26 PM PDT 24
Peak memory 242272 kb
Host smart-4acd57ca-5b93-4734-b995-bb0e3d737a6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2823291932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.2823291932
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.1146076959
Short name T1101
Test name
Test status
Simulation time 208972607 ps
CPU time 3.16 seconds
Started Jun 04 03:00:07 PM PDT 24
Finished Jun 04 03:00:12 PM PDT 24
Peak memory 242200 kb
Host smart-ff0456ce-bcf3-444c-90ed-b3a4eb26cbb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1146076959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.1146076959
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.3400579564
Short name T1128
Test name
Test status
Simulation time 530292841 ps
CPU time 10.61 seconds
Started Jun 04 03:00:01 PM PDT 24
Finished Jun 04 03:00:13 PM PDT 24
Peak memory 242612 kb
Host smart-209840e4-eec8-4e66-a840-077d1aa470e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400579564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.3400579564
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.1532782144
Short name T504
Test name
Test status
Simulation time 25675882572 ps
CPU time 140.96 seconds
Started Jun 04 03:00:08 PM PDT 24
Finished Jun 04 03:02:30 PM PDT 24
Peak memory 275816 kb
Host smart-6bd389f4-e7b3-4049-aef3-4288e705f1b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532782144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.1532782144
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.2063270886
Short name T1057
Test name
Test status
Simulation time 547737623675 ps
CPU time 1372.35 seconds
Started Jun 04 03:00:07 PM PDT 24
Finished Jun 04 03:23:01 PM PDT 24
Peak memory 299776 kb
Host smart-a751140e-457f-4866-a227-84b286b43072
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063270886 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.2063270886
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.1474897098
Short name T821
Test name
Test status
Simulation time 4258655466 ps
CPU time 24.04 seconds
Started Jun 04 03:00:07 PM PDT 24
Finished Jun 04 03:00:32 PM PDT 24
Peak memory 243596 kb
Host smart-dc9f5724-15b4-45b1-b323-ab0337427172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474897098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.1474897098
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.1376458080
Short name T1191
Test name
Test status
Simulation time 347196506 ps
CPU time 4.06 seconds
Started Jun 04 03:03:34 PM PDT 24
Finished Jun 04 03:03:39 PM PDT 24
Peak memory 242296 kb
Host smart-6b27d1fb-8861-4d9d-994b-1a704ac08817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376458080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.1376458080
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.1849297416
Short name T436
Test name
Test status
Simulation time 961880831 ps
CPU time 6.42 seconds
Started Jun 04 03:03:37 PM PDT 24
Finished Jun 04 03:03:44 PM PDT 24
Peak memory 242536 kb
Host smart-b79a712d-151d-48cc-9358-49378bcfadaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849297416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.1849297416
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.2255977380
Short name T817
Test name
Test status
Simulation time 591814096 ps
CPU time 5.03 seconds
Started Jun 04 03:03:37 PM PDT 24
Finished Jun 04 03:03:43 PM PDT 24
Peak memory 242388 kb
Host smart-f758c179-e3de-49d1-a3c6-38b18382b13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255977380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.2255977380
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.385340014
Short name T348
Test name
Test status
Simulation time 325609384 ps
CPU time 7.73 seconds
Started Jun 04 03:03:39 PM PDT 24
Finished Jun 04 03:03:47 PM PDT 24
Peak memory 242224 kb
Host smart-65c525e0-7068-402f-bfb8-90dc62f34449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385340014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.385340014
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.504918995
Short name T706
Test name
Test status
Simulation time 826630967 ps
CPU time 7.65 seconds
Started Jun 04 03:03:41 PM PDT 24
Finished Jun 04 03:03:49 PM PDT 24
Peak memory 242228 kb
Host smart-76271bd8-0c8e-4709-aaa5-c4cb50ec5148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504918995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.504918995
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.2923983554
Short name T1140
Test name
Test status
Simulation time 263831373 ps
CPU time 7.28 seconds
Started Jun 04 03:03:36 PM PDT 24
Finished Jun 04 03:03:44 PM PDT 24
Peak memory 242196 kb
Host smart-c0dff2e2-e438-41e5-a85d-d1bd9950a92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923983554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.2923983554
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.2438966246
Short name T84
Test name
Test status
Simulation time 581538676 ps
CPU time 4.69 seconds
Started Jun 04 03:03:37 PM PDT 24
Finished Jun 04 03:03:42 PM PDT 24
Peak memory 242452 kb
Host smart-e2f7b742-da3b-4827-a031-2b3ae5bd90ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438966246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.2438966246
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.624400324
Short name T114
Test name
Test status
Simulation time 959169701 ps
CPU time 16.3 seconds
Started Jun 04 03:03:39 PM PDT 24
Finished Jun 04 03:03:56 PM PDT 24
Peak memory 242264 kb
Host smart-a0184ccd-c1b1-4e7d-a348-a27be63fb300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624400324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.624400324
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.2738330928
Short name T1075
Test name
Test status
Simulation time 116837361 ps
CPU time 4.27 seconds
Started Jun 04 03:03:48 PM PDT 24
Finished Jun 04 03:03:55 PM PDT 24
Peak memory 242416 kb
Host smart-2cbd3349-db63-43c3-92d6-7cf8bc97d771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738330928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.2738330928
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.815325175
Short name T932
Test name
Test status
Simulation time 4599131647 ps
CPU time 14.07 seconds
Started Jun 04 03:03:46 PM PDT 24
Finished Jun 04 03:04:01 PM PDT 24
Peak memory 242324 kb
Host smart-f1ffb809-b2d8-4413-b84a-59af4e4d2d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815325175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.815325175
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.1233801500
Short name T740
Test name
Test status
Simulation time 211516464 ps
CPU time 3.83 seconds
Started Jun 04 03:03:49 PM PDT 24
Finished Jun 04 03:03:55 PM PDT 24
Peak memory 242700 kb
Host smart-3e84f19e-65ab-46b5-a74e-11d1b469a3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233801500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.1233801500
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.1877292192
Short name T346
Test name
Test status
Simulation time 11704527473 ps
CPU time 39.31 seconds
Started Jun 04 03:03:45 PM PDT 24
Finished Jun 04 03:04:25 PM PDT 24
Peak memory 242708 kb
Host smart-bea7c2b4-c2ac-4b72-97f1-7d27f375533a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877292192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.1877292192
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.4287040803
Short name T954
Test name
Test status
Simulation time 116134555 ps
CPU time 4.15 seconds
Started Jun 04 03:03:49 PM PDT 24
Finished Jun 04 03:03:55 PM PDT 24
Peak memory 242368 kb
Host smart-10b3562d-6aaf-4416-81eb-95ed58142b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287040803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.4287040803
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.1003753291
Short name T205
Test name
Test status
Simulation time 212212371 ps
CPU time 3.82 seconds
Started Jun 04 03:03:49 PM PDT 24
Finished Jun 04 03:03:55 PM PDT 24
Peak memory 242088 kb
Host smart-fa9049ea-ab16-41d5-b918-ba74c29dabe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003753291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.1003753291
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.3214034257
Short name T838
Test name
Test status
Simulation time 114438064 ps
CPU time 3.01 seconds
Started Jun 04 03:03:46 PM PDT 24
Finished Jun 04 03:03:50 PM PDT 24
Peak memory 242356 kb
Host smart-959d65b3-7fa4-40cf-ad54-3c6af93417cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214034257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.3214034257
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.2288457944
Short name T1026
Test name
Test status
Simulation time 5840180299 ps
CPU time 17.58 seconds
Started Jun 04 03:03:45 PM PDT 24
Finished Jun 04 03:04:03 PM PDT 24
Peak memory 242244 kb
Host smart-8ca13ca4-1202-4404-80d4-5ba6a8e776f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288457944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.2288457944
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.2957492594
Short name T848
Test name
Test status
Simulation time 141683074 ps
CPU time 3.74 seconds
Started Jun 04 03:03:46 PM PDT 24
Finished Jun 04 03:03:51 PM PDT 24
Peak memory 242472 kb
Host smart-3ac3799f-723c-449a-accc-468486f923d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957492594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.2957492594
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.2389530442
Short name T184
Test name
Test status
Simulation time 211962233 ps
CPU time 4.66 seconds
Started Jun 04 03:03:48 PM PDT 24
Finished Jun 04 03:03:54 PM PDT 24
Peak memory 242532 kb
Host smart-02744469-1a1d-482d-afeb-5ab8ce381673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389530442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.2389530442
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.1136167833
Short name T1108
Test name
Test status
Simulation time 61565207 ps
CPU time 2.07 seconds
Started Jun 04 03:00:16 PM PDT 24
Finished Jun 04 03:00:19 PM PDT 24
Peak memory 241184 kb
Host smart-06731ba7-f1d7-414f-ab39-8822ed4e208b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136167833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.1136167833
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.3964238600
Short name T1113
Test name
Test status
Simulation time 1648304852 ps
CPU time 18.26 seconds
Started Jun 04 03:00:12 PM PDT 24
Finished Jun 04 03:00:31 PM PDT 24
Peak memory 248940 kb
Host smart-3b6c5333-dd2a-4c68-80d9-bbdae21c6848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964238600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.3964238600
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.1839886701
Short name T427
Test name
Test status
Simulation time 1443475556 ps
CPU time 19.36 seconds
Started Jun 04 03:00:10 PM PDT 24
Finished Jun 04 03:00:31 PM PDT 24
Peak memory 242364 kb
Host smart-e33f8903-68f9-45cd-8881-d57f41f65b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839886701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.1839886701
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.3005994784
Short name T563
Test name
Test status
Simulation time 865395359 ps
CPU time 7.84 seconds
Started Jun 04 03:00:11 PM PDT 24
Finished Jun 04 03:00:20 PM PDT 24
Peak memory 242488 kb
Host smart-717f8d87-7602-47ba-b075-4d9d5028b879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005994784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.3005994784
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.3462401832
Short name T201
Test name
Test status
Simulation time 115557697 ps
CPU time 3.44 seconds
Started Jun 04 03:00:07 PM PDT 24
Finished Jun 04 03:00:12 PM PDT 24
Peak memory 242492 kb
Host smart-1f6b00fb-c96a-4163-9923-0b3ecd8d574b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462401832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.3462401832
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.3066509494
Short name T1056
Test name
Test status
Simulation time 8422968976 ps
CPU time 32.82 seconds
Started Jun 04 03:00:08 PM PDT 24
Finished Jun 04 03:00:42 PM PDT 24
Peak memory 248932 kb
Host smart-0a502342-6c6b-40b0-afc7-f084b67adbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066509494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.3066509494
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.1459730936
Short name T985
Test name
Test status
Simulation time 1858997251 ps
CPU time 23.13 seconds
Started Jun 04 03:00:10 PM PDT 24
Finished Jun 04 03:00:35 PM PDT 24
Peak memory 242300 kb
Host smart-5e6a6f7b-e860-4993-9042-717175ddd2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459730936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.1459730936
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.2632167208
Short name T259
Test name
Test status
Simulation time 131575466 ps
CPU time 3.71 seconds
Started Jun 04 03:00:11 PM PDT 24
Finished Jun 04 03:00:15 PM PDT 24
Peak memory 242196 kb
Host smart-5ddf3b8e-e3c1-4af1-885d-662146ee2dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632167208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.2632167208
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.1609853045
Short name T720
Test name
Test status
Simulation time 735397075 ps
CPU time 11.98 seconds
Started Jun 04 03:00:08 PM PDT 24
Finished Jun 04 03:00:20 PM PDT 24
Peak memory 242444 kb
Host smart-2aa68a7c-2845-43c7-a5ee-296ef09b573a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1609853045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.1609853045
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.2564853253
Short name T368
Test name
Test status
Simulation time 479705054 ps
CPU time 8.73 seconds
Started Jun 04 03:00:14 PM PDT 24
Finished Jun 04 03:00:25 PM PDT 24
Peak memory 242300 kb
Host smart-5831612e-2802-4e3a-b42c-a1b8278aa3b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2564853253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2564853253
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.119318172
Short name T570
Test name
Test status
Simulation time 61267221702 ps
CPU time 961.13 seconds
Started Jun 04 03:00:15 PM PDT 24
Finished Jun 04 03:16:18 PM PDT 24
Peak memory 295928 kb
Host smart-50956bf6-c98e-4bd3-b781-01dbb9bf12e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119318172 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.119318172
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.1093206281
Short name T742
Test name
Test status
Simulation time 6607213562 ps
CPU time 35.56 seconds
Started Jun 04 03:00:14 PM PDT 24
Finished Jun 04 03:00:51 PM PDT 24
Peak memory 248964 kb
Host smart-7980596a-1ca3-4fe6-8401-bf70e7fb16b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093206281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.1093206281
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.1335631260
Short name T629
Test name
Test status
Simulation time 2002468910 ps
CPU time 6.06 seconds
Started Jun 04 03:03:46 PM PDT 24
Finished Jun 04 03:03:53 PM PDT 24
Peak memory 242312 kb
Host smart-4acc8140-b991-4913-a1f3-8f868a3ec12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335631260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.1335631260
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.2101490610
Short name T863
Test name
Test status
Simulation time 377620187 ps
CPU time 4.19 seconds
Started Jun 04 03:03:48 PM PDT 24
Finished Jun 04 03:03:55 PM PDT 24
Peak memory 242468 kb
Host smart-f3f5c834-6556-4773-a7e3-18e8f77cc975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101490610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.2101490610
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.2466679513
Short name T24
Test name
Test status
Simulation time 441807467 ps
CPU time 5.23 seconds
Started Jun 04 03:03:47 PM PDT 24
Finished Jun 04 03:03:54 PM PDT 24
Peak memory 242344 kb
Host smart-febe0699-fd57-47dc-9145-5910c1dd0647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466679513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.2466679513
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.729694959
Short name T560
Test name
Test status
Simulation time 1263507166 ps
CPU time 30.28 seconds
Started Jun 04 03:03:50 PM PDT 24
Finished Jun 04 03:04:22 PM PDT 24
Peak memory 242376 kb
Host smart-af9c7806-7ab5-4ec5-a007-92e994255ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729694959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.729694959
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.2990688429
Short name T414
Test name
Test status
Simulation time 94272055 ps
CPU time 2.63 seconds
Started Jun 04 03:03:46 PM PDT 24
Finished Jun 04 03:03:49 PM PDT 24
Peak memory 242012 kb
Host smart-677981b2-f72d-4678-b1f6-0eaf2a652516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990688429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.2990688429
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.3588284952
Short name T916
Test name
Test status
Simulation time 409445433 ps
CPU time 11.28 seconds
Started Jun 04 03:03:48 PM PDT 24
Finished Jun 04 03:04:01 PM PDT 24
Peak memory 242284 kb
Host smart-638d676a-b203-43e8-b721-f7a3ce457a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588284952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.3588284952
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.4036723595
Short name T1007
Test name
Test status
Simulation time 284059223 ps
CPU time 4.62 seconds
Started Jun 04 03:03:49 PM PDT 24
Finished Jun 04 03:03:56 PM PDT 24
Peak memory 242696 kb
Host smart-cc2939b4-7b0b-48bb-86fe-0138ad3d6889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036723595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.4036723595
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.827098087
Short name T1038
Test name
Test status
Simulation time 555575832 ps
CPU time 18.33 seconds
Started Jun 04 03:03:46 PM PDT 24
Finished Jun 04 03:04:06 PM PDT 24
Peak memory 242260 kb
Host smart-3340dde0-7106-4ad5-9562-fbcad4b6a17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827098087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.827098087
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.797813757
Short name T548
Test name
Test status
Simulation time 2503097474 ps
CPU time 6.09 seconds
Started Jun 04 03:03:44 PM PDT 24
Finished Jun 04 03:03:51 PM PDT 24
Peak memory 242400 kb
Host smart-8015cfbc-3dbe-4b17-b58f-8bc157d8f3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797813757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.797813757
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.536541063
Short name T878
Test name
Test status
Simulation time 540732557 ps
CPU time 15.95 seconds
Started Jun 04 03:03:48 PM PDT 24
Finished Jun 04 03:04:06 PM PDT 24
Peak memory 242340 kb
Host smart-fe9168e4-fa05-49da-a97d-f5661e93e7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536541063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.536541063
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.3249250368
Short name T134
Test name
Test status
Simulation time 296949347 ps
CPU time 4.9 seconds
Started Jun 04 03:03:47 PM PDT 24
Finished Jun 04 03:03:53 PM PDT 24
Peak memory 242348 kb
Host smart-32b96202-f55f-443a-b222-a7a346aeadc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249250368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.3249250368
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.3473356344
Short name T1196
Test name
Test status
Simulation time 134883527 ps
CPU time 5.14 seconds
Started Jun 04 03:03:47 PM PDT 24
Finished Jun 04 03:03:55 PM PDT 24
Peak memory 242488 kb
Host smart-cc48b67c-f4d7-45c9-ae54-417abf78ec53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473356344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.3473356344
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.3352077225
Short name T818
Test name
Test status
Simulation time 171072146 ps
CPU time 4.43 seconds
Started Jun 04 03:03:46 PM PDT 24
Finished Jun 04 03:03:52 PM PDT 24
Peak memory 242384 kb
Host smart-8db364d0-4850-4e42-9969-6cf4b9bd92e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352077225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.3352077225
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.3576589570
Short name T186
Test name
Test status
Simulation time 629045119 ps
CPU time 8.54 seconds
Started Jun 04 03:03:51 PM PDT 24
Finished Jun 04 03:04:01 PM PDT 24
Peak memory 242188 kb
Host smart-41874670-1b6d-44be-bfbd-268a2fc8e024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576589570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.3576589570
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.2271794923
Short name T980
Test name
Test status
Simulation time 273958242 ps
CPU time 3.92 seconds
Started Jun 04 03:03:49 PM PDT 24
Finished Jun 04 03:03:55 PM PDT 24
Peak memory 242308 kb
Host smart-37e5d3a7-3905-444c-8c8b-ffc8512eff9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271794923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.2271794923
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.1204689585
Short name T998
Test name
Test status
Simulation time 293540717 ps
CPU time 3.82 seconds
Started Jun 04 03:03:47 PM PDT 24
Finished Jun 04 03:03:52 PM PDT 24
Peak memory 242584 kb
Host smart-d6a0ae99-f645-4cc3-945a-091d4ebb279e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204689585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.1204689585
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.631367239
Short name T1080
Test name
Test status
Simulation time 204992201 ps
CPU time 3.25 seconds
Started Jun 04 03:03:48 PM PDT 24
Finished Jun 04 03:03:54 PM PDT 24
Peak memory 242496 kb
Host smart-259c3824-937f-4531-be05-9bd29c27ed8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631367239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.631367239
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.2157982882
Short name T453
Test name
Test status
Simulation time 645496296 ps
CPU time 1.94 seconds
Started Jun 04 03:00:21 PM PDT 24
Finished Jun 04 03:00:24 PM PDT 24
Peak memory 241148 kb
Host smart-abd792fd-943e-4631-b3df-1a56faf682b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157982882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.2157982882
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.1800220083
Short name T1185
Test name
Test status
Simulation time 1214113138 ps
CPU time 19.87 seconds
Started Jun 04 03:00:15 PM PDT 24
Finished Jun 04 03:00:36 PM PDT 24
Peak memory 248976 kb
Host smart-87466a65-b9cf-429f-a36e-4c8c058bd30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800220083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.1800220083
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.1582886045
Short name T517
Test name
Test status
Simulation time 2167771189 ps
CPU time 31.24 seconds
Started Jun 04 03:00:17 PM PDT 24
Finished Jun 04 03:00:49 PM PDT 24
Peak memory 242576 kb
Host smart-79e7bbe6-cf65-4662-9ab5-2c18478fe5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582886045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.1582886045
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.3735318202
Short name T502
Test name
Test status
Simulation time 440060838 ps
CPU time 3.29 seconds
Started Jun 04 03:00:15 PM PDT 24
Finished Jun 04 03:00:20 PM PDT 24
Peak memory 242280 kb
Host smart-f8323960-9bd2-476e-a65f-83ce4a73ecdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735318202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.3735318202
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.3468309770
Short name T999
Test name
Test status
Simulation time 1701834814 ps
CPU time 36.46 seconds
Started Jun 04 03:00:13 PM PDT 24
Finished Jun 04 03:00:51 PM PDT 24
Peak memory 257088 kb
Host smart-21592fb7-2bd9-4039-acd8-9c3e40e7115a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468309770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.3468309770
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.2717891465
Short name T588
Test name
Test status
Simulation time 143585473 ps
CPU time 6.88 seconds
Started Jun 04 03:00:14 PM PDT 24
Finished Jun 04 03:00:23 PM PDT 24
Peak memory 242140 kb
Host smart-72051c2f-1228-45d8-9a61-d0ae7fff3e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717891465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.2717891465
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.3454956341
Short name T810
Test name
Test status
Simulation time 3619758462 ps
CPU time 9.44 seconds
Started Jun 04 03:00:14 PM PDT 24
Finished Jun 04 03:00:25 PM PDT 24
Peak memory 242380 kb
Host smart-28fc6205-1f79-463e-a43b-c0f255213cd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3454956341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.3454956341
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.2330528577
Short name T467
Test name
Test status
Simulation time 2981915713 ps
CPU time 10.23 seconds
Started Jun 04 03:00:13 PM PDT 24
Finished Jun 04 03:00:24 PM PDT 24
Peak memory 242268 kb
Host smart-f1bff612-9ebb-4610-9bad-20bec21f91f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2330528577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.2330528577
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.2359292769
Short name T911
Test name
Test status
Simulation time 1449787215 ps
CPU time 10.44 seconds
Started Jun 04 03:00:14 PM PDT 24
Finished Jun 04 03:00:26 PM PDT 24
Peak memory 242456 kb
Host smart-ad77faa1-f65c-4bac-bbf4-96864891f97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359292769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.2359292769
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.3715983241
Short name T267
Test name
Test status
Simulation time 1532500265 ps
CPU time 50.9 seconds
Started Jun 04 03:00:23 PM PDT 24
Finished Jun 04 03:01:15 PM PDT 24
Peak memory 251580 kb
Host smart-46f9fe36-3e02-4c6e-bea0-26241d570843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715983241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all
.3715983241
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.501062076
Short name T1040
Test name
Test status
Simulation time 48010456548 ps
CPU time 377.48 seconds
Started Jun 04 03:00:15 PM PDT 24
Finished Jun 04 03:06:34 PM PDT 24
Peak memory 257184 kb
Host smart-73bd4292-5e5e-41a5-93c7-94e4ffd42b56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501062076 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.501062076
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.796875187
Short name T1013
Test name
Test status
Simulation time 1295692195 ps
CPU time 24.87 seconds
Started Jun 04 03:00:16 PM PDT 24
Finished Jun 04 03:00:42 PM PDT 24
Peak memory 242380 kb
Host smart-b6cd1bcf-c21f-443d-bc3d-04707c4c4dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796875187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.796875187
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.2810930345
Short name T633
Test name
Test status
Simulation time 132081880 ps
CPU time 3.39 seconds
Started Jun 04 03:03:47 PM PDT 24
Finished Jun 04 03:03:52 PM PDT 24
Peak memory 242400 kb
Host smart-c489cb22-7179-48da-9fb8-ce649afd8c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810930345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.2810930345
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.3584084680
Short name T849
Test name
Test status
Simulation time 1881756172 ps
CPU time 5.61 seconds
Started Jun 04 03:03:49 PM PDT 24
Finished Jun 04 03:03:56 PM PDT 24
Peak memory 242204 kb
Host smart-d41db64e-1187-4df9-bbe1-f08de3cac600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584084680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.3584084680
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.2994260894
Short name T464
Test name
Test status
Simulation time 548675466 ps
CPU time 8.76 seconds
Started Jun 04 03:03:47 PM PDT 24
Finished Jun 04 03:03:57 PM PDT 24
Peak memory 242432 kb
Host smart-d928eb31-0437-4ead-a68c-3aa6d0e4efc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994260894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.2994260894
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.1646701392
Short name T880
Test name
Test status
Simulation time 2834019945 ps
CPU time 5.12 seconds
Started Jun 04 03:03:48 PM PDT 24
Finished Jun 04 03:03:55 PM PDT 24
Peak memory 242804 kb
Host smart-c33f6f07-2fd8-466d-b9ec-625b2595b79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646701392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.1646701392
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.3443331963
Short name T1127
Test name
Test status
Simulation time 455175347 ps
CPU time 14.24 seconds
Started Jun 04 03:03:47 PM PDT 24
Finished Jun 04 03:04:03 PM PDT 24
Peak memory 242276 kb
Host smart-bf306add-8554-46a3-9e31-94aab8cff474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443331963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.3443331963
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.2346373253
Short name T929
Test name
Test status
Simulation time 331509811 ps
CPU time 3.66 seconds
Started Jun 04 03:03:49 PM PDT 24
Finished Jun 04 03:03:54 PM PDT 24
Peak memory 242336 kb
Host smart-1c334a13-9595-458e-9b12-3b47043c6b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346373253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.2346373253
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.974934621
Short name T640
Test name
Test status
Simulation time 3416817062 ps
CPU time 7.78 seconds
Started Jun 04 03:03:48 PM PDT 24
Finished Jun 04 03:03:57 PM PDT 24
Peak memory 242432 kb
Host smart-e4edcf2a-047b-49b7-a227-4cf11c43e0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974934621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.974934621
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.1029709254
Short name T730
Test name
Test status
Simulation time 141928079 ps
CPU time 4.2 seconds
Started Jun 04 03:03:49 PM PDT 24
Finished Jun 04 03:03:55 PM PDT 24
Peak memory 242392 kb
Host smart-34c729f6-fe35-4062-8103-4273f713ddb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029709254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.1029709254
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.2383084234
Short name T530
Test name
Test status
Simulation time 138196005 ps
CPU time 3.24 seconds
Started Jun 04 03:03:47 PM PDT 24
Finished Jun 04 03:03:52 PM PDT 24
Peak memory 242360 kb
Host smart-dd0fe1be-5315-468e-b72e-030b224a1c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383084234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.2383084234
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.3165728404
Short name T1156
Test name
Test status
Simulation time 143281624 ps
CPU time 3.17 seconds
Started Jun 04 03:03:49 PM PDT 24
Finished Jun 04 03:03:54 PM PDT 24
Peak memory 242464 kb
Host smart-63397a95-f4af-42fb-b080-fa424906cade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165728404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.3165728404
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.2267390780
Short name T1053
Test name
Test status
Simulation time 194428119 ps
CPU time 2.89 seconds
Started Jun 04 03:03:46 PM PDT 24
Finished Jun 04 03:03:50 PM PDT 24
Peak memory 242268 kb
Host smart-3389942a-2815-441d-9a09-2a173d1a4cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267390780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.2267390780
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.357083168
Short name T1157
Test name
Test status
Simulation time 244175477 ps
CPU time 4 seconds
Started Jun 04 03:03:49 PM PDT 24
Finished Jun 04 03:03:55 PM PDT 24
Peak memory 242228 kb
Host smart-c494c0aa-53b7-46af-bbac-d43cc01c12ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357083168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.357083168
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.2451729643
Short name T255
Test name
Test status
Simulation time 2904713363 ps
CPU time 25.76 seconds
Started Jun 04 03:03:49 PM PDT 24
Finished Jun 04 03:04:17 PM PDT 24
Peak memory 242596 kb
Host smart-294ecc5b-8c65-41ba-b9bd-bcb940cb499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451729643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.2451729643
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.3038704709
Short name T688
Test name
Test status
Simulation time 1651149241 ps
CPU time 5.76 seconds
Started Jun 04 03:03:47 PM PDT 24
Finished Jun 04 03:03:55 PM PDT 24
Peak memory 242304 kb
Host smart-dc69515b-068a-4a96-9b41-92a76cf20460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038704709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.3038704709
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.1727204794
Short name T836
Test name
Test status
Simulation time 4243559938 ps
CPU time 17.15 seconds
Started Jun 04 03:03:47 PM PDT 24
Finished Jun 04 03:04:06 PM PDT 24
Peak memory 242580 kb
Host smart-e8b9ad9a-b0c9-4b9e-a597-23fe432b5bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727204794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.1727204794
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.3645668390
Short name T581
Test name
Test status
Simulation time 132160467 ps
CPU time 3.84 seconds
Started Jun 04 03:03:48 PM PDT 24
Finished Jun 04 03:03:54 PM PDT 24
Peak memory 242652 kb
Host smart-9e4b7aed-89d3-442e-86b5-9506de381943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645668390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.3645668390
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.3278975726
Short name T304
Test name
Test status
Simulation time 510545389 ps
CPU time 7.86 seconds
Started Jun 04 03:04:00 PM PDT 24
Finished Jun 04 03:04:09 PM PDT 24
Peak memory 242548 kb
Host smart-e1ee927e-616e-4d0f-b026-5f82af940136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278975726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.3278975726
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.4277852969
Short name T1183
Test name
Test status
Simulation time 1962617305 ps
CPU time 4.28 seconds
Started Jun 04 03:03:57 PM PDT 24
Finished Jun 04 03:04:02 PM PDT 24
Peak memory 242628 kb
Host smart-0ef735a7-1b66-4675-8454-b643da6a2845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277852969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.4277852969
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.1833317982
Short name T844
Test name
Test status
Simulation time 686940003 ps
CPU time 7.12 seconds
Started Jun 04 03:03:57 PM PDT 24
Finished Jun 04 03:04:05 PM PDT 24
Peak memory 242552 kb
Host smart-ccd31986-8a1a-45d3-b52b-d6dbe1caa6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833317982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.1833317982
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.3507093298
Short name T1104
Test name
Test status
Simulation time 622796077 ps
CPU time 1.86 seconds
Started Jun 04 03:00:22 PM PDT 24
Finished Jun 04 03:00:25 PM PDT 24
Peak memory 240736 kb
Host smart-6bf2c0bb-15c5-48c7-8de8-8852eec0db53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507093298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.3507093298
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.2719559564
Short name T774
Test name
Test status
Simulation time 845355411 ps
CPU time 7.01 seconds
Started Jun 04 03:00:23 PM PDT 24
Finished Jun 04 03:00:31 PM PDT 24
Peak memory 242348 kb
Host smart-83031757-a968-4269-b9bd-c061cf2a4662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719559564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.2719559564
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.1247767516
Short name T397
Test name
Test status
Simulation time 432812778 ps
CPU time 18.35 seconds
Started Jun 04 03:00:20 PM PDT 24
Finished Jun 04 03:00:40 PM PDT 24
Peak memory 242376 kb
Host smart-4e4cb318-6f4a-438e-84f4-a90287729461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247767516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.1247767516
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.2541826656
Short name T1012
Test name
Test status
Simulation time 1212586850 ps
CPU time 16.83 seconds
Started Jun 04 03:00:23 PM PDT 24
Finished Jun 04 03:00:41 PM PDT 24
Peak memory 242512 kb
Host smart-2f5b9178-f6d3-4dd1-b64a-93a88f276d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541826656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.2541826656
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.1639138060
Short name T939
Test name
Test status
Simulation time 306283097 ps
CPU time 5.56 seconds
Started Jun 04 03:00:21 PM PDT 24
Finished Jun 04 03:00:28 PM PDT 24
Peak memory 242508 kb
Host smart-bf232fd7-c72f-459a-bcfd-58c956351f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639138060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.1639138060
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.3397016544
Short name T193
Test name
Test status
Simulation time 1466693031 ps
CPU time 34.15 seconds
Started Jun 04 03:00:32 PM PDT 24
Finished Jun 04 03:01:08 PM PDT 24
Peak memory 257128 kb
Host smart-6a703241-b075-42cf-b388-807f72e45f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397016544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.3397016544
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.689043194
Short name T745
Test name
Test status
Simulation time 207988632 ps
CPU time 4.33 seconds
Started Jun 04 03:00:22 PM PDT 24
Finished Jun 04 03:00:27 PM PDT 24
Peak memory 248416 kb
Host smart-4aef4d0c-f108-4337-8aa5-5f5ba1afa9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689043194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.689043194
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.2181589940
Short name T646
Test name
Test status
Simulation time 242115988 ps
CPU time 7.01 seconds
Started Jun 04 03:00:24 PM PDT 24
Finished Jun 04 03:00:32 PM PDT 24
Peak memory 242244 kb
Host smart-8c2c80e3-6094-47c6-98b9-fa87f44ad8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181589940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.2181589940
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.373416915
Short name T96
Test name
Test status
Simulation time 218454906 ps
CPU time 6.97 seconds
Started Jun 04 03:00:23 PM PDT 24
Finished Jun 04 03:00:31 PM PDT 24
Peak memory 242412 kb
Host smart-ded4052e-6317-4701-a427-b0aab4a7e234
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=373416915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.373416915
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.4133597043
Short name T594
Test name
Test status
Simulation time 586550032 ps
CPU time 5.93 seconds
Started Jun 04 03:00:32 PM PDT 24
Finished Jun 04 03:00:39 PM PDT 24
Peak memory 242488 kb
Host smart-36e7492e-f30b-4d28-b0b4-253acd05c382
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4133597043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.4133597043
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.3474234559
Short name T411
Test name
Test status
Simulation time 154843898 ps
CPU time 3.92 seconds
Started Jun 04 03:00:23 PM PDT 24
Finished Jun 04 03:00:28 PM PDT 24
Peak memory 242484 kb
Host smart-b7ac4539-4316-485a-8568-37f340d378e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474234559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.3474234559
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.1894859570
Short name T1084
Test name
Test status
Simulation time 46262668084 ps
CPU time 277.91 seconds
Started Jun 04 03:00:22 PM PDT 24
Finished Jun 04 03:05:01 PM PDT 24
Peak memory 257252 kb
Host smart-a71aaf2c-d1ff-42dd-bac8-cf33dbde48fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894859570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all
.1894859570
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.2488966491
Short name T654
Test name
Test status
Simulation time 603070023 ps
CPU time 5.14 seconds
Started Jun 04 03:00:22 PM PDT 24
Finished Jun 04 03:00:28 PM PDT 24
Peak memory 242484 kb
Host smart-3fd35f2f-f7ca-456d-ba54-4e488ae8b1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488966491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.2488966491
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.4103010645
Short name T660
Test name
Test status
Simulation time 407236672 ps
CPU time 4.64 seconds
Started Jun 04 03:03:56 PM PDT 24
Finished Jun 04 03:04:02 PM PDT 24
Peak memory 242432 kb
Host smart-34dca9e0-7fed-433e-85e4-9ab6c35f53cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103010645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.4103010645
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.1456158596
Short name T965
Test name
Test status
Simulation time 2005230732 ps
CPU time 3.45 seconds
Started Jun 04 03:03:56 PM PDT 24
Finished Jun 04 03:04:00 PM PDT 24
Peak memory 242164 kb
Host smart-1ccbba3f-6474-42e9-b364-1901e033d7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456158596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.1456158596
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.737155533
Short name T200
Test name
Test status
Simulation time 127585049 ps
CPU time 4.1 seconds
Started Jun 04 03:04:00 PM PDT 24
Finished Jun 04 03:04:05 PM PDT 24
Peak memory 242316 kb
Host smart-a426b299-a16f-42f5-a15b-9e7402c1f95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737155533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.737155533
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.3369902157
Short name T928
Test name
Test status
Simulation time 1075222362 ps
CPU time 18.05 seconds
Started Jun 04 03:03:58 PM PDT 24
Finished Jun 04 03:04:17 PM PDT 24
Peak memory 242268 kb
Host smart-3bec6c6b-8a38-4638-8053-c11f70133aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369902157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.3369902157
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.1602920825
Short name T1124
Test name
Test status
Simulation time 167502458 ps
CPU time 4.61 seconds
Started Jun 04 03:03:58 PM PDT 24
Finished Jun 04 03:04:04 PM PDT 24
Peak memory 242308 kb
Host smart-f801c8c5-c653-413b-8895-45cf934770b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602920825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.1602920825
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.2512375478
Short name T686
Test name
Test status
Simulation time 211958557 ps
CPU time 3.37 seconds
Started Jun 04 03:03:59 PM PDT 24
Finished Jun 04 03:04:04 PM PDT 24
Peak memory 242520 kb
Host smart-21867d8b-9282-498e-99e1-fc2dc1bed764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512375478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.2512375478
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.3193103176
Short name T626
Test name
Test status
Simulation time 146003982 ps
CPU time 4.06 seconds
Started Jun 04 03:03:59 PM PDT 24
Finished Jun 04 03:04:04 PM PDT 24
Peak memory 242700 kb
Host smart-89d9c723-4154-47cd-a136-6b105c7a1f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193103176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.3193103176
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.3366741251
Short name T1174
Test name
Test status
Simulation time 3404390012 ps
CPU time 23.9 seconds
Started Jun 04 03:03:58 PM PDT 24
Finished Jun 04 03:04:23 PM PDT 24
Peak memory 242476 kb
Host smart-72b75f0b-a176-463e-8a1e-e0bb89bb17a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366741251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.3366741251
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.267422119
Short name T556
Test name
Test status
Simulation time 680069989 ps
CPU time 4.7 seconds
Started Jun 04 03:04:03 PM PDT 24
Finished Jun 04 03:04:08 PM PDT 24
Peak memory 242392 kb
Host smart-51de4972-6baa-4491-9d09-f0ac0d95972c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267422119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.267422119
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.1356574206
Short name T395
Test name
Test status
Simulation time 3085023712 ps
CPU time 6.87 seconds
Started Jun 04 03:03:57 PM PDT 24
Finished Jun 04 03:04:05 PM PDT 24
Peak memory 247448 kb
Host smart-7c9e05ae-e2f7-4085-a8b9-db76b123b400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356574206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.1356574206
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.765230196
Short name T1175
Test name
Test status
Simulation time 2540375957 ps
CPU time 6.13 seconds
Started Jun 04 03:04:00 PM PDT 24
Finished Jun 04 03:04:07 PM PDT 24
Peak memory 242548 kb
Host smart-0e3efbca-1f97-48e9-8279-bc4ca8d5a466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765230196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.765230196
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.3658994398
Short name T956
Test name
Test status
Simulation time 1025311608 ps
CPU time 16.47 seconds
Started Jun 04 03:04:02 PM PDT 24
Finished Jun 04 03:04:20 PM PDT 24
Peak memory 242248 kb
Host smart-ceb754f0-50db-4749-bbc2-73efb41e5df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658994398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.3658994398
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.184211803
Short name T949
Test name
Test status
Simulation time 1649892767 ps
CPU time 5.55 seconds
Started Jun 04 03:04:00 PM PDT 24
Finished Jun 04 03:04:07 PM PDT 24
Peak memory 242424 kb
Host smart-be432d4b-3b9b-4707-ad38-952342207088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184211803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.184211803
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.807209076
Short name T1091
Test name
Test status
Simulation time 14356916925 ps
CPU time 27.16 seconds
Started Jun 04 03:03:59 PM PDT 24
Finished Jun 04 03:04:27 PM PDT 24
Peak memory 242748 kb
Host smart-aa9f2f4c-ea9f-4160-820f-1f354ddd8bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807209076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.807209076
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.3524915017
Short name T881
Test name
Test status
Simulation time 282165054 ps
CPU time 4.37 seconds
Started Jun 04 03:03:58 PM PDT 24
Finished Jun 04 03:04:03 PM PDT 24
Peak memory 242392 kb
Host smart-3129ab13-36a0-44c1-97b4-29ed5ac55943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524915017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.3524915017
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.1169523606
Short name T636
Test name
Test status
Simulation time 168907874 ps
CPU time 4.46 seconds
Started Jun 04 03:03:58 PM PDT 24
Finished Jun 04 03:04:04 PM PDT 24
Peak memory 242520 kb
Host smart-15701415-177a-41de-862d-7ff421e2de7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169523606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.1169523606
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.3867794664
Short name T135
Test name
Test status
Simulation time 176373755 ps
CPU time 4.37 seconds
Started Jun 04 03:03:57 PM PDT 24
Finished Jun 04 03:04:02 PM PDT 24
Peak memory 242712 kb
Host smart-cf9b60c0-a5ba-43dc-a165-16355f7329f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867794664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.3867794664
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.300969361
Short name T422
Test name
Test status
Simulation time 601251273 ps
CPU time 8.24 seconds
Started Jun 04 03:04:00 PM PDT 24
Finished Jun 04 03:04:09 PM PDT 24
Peak memory 242592 kb
Host smart-31e5cc15-3acd-410e-b86c-61a9c31c2e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300969361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.300969361
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.385085690
Short name T450
Test name
Test status
Simulation time 248194209 ps
CPU time 3.72 seconds
Started Jun 04 03:03:58 PM PDT 24
Finished Jun 04 03:04:03 PM PDT 24
Peak memory 242336 kb
Host smart-1041e511-8b98-4762-896b-a2daebf06bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385085690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.385085690
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.3142677200
Short name T976
Test name
Test status
Simulation time 460611545 ps
CPU time 6.84 seconds
Started Jun 04 03:04:01 PM PDT 24
Finished Jun 04 03:04:09 PM PDT 24
Peak memory 242640 kb
Host smart-c363d3d1-14b0-463f-8171-0cd66dcb000a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142677200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.3142677200
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.1544404034
Short name T867
Test name
Test status
Simulation time 95685933 ps
CPU time 1.55 seconds
Started Jun 04 03:00:31 PM PDT 24
Finished Jun 04 03:00:33 PM PDT 24
Peak memory 240940 kb
Host smart-989c6ba2-a21e-42a6-acab-66d890305898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544404034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.1544404034
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.4163843639
Short name T1016
Test name
Test status
Simulation time 147665792 ps
CPU time 2.91 seconds
Started Jun 04 03:00:21 PM PDT 24
Finished Jun 04 03:00:25 PM PDT 24
Peak memory 246772 kb
Host smart-58fe43f7-5bc4-40d4-ad0a-7e52ab3a25fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163843639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.4163843639
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.4273090248
Short name T689
Test name
Test status
Simulation time 4290774771 ps
CPU time 33.46 seconds
Started Jun 04 03:00:32 PM PDT 24
Finished Jun 04 03:01:06 PM PDT 24
Peak memory 248604 kb
Host smart-83d81775-3c3c-4c60-b62b-bd5d9c7b983c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273090248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.4273090248
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.1863649606
Short name T892
Test name
Test status
Simulation time 5403457647 ps
CPU time 36.66 seconds
Started Jun 04 03:00:33 PM PDT 24
Finished Jun 04 03:01:11 PM PDT 24
Peak memory 242260 kb
Host smart-e7cdb3b0-e914-436e-a83f-58a3fe05c25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863649606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.1863649606
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.2719021306
Short name T1106
Test name
Test status
Simulation time 525743102 ps
CPU time 4.17 seconds
Started Jun 04 03:00:23 PM PDT 24
Finished Jun 04 03:00:29 PM PDT 24
Peak memory 242388 kb
Host smart-ba8c6320-e487-4c2b-89f1-20e63d4cc6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719021306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.2719021306
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.2903236758
Short name T355
Test name
Test status
Simulation time 129957673 ps
CPU time 2.88 seconds
Started Jun 04 03:00:33 PM PDT 24
Finished Jun 04 03:00:37 PM PDT 24
Peak memory 242576 kb
Host smart-e9baafce-fe31-4e10-9946-5d9fee62b263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903236758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.2903236758
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.4139116993
Short name T497
Test name
Test status
Simulation time 1979277671 ps
CPU time 25.39 seconds
Started Jun 04 03:00:32 PM PDT 24
Finished Jun 04 03:00:59 PM PDT 24
Peak memory 242708 kb
Host smart-961e2747-0c7c-40ec-8e49-cdd95acff2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139116993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.4139116993
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.438572956
Short name T680
Test name
Test status
Simulation time 808983081 ps
CPU time 12.94 seconds
Started Jun 04 03:00:32 PM PDT 24
Finished Jun 04 03:00:45 PM PDT 24
Peak memory 242444 kb
Host smart-8f704fc8-154b-4f06-ad07-270335e4ae27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438572956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.438572956
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.3019026282
Short name T773
Test name
Test status
Simulation time 652569107 ps
CPU time 16.68 seconds
Started Jun 04 03:00:22 PM PDT 24
Finished Jun 04 03:00:40 PM PDT 24
Peak memory 242272 kb
Host smart-1085498b-c851-41b4-a95d-af2815c29ae2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3019026282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.3019026282
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.803037417
Short name T372
Test name
Test status
Simulation time 308407583 ps
CPU time 5.16 seconds
Started Jun 04 03:00:23 PM PDT 24
Finished Jun 04 03:00:29 PM PDT 24
Peak memory 242660 kb
Host smart-61668321-1f61-42db-9370-914d998cb7fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=803037417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.803037417
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.3855406817
Short name T586
Test name
Test status
Simulation time 314686511 ps
CPU time 4.14 seconds
Started Jun 04 03:00:31 PM PDT 24
Finished Jun 04 03:00:35 PM PDT 24
Peak memory 242708 kb
Host smart-5f600e7c-4df7-4399-87ed-7b2098d26dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855406817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.3855406817
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.1670748234
Short name T1044
Test name
Test status
Simulation time 63211694235 ps
CPU time 108.11 seconds
Started Jun 04 03:00:32 PM PDT 24
Finished Jun 04 03:02:20 PM PDT 24
Peak memory 246448 kb
Host smart-45b472df-2688-46ff-9f5a-f7afae4ebdec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670748234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all
.1670748234
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.418968931
Short name T869
Test name
Test status
Simulation time 78129879020 ps
CPU time 1052.39 seconds
Started Jun 04 03:00:32 PM PDT 24
Finished Jun 04 03:18:06 PM PDT 24
Peak memory 287572 kb
Host smart-f1caa8aa-f6a8-49a4-9d5b-6739f602badf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418968931 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.418968931
Directory /workspace/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.1553252726
Short name T1123
Test name
Test status
Simulation time 12353856026 ps
CPU time 42.07 seconds
Started Jun 04 03:00:32 PM PDT 24
Finished Jun 04 03:01:15 PM PDT 24
Peak memory 248904 kb
Host smart-1aacd303-8682-4bee-ac8b-8e21bd4fdaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553252726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.1553252726
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.3294840104
Short name T130
Test name
Test status
Simulation time 284983682 ps
CPU time 4.47 seconds
Started Jun 04 03:03:56 PM PDT 24
Finished Jun 04 03:04:02 PM PDT 24
Peak memory 242744 kb
Host smart-1cfaa9ab-2b13-43d7-8800-5d253548595b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294840104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.3294840104
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.2614212840
Short name T1092
Test name
Test status
Simulation time 106283630 ps
CPU time 3.87 seconds
Started Jun 04 03:03:57 PM PDT 24
Finished Jun 04 03:04:02 PM PDT 24
Peak memory 242152 kb
Host smart-6da53f38-eab0-478a-98b6-b7ae3581018b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614212840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.2614212840
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.4069384542
Short name T722
Test name
Test status
Simulation time 8558437016 ps
CPU time 18.36 seconds
Started Jun 04 03:03:57 PM PDT 24
Finished Jun 04 03:04:17 PM PDT 24
Peak memory 242460 kb
Host smart-c9e845a8-9d38-4306-8f27-6d60550ceb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069384542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.4069384542
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.1985012374
Short name T662
Test name
Test status
Simulation time 115751950 ps
CPU time 4.56 seconds
Started Jun 04 03:03:58 PM PDT 24
Finished Jun 04 03:04:03 PM PDT 24
Peak memory 242240 kb
Host smart-7d2b1362-6b3c-40ba-90c4-4ec4fddddb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985012374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.1985012374
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.4001047110
Short name T28
Test name
Test status
Simulation time 153610144 ps
CPU time 4.97 seconds
Started Jun 04 03:03:57 PM PDT 24
Finished Jun 04 03:04:04 PM PDT 24
Peak memory 242272 kb
Host smart-841eed2b-7270-4c85-8002-1a47ea9b5a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001047110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.4001047110
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.2023077720
Short name T347
Test name
Test status
Simulation time 18442659918 ps
CPU time 30.99 seconds
Started Jun 04 03:03:57 PM PDT 24
Finished Jun 04 03:04:29 PM PDT 24
Peak memory 242568 kb
Host smart-0d4f46cc-8367-436d-84f8-e891d88b6c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023077720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.2023077720
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.1260050885
Short name T393
Test name
Test status
Simulation time 627916773 ps
CPU time 6.11 seconds
Started Jun 04 03:03:58 PM PDT 24
Finished Jun 04 03:04:05 PM PDT 24
Peak memory 242464 kb
Host smart-3ec4196b-d610-4f83-9928-843830de54f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260050885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.1260050885
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.3852253377
Short name T540
Test name
Test status
Simulation time 1562653112 ps
CPU time 5.41 seconds
Started Jun 04 03:03:57 PM PDT 24
Finished Jun 04 03:04:03 PM PDT 24
Peak memory 242288 kb
Host smart-65f016fd-7383-4bf8-848f-b3fbb517dacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852253377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.3852253377
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.1986424567
Short name T234
Test name
Test status
Simulation time 1747380164 ps
CPU time 18.68 seconds
Started Jun 04 03:03:57 PM PDT 24
Finished Jun 04 03:04:16 PM PDT 24
Peak memory 242296 kb
Host smart-ce4e0f62-1e16-41eb-a77e-31f2c4924b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986424567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.1986424567
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.3231955750
Short name T1029
Test name
Test status
Simulation time 2431348388 ps
CPU time 4.33 seconds
Started Jun 04 03:03:56 PM PDT 24
Finished Jun 04 03:04:01 PM PDT 24
Peak memory 242556 kb
Host smart-699dbdf6-ace8-4912-b1bd-290067e91b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231955750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.3231955750
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.2433599331
Short name T891
Test name
Test status
Simulation time 2684343807 ps
CPU time 12.2 seconds
Started Jun 04 03:04:00 PM PDT 24
Finished Jun 04 03:04:14 PM PDT 24
Peak memory 242392 kb
Host smart-91374f5d-9ab7-42c5-9f9a-61f4313dff77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433599331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.2433599331
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.1279832093
Short name T76
Test name
Test status
Simulation time 117283277 ps
CPU time 4.16 seconds
Started Jun 04 03:04:00 PM PDT 24
Finished Jun 04 03:04:06 PM PDT 24
Peak memory 242264 kb
Host smart-8a1d0724-7a2c-423c-b460-c62b4832aabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279832093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.1279832093
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.2620604503
Short name T778
Test name
Test status
Simulation time 798563159 ps
CPU time 9.29 seconds
Started Jun 04 03:04:00 PM PDT 24
Finished Jun 04 03:04:11 PM PDT 24
Peak memory 242232 kb
Host smart-8374f0f3-d15f-42c7-a736-cccea2838786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620604503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.2620604503
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.2355936331
Short name T163
Test name
Test status
Simulation time 139047412 ps
CPU time 3.54 seconds
Started Jun 04 03:03:56 PM PDT 24
Finished Jun 04 03:04:01 PM PDT 24
Peak memory 242428 kb
Host smart-33325273-4dc9-4dae-948e-de6debbe39a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355936331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.2355936331
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.1081417786
Short name T618
Test name
Test status
Simulation time 160453612 ps
CPU time 3.67 seconds
Started Jun 04 03:03:58 PM PDT 24
Finished Jun 04 03:04:02 PM PDT 24
Peak memory 242660 kb
Host smart-79ee58e0-69e9-43b9-9972-b66ef339cfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081417786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.1081417786
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.1959565660
Short name T1187
Test name
Test status
Simulation time 213123444 ps
CPU time 4.6 seconds
Started Jun 04 03:03:56 PM PDT 24
Finished Jun 04 03:04:02 PM PDT 24
Peak memory 242416 kb
Host smart-719e33f6-41bb-4e1c-9f4b-7d7e724b7b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959565660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.1959565660
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.829956713
Short name T842
Test name
Test status
Simulation time 1404859045 ps
CPU time 11.18 seconds
Started Jun 04 03:03:58 PM PDT 24
Finished Jun 04 03:04:10 PM PDT 24
Peak memory 242268 kb
Host smart-b5d5092d-a463-4bd9-bda2-f239f6212629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829956713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.829956713
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.637653147
Short name T441
Test name
Test status
Simulation time 62002882 ps
CPU time 1.81 seconds
Started Jun 04 03:00:32 PM PDT 24
Finished Jun 04 03:00:35 PM PDT 24
Peak memory 240680 kb
Host smart-9b859fe8-e5f5-4ff0-bc6a-c73604d6d2cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637653147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.637653147
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.2694601593
Short name T1011
Test name
Test status
Simulation time 7177025061 ps
CPU time 16.14 seconds
Started Jun 04 03:00:33 PM PDT 24
Finished Jun 04 03:00:50 PM PDT 24
Peak memory 249032 kb
Host smart-a895aa97-ad37-4f14-af21-3766cdbcfe31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694601593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.2694601593
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.1889203830
Short name T870
Test name
Test status
Simulation time 4166145847 ps
CPU time 35.58 seconds
Started Jun 04 03:00:32 PM PDT 24
Finished Jun 04 03:01:08 PM PDT 24
Peak memory 247136 kb
Host smart-99bc20d7-2dca-4a39-bfe4-5b26d8151e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889203830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.1889203830
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.4156185114
Short name T209
Test name
Test status
Simulation time 3550094953 ps
CPU time 38.19 seconds
Started Jun 04 03:00:33 PM PDT 24
Finished Jun 04 03:01:12 PM PDT 24
Peak memory 242388 kb
Host smart-e43c0bb6-9964-44ac-97eb-dc3462db828d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156185114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.4156185114
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.2333597660
Short name T1008
Test name
Test status
Simulation time 2098219078 ps
CPU time 4.48 seconds
Started Jun 04 03:00:31 PM PDT 24
Finished Jun 04 03:00:36 PM PDT 24
Peak memory 242372 kb
Host smart-b737540a-0462-491b-ac40-ef434335eb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333597660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.2333597660
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.1975831503
Short name T809
Test name
Test status
Simulation time 3374057672 ps
CPU time 42.29 seconds
Started Jun 04 03:00:35 PM PDT 24
Finished Jun 04 03:01:18 PM PDT 24
Peak memory 248976 kb
Host smart-5d6b074d-dd85-4d50-90a3-86bf702c7c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975831503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.1975831503
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.2954869202
Short name T1059
Test name
Test status
Simulation time 1130531160 ps
CPU time 16.46 seconds
Started Jun 04 03:00:32 PM PDT 24
Finished Jun 04 03:00:50 PM PDT 24
Peak memory 242480 kb
Host smart-562173f4-ddec-489d-b838-409754833ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954869202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.2954869202
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.21050326
Short name T1054
Test name
Test status
Simulation time 428755182 ps
CPU time 7.86 seconds
Started Jun 04 03:00:34 PM PDT 24
Finished Jun 04 03:00:43 PM PDT 24
Peak memory 242164 kb
Host smart-96dc56d5-9471-4199-8b86-c265f64cf4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21050326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.21050326
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.1695892440
Short name T989
Test name
Test status
Simulation time 2872776093 ps
CPU time 25.98 seconds
Started Jun 04 03:00:31 PM PDT 24
Finished Jun 04 03:00:58 PM PDT 24
Peak memory 242468 kb
Host smart-46453187-f98a-42b4-b416-ce1dd1e5fc30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1695892440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.1695892440
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.2327229081
Short name T305
Test name
Test status
Simulation time 2057517611 ps
CPU time 5.43 seconds
Started Jun 04 03:00:33 PM PDT 24
Finished Jun 04 03:00:39 PM PDT 24
Peak memory 242440 kb
Host smart-c4ec35c5-6c21-4a49-bdca-701210eb960a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2327229081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.2327229081
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.434301092
Short name T398
Test name
Test status
Simulation time 1295261071 ps
CPU time 11.56 seconds
Started Jun 04 03:00:35 PM PDT 24
Finished Jun 04 03:00:47 PM PDT 24
Peak memory 242324 kb
Host smart-7d6a6692-a43b-485f-be2b-6fa4033c7dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434301092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.434301092
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.4293149398
Short name T518
Test name
Test status
Simulation time 6143812035 ps
CPU time 39 seconds
Started Jun 04 03:00:31 PM PDT 24
Finished Jun 04 03:01:10 PM PDT 24
Peak memory 244076 kb
Host smart-ed5fe791-2720-4c0a-957d-68380f6e744e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293149398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all
.4293149398
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.50385787
Short name T291
Test name
Test status
Simulation time 279562279553 ps
CPU time 1628.06 seconds
Started Jun 04 03:00:31 PM PDT 24
Finished Jun 04 03:27:40 PM PDT 24
Peak memory 382320 kb
Host smart-baacb41b-a22a-42e2-a3af-8af204e6d0cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50385787 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.50385787
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.3881021391
Short name T449
Test name
Test status
Simulation time 1181992257 ps
CPU time 32.94 seconds
Started Jun 04 03:00:32 PM PDT 24
Finished Jun 04 03:01:07 PM PDT 24
Peak memory 248876 kb
Host smart-952ed5aa-2b94-4fbd-8cbb-3e2a73ba0da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881021391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.3881021391
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.1956085870
Short name T82
Test name
Test status
Simulation time 199432930 ps
CPU time 4.32 seconds
Started Jun 04 03:04:00 PM PDT 24
Finished Jun 04 03:04:05 PM PDT 24
Peak memory 242520 kb
Host smart-ac77643d-c72b-4d32-844e-7547e5d42ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956085870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.1956085870
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.2390084337
Short name T657
Test name
Test status
Simulation time 223169384 ps
CPU time 9.61 seconds
Started Jun 04 03:04:00 PM PDT 24
Finished Jun 04 03:04:11 PM PDT 24
Peak memory 242224 kb
Host smart-24d969da-df28-423e-a81b-fff0a966643e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390084337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.2390084337
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.3679402852
Short name T173
Test name
Test status
Simulation time 479844057 ps
CPU time 4.51 seconds
Started Jun 04 03:03:57 PM PDT 24
Finished Jun 04 03:04:03 PM PDT 24
Peak memory 242616 kb
Host smart-bf6c7798-28c8-4866-8076-32b443bab269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679402852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.3679402852
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.2213302218
Short name T345
Test name
Test status
Simulation time 122477130 ps
CPU time 4.46 seconds
Started Jun 04 03:04:04 PM PDT 24
Finished Jun 04 03:04:09 PM PDT 24
Peak memory 242404 kb
Host smart-e2635622-2908-48b0-a86e-a0a8d4a06521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213302218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.2213302218
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.1941200061
Short name T498
Test name
Test status
Simulation time 329493871 ps
CPU time 4.63 seconds
Started Jun 04 03:04:06 PM PDT 24
Finished Jun 04 03:04:12 PM PDT 24
Peak memory 242456 kb
Host smart-617d967e-26c3-4369-adac-010056ef8dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941200061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.1941200061
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.2210422786
Short name T919
Test name
Test status
Simulation time 211971071 ps
CPU time 4.24 seconds
Started Jun 04 03:04:05 PM PDT 24
Finished Jun 04 03:04:11 PM PDT 24
Peak memory 242528 kb
Host smart-e0079f87-04af-441a-b4d7-5b62cf7846d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210422786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.2210422786
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.1217437752
Short name T567
Test name
Test status
Simulation time 149358191 ps
CPU time 4.17 seconds
Started Jun 04 03:04:06 PM PDT 24
Finished Jun 04 03:04:12 PM PDT 24
Peak memory 242372 kb
Host smart-184c5b55-c1ec-4f9a-bb04-a825dc97f617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217437752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.1217437752
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.1480078440
Short name T1105
Test name
Test status
Simulation time 351690106 ps
CPU time 8 seconds
Started Jun 04 03:04:05 PM PDT 24
Finished Jun 04 03:04:15 PM PDT 24
Peak memory 242268 kb
Host smart-de8271e2-04f1-4783-b6e3-f5cd99a9bed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480078440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.1480078440
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.2790168097
Short name T1195
Test name
Test status
Simulation time 541224048 ps
CPU time 3.69 seconds
Started Jun 04 03:04:05 PM PDT 24
Finished Jun 04 03:04:10 PM PDT 24
Peak memory 242668 kb
Host smart-80cb88ac-6f49-455c-bad9-afd4759b2a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790168097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.2790168097
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.4253482755
Short name T593
Test name
Test status
Simulation time 182312899 ps
CPU time 4.88 seconds
Started Jun 04 03:04:05 PM PDT 24
Finished Jun 04 03:04:11 PM PDT 24
Peak memory 242600 kb
Host smart-0c510a3b-08b5-491d-81d3-cebc78a33f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253482755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.4253482755
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.1087235622
Short name T1166
Test name
Test status
Simulation time 401807957 ps
CPU time 4.21 seconds
Started Jun 04 03:04:06 PM PDT 24
Finished Jun 04 03:04:11 PM PDT 24
Peak memory 242760 kb
Host smart-41c93122-3c59-44de-9af0-02b30383fa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087235622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.1087235622
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.3861304544
Short name T376
Test name
Test status
Simulation time 163576711 ps
CPU time 4.96 seconds
Started Jun 04 03:04:07 PM PDT 24
Finished Jun 04 03:04:13 PM PDT 24
Peak memory 242312 kb
Host smart-5b3b45f4-a52a-425f-8c30-5c004ebab755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861304544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.3861304544
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.278428223
Short name T1126
Test name
Test status
Simulation time 388444957 ps
CPU time 4.21 seconds
Started Jun 04 03:04:05 PM PDT 24
Finished Jun 04 03:04:10 PM PDT 24
Peak memory 242636 kb
Host smart-bff063cb-e80c-41a9-873e-038164589b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278428223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.278428223
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.1613430272
Short name T1125
Test name
Test status
Simulation time 231502850 ps
CPU time 6.03 seconds
Started Jun 04 03:04:05 PM PDT 24
Finished Jun 04 03:04:12 PM PDT 24
Peak memory 242544 kb
Host smart-5e3612e8-d7a0-42f5-ac01-cda0f10090ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613430272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.1613430272
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.2590161212
Short name T1202
Test name
Test status
Simulation time 871103187 ps
CPU time 19.03 seconds
Started Jun 04 03:04:12 PM PDT 24
Finished Jun 04 03:04:32 PM PDT 24
Peak memory 242220 kb
Host smart-ab664d03-592d-4ced-aa4c-5686314ce93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590161212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.2590161212
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.2898875853
Short name T669
Test name
Test status
Simulation time 147339097 ps
CPU time 4.42 seconds
Started Jun 04 03:04:11 PM PDT 24
Finished Jun 04 03:04:15 PM PDT 24
Peak memory 242664 kb
Host smart-5fd8cb72-59d7-4ad8-b1dd-9fa37511e4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898875853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.2898875853
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.1547111303
Short name T630
Test name
Test status
Simulation time 10111488795 ps
CPU time 26.58 seconds
Started Jun 04 03:04:07 PM PDT 24
Finished Jun 04 03:04:34 PM PDT 24
Peak memory 248976 kb
Host smart-9ec8a02a-f607-4ae8-a8d3-6e6cb7f4df70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547111303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.1547111303
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.2775207987
Short name T162
Test name
Test status
Simulation time 115917815 ps
CPU time 3.92 seconds
Started Jun 04 03:04:11 PM PDT 24
Finished Jun 04 03:04:16 PM PDT 24
Peak memory 242616 kb
Host smart-e9e519fa-53c8-4edb-aba8-f8617e45636b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775207987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.2775207987
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.1543792347
Short name T493
Test name
Test status
Simulation time 377868298 ps
CPU time 8.82 seconds
Started Jun 04 03:04:11 PM PDT 24
Finished Jun 04 03:04:21 PM PDT 24
Peak memory 242532 kb
Host smart-59f71872-52bb-4254-ac70-5e95b1f9a5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543792347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.1543792347
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.316753363
Short name T424
Test name
Test status
Simulation time 88161331 ps
CPU time 1.66 seconds
Started Jun 04 03:00:39 PM PDT 24
Finished Jun 04 03:00:42 PM PDT 24
Peak memory 241264 kb
Host smart-e467a514-b73e-44ec-8988-71a3190b43e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316753363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.316753363
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.1824497666
Short name T69
Test name
Test status
Simulation time 1432797905 ps
CPU time 14.01 seconds
Started Jun 04 03:00:42 PM PDT 24
Finished Jun 04 03:00:57 PM PDT 24
Peak memory 243004 kb
Host smart-119a6b27-83a9-403a-9379-a4b7698cb3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824497666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.1824497666
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.276233433
Short name T1137
Test name
Test status
Simulation time 310467895 ps
CPU time 8.56 seconds
Started Jun 04 03:00:39 PM PDT 24
Finished Jun 04 03:00:49 PM PDT 24
Peak memory 242400 kb
Host smart-d98637e9-2007-4f1c-9478-98a694c4dc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276233433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.276233433
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.2962287743
Short name T973
Test name
Test status
Simulation time 882495245 ps
CPU time 15.87 seconds
Started Jun 04 03:00:49 PM PDT 24
Finished Jun 04 03:01:07 PM PDT 24
Peak memory 242564 kb
Host smart-9784f426-0b06-4dcb-bbb5-99411c4f189c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962287743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.2962287743
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.4099225174
Short name T1046
Test name
Test status
Simulation time 132769401 ps
CPU time 3.62 seconds
Started Jun 04 03:00:49 PM PDT 24
Finished Jun 04 03:00:55 PM PDT 24
Peak memory 242708 kb
Host smart-d42f76b2-016a-481c-9619-334c249ae83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099225174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.4099225174
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.154695844
Short name T1067
Test name
Test status
Simulation time 1956201832 ps
CPU time 53.41 seconds
Started Jun 04 03:00:40 PM PDT 24
Finished Jun 04 03:01:34 PM PDT 24
Peak memory 257212 kb
Host smart-afdf0101-64b2-46bd-9916-4f9b1c4aaffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154695844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.154695844
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.2773094753
Short name T862
Test name
Test status
Simulation time 1169572415 ps
CPU time 26.57 seconds
Started Jun 04 03:00:40 PM PDT 24
Finished Jun 04 03:01:07 PM PDT 24
Peak memory 242564 kb
Host smart-ee767a89-1ce3-4ed5-816d-04f54fd1d82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773094753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.2773094753
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.548055858
Short name T503
Test name
Test status
Simulation time 252830979 ps
CPU time 5.2 seconds
Started Jun 04 03:00:49 PM PDT 24
Finished Jun 04 03:00:56 PM PDT 24
Peak memory 241856 kb
Host smart-2494a976-fcb8-42a3-bcdf-74d3706c8ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548055858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.548055858
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.743418725
Short name T1030
Test name
Test status
Simulation time 2706599472 ps
CPU time 20.95 seconds
Started Jun 04 03:00:42 PM PDT 24
Finished Jun 04 03:01:04 PM PDT 24
Peak memory 242292 kb
Host smart-e3c30bde-59e7-4260-83c2-c8fe3cbaf3f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=743418725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.743418725
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.3031854601
Short name T1111
Test name
Test status
Simulation time 255888839 ps
CPU time 3.53 seconds
Started Jun 04 03:00:49 PM PDT 24
Finished Jun 04 03:00:54 PM PDT 24
Peak memory 242260 kb
Host smart-6caf3651-9853-4113-9e01-d96ed01506a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3031854601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.3031854601
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.1921814765
Short name T732
Test name
Test status
Simulation time 1849523804 ps
CPU time 12.75 seconds
Started Jun 04 03:00:40 PM PDT 24
Finished Jun 04 03:00:54 PM PDT 24
Peak memory 242244 kb
Host smart-ca85e518-d614-4bfc-9aef-b72bd6e1701b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921814765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.1921814765
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.1423035363
Short name T1165
Test name
Test status
Simulation time 209199208 ps
CPU time 3.76 seconds
Started Jun 04 03:00:39 PM PDT 24
Finished Jun 04 03:00:44 PM PDT 24
Peak memory 242260 kb
Host smart-ac0f7e5d-d005-42a2-b728-522c27f9d6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423035363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.1423035363
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.3226429906
Short name T752
Test name
Test status
Simulation time 290433405 ps
CPU time 4.22 seconds
Started Jun 04 03:04:12 PM PDT 24
Finished Jun 04 03:04:17 PM PDT 24
Peak memory 242584 kb
Host smart-4a2cbb34-99c4-427a-83d7-8d49c1ce3c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226429906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.3226429906
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.3562246507
Short name T710
Test name
Test status
Simulation time 569017245 ps
CPU time 4.84 seconds
Started Jun 04 03:04:07 PM PDT 24
Finished Jun 04 03:04:12 PM PDT 24
Peak memory 242348 kb
Host smart-3949c612-74f1-4c15-a45c-4ae577ab84e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562246507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.3562246507
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.255100525
Short name T614
Test name
Test status
Simulation time 504753537 ps
CPU time 4.01 seconds
Started Jun 04 03:04:12 PM PDT 24
Finished Jun 04 03:04:17 PM PDT 24
Peak memory 242364 kb
Host smart-b4d716c2-0a4f-43cc-845b-bb688c336bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255100525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.255100525
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.3927102171
Short name T227
Test name
Test status
Simulation time 449771234 ps
CPU time 12.31 seconds
Started Jun 04 03:04:11 PM PDT 24
Finished Jun 04 03:04:24 PM PDT 24
Peak memory 242588 kb
Host smart-12335134-7666-4093-94cd-311602ac967b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927102171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.3927102171
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.2723271586
Short name T840
Test name
Test status
Simulation time 246240281 ps
CPU time 3.81 seconds
Started Jun 04 03:04:06 PM PDT 24
Finished Jun 04 03:04:11 PM PDT 24
Peak memory 242676 kb
Host smart-80f8de8a-7404-4a51-98fd-64eecbef2f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723271586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.2723271586
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.2098107996
Short name T505
Test name
Test status
Simulation time 176038037 ps
CPU time 8.77 seconds
Started Jun 04 03:04:11 PM PDT 24
Finished Jun 04 03:04:21 PM PDT 24
Peak memory 242152 kb
Host smart-fc4c5b05-15ac-4c53-9ca1-b68d49ec3e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098107996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.2098107996
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.3507573724
Short name T765
Test name
Test status
Simulation time 253416118 ps
CPU time 4.44 seconds
Started Jun 04 03:04:16 PM PDT 24
Finished Jun 04 03:04:22 PM PDT 24
Peak memory 242656 kb
Host smart-4a49ed17-f997-4544-874f-d930ddfec279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507573724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.3507573724
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.2121825655
Short name T771
Test name
Test status
Simulation time 1297702735 ps
CPU time 4.91 seconds
Started Jun 04 03:04:15 PM PDT 24
Finished Jun 04 03:04:21 PM PDT 24
Peak memory 241960 kb
Host smart-897eefa2-f690-413f-b9e0-7a43167c399e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121825655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.2121825655
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.1118147370
Short name T685
Test name
Test status
Simulation time 166954339 ps
CPU time 4.52 seconds
Started Jun 04 03:04:13 PM PDT 24
Finished Jun 04 03:04:18 PM PDT 24
Peak memory 242680 kb
Host smart-16b99b29-d188-4fcf-906f-78f06d5b71f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118147370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.1118147370
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.183828483
Short name T960
Test name
Test status
Simulation time 1845229500 ps
CPU time 25.23 seconds
Started Jun 04 03:04:17 PM PDT 24
Finished Jun 04 03:04:43 PM PDT 24
Peak memory 242160 kb
Host smart-648bf468-9892-4f2c-8414-e6bf9b4ce888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183828483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.183828483
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.1277519031
Short name T451
Test name
Test status
Simulation time 1317657846 ps
CPU time 3.5 seconds
Started Jun 04 03:04:13 PM PDT 24
Finished Jun 04 03:04:17 PM PDT 24
Peak memory 242560 kb
Host smart-6299453c-c1a6-4585-9f2d-9a98e8a374b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277519031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.1277519031
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.3903893002
Short name T510
Test name
Test status
Simulation time 252013053 ps
CPU time 3.51 seconds
Started Jun 04 03:04:14 PM PDT 24
Finished Jun 04 03:04:18 PM PDT 24
Peak memory 242772 kb
Host smart-e705409a-7778-40ad-8fca-224e4cd7a948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903893002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.3903893002
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.2342595640
Short name T828
Test name
Test status
Simulation time 337734093 ps
CPU time 10.1 seconds
Started Jun 04 03:04:15 PM PDT 24
Finished Jun 04 03:04:26 PM PDT 24
Peak memory 242664 kb
Host smart-754458f7-63f8-40dc-9fd8-b4b289819993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342595640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.2342595640
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.1904337716
Short name T874
Test name
Test status
Simulation time 448885012 ps
CPU time 3.76 seconds
Started Jun 04 03:04:15 PM PDT 24
Finished Jun 04 03:04:19 PM PDT 24
Peak memory 242660 kb
Host smart-3f2b5d98-09ea-48d1-ab0d-87772eb3777f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904337716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.1904337716
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.3604574175
Short name T578
Test name
Test status
Simulation time 3570862161 ps
CPU time 33.09 seconds
Started Jun 04 03:04:16 PM PDT 24
Finished Jun 04 03:04:50 PM PDT 24
Peak memory 242320 kb
Host smart-e7940b7d-dd4e-4f4d-bac6-201322bf848f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604574175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.3604574175
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.1371726408
Short name T57
Test name
Test status
Simulation time 150958484 ps
CPU time 3.64 seconds
Started Jun 04 03:04:22 PM PDT 24
Finished Jun 04 03:04:26 PM PDT 24
Peak memory 242356 kb
Host smart-cb5f4b18-74f0-4979-ab36-e98b3ddde1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371726408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.1371726408
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.3494154957
Short name T479
Test name
Test status
Simulation time 409734592 ps
CPU time 12.93 seconds
Started Jun 04 03:04:21 PM PDT 24
Finished Jun 04 03:04:35 PM PDT 24
Peak memory 242260 kb
Host smart-548cc054-c023-4d47-987d-f219cb000cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494154957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.3494154957
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.4086677432
Short name T544
Test name
Test status
Simulation time 167809364 ps
CPU time 4.43 seconds
Started Jun 04 03:04:14 PM PDT 24
Finished Jun 04 03:04:20 PM PDT 24
Peak memory 242348 kb
Host smart-903a22ec-b795-4a0c-ac71-428b0593751c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086677432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.4086677432
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.3240357546
Short name T658
Test name
Test status
Simulation time 101186604 ps
CPU time 3.99 seconds
Started Jun 04 03:04:11 PM PDT 24
Finished Jun 04 03:04:16 PM PDT 24
Peak memory 242564 kb
Host smart-df597f17-5543-44be-9612-682f758867e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240357546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.3240357546
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.3159164013
Short name T851
Test name
Test status
Simulation time 98172216 ps
CPU time 1.61 seconds
Started Jun 04 03:00:42 PM PDT 24
Finished Jun 04 03:00:44 PM PDT 24
Peak memory 240684 kb
Host smart-c6ac8ff4-c7df-482b-b025-5a6f11736f46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159164013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.3159164013
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.1145133277
Short name T546
Test name
Test status
Simulation time 497077413 ps
CPU time 16.67 seconds
Started Jun 04 03:00:42 PM PDT 24
Finished Jun 04 03:01:00 PM PDT 24
Peak memory 242280 kb
Host smart-74f95af8-2cd1-4371-a432-594677d7ef40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145133277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.1145133277
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.984170885
Short name T481
Test name
Test status
Simulation time 812254691 ps
CPU time 5.91 seconds
Started Jun 04 03:00:42 PM PDT 24
Finished Jun 04 03:00:49 PM PDT 24
Peak memory 242232 kb
Host smart-e78c4f9b-8c68-4e47-93c1-47844300473c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984170885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.984170885
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.3891312798
Short name T46
Test name
Test status
Simulation time 1837908312 ps
CPU time 7.29 seconds
Started Jun 04 03:00:41 PM PDT 24
Finished Jun 04 03:00:50 PM PDT 24
Peak memory 242300 kb
Host smart-3b8180f9-8504-4246-9d4f-06f6027edf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891312798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.3891312798
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.2638019003
Short name T898
Test name
Test status
Simulation time 2604218683 ps
CPU time 35.85 seconds
Started Jun 04 03:00:42 PM PDT 24
Finished Jun 04 03:01:19 PM PDT 24
Peak memory 261556 kb
Host smart-d675c6a8-856d-41bc-be37-4a9ff2c0148c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638019003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.2638019003
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.454066705
Short name T1098
Test name
Test status
Simulation time 317333489 ps
CPU time 7.69 seconds
Started Jun 04 03:00:42 PM PDT 24
Finished Jun 04 03:00:51 PM PDT 24
Peak memory 242508 kb
Host smart-80682358-ed5d-4f6d-99db-d921915a69db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454066705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.454066705
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.3079528691
Short name T257
Test name
Test status
Simulation time 6701366247 ps
CPU time 13.97 seconds
Started Jun 04 03:00:41 PM PDT 24
Finished Jun 04 03:00:55 PM PDT 24
Peak memory 242388 kb
Host smart-8e42ce0d-ff50-4173-a4bf-4ffba6ca9a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079528691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.3079528691
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.1026711986
Short name T800
Test name
Test status
Simulation time 292552860 ps
CPU time 9.75 seconds
Started Jun 04 03:00:41 PM PDT 24
Finished Jun 04 03:00:52 PM PDT 24
Peak memory 242220 kb
Host smart-3967f30e-c3ff-49d1-9a84-757f3c756387
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1026711986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.1026711986
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.1090256113
Short name T371
Test name
Test status
Simulation time 266391248 ps
CPU time 8.9 seconds
Started Jun 04 03:00:40 PM PDT 24
Finished Jun 04 03:00:50 PM PDT 24
Peak memory 242164 kb
Host smart-adc7f188-c77e-4146-8758-8c2eee822949
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1090256113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.1090256113
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.1790925468
Short name T442
Test name
Test status
Simulation time 1052647013 ps
CPU time 8.6 seconds
Started Jun 04 03:00:42 PM PDT 24
Finished Jun 04 03:00:52 PM PDT 24
Peak memory 248724 kb
Host smart-eb196e5d-2cfc-4ff3-99c5-3251ea98bdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790925468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.1790925468
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.2545052641
Short name T217
Test name
Test status
Simulation time 31928115045 ps
CPU time 250.08 seconds
Started Jun 04 03:00:41 PM PDT 24
Finished Jun 04 03:04:52 PM PDT 24
Peak memory 275228 kb
Host smart-ee6c2f5b-9213-41e4-939b-29894d3bd55e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545052641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.2545052641
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.1540633012
Short name T333
Test name
Test status
Simulation time 48736886261 ps
CPU time 1095.44 seconds
Started Jun 04 03:00:43 PM PDT 24
Finished Jun 04 03:18:59 PM PDT 24
Peak memory 279636 kb
Host smart-00477e89-58e5-4c9e-a220-8fb6e49b2ddb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540633012 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.1540633012
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.826054351
Short name T10
Test name
Test status
Simulation time 30825676837 ps
CPU time 37.38 seconds
Started Jun 04 03:00:41 PM PDT 24
Finished Jun 04 03:01:19 PM PDT 24
Peak memory 248972 kb
Host smart-fbbaa6a8-8d79-4ff6-b05b-1e81b6c52ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826054351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.826054351
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.3579644183
Short name T839
Test name
Test status
Simulation time 89671319 ps
CPU time 3.56 seconds
Started Jun 04 03:04:13 PM PDT 24
Finished Jun 04 03:04:17 PM PDT 24
Peak memory 242484 kb
Host smart-f83cc509-c0d4-426e-80f9-f4629c0f63d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579644183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.3579644183
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.1446298611
Short name T1186
Test name
Test status
Simulation time 214435153 ps
CPU time 4.92 seconds
Started Jun 04 03:04:19 PM PDT 24
Finished Jun 04 03:04:24 PM PDT 24
Peak memory 242300 kb
Host smart-b5c86a08-ad13-432a-a882-b88b6d8afea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446298611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.1446298611
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.1143206999
Short name T1172
Test name
Test status
Simulation time 115666952 ps
CPU time 3.38 seconds
Started Jun 04 03:04:22 PM PDT 24
Finished Jun 04 03:04:26 PM PDT 24
Peak memory 242356 kb
Host smart-d4a8a68f-5f77-4040-a577-ed7163d1b460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143206999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.1143206999
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.1098096432
Short name T736
Test name
Test status
Simulation time 1136897535 ps
CPU time 3.6 seconds
Started Jun 04 03:04:18 PM PDT 24
Finished Jun 04 03:04:22 PM PDT 24
Peak memory 246804 kb
Host smart-6390c36e-d7e0-4704-b539-65b06190a574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098096432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.1098096432
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.1291736006
Short name T525
Test name
Test status
Simulation time 203164781 ps
CPU time 4.51 seconds
Started Jun 04 03:04:22 PM PDT 24
Finished Jun 04 03:04:27 PM PDT 24
Peak memory 242428 kb
Host smart-cbffef5a-ca06-4f2a-b120-c0c14c7be8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291736006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.1291736006
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.130741222
Short name T1006
Test name
Test status
Simulation time 376031633 ps
CPU time 4.69 seconds
Started Jun 04 03:04:15 PM PDT 24
Finished Jun 04 03:04:20 PM PDT 24
Peak memory 242260 kb
Host smart-514dac65-4790-4e64-a841-d70fed978602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130741222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.130741222
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.1893791438
Short name T1065
Test name
Test status
Simulation time 115953803 ps
CPU time 4.82 seconds
Started Jun 04 03:04:14 PM PDT 24
Finished Jun 04 03:04:19 PM PDT 24
Peak memory 242304 kb
Host smart-4803f47a-2f48-48fb-bfbd-c24704909b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893791438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.1893791438
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.1577656029
Short name T719
Test name
Test status
Simulation time 605202434 ps
CPU time 9.99 seconds
Started Jun 04 03:04:15 PM PDT 24
Finished Jun 04 03:04:26 PM PDT 24
Peak memory 242208 kb
Host smart-00aac9d9-9013-4975-90f1-bf17de355a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577656029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.1577656029
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.3657564391
Short name T477
Test name
Test status
Simulation time 918814703 ps
CPU time 17.49 seconds
Started Jun 04 03:04:14 PM PDT 24
Finished Jun 04 03:04:32 PM PDT 24
Peak memory 242416 kb
Host smart-58c29dc7-5fb1-49e1-92bf-d8ec671b6e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657564391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.3657564391
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.2146931067
Short name T573
Test name
Test status
Simulation time 319572812 ps
CPU time 4.57 seconds
Started Jun 04 03:04:12 PM PDT 24
Finished Jun 04 03:04:17 PM PDT 24
Peak memory 242540 kb
Host smart-e32e1459-dc6f-4354-8944-37768f47c4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146931067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.2146931067
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.1602732447
Short name T791
Test name
Test status
Simulation time 510365859 ps
CPU time 13.43 seconds
Started Jun 04 03:04:19 PM PDT 24
Finished Jun 04 03:04:33 PM PDT 24
Peak memory 242372 kb
Host smart-8584a172-8797-426d-a5b8-dc1173cac8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602732447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.1602732447
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.1807920024
Short name T204
Test name
Test status
Simulation time 177045583 ps
CPU time 3.99 seconds
Started Jun 04 03:04:15 PM PDT 24
Finished Jun 04 03:04:19 PM PDT 24
Peak memory 242356 kb
Host smart-c8e2bb44-a90d-4246-8ac2-5d25d18391f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807920024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.1807920024
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.2546647698
Short name T788
Test name
Test status
Simulation time 263560364 ps
CPU time 8.03 seconds
Started Jun 04 03:04:22 PM PDT 24
Finished Jun 04 03:04:31 PM PDT 24
Peak memory 242268 kb
Host smart-d64656ee-bed8-4a25-965e-ada3630b250b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546647698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.2546647698
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.2665973973
Short name T1138
Test name
Test status
Simulation time 1957498007 ps
CPU time 5.15 seconds
Started Jun 04 03:04:12 PM PDT 24
Finished Jun 04 03:04:18 PM PDT 24
Peak memory 242408 kb
Host smart-e344b4b1-cebe-48f7-8ffe-2cd025f22aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665973973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.2665973973
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.306386515
Short name T1081
Test name
Test status
Simulation time 165658441 ps
CPU time 4.18 seconds
Started Jun 04 03:04:18 PM PDT 24
Finished Jun 04 03:04:23 PM PDT 24
Peak memory 242492 kb
Host smart-0539f261-2355-432b-b107-9d8d6ce3b17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306386515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.306386515
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.3267706752
Short name T1060
Test name
Test status
Simulation time 262511353 ps
CPU time 3.96 seconds
Started Jun 04 03:04:21 PM PDT 24
Finished Jun 04 03:04:26 PM PDT 24
Peak memory 242456 kb
Host smart-6677dbd9-bf3d-4398-8d81-cd7069f67218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267706752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.3267706752
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.1070153229
Short name T908
Test name
Test status
Simulation time 889479034 ps
CPU time 6.39 seconds
Started Jun 04 03:04:13 PM PDT 24
Finished Jun 04 03:04:20 PM PDT 24
Peak memory 242508 kb
Host smart-04cb2d90-68c3-4e13-a3cf-5ed39544241d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070153229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.1070153229
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.1091635542
Short name T1048
Test name
Test status
Simulation time 484484343 ps
CPU time 5.74 seconds
Started Jun 04 03:04:15 PM PDT 24
Finished Jun 04 03:04:22 PM PDT 24
Peak memory 242228 kb
Host smart-beda3e87-9f50-40d4-81f9-bb48670473b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091635542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.1091635542
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.946577774
Short name T230
Test name
Test status
Simulation time 692812493 ps
CPU time 10.96 seconds
Started Jun 04 03:04:17 PM PDT 24
Finished Jun 04 03:04:29 PM PDT 24
Peak memory 242228 kb
Host smart-6b3e0668-455b-463f-b248-b387db45025a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946577774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.946577774
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.3685744423
Short name T406
Test name
Test status
Simulation time 106903304 ps
CPU time 1.77 seconds
Started Jun 04 03:00:50 PM PDT 24
Finished Jun 04 03:00:54 PM PDT 24
Peak memory 241236 kb
Host smart-cd8e0cc0-20f0-47bf-9e5f-e83ede0cd54b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685744423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.3685744423
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.4073846971
Short name T400
Test name
Test status
Simulation time 661536576 ps
CPU time 21.39 seconds
Started Jun 04 03:00:52 PM PDT 24
Finished Jun 04 03:01:14 PM PDT 24
Peak memory 242272 kb
Host smart-cabb00e6-3a29-4325-9082-a43e853f5e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073846971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.4073846971
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.3218969418
Short name T946
Test name
Test status
Simulation time 9062329735 ps
CPU time 69.98 seconds
Started Jun 04 03:00:50 PM PDT 24
Finished Jun 04 03:02:02 PM PDT 24
Peak memory 243944 kb
Host smart-8ea6bea4-b701-4086-9087-f4eb2fc47872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218969418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.3218969418
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.934345787
Short name T423
Test name
Test status
Simulation time 252124212 ps
CPU time 3.57 seconds
Started Jun 04 03:00:51 PM PDT 24
Finished Jun 04 03:00:56 PM PDT 24
Peak memory 242456 kb
Host smart-28f3021b-e131-493e-b512-5d156d026eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934345787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.934345787
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.989306145
Short name T703
Test name
Test status
Simulation time 1090890489 ps
CPU time 18.48 seconds
Started Jun 04 03:00:52 PM PDT 24
Finished Jun 04 03:01:11 PM PDT 24
Peak memory 242228 kb
Host smart-b8b26f33-4499-46bc-bb9b-5085e8a3820e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989306145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.989306145
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.4146811025
Short name T792
Test name
Test status
Simulation time 818621117 ps
CPU time 28.12 seconds
Started Jun 04 03:00:52 PM PDT 24
Finished Jun 04 03:01:21 PM PDT 24
Peak memory 242208 kb
Host smart-b2e7cdeb-afed-436d-89a2-abba4d5da3a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4146811025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.4146811025
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.1647786837
Short name T790
Test name
Test status
Simulation time 326340681 ps
CPU time 9.59 seconds
Started Jun 04 03:00:51 PM PDT 24
Finished Jun 04 03:01:02 PM PDT 24
Peak memory 242160 kb
Host smart-1a1af852-bf2d-403b-bcea-3bfd3b230c6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647786837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.1647786837
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.2641336688
Short name T670
Test name
Test status
Simulation time 276734935 ps
CPU time 4.1 seconds
Started Jun 04 03:00:50 PM PDT 24
Finished Jun 04 03:00:56 PM PDT 24
Peak memory 242216 kb
Host smart-d37c7c24-400c-48a8-a17b-793edfe77766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641336688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.2641336688
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.1970033619
Short name T112
Test name
Test status
Simulation time 23946051530 ps
CPU time 196.83 seconds
Started Jun 04 03:00:52 PM PDT 24
Finished Jun 04 03:04:10 PM PDT 24
Peak memory 257592 kb
Host smart-a1f2e6dc-e14f-4801-83d5-ebb151a75663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970033619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.1970033619
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.2195624341
Short name T292
Test name
Test status
Simulation time 149506166567 ps
CPU time 1896.19 seconds
Started Jun 04 03:00:49 PM PDT 24
Finished Jun 04 03:32:28 PM PDT 24
Peak memory 384320 kb
Host smart-489356a1-95b8-420e-8a1b-fdf8363442bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195624341 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.2195624341
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.1758052586
Short name T1198
Test name
Test status
Simulation time 2966997436 ps
CPU time 5.28 seconds
Started Jun 04 03:00:52 PM PDT 24
Finished Jun 04 03:00:58 PM PDT 24
Peak memory 248828 kb
Host smart-0f6e8f01-6801-4f53-8477-f2c1dfe273fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758052586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.1758052586
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.185383057
Short name T1073
Test name
Test status
Simulation time 1485643610 ps
CPU time 4.78 seconds
Started Jun 04 03:04:13 PM PDT 24
Finished Jun 04 03:04:18 PM PDT 24
Peak memory 242340 kb
Host smart-f64c5833-46d2-499f-978f-d4dbc0bbaec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185383057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.185383057
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.802455228
Short name T455
Test name
Test status
Simulation time 437709511 ps
CPU time 6.6 seconds
Started Jun 04 03:04:15 PM PDT 24
Finished Jun 04 03:04:23 PM PDT 24
Peak memory 242412 kb
Host smart-bed32c92-5f82-4f43-b4f9-98dae87bdd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802455228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.802455228
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.1132552357
Short name T500
Test name
Test status
Simulation time 111367187 ps
CPU time 3.97 seconds
Started Jun 04 03:04:17 PM PDT 24
Finished Jun 04 03:04:22 PM PDT 24
Peak memory 242676 kb
Host smart-f7b585ed-42d6-453b-952d-73771348c50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132552357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.1132552357
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.90888994
Short name T591
Test name
Test status
Simulation time 228063238 ps
CPU time 9.99 seconds
Started Jun 04 03:04:12 PM PDT 24
Finished Jun 04 03:04:23 PM PDT 24
Peak memory 242344 kb
Host smart-24e6cf1f-9171-4059-bf70-3b174aeb6b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90888994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.90888994
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.3987602772
Short name T558
Test name
Test status
Simulation time 2739556634 ps
CPU time 6.61 seconds
Started Jun 04 03:04:23 PM PDT 24
Finished Jun 04 03:04:31 PM PDT 24
Peak memory 242416 kb
Host smart-5268c318-bd45-427e-b029-20aa0fc378aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987602772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.3987602772
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.838297061
Short name T29
Test name
Test status
Simulation time 249004097 ps
CPU time 5.37 seconds
Started Jun 04 03:04:22 PM PDT 24
Finished Jun 04 03:04:28 PM PDT 24
Peak memory 242368 kb
Host smart-5a21f558-cb4e-4d10-bd79-c027bd898eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838297061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.838297061
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.2296044260
Short name T266
Test name
Test status
Simulation time 195892685 ps
CPU time 5.59 seconds
Started Jun 04 03:04:25 PM PDT 24
Finished Jun 04 03:04:31 PM PDT 24
Peak memory 242376 kb
Host smart-39c5b626-9e1d-46ed-8369-d3cedec5d38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296044260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.2296044260
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.2240963959
Short name T164
Test name
Test status
Simulation time 112919516 ps
CPU time 3.33 seconds
Started Jun 04 03:04:22 PM PDT 24
Finished Jun 04 03:04:26 PM PDT 24
Peak memory 242528 kb
Host smart-f0aa503d-8c63-4750-940c-a2bc07b5656d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240963959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.2240963959
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.3926498268
Short name T761
Test name
Test status
Simulation time 595658929 ps
CPU time 16.21 seconds
Started Jun 04 03:04:22 PM PDT 24
Finished Jun 04 03:04:39 PM PDT 24
Peak memory 242312 kb
Host smart-983178d1-7182-4f57-a1ba-bcea6af2a2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926498268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.3926498268
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.2992077703
Short name T575
Test name
Test status
Simulation time 144646279 ps
CPU time 4.21 seconds
Started Jun 04 03:04:23 PM PDT 24
Finished Jun 04 03:04:28 PM PDT 24
Peak memory 242668 kb
Host smart-13c07d38-b66b-4d07-bf94-794ce5136bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992077703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.2992077703
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.815639455
Short name T1189
Test name
Test status
Simulation time 445237546 ps
CPU time 6.41 seconds
Started Jun 04 03:04:22 PM PDT 24
Finished Jun 04 03:04:29 PM PDT 24
Peak memory 242568 kb
Host smart-8221716d-88da-4f8a-b0d6-55754f019159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815639455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.815639455
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.1271693846
Short name T555
Test name
Test status
Simulation time 145640916 ps
CPU time 4.45 seconds
Started Jun 04 03:04:21 PM PDT 24
Finished Jun 04 03:04:27 PM PDT 24
Peak memory 242412 kb
Host smart-468cb428-f5c9-4f26-94b7-ae4c8308658d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271693846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.1271693846
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.200332066
Short name T994
Test name
Test status
Simulation time 504074172 ps
CPU time 13.15 seconds
Started Jun 04 03:04:25 PM PDT 24
Finished Jun 04 03:04:39 PM PDT 24
Peak memory 242228 kb
Host smart-7218fa26-0502-4da0-bae5-aabcc88af443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200332066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.200332066
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.3852979309
Short name T1181
Test name
Test status
Simulation time 249825287 ps
CPU time 3.63 seconds
Started Jun 04 03:04:24 PM PDT 24
Finished Jun 04 03:04:29 PM PDT 24
Peak memory 242728 kb
Host smart-ffa03b6a-9864-4f6e-8f87-8f09c8f59ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852979309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.3852979309
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.336960116
Short name T754
Test name
Test status
Simulation time 2835237346 ps
CPU time 7.72 seconds
Started Jun 04 03:04:26 PM PDT 24
Finished Jun 04 03:04:34 PM PDT 24
Peak memory 242260 kb
Host smart-f0cea53f-d2a8-454a-a728-65f2aea96f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336960116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.336960116
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.1653365782
Short name T884
Test name
Test status
Simulation time 215759384 ps
CPU time 4.2 seconds
Started Jun 04 03:04:24 PM PDT 24
Finished Jun 04 03:04:28 PM PDT 24
Peak memory 242684 kb
Host smart-0b4df317-db0d-4cb7-b25c-bc6bdfdefa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653365782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.1653365782
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.3197072176
Short name T692
Test name
Test status
Simulation time 98558624 ps
CPU time 2.99 seconds
Started Jun 04 03:04:24 PM PDT 24
Finished Jun 04 03:04:28 PM PDT 24
Peak memory 242220 kb
Host smart-7fda93ca-e26a-4454-8f44-9c2fd3a469b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197072176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.3197072176
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.3895400868
Short name T1085
Test name
Test status
Simulation time 235556262 ps
CPU time 4.56 seconds
Started Jun 04 03:04:24 PM PDT 24
Finished Jun 04 03:04:29 PM PDT 24
Peak memory 242360 kb
Host smart-8ea49ef4-7e71-408b-9acd-8db0dec97bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895400868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.3895400868
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.1736159187
Short name T448
Test name
Test status
Simulation time 122503282 ps
CPU time 2.48 seconds
Started Jun 04 02:59:14 PM PDT 24
Finished Jun 04 02:59:17 PM PDT 24
Peak memory 241080 kb
Host smart-717065fe-285a-402a-baf5-d15e42d314f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736159187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.1736159187
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.3334307782
Short name T426
Test name
Test status
Simulation time 652702176 ps
CPU time 12.43 seconds
Started Jun 04 02:59:08 PM PDT 24
Finished Jun 04 02:59:21 PM PDT 24
Peak memory 242812 kb
Host smart-847669fe-7de3-44f7-99db-7980bdfa1d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334307782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.3334307782
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.610451335
Short name T58
Test name
Test status
Simulation time 7441713737 ps
CPU time 18.8 seconds
Started Jun 04 02:59:07 PM PDT 24
Finished Jun 04 02:59:27 PM PDT 24
Peak memory 243672 kb
Host smart-780d5586-4dc9-4ee8-8365-03197ec9ddc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610451335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.610451335
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.25247713
Short name T883
Test name
Test status
Simulation time 17669814638 ps
CPU time 45.91 seconds
Started Jun 04 02:59:07 PM PDT 24
Finished Jun 04 02:59:53 PM PDT 24
Peak memory 248472 kb
Host smart-1816d206-4e0a-472c-8b1b-97f70b174c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25247713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.25247713
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.694678940
Short name T585
Test name
Test status
Simulation time 1810878293 ps
CPU time 23.48 seconds
Started Jun 04 02:59:06 PM PDT 24
Finished Jun 04 02:59:30 PM PDT 24
Peak memory 248896 kb
Host smart-77f47766-698c-420c-b45f-3844dee269ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694678940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.694678940
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.782320485
Short name T907
Test name
Test status
Simulation time 178265416 ps
CPU time 4.05 seconds
Started Jun 04 02:59:08 PM PDT 24
Finished Jun 04 02:59:13 PM PDT 24
Peak memory 242464 kb
Host smart-15c1f977-8010-4ed4-a1f0-12ecd852aec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782320485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.782320485
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.4050939056
Short name T1078
Test name
Test status
Simulation time 1980522761 ps
CPU time 35.96 seconds
Started Jun 04 02:59:06 PM PDT 24
Finished Jun 04 02:59:42 PM PDT 24
Peak memory 248952 kb
Host smart-50637ae0-7c15-4af6-acdf-a1fece555e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050939056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.4050939056
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.3914075198
Short name T871
Test name
Test status
Simulation time 2161253130 ps
CPU time 27.15 seconds
Started Jun 04 02:59:07 PM PDT 24
Finished Jun 04 02:59:35 PM PDT 24
Peak memory 242536 kb
Host smart-d9b7dd0c-e01d-44f8-a2d3-1452c5fcafac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914075198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.3914075198
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.2739751055
Short name T271
Test name
Test status
Simulation time 2428253869 ps
CPU time 8.47 seconds
Started Jun 04 02:59:05 PM PDT 24
Finished Jun 04 02:59:14 PM PDT 24
Peak memory 242176 kb
Host smart-538871a9-a665-41ba-abbf-36fe2bd13f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739751055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.2739751055
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.1292030302
Short name T220
Test name
Test status
Simulation time 272158196 ps
CPU time 6.85 seconds
Started Jun 04 02:59:06 PM PDT 24
Finished Jun 04 02:59:14 PM PDT 24
Peak memory 242328 kb
Host smart-3ed7c56a-48a4-4b65-a65e-948335d6550d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1292030302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.1292030302
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.3929809594
Short name T369
Test name
Test status
Simulation time 148766008 ps
CPU time 4.75 seconds
Started Jun 04 02:59:08 PM PDT 24
Finished Jun 04 02:59:13 PM PDT 24
Peak memory 248876 kb
Host smart-2559cc8c-f62a-490f-80f5-1f97324c9b3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3929809594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.3929809594
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.3899303118
Short name T248
Test name
Test status
Simulation time 39644906577 ps
CPU time 185.14 seconds
Started Jun 04 02:59:16 PM PDT 24
Finished Jun 04 03:02:22 PM PDT 24
Peak memory 263200 kb
Host smart-74e0cea1-4916-4a5e-a64e-f8d7101b298c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899303118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.3899303118
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.4100302419
Short name T562
Test name
Test status
Simulation time 321931317 ps
CPU time 5.29 seconds
Started Jun 04 02:59:06 PM PDT 24
Finished Jun 04 02:59:12 PM PDT 24
Peak memory 242008 kb
Host smart-b1f3f777-5722-4380-a85a-2d31909d4624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100302419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.4100302419
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.4080885846
Short name T701
Test name
Test status
Simulation time 12648514038 ps
CPU time 173.48 seconds
Started Jun 04 02:59:15 PM PDT 24
Finished Jun 04 03:02:10 PM PDT 24
Peak memory 273680 kb
Host smart-7ca7c34f-a2b9-41f4-9d63-19b2b2a0f275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080885846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.
4080885846
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.1875497619
Short name T1058
Test name
Test status
Simulation time 185387341 ps
CPU time 4.82 seconds
Started Jun 04 02:59:07 PM PDT 24
Finished Jun 04 02:59:13 PM PDT 24
Peak memory 248796 kb
Host smart-ef370d36-7d64-45e5-aca8-414035b08bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875497619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.1875497619
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.3838388075
Short name T246
Test name
Test status
Simulation time 77543120 ps
CPU time 2.03 seconds
Started Jun 04 03:00:50 PM PDT 24
Finished Jun 04 03:00:54 PM PDT 24
Peak memory 240748 kb
Host smart-deed0f91-210c-4047-b7d4-ee95fca1a3ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838388075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.3838388075
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.3123275481
Short name T27
Test name
Test status
Simulation time 474197253 ps
CPU time 17.69 seconds
Started Jun 04 03:00:50 PM PDT 24
Finished Jun 04 03:01:10 PM PDT 24
Peak memory 242716 kb
Host smart-70f5758d-5e2a-4977-ad35-6c4ec5067662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123275481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.3123275481
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.1605955367
Short name T1155
Test name
Test status
Simulation time 2467521735 ps
CPU time 8.04 seconds
Started Jun 04 03:00:48 PM PDT 24
Finished Jun 04 03:00:58 PM PDT 24
Peak memory 242788 kb
Host smart-8a04d5d0-7626-42ca-9eb8-9c3f8eacbada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605955367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.1605955367
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.4044397097
Short name T596
Test name
Test status
Simulation time 785391824 ps
CPU time 28.06 seconds
Started Jun 04 03:00:51 PM PDT 24
Finished Jun 04 03:01:20 PM PDT 24
Peak memory 242496 kb
Host smart-172acc49-5a08-4013-8866-93029c60ced5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044397097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.4044397097
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.4045267733
Short name T140
Test name
Test status
Simulation time 151638496 ps
CPU time 3.99 seconds
Started Jun 04 03:00:51 PM PDT 24
Finished Jun 04 03:00:57 PM PDT 24
Peak memory 242792 kb
Host smart-ac1b7aab-bdeb-49e7-858f-78884fdcd3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045267733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.4045267733
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.2711644759
Short name T543
Test name
Test status
Simulation time 4362164628 ps
CPU time 55.72 seconds
Started Jun 04 03:00:49 PM PDT 24
Finished Jun 04 03:01:46 PM PDT 24
Peak memory 258040 kb
Host smart-83460cfa-8295-46e0-9e3b-e8422518061f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711644759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.2711644759
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.1441463696
Short name T307
Test name
Test status
Simulation time 215341391 ps
CPU time 10.26 seconds
Started Jun 04 03:00:50 PM PDT 24
Finished Jun 04 03:01:02 PM PDT 24
Peak memory 242308 kb
Host smart-cea80c8e-19ab-4ec1-874c-590e4e9fcffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441463696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.1441463696
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.591988111
Short name T470
Test name
Test status
Simulation time 284083590 ps
CPU time 3.97 seconds
Started Jun 04 03:00:50 PM PDT 24
Finished Jun 04 03:00:56 PM PDT 24
Peak memory 242168 kb
Host smart-a2d538e5-3050-4b82-b1bb-56ad19adc771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591988111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.591988111
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.3210323058
Short name T488
Test name
Test status
Simulation time 367613122 ps
CPU time 11.43 seconds
Started Jun 04 03:00:49 PM PDT 24
Finished Jun 04 03:01:03 PM PDT 24
Peak memory 242160 kb
Host smart-9755d3b0-358a-4d1f-acca-14988909a54e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3210323058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.3210323058
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.258551027
Short name T404
Test name
Test status
Simulation time 152696311 ps
CPU time 4.59 seconds
Started Jun 04 03:00:50 PM PDT 24
Finished Jun 04 03:00:57 PM PDT 24
Peak memory 242148 kb
Host smart-b61fee82-29ad-4afd-8191-9bc1ed9c39f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=258551027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.258551027
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.1559322685
Short name T656
Test name
Test status
Simulation time 571114035 ps
CPU time 9.36 seconds
Started Jun 04 03:00:48 PM PDT 24
Finished Jun 04 03:00:59 PM PDT 24
Peak memory 242232 kb
Host smart-e91eb9b8-4267-4f9e-8c28-7b3934a9567e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559322685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.1559322685
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.4259706330
Short name T1000
Test name
Test status
Simulation time 315488353 ps
CPU time 7.06 seconds
Started Jun 04 03:00:51 PM PDT 24
Finished Jun 04 03:00:59 PM PDT 24
Peak memory 242004 kb
Host smart-ba03e516-e50c-4ab9-9fac-31d3f0f92fef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259706330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all
.4259706330
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.1391585038
Short name T766
Test name
Test status
Simulation time 451308465223 ps
CPU time 1294.01 seconds
Started Jun 04 03:00:51 PM PDT 24
Finished Jun 04 03:22:27 PM PDT 24
Peak memory 264456 kb
Host smart-9cb9325f-78fb-4eff-8d9e-6427893d4b3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391585038 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.1391585038
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.366904663
Short name T412
Test name
Test status
Simulation time 797559033 ps
CPU time 5.51 seconds
Started Jun 04 03:00:50 PM PDT 24
Finished Jun 04 03:00:57 PM PDT 24
Peak memory 242504 kb
Host smart-72ca2bf6-b308-45b0-97f7-b8df12b34fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366904663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.366904663
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.1090183650
Short name T841
Test name
Test status
Simulation time 544040400 ps
CPU time 3.64 seconds
Started Jun 04 03:04:25 PM PDT 24
Finished Jun 04 03:04:29 PM PDT 24
Peak memory 242744 kb
Host smart-6eb0767f-48af-4570-9043-b3befd5e14b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090183650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.1090183650
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.3471388904
Short name T1010
Test name
Test status
Simulation time 133931815 ps
CPU time 5.12 seconds
Started Jun 04 03:04:23 PM PDT 24
Finished Jun 04 03:04:28 PM PDT 24
Peak memory 242704 kb
Host smart-ba2d7a8b-c68b-4427-a86e-559ef8eed071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471388904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.3471388904
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.1406388384
Short name T207
Test name
Test status
Simulation time 471265118 ps
CPU time 3.58 seconds
Started Jun 04 03:04:26 PM PDT 24
Finished Jun 04 03:04:30 PM PDT 24
Peak memory 242716 kb
Host smart-6d0cc68d-a55f-4aa9-904a-c4467d92b186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406388384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.1406388384
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.1743299057
Short name T30
Test name
Test status
Simulation time 2695811958 ps
CPU time 8.32 seconds
Started Jun 04 03:04:21 PM PDT 24
Finished Jun 04 03:04:30 PM PDT 24
Peak memory 242452 kb
Host smart-966c72e2-4b7f-4a86-a6b0-fee3e983b0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743299057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.1743299057
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.2027383816
Short name T65
Test name
Test status
Simulation time 96547201 ps
CPU time 3.7 seconds
Started Jun 04 03:04:26 PM PDT 24
Finished Jun 04 03:04:30 PM PDT 24
Peak memory 242740 kb
Host smart-be5439aa-6d9c-4e04-a18b-cf416cfd3093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027383816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.2027383816
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.2885396912
Short name T865
Test name
Test status
Simulation time 264083317 ps
CPU time 4.38 seconds
Started Jun 04 03:04:23 PM PDT 24
Finished Jun 04 03:04:28 PM PDT 24
Peak memory 242384 kb
Host smart-6d53ffa3-c177-4292-934a-d9b1b5d5c0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885396912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.2885396912
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.1152506502
Short name T1152
Test name
Test status
Simulation time 102448158 ps
CPU time 4.05 seconds
Started Jun 04 03:04:24 PM PDT 24
Finished Jun 04 03:04:29 PM PDT 24
Peak memory 242316 kb
Host smart-54624f2a-fbd3-4770-8518-7fe830b00f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152506502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.1152506502
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.2977140961
Short name T813
Test name
Test status
Simulation time 175658588 ps
CPU time 3.87 seconds
Started Jun 04 03:04:22 PM PDT 24
Finished Jun 04 03:04:27 PM PDT 24
Peak memory 242252 kb
Host smart-d32ad906-ca3b-4253-9c9a-134377288c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977140961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.2977140961
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.4228368737
Short name T465
Test name
Test status
Simulation time 266158131 ps
CPU time 1.71 seconds
Started Jun 04 03:01:01 PM PDT 24
Finished Jun 04 03:01:05 PM PDT 24
Peak memory 241148 kb
Host smart-56662e0f-1e4f-4ccc-9355-3e73204980af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228368737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.4228368737
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.1560120595
Short name T34
Test name
Test status
Simulation time 749549847 ps
CPU time 10.36 seconds
Started Jun 04 03:01:00 PM PDT 24
Finished Jun 04 03:01:11 PM PDT 24
Peak memory 248956 kb
Host smart-4494a6b6-7235-4a27-9629-5e01248e247d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560120595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.1560120595
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.3973421728
Short name T519
Test name
Test status
Simulation time 2799826343 ps
CPU time 20.58 seconds
Started Jun 04 03:01:01 PM PDT 24
Finished Jun 04 03:01:23 PM PDT 24
Peak memory 242420 kb
Host smart-9f53ded5-bde0-4107-b8dc-0aa641ac1eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973421728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.3973421728
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.2945230141
Short name T902
Test name
Test status
Simulation time 2990573243 ps
CPU time 29.77 seconds
Started Jun 04 03:01:03 PM PDT 24
Finished Jun 04 03:01:35 PM PDT 24
Peak memory 242312 kb
Host smart-0aa081d0-45ca-45da-8fdb-6006093689fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945230141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.2945230141
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.2467356228
Short name T635
Test name
Test status
Simulation time 1346676592 ps
CPU time 18.42 seconds
Started Jun 04 03:01:03 PM PDT 24
Finished Jun 04 03:01:24 PM PDT 24
Peak memory 248960 kb
Host smart-322b5828-34bc-44da-a88c-4582985a89d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467356228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.2467356228
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.2703057713
Short name T814
Test name
Test status
Simulation time 519400375 ps
CPU time 16.25 seconds
Started Jun 04 03:01:02 PM PDT 24
Finished Jun 04 03:01:20 PM PDT 24
Peak memory 242532 kb
Host smart-cbece80a-6564-4a85-8fdc-34d17f12d7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703057713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.2703057713
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.3541086839
Short name T433
Test name
Test status
Simulation time 439108249 ps
CPU time 5.58 seconds
Started Jun 04 03:01:00 PM PDT 24
Finished Jun 04 03:01:08 PM PDT 24
Peak memory 242584 kb
Host smart-544ea0e0-bcaa-4324-9740-66e83a4f934a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541086839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.3541086839
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.1124520494
Short name T584
Test name
Test status
Simulation time 486300080 ps
CPU time 8.03 seconds
Started Jun 04 03:01:02 PM PDT 24
Finished Jun 04 03:01:13 PM PDT 24
Peak memory 248832 kb
Host smart-9311cb66-29f9-4ce2-aaec-3ee2ca05e1b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1124520494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.1124520494
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.1768986289
Short name T893
Test name
Test status
Simulation time 382149177 ps
CPU time 6.23 seconds
Started Jun 04 03:01:03 PM PDT 24
Finished Jun 04 03:01:11 PM PDT 24
Peak memory 242244 kb
Host smart-8efb9486-fca3-47b6-9d59-0b8d51e5622a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1768986289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.1768986289
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.2696840747
Short name T886
Test name
Test status
Simulation time 599742814 ps
CPU time 10.96 seconds
Started Jun 04 03:00:48 PM PDT 24
Finished Jun 04 03:00:59 PM PDT 24
Peak memory 242168 kb
Host smart-dfd333c2-7caa-4a88-bf56-bfa4436872a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696840747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.2696840747
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.513353778
Short name T383
Test name
Test status
Simulation time 6009110678 ps
CPU time 188.81 seconds
Started Jun 04 03:01:00 PM PDT 24
Finished Jun 04 03:04:11 PM PDT 24
Peak memory 246552 kb
Host smart-1826a295-6f20-44f1-bbd9-9ba4e379a1a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513353778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.
513353778
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.1648077157
Short name T982
Test name
Test status
Simulation time 388217020 ps
CPU time 11.08 seconds
Started Jun 04 03:01:03 PM PDT 24
Finished Jun 04 03:01:16 PM PDT 24
Peak memory 242132 kb
Host smart-28f250b0-131a-4bd2-a2cb-b73d9c21f8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648077157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.1648077157
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.2645660506
Short name T194
Test name
Test status
Simulation time 180336462 ps
CPU time 4.61 seconds
Started Jun 04 03:04:30 PM PDT 24
Finished Jun 04 03:04:35 PM PDT 24
Peak memory 242720 kb
Host smart-6a7b4388-8495-42fb-9d1d-87ef6d3a0b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645660506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.2645660506
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.2885381450
Short name T431
Test name
Test status
Simulation time 210701545 ps
CPU time 4.4 seconds
Started Jun 04 03:04:32 PM PDT 24
Finished Jun 04 03:04:37 PM PDT 24
Peak memory 242416 kb
Host smart-a1beb6d3-66eb-4dfb-88b0-17d15b15947e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885381450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.2885381450
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.3960230606
Short name T912
Test name
Test status
Simulation time 491627478 ps
CPU time 4.24 seconds
Started Jun 04 03:04:40 PM PDT 24
Finished Jun 04 03:04:45 PM PDT 24
Peak memory 242360 kb
Host smart-559370d6-ce9b-4659-ba6d-0ba1fade7c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960230606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.3960230606
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.647932398
Short name T1019
Test name
Test status
Simulation time 143888785 ps
CPU time 4 seconds
Started Jun 04 03:04:35 PM PDT 24
Finished Jun 04 03:04:40 PM PDT 24
Peak memory 242712 kb
Host smart-0680df20-1c3e-4b43-8799-67fcbd674053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647932398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.647932398
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.3350540940
Short name T1205
Test name
Test status
Simulation time 147965324 ps
CPU time 3.94 seconds
Started Jun 04 03:04:33 PM PDT 24
Finished Jun 04 03:04:38 PM PDT 24
Peak memory 242448 kb
Host smart-303fba7f-3dfa-4b78-9706-3bf0c6305522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350540940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.3350540940
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.2830916375
Short name T12
Test name
Test status
Simulation time 222758445 ps
CPU time 4.11 seconds
Started Jun 04 03:04:29 PM PDT 24
Finished Jun 04 03:04:34 PM PDT 24
Peak memory 242580 kb
Host smart-d6a6f135-bb0d-40f9-807a-1e8d736a912d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830916375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.2830916375
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.835182654
Short name T876
Test name
Test status
Simulation time 2623813598 ps
CPU time 5.34 seconds
Started Jun 04 03:04:30 PM PDT 24
Finished Jun 04 03:04:36 PM PDT 24
Peak memory 242804 kb
Host smart-9e6767ec-ea48-4bae-b9b3-a3fa2ea19198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835182654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.835182654
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.1449117328
Short name T105
Test name
Test status
Simulation time 404628380 ps
CPU time 4.81 seconds
Started Jun 04 03:04:32 PM PDT 24
Finished Jun 04 03:04:37 PM PDT 24
Peak memory 242528 kb
Host smart-bb297f79-6ed3-4f99-a44e-7e8f514b89f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449117328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.1449117328
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.1509977405
Short name T607
Test name
Test status
Simulation time 139228506 ps
CPU time 4.02 seconds
Started Jun 04 03:04:31 PM PDT 24
Finished Jun 04 03:04:36 PM PDT 24
Peak memory 242588 kb
Host smart-2d673937-64e0-410c-8b87-777ee5985e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509977405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.1509977405
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.932722892
Short name T858
Test name
Test status
Simulation time 386856670 ps
CPU time 4.1 seconds
Started Jun 04 03:04:30 PM PDT 24
Finished Jun 04 03:04:35 PM PDT 24
Peak memory 242332 kb
Host smart-8e5ae0de-5ccf-47df-bda5-1aad41c62e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932722892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.932722892
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.3865721362
Short name T990
Test name
Test status
Simulation time 81290103 ps
CPU time 1.9 seconds
Started Jun 04 03:01:00 PM PDT 24
Finished Jun 04 03:01:03 PM PDT 24
Peak memory 241056 kb
Host smart-569996ab-e6d3-4c24-b059-9f38c38d6c60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865721362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.3865721362
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.4264107730
Short name T116
Test name
Test status
Simulation time 1307671573 ps
CPU time 16.03 seconds
Started Jun 04 03:01:05 PM PDT 24
Finished Jun 04 03:01:23 PM PDT 24
Peak memory 242972 kb
Host smart-ee97bc30-5ba5-4c59-8af2-50836490b510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264107730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.4264107730
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.1266030866
Short name T1199
Test name
Test status
Simulation time 5355859863 ps
CPU time 24.19 seconds
Started Jun 04 03:01:03 PM PDT 24
Finished Jun 04 03:01:29 PM PDT 24
Peak memory 242652 kb
Host smart-18551e99-4f5b-4aba-8533-8b8d992cdd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266030866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.1266030866
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.3905134457
Short name T214
Test name
Test status
Simulation time 289043867 ps
CPU time 3.98 seconds
Started Jun 04 03:01:01 PM PDT 24
Finished Jun 04 03:01:08 PM PDT 24
Peak memory 242448 kb
Host smart-d84d9c52-bb10-40c8-9b20-a0a80ad2a143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905134457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.3905134457
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.606487018
Short name T747
Test name
Test status
Simulation time 1504238165 ps
CPU time 9.13 seconds
Started Jun 04 03:01:00 PM PDT 24
Finished Jun 04 03:01:11 PM PDT 24
Peak memory 242432 kb
Host smart-446d985d-305c-4395-aff3-71287ea40227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606487018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.606487018
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.2888870485
Short name T605
Test name
Test status
Simulation time 1721825686 ps
CPU time 13.71 seconds
Started Jun 04 03:01:01 PM PDT 24
Finished Jun 04 03:01:16 PM PDT 24
Peak memory 242248 kb
Host smart-93748b63-351f-46f3-beb4-bceb42f836b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888870485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.2888870485
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.4280087698
Short name T634
Test name
Test status
Simulation time 818123449 ps
CPU time 13.07 seconds
Started Jun 04 03:01:00 PM PDT 24
Finished Jun 04 03:01:14 PM PDT 24
Peak memory 242412 kb
Host smart-5456f32d-55cb-4b3f-a4c2-27e201a212f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280087698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.4280087698
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.2885337205
Short name T434
Test name
Test status
Simulation time 236889201 ps
CPU time 7.63 seconds
Started Jun 04 03:01:03 PM PDT 24
Finished Jun 04 03:01:13 PM PDT 24
Peak memory 242280 kb
Host smart-95ede1a5-4bcb-4622-84ed-8c42a8c16060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2885337205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.2885337205
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.1748601273
Short name T628
Test name
Test status
Simulation time 267412208 ps
CPU time 4.46 seconds
Started Jun 04 03:01:03 PM PDT 24
Finished Jun 04 03:01:10 PM PDT 24
Peak memory 242208 kb
Host smart-feee3efd-b846-4fbc-afc5-8e4ded308326
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1748601273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.1748601273
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.358678134
Short name T847
Test name
Test status
Simulation time 280549306 ps
CPU time 9.47 seconds
Started Jun 04 03:01:00 PM PDT 24
Finished Jun 04 03:01:11 PM PDT 24
Peak memory 242236 kb
Host smart-f71b10f5-eb13-4496-ac05-05bec5ad218a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358678134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.358678134
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.2960565221
Short name T678
Test name
Test status
Simulation time 279354165395 ps
CPU time 614.46 seconds
Started Jun 04 03:01:01 PM PDT 24
Finished Jun 04 03:11:18 PM PDT 24
Peak memory 309996 kb
Host smart-07fb9db6-a6e0-4ace-b8e0-e416fbf0f508
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960565221 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.2960565221
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.2968187894
Short name T970
Test name
Test status
Simulation time 386482702 ps
CPU time 4.84 seconds
Started Jun 04 03:01:03 PM PDT 24
Finished Jun 04 03:01:10 PM PDT 24
Peak memory 242196 kb
Host smart-70810d58-0714-4e85-aa7a-d0211f6af7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968187894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.2968187894
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.1844736012
Short name T447
Test name
Test status
Simulation time 2317949544 ps
CPU time 5.69 seconds
Started Jun 04 03:04:40 PM PDT 24
Finished Jun 04 03:04:47 PM PDT 24
Peak memory 242708 kb
Host smart-8f2b919e-0f83-42a4-aaf8-2be74e48d078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844736012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.1844736012
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.477699177
Short name T51
Test name
Test status
Simulation time 309997199 ps
CPU time 4.11 seconds
Started Jun 04 03:04:31 PM PDT 24
Finished Jun 04 03:04:36 PM PDT 24
Peak memory 242332 kb
Host smart-79daef96-2667-4a39-9cd7-adcdf2cf562a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477699177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.477699177
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.712052491
Short name T165
Test name
Test status
Simulation time 439972978 ps
CPU time 4.17 seconds
Started Jun 04 03:04:30 PM PDT 24
Finished Jun 04 03:04:35 PM PDT 24
Peak memory 242416 kb
Host smart-360da711-1ce6-4bca-ae5e-8178843a8d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712052491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.712052491
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.4239252242
Short name T139
Test name
Test status
Simulation time 693884498 ps
CPU time 4.26 seconds
Started Jun 04 03:04:40 PM PDT 24
Finished Jun 04 03:04:45 PM PDT 24
Peak memory 242708 kb
Host smart-fbdb94d8-8db6-4c99-aec6-c847a5e5999d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239252242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.4239252242
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.2581377301
Short name T1068
Test name
Test status
Simulation time 2495239068 ps
CPU time 5.77 seconds
Started Jun 04 03:04:35 PM PDT 24
Finished Jun 04 03:04:42 PM PDT 24
Peak memory 242492 kb
Host smart-cd125558-f8be-4232-9f57-5dde73fa62dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581377301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.2581377301
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.3687198463
Short name T1145
Test name
Test status
Simulation time 415303793 ps
CPU time 3.96 seconds
Started Jun 04 03:04:31 PM PDT 24
Finished Jun 04 03:04:35 PM PDT 24
Peak memory 242760 kb
Host smart-8111fec2-f9cf-4dd4-a84a-2dbb85965882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687198463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.3687198463
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.334527952
Short name T418
Test name
Test status
Simulation time 2580177025 ps
CPU time 4.19 seconds
Started Jun 04 03:04:33 PM PDT 24
Finished Jun 04 03:04:38 PM PDT 24
Peak memory 242768 kb
Host smart-cf475370-9585-44bd-8ba6-c91b134ff254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334527952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.334527952
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.246983662
Short name T440
Test name
Test status
Simulation time 486826395 ps
CPU time 4.55 seconds
Started Jun 04 03:04:31 PM PDT 24
Finished Jun 04 03:04:36 PM PDT 24
Peak memory 242660 kb
Host smart-76556b1f-8a69-4c98-a839-baa3c0a23fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246983662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.246983662
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.214447747
Short name T875
Test name
Test status
Simulation time 162591013 ps
CPU time 4.85 seconds
Started Jun 04 03:04:31 PM PDT 24
Finished Jun 04 03:04:36 PM PDT 24
Peak memory 242772 kb
Host smart-7fb12319-3b2c-4960-a9d8-10003aa5a208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214447747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.214447747
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.637699562
Short name T36
Test name
Test status
Simulation time 284754696 ps
CPU time 3.99 seconds
Started Jun 04 03:04:32 PM PDT 24
Finished Jun 04 03:04:36 PM PDT 24
Peak memory 242684 kb
Host smart-9dfd9779-d860-4c11-ab4b-2f83d640d52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637699562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.637699562
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.1776643755
Short name T483
Test name
Test status
Simulation time 163043971 ps
CPU time 1.92 seconds
Started Jun 04 03:01:07 PM PDT 24
Finished Jun 04 03:01:11 PM PDT 24
Peak memory 240684 kb
Host smart-a090cc5b-c0c7-4c0d-a173-710600ff5a52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776643755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.1776643755
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.784803509
Short name T798
Test name
Test status
Simulation time 799877273 ps
CPU time 23.47 seconds
Started Jun 04 03:01:10 PM PDT 24
Finished Jun 04 03:01:36 PM PDT 24
Peak memory 242592 kb
Host smart-b688e74a-f34f-4468-a416-bf37646c96e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784803509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.784803509
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.1227270540
Short name T218
Test name
Test status
Simulation time 3502236660 ps
CPU time 24.54 seconds
Started Jun 04 03:01:12 PM PDT 24
Finished Jun 04 03:01:40 PM PDT 24
Peak memory 248908 kb
Host smart-bf65ae47-7645-42ea-bb7a-76ef4d6686c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227270540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.1227270540
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.664386545
Short name T700
Test name
Test status
Simulation time 295625461 ps
CPU time 3.97 seconds
Started Jun 04 03:01:02 PM PDT 24
Finished Jun 04 03:01:08 PM PDT 24
Peak memory 242588 kb
Host smart-7e5a757d-705f-4799-9b02-2fdcd6cdb307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664386545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.664386545
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.3586052246
Short name T783
Test name
Test status
Simulation time 5814391088 ps
CPU time 12.79 seconds
Started Jun 04 03:01:09 PM PDT 24
Finished Jun 04 03:01:24 PM PDT 24
Peak memory 242356 kb
Host smart-d4546a5e-d413-4f9b-852b-ad00005702d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586052246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.3586052246
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.59321741
Short name T683
Test name
Test status
Simulation time 514524373 ps
CPU time 13.99 seconds
Started Jun 04 03:01:12 PM PDT 24
Finished Jun 04 03:01:29 PM PDT 24
Peak memory 242304 kb
Host smart-6a562361-1d9e-4c01-a5e1-c9f4f71ddf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59321741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.59321741
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.864202406
Short name T631
Test name
Test status
Simulation time 228988111 ps
CPU time 4.67 seconds
Started Jun 04 03:01:00 PM PDT 24
Finished Jun 04 03:01:07 PM PDT 24
Peak memory 242460 kb
Host smart-96b8b24d-9656-493f-84aa-df9380b8ea83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864202406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.864202406
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.3239725687
Short name T384
Test name
Test status
Simulation time 841177620 ps
CPU time 11.9 seconds
Started Jun 04 03:01:00 PM PDT 24
Finished Jun 04 03:01:14 PM PDT 24
Peak memory 248724 kb
Host smart-b1ebaf55-dde3-4438-bf4b-8228b0853e64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3239725687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.3239725687
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.3366110866
Short name T537
Test name
Test status
Simulation time 203242187 ps
CPU time 5.94 seconds
Started Jun 04 03:01:32 PM PDT 24
Finished Jun 04 03:01:39 PM PDT 24
Peak memory 242432 kb
Host smart-a95a8801-1b47-470b-874b-cb47abe54eea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3366110866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.3366110866
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.3612060972
Short name T1116
Test name
Test status
Simulation time 1819296780 ps
CPU time 8.96 seconds
Started Jun 04 03:01:03 PM PDT 24
Finished Jun 04 03:01:14 PM PDT 24
Peak memory 242208 kb
Host smart-243429e1-43aa-4895-b0f0-4632fbea7554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612060972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.3612060972
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.4153841559
Short name T261
Test name
Test status
Simulation time 15103631930 ps
CPU time 282.75 seconds
Started Jun 04 03:01:09 PM PDT 24
Finished Jun 04 03:05:55 PM PDT 24
Peak memory 290020 kb
Host smart-de80d512-f64b-4021-893c-19f4f964f5e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153841559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.4153841559
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.1220281092
Short name T335
Test name
Test status
Simulation time 281089457549 ps
CPU time 2980.8 seconds
Started Jun 04 03:01:09 PM PDT 24
Finished Jun 04 03:50:52 PM PDT 24
Peak memory 739100 kb
Host smart-98ca89cc-6d07-4aac-b546-b0f01602b9d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220281092 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.1220281092
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.353231979
Short name T1110
Test name
Test status
Simulation time 1510714872 ps
CPU time 35.11 seconds
Started Jun 04 03:01:09 PM PDT 24
Finished Jun 04 03:01:47 PM PDT 24
Peak memory 242684 kb
Host smart-14b4e499-6fa9-489d-8ce8-9641cdf24721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353231979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.353231979
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.2838229381
Short name T428
Test name
Test status
Simulation time 2189572431 ps
CPU time 5.21 seconds
Started Jun 04 03:04:31 PM PDT 24
Finished Jun 04 03:04:37 PM PDT 24
Peak memory 242344 kb
Host smart-5e334956-58b9-40f4-935a-f202d71de549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838229381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.2838229381
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.2302373738
Short name T647
Test name
Test status
Simulation time 165516269 ps
CPU time 4.18 seconds
Started Jun 04 03:04:32 PM PDT 24
Finished Jun 04 03:04:37 PM PDT 24
Peak memory 242752 kb
Host smart-eef0265a-ed53-4e99-bab7-a5c944fe9c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302373738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.2302373738
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.23715903
Short name T167
Test name
Test status
Simulation time 143585381 ps
CPU time 3.19 seconds
Started Jun 04 03:04:30 PM PDT 24
Finished Jun 04 03:04:33 PM PDT 24
Peak memory 242544 kb
Host smart-4d12df83-1bc5-488b-b879-ee794146d31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23715903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.23715903
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.3150013554
Short name T653
Test name
Test status
Simulation time 129257606 ps
CPU time 4.1 seconds
Started Jun 04 03:04:31 PM PDT 24
Finished Jun 04 03:04:36 PM PDT 24
Peak memory 242356 kb
Host smart-5ed2eb76-22c0-4cd5-abda-cb2bf699cd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150013554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.3150013554
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.473787479
Short name T746
Test name
Test status
Simulation time 464939363 ps
CPU time 3.73 seconds
Started Jun 04 03:04:32 PM PDT 24
Finished Jun 04 03:04:36 PM PDT 24
Peak memory 242712 kb
Host smart-98312355-3958-4c6e-b64e-2083c654d0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473787479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.473787479
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.3976580872
Short name T604
Test name
Test status
Simulation time 280802467 ps
CPU time 5.08 seconds
Started Jun 04 03:04:40 PM PDT 24
Finished Jun 04 03:04:46 PM PDT 24
Peak memory 242752 kb
Host smart-a13ce208-f1f1-4740-8178-f6d4ba7199f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976580872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.3976580872
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.3448803569
Short name T1203
Test name
Test status
Simulation time 2948567923 ps
CPU time 5.39 seconds
Started Jun 04 03:04:32 PM PDT 24
Finished Jun 04 03:04:38 PM PDT 24
Peak memory 242516 kb
Host smart-22ac5405-0d70-45be-810d-1e7b9de57e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448803569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.3448803569
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.718545074
Short name T620
Test name
Test status
Simulation time 289924859 ps
CPU time 4.4 seconds
Started Jun 04 03:04:35 PM PDT 24
Finished Jun 04 03:04:40 PM PDT 24
Peak memory 242424 kb
Host smart-58eed5bb-97ce-486b-9c6f-c515bcb7e418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718545074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.718545074
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.843615528
Short name T97
Test name
Test status
Simulation time 214874456 ps
CPU time 4.56 seconds
Started Jun 04 03:04:32 PM PDT 24
Finished Jun 04 03:04:37 PM PDT 24
Peak memory 242604 kb
Host smart-6fb20f11-62ef-44c1-a661-58497d6520ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843615528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.843615528
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.2048083185
Short name T852
Test name
Test status
Simulation time 274732252 ps
CPU time 3.68 seconds
Started Jun 04 03:04:35 PM PDT 24
Finished Jun 04 03:04:40 PM PDT 24
Peak memory 242448 kb
Host smart-4d0769c3-bfb8-4b7e-8236-d263630b9d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048083185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.2048083185
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.2050848369
Short name T460
Test name
Test status
Simulation time 118838939 ps
CPU time 2.12 seconds
Started Jun 04 03:01:10 PM PDT 24
Finished Jun 04 03:01:16 PM PDT 24
Peak memory 240864 kb
Host smart-682d04a0-6e54-40d4-bfaf-7ce18dfa6ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050848369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.2050848369
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.1443347915
Short name T469
Test name
Test status
Simulation time 11761094471 ps
CPU time 26.97 seconds
Started Jun 04 03:01:12 PM PDT 24
Finished Jun 04 03:01:42 PM PDT 24
Peak memory 243940 kb
Host smart-63356a25-c850-4186-9f5d-4253446e410f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443347915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.1443347915
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.610322893
Short name T769
Test name
Test status
Simulation time 1345832653 ps
CPU time 13.67 seconds
Started Jun 04 03:01:10 PM PDT 24
Finished Jun 04 03:01:26 PM PDT 24
Peak memory 242280 kb
Host smart-5c14a780-2a0a-4134-b667-cff713c572e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610322893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.610322893
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.465439472
Short name T155
Test name
Test status
Simulation time 3329294964 ps
CPU time 33.34 seconds
Started Jun 04 03:01:08 PM PDT 24
Finished Jun 04 03:01:44 PM PDT 24
Peak memory 243192 kb
Host smart-d08d3865-a7a4-4af7-b633-ebd7c609f02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465439472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.465439472
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.1666990674
Short name T1032
Test name
Test status
Simulation time 148329307 ps
CPU time 3.74 seconds
Started Jun 04 03:01:08 PM PDT 24
Finished Jun 04 03:01:14 PM PDT 24
Peak memory 242316 kb
Host smart-72601d20-18f9-44db-b596-0a55686433a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666990674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.1666990674
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.8779222
Short name T961
Test name
Test status
Simulation time 3548128734 ps
CPU time 21.86 seconds
Started Jun 04 03:01:12 PM PDT 24
Finished Jun 04 03:01:37 PM PDT 24
Peak memory 248984 kb
Host smart-a2e13041-c30e-4bab-918c-2b7ae454019b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8779222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.8779222
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.1321511268
Short name T855
Test name
Test status
Simulation time 533543750 ps
CPU time 13.99 seconds
Started Jun 04 03:01:10 PM PDT 24
Finished Jun 04 03:01:27 PM PDT 24
Peak memory 242580 kb
Host smart-348bee69-933a-44a6-acf9-6fb57d3e28df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321511268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.1321511268
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.3939817523
Short name T937
Test name
Test status
Simulation time 760246912 ps
CPU time 24.18 seconds
Started Jun 04 03:01:10 PM PDT 24
Finished Jun 04 03:01:37 PM PDT 24
Peak memory 242348 kb
Host smart-5082d08f-233b-4b2e-89f0-504ccd839b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939817523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.3939817523
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.1541628798
Short name T986
Test name
Test status
Simulation time 1640746251 ps
CPU time 19.76 seconds
Started Jun 04 03:01:08 PM PDT 24
Finished Jun 04 03:01:29 PM PDT 24
Peak memory 248844 kb
Host smart-c13668c9-3052-425a-9bb7-cf49e4f1edf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541628798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.1541628798
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.1944891961
Short name T195
Test name
Test status
Simulation time 512700151 ps
CPU time 9.25 seconds
Started Jun 04 03:01:09 PM PDT 24
Finished Jun 04 03:01:21 PM PDT 24
Peak memory 242068 kb
Host smart-445845be-9553-46ea-ae68-0f0f25097aed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944891961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.1944891961
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.3201645952
Short name T872
Test name
Test status
Simulation time 287180877 ps
CPU time 10.98 seconds
Started Jun 04 03:01:09 PM PDT 24
Finished Jun 04 03:01:22 PM PDT 24
Peak memory 242556 kb
Host smart-17c08645-49bb-44fc-908a-260a2a53f2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201645952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.3201645952
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.3738766804
Short name T687
Test name
Test status
Simulation time 3873354696 ps
CPU time 64.4 seconds
Started Jun 04 03:01:09 PM PDT 24
Finished Jun 04 03:02:16 PM PDT 24
Peak memory 245100 kb
Host smart-25a6f8aa-63cd-4f04-82b6-1057ef095519
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738766804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.3738766804
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.3635932544
Short name T232
Test name
Test status
Simulation time 369142465856 ps
CPU time 1117.11 seconds
Started Jun 04 03:01:11 PM PDT 24
Finished Jun 04 03:19:51 PM PDT 24
Peak memory 281824 kb
Host smart-6f587a7d-fe64-4619-89a9-ea27c1e5d2f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635932544 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.3635932544
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.301070684
Short name T206
Test name
Test status
Simulation time 303093418 ps
CPU time 4.88 seconds
Started Jun 04 03:04:41 PM PDT 24
Finished Jun 04 03:04:47 PM PDT 24
Peak memory 242748 kb
Host smart-4378d651-88d9-47e4-9e5c-872d4c9877d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301070684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.301070684
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.759784234
Short name T953
Test name
Test status
Simulation time 196414526 ps
CPU time 3.41 seconds
Started Jun 04 03:04:43 PM PDT 24
Finished Jun 04 03:04:47 PM PDT 24
Peak memory 242712 kb
Host smart-79dcd073-e4f7-43c5-be62-97b510bd9c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759784234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.759784234
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.1743142715
Short name T1109
Test name
Test status
Simulation time 141219746 ps
CPU time 3.84 seconds
Started Jun 04 03:04:38 PM PDT 24
Finished Jun 04 03:04:43 PM PDT 24
Peak memory 242500 kb
Host smart-4b005329-712d-4312-b250-8bc1832b2e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743142715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.1743142715
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.699406642
Short name T624
Test name
Test status
Simulation time 189668703 ps
CPU time 4.08 seconds
Started Jun 04 03:04:44 PM PDT 24
Finished Jun 04 03:04:48 PM PDT 24
Peak memory 242368 kb
Host smart-511e1ead-628a-413b-90cf-da41b3b245ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699406642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.699406642
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.2301160853
Short name T639
Test name
Test status
Simulation time 349559543 ps
CPU time 4.74 seconds
Started Jun 04 03:04:41 PM PDT 24
Finished Jun 04 03:04:47 PM PDT 24
Peak memory 242768 kb
Host smart-54b28064-40e8-4226-ac97-f22dd53b9903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301160853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.2301160853
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.1384648406
Short name T574
Test name
Test status
Simulation time 323600714 ps
CPU time 4.28 seconds
Started Jun 04 03:04:46 PM PDT 24
Finished Jun 04 03:04:51 PM PDT 24
Peak memory 242544 kb
Host smart-58772be7-e3de-4936-b0ff-40d612b8d803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384648406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.1384648406
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.1697255988
Short name T408
Test name
Test status
Simulation time 339718690 ps
CPU time 5.17 seconds
Started Jun 04 03:04:43 PM PDT 24
Finished Jun 04 03:04:49 PM PDT 24
Peak memory 242364 kb
Host smart-56005657-9f9f-4676-b456-b3db6dd96796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697255988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.1697255988
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.711984927
Short name T37
Test name
Test status
Simulation time 2068865117 ps
CPU time 5.6 seconds
Started Jun 04 03:04:42 PM PDT 24
Finished Jun 04 03:04:49 PM PDT 24
Peak memory 242776 kb
Host smart-3fb00c57-21b0-4c55-b5a0-844a42b0572f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711984927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.711984927
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.2632359757
Short name T494
Test name
Test status
Simulation time 177716309 ps
CPU time 4.02 seconds
Started Jun 04 03:04:41 PM PDT 24
Finished Jun 04 03:04:46 PM PDT 24
Peak memory 242424 kb
Host smart-013d430d-50c8-43cf-8065-31924b8dd051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632359757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.2632359757
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.3044888312
Short name T714
Test name
Test status
Simulation time 168593870 ps
CPU time 4.18 seconds
Started Jun 04 03:04:42 PM PDT 24
Finished Jun 04 03:04:47 PM PDT 24
Peak memory 242416 kb
Host smart-ab2ccea6-1e5e-41a1-8698-e5913cfb0e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044888312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.3044888312
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.4082808738
Short name T1034
Test name
Test status
Simulation time 171631876 ps
CPU time 2.82 seconds
Started Jun 04 03:01:09 PM PDT 24
Finished Jun 04 03:01:15 PM PDT 24
Peak memory 241236 kb
Host smart-61a90234-dc19-4b37-aefa-b11ccd286b1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082808738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.4082808738
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.1950736971
Short name T598
Test name
Test status
Simulation time 1563472147 ps
CPU time 24.08 seconds
Started Jun 04 03:01:12 PM PDT 24
Finished Jun 04 03:01:40 PM PDT 24
Peak memory 242308 kb
Host smart-9ffe6387-80e1-470a-9fbb-8ae5752e2beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950736971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.1950736971
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.2226925189
Short name T550
Test name
Test status
Simulation time 4188612027 ps
CPU time 12.91 seconds
Started Jun 04 03:01:09 PM PDT 24
Finished Jun 04 03:01:24 PM PDT 24
Peak memory 243248 kb
Host smart-c01725e3-ac51-44a9-a4ed-91f2b7514d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226925189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.2226925189
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.3577739926
Short name T539
Test name
Test status
Simulation time 167746168 ps
CPU time 4.43 seconds
Started Jun 04 03:01:08 PM PDT 24
Finished Jun 04 03:01:14 PM PDT 24
Peak memory 242380 kb
Host smart-78475e6a-2a69-46ea-ad74-aec51d1d7578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577739926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.3577739926
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.3027609680
Short name T580
Test name
Test status
Simulation time 1163588558 ps
CPU time 15.87 seconds
Started Jun 04 03:01:08 PM PDT 24
Finished Jun 04 03:01:25 PM PDT 24
Peak memory 242736 kb
Host smart-be75ea12-8d39-4f3d-9bce-c4991a2fdc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027609680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.3027609680
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.2495840869
Short name T94
Test name
Test status
Simulation time 900631287 ps
CPU time 19.21 seconds
Started Jun 04 03:01:12 PM PDT 24
Finished Jun 04 03:01:35 PM PDT 24
Peak memory 242252 kb
Host smart-b15c727e-825b-43e7-a743-770f24715df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495840869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.2495840869
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.2402909347
Short name T610
Test name
Test status
Simulation time 1036685499 ps
CPU time 14.34 seconds
Started Jun 04 03:01:09 PM PDT 24
Finished Jun 04 03:01:27 PM PDT 24
Peak memory 242596 kb
Host smart-ffae5d93-b47d-4983-bfff-6f87bf9b6b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402909347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.2402909347
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.563361546
Short name T446
Test name
Test status
Simulation time 1040723460 ps
CPU time 18.14 seconds
Started Jun 04 03:01:08 PM PDT 24
Finished Jun 04 03:01:27 PM PDT 24
Peak memory 242176 kb
Host smart-4c200bdf-cefb-45ce-adae-35425732553c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=563361546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.563361546
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.3214175841
Short name T1031
Test name
Test status
Simulation time 1008606211 ps
CPU time 9.44 seconds
Started Jun 04 03:01:09 PM PDT 24
Finished Jun 04 03:01:21 PM PDT 24
Peak memory 242276 kb
Host smart-2dd1e14a-639c-4a4c-b900-34dfc5e9178f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3214175841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.3214175841
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.2919165305
Short name T991
Test name
Test status
Simulation time 131511594 ps
CPU time 4.78 seconds
Started Jun 04 03:01:08 PM PDT 24
Finished Jun 04 03:01:14 PM PDT 24
Peak memory 242484 kb
Host smart-2e6c4621-f7ae-4d78-9beb-bf51dba11c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919165305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.2919165305
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.3637300233
Short name T17
Test name
Test status
Simulation time 149239532260 ps
CPU time 4060.54 seconds
Started Jun 04 03:01:13 PM PDT 24
Finished Jun 04 04:08:57 PM PDT 24
Peak memory 590852 kb
Host smart-22ae8539-38d8-4b10-b762-6f5dea763243
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637300233 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.3637300233
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.3326133702
Short name T108
Test name
Test status
Simulation time 31524687759 ps
CPU time 50.13 seconds
Started Jun 04 03:01:08 PM PDT 24
Finished Jun 04 03:01:59 PM PDT 24
Peak memory 242280 kb
Host smart-d525a4a7-bfa7-468b-abaf-4b17b64bb0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326133702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.3326133702
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.1218555437
Short name T1015
Test name
Test status
Simulation time 322811553 ps
CPU time 5.19 seconds
Started Jun 04 03:04:42 PM PDT 24
Finished Jun 04 03:04:48 PM PDT 24
Peak memory 242304 kb
Host smart-05099356-3c83-4996-ba9a-12a04f828140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218555437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.1218555437
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.626189911
Short name T952
Test name
Test status
Simulation time 300038477 ps
CPU time 4.83 seconds
Started Jun 04 03:04:42 PM PDT 24
Finished Jun 04 03:04:48 PM PDT 24
Peak memory 242116 kb
Host smart-3fb5d327-0038-4139-9104-49d07590a2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626189911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.626189911
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.2631452418
Short name T775
Test name
Test status
Simulation time 163544389 ps
CPU time 3.68 seconds
Started Jun 04 03:04:40 PM PDT 24
Finished Jun 04 03:04:45 PM PDT 24
Peak memory 242604 kb
Host smart-eef49a72-50d0-4b76-9f41-9b398b868043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631452418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.2631452418
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.2362047591
Short name T699
Test name
Test status
Simulation time 129887827 ps
CPU time 4.12 seconds
Started Jun 04 03:04:41 PM PDT 24
Finished Jun 04 03:04:46 PM PDT 24
Peak memory 242452 kb
Host smart-1d47b977-f9b3-4a5c-9644-5acdf46e4343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362047591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.2362047591
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.367665694
Short name T612
Test name
Test status
Simulation time 279065202 ps
CPU time 5.61 seconds
Started Jun 04 03:04:42 PM PDT 24
Finished Jun 04 03:04:49 PM PDT 24
Peak memory 242752 kb
Host smart-722ea8a9-05af-4c08-a653-cef17d436961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367665694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.367665694
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.1744226786
Short name T47
Test name
Test status
Simulation time 304142576 ps
CPU time 4.82 seconds
Started Jun 04 03:04:39 PM PDT 24
Finished Jun 04 03:04:45 PM PDT 24
Peak memory 242656 kb
Host smart-6f248f73-6a84-4d11-bde0-4fb98b10c80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744226786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.1744226786
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.1624218420
Short name T843
Test name
Test status
Simulation time 563592138 ps
CPU time 5.04 seconds
Started Jun 04 03:04:40 PM PDT 24
Finished Jun 04 03:04:46 PM PDT 24
Peak memory 242692 kb
Host smart-967ef82b-96b7-4668-920f-023195737cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624218420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.1624218420
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.3826299814
Short name T405
Test name
Test status
Simulation time 307514786 ps
CPU time 4.66 seconds
Started Jun 04 03:04:44 PM PDT 24
Finished Jun 04 03:04:49 PM PDT 24
Peak memory 242424 kb
Host smart-5aacfb06-e63c-4168-b69c-638c8b8fd256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826299814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.3826299814
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.31170475
Short name T805
Test name
Test status
Simulation time 170830675 ps
CPU time 4.6 seconds
Started Jun 04 03:04:44 PM PDT 24
Finished Jun 04 03:04:49 PM PDT 24
Peak memory 242364 kb
Host smart-d147482e-5d8b-4ebe-b126-e4a1d1bdd135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31170475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.31170475
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.3166979240
Short name T38
Test name
Test status
Simulation time 2219168400 ps
CPU time 6.1 seconds
Started Jun 04 03:04:40 PM PDT 24
Finished Jun 04 03:04:47 PM PDT 24
Peak memory 242440 kb
Host smart-7964c809-f581-4e17-8a9d-3d550405506b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166979240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.3166979240
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.3449398895
Short name T409
Test name
Test status
Simulation time 163900100 ps
CPU time 1.83 seconds
Started Jun 04 03:01:18 PM PDT 24
Finished Jun 04 03:01:21 PM PDT 24
Peak memory 241104 kb
Host smart-5c6966d2-8f71-424c-93c8-b8c29ca8ad98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449398895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.3449398895
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.3545957534
Short name T506
Test name
Test status
Simulation time 301747415 ps
CPU time 6.49 seconds
Started Jun 04 03:01:17 PM PDT 24
Finished Jun 04 03:01:24 PM PDT 24
Peak memory 242340 kb
Host smart-1ed3253f-3161-4534-beb0-10fd02248677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545957534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.3545957534
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.3388539415
Short name T514
Test name
Test status
Simulation time 382763600 ps
CPU time 9.97 seconds
Started Jun 04 03:01:18 PM PDT 24
Finished Jun 04 03:01:30 PM PDT 24
Peak memory 242664 kb
Host smart-991c0e1d-a866-4844-99b3-3e426e19ff51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388539415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.3388539415
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.2453761474
Short name T830
Test name
Test status
Simulation time 736235037 ps
CPU time 14.93 seconds
Started Jun 04 03:01:18 PM PDT 24
Finished Jun 04 03:01:34 PM PDT 24
Peak memory 248892 kb
Host smart-673cdb7a-3e62-4e67-9b2f-8d8c178ec6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453761474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.2453761474
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.2601683605
Short name T79
Test name
Test status
Simulation time 502258315 ps
CPU time 5.3 seconds
Started Jun 04 03:01:23 PM PDT 24
Finished Jun 04 03:01:28 PM PDT 24
Peak memory 242432 kb
Host smart-cf929921-0781-40f7-a1bd-f116aa1269a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601683605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.2601683605
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.2260870337
Short name T1022
Test name
Test status
Simulation time 220074368 ps
CPU time 4.69 seconds
Started Jun 04 03:01:20 PM PDT 24
Finished Jun 04 03:01:26 PM PDT 24
Peak memory 242648 kb
Host smart-955a47f2-d9c4-4f1e-89f6-1b082294d55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260870337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.2260870337
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.2292858380
Short name T936
Test name
Test status
Simulation time 363063879 ps
CPU time 7.98 seconds
Started Jun 04 03:01:25 PM PDT 24
Finished Jun 04 03:01:34 PM PDT 24
Peak memory 242292 kb
Host smart-b50d56fd-c8c6-4b70-9999-175e346c7427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292858380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.2292858380
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.1903093527
Short name T733
Test name
Test status
Simulation time 991736804 ps
CPU time 16.02 seconds
Started Jun 04 03:01:20 PM PDT 24
Finished Jun 04 03:01:37 PM PDT 24
Peak memory 242224 kb
Host smart-fdf11b3f-b8f1-4c2f-b774-a98a72eebb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903093527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.1903093527
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.589237146
Short name T378
Test name
Test status
Simulation time 271942982 ps
CPU time 8.56 seconds
Started Jun 04 03:01:22 PM PDT 24
Finished Jun 04 03:01:32 PM PDT 24
Peak memory 242204 kb
Host smart-fba1b7d3-0b73-45c2-b260-dae9dfca2f18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=589237146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.589237146
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.1407364809
Short name T401
Test name
Test status
Simulation time 255250198 ps
CPU time 5.52 seconds
Started Jun 04 03:01:20 PM PDT 24
Finished Jun 04 03:01:26 PM PDT 24
Peak memory 242284 kb
Host smart-d5d19c88-5bf3-4bbf-8a33-5808d2e79943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407364809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.1407364809
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.723949751
Short name T113
Test name
Test status
Simulation time 13744653427 ps
CPU time 239.88 seconds
Started Jun 04 03:01:17 PM PDT 24
Finished Jun 04 03:05:18 PM PDT 24
Peak memory 249884 kb
Host smart-c97c77e6-e4d1-41f3-9077-378aa45d95be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723949751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.
723949751
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.2585160659
Short name T1099
Test name
Test status
Simulation time 113187526905 ps
CPU time 817.39 seconds
Started Jun 04 03:01:23 PM PDT 24
Finished Jun 04 03:15:01 PM PDT 24
Peak memory 257296 kb
Host smart-d3ad0f7a-9ce6-43ee-86ff-1511ad87c228
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585160659 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.2585160659
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.3629849390
Short name T1050
Test name
Test status
Simulation time 648165072 ps
CPU time 15.87 seconds
Started Jun 04 03:01:18 PM PDT 24
Finished Jun 04 03:01:35 PM PDT 24
Peak memory 242532 kb
Host smart-b9b0450a-953e-4397-8602-0ebf0ffc172c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629849390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.3629849390
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.1819608876
Short name T650
Test name
Test status
Simulation time 235587395 ps
CPU time 4.85 seconds
Started Jun 04 03:04:45 PM PDT 24
Finished Jun 04 03:04:50 PM PDT 24
Peak memory 242488 kb
Host smart-c457448d-5976-4b3a-83a4-73d6cb2fb9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819608876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.1819608876
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.2170869051
Short name T310
Test name
Test status
Simulation time 262334579 ps
CPU time 5.16 seconds
Started Jun 04 03:04:41 PM PDT 24
Finished Jun 04 03:04:47 PM PDT 24
Peak memory 242248 kb
Host smart-1cd35b20-037f-4872-bdd7-1f3ece930938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170869051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.2170869051
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.3157316876
Short name T606
Test name
Test status
Simulation time 226936829 ps
CPU time 4.37 seconds
Started Jun 04 03:04:41 PM PDT 24
Finished Jun 04 03:04:47 PM PDT 24
Peak memory 242272 kb
Host smart-905bed4b-2284-47aa-be52-cf135c343913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157316876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.3157316876
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.398803003
Short name T158
Test name
Test status
Simulation time 2105665138 ps
CPU time 5.49 seconds
Started Jun 04 03:04:43 PM PDT 24
Finished Jun 04 03:04:49 PM PDT 24
Peak memory 242572 kb
Host smart-a5cc2c3a-cb1e-46ab-a75f-75595e765ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398803003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.398803003
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.985335570
Short name T104
Test name
Test status
Simulation time 605551123 ps
CPU time 4.37 seconds
Started Jun 04 03:04:41 PM PDT 24
Finished Jun 04 03:04:46 PM PDT 24
Peak memory 242420 kb
Host smart-a9c70732-55f7-424e-94e2-24ca487f9084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985335570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.985335570
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.2905602933
Short name T49
Test name
Test status
Simulation time 188298573 ps
CPU time 4.95 seconds
Started Jun 04 03:04:41 PM PDT 24
Finished Jun 04 03:04:47 PM PDT 24
Peak memory 242384 kb
Host smart-921a49f9-d488-4b29-b910-1af7bda831bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905602933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.2905602933
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.4047840097
Short name T718
Test name
Test status
Simulation time 404706873 ps
CPU time 4.5 seconds
Started Jun 04 03:04:44 PM PDT 24
Finished Jun 04 03:04:50 PM PDT 24
Peak memory 242340 kb
Host smart-04500bdd-57d1-4256-9da0-56d6a6ab1058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047840097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.4047840097
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.956728303
Short name T671
Test name
Test status
Simulation time 185551761 ps
CPU time 4.88 seconds
Started Jun 04 03:04:44 PM PDT 24
Finished Jun 04 03:04:49 PM PDT 24
Peak memory 242412 kb
Host smart-05a50523-15ad-4406-bf49-e8754faec257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956728303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.956728303
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.22244375
Short name T684
Test name
Test status
Simulation time 103568372 ps
CPU time 3.59 seconds
Started Jun 04 03:04:41 PM PDT 24
Finished Jun 04 03:04:46 PM PDT 24
Peak memory 242668 kb
Host smart-7c9b7498-542b-4a8e-adfb-f35b1cc9f142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22244375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.22244375
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.432628488
Short name T1036
Test name
Test status
Simulation time 316590060 ps
CPU time 3.23 seconds
Started Jun 04 03:04:41 PM PDT 24
Finished Jun 04 03:04:46 PM PDT 24
Peak memory 242380 kb
Host smart-53b36a9c-2ea9-4b07-9fb6-d667574b4316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432628488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.432628488
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.1399864896
Short name T1024
Test name
Test status
Simulation time 159971250 ps
CPU time 2.64 seconds
Started Jun 04 03:01:18 PM PDT 24
Finished Jun 04 03:01:22 PM PDT 24
Peak memory 241108 kb
Host smart-70a34b72-8b88-447c-a4f6-0e58837f311e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399864896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.1399864896
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.921723649
Short name T808
Test name
Test status
Simulation time 1580255781 ps
CPU time 15.98 seconds
Started Jun 04 03:01:40 PM PDT 24
Finished Jun 04 03:01:57 PM PDT 24
Peak memory 249080 kb
Host smart-5d6113e5-5e79-4162-ab9e-f0486d461966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921723649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.921723649
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.817241556
Short name T642
Test name
Test status
Simulation time 649896655 ps
CPU time 10.11 seconds
Started Jun 04 03:01:19 PM PDT 24
Finished Jun 04 03:01:30 PM PDT 24
Peak memory 242624 kb
Host smart-c5a8a025-65f1-428e-a76e-36e6e6275372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817241556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.817241556
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.2371255199
Short name T777
Test name
Test status
Simulation time 443188044 ps
CPU time 10.3 seconds
Started Jun 04 03:01:17 PM PDT 24
Finished Jun 04 03:01:29 PM PDT 24
Peak memory 242420 kb
Host smart-21056bf5-0431-4d8e-9bbf-6ecc2741c459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371255199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.2371255199
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.1763229951
Short name T1170
Test name
Test status
Simulation time 127527557 ps
CPU time 3.38 seconds
Started Jun 04 03:01:19 PM PDT 24
Finished Jun 04 03:01:23 PM PDT 24
Peak memory 242276 kb
Host smart-fe24b86b-d4df-4626-b588-2b0ae671ad4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763229951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.1763229951
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.2781078041
Short name T553
Test name
Test status
Simulation time 1508678387 ps
CPU time 28.6 seconds
Started Jun 04 03:01:17 PM PDT 24
Finished Jun 04 03:01:47 PM PDT 24
Peak memory 242724 kb
Host smart-53bc8c7d-ceb1-4bd3-ab4f-872a66538728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781078041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.2781078041
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.3055293491
Short name T178
Test name
Test status
Simulation time 763480176 ps
CPU time 6.72 seconds
Started Jun 04 03:01:26 PM PDT 24
Finished Jun 04 03:01:33 PM PDT 24
Peak memory 242360 kb
Host smart-2e030ed6-d6b5-437f-9542-2041dbebf4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055293491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.3055293491
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.2021790365
Short name T146
Test name
Test status
Simulation time 564960845 ps
CPU time 15.15 seconds
Started Jun 04 03:01:19 PM PDT 24
Finished Jun 04 03:01:35 PM PDT 24
Peak memory 242176 kb
Host smart-05c390ec-b814-4f4a-a042-2dee264f39a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021790365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.2021790365
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.2625103266
Short name T846
Test name
Test status
Simulation time 967145118 ps
CPU time 30.68 seconds
Started Jun 04 03:01:18 PM PDT 24
Finished Jun 04 03:01:50 PM PDT 24
Peak memory 242172 kb
Host smart-2e155e05-be1c-497c-94ea-90c97b609426
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2625103266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.2625103266
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.622953208
Short name T1122
Test name
Test status
Simulation time 3325197320 ps
CPU time 10.17 seconds
Started Jun 04 03:01:18 PM PDT 24
Finished Jun 04 03:01:29 PM PDT 24
Peak memory 242208 kb
Host smart-9c993cea-cdc6-49ee-9b4f-2fc9a5fb1851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=622953208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.622953208
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.3770822563
Short name T666
Test name
Test status
Simulation time 474460029 ps
CPU time 6.07 seconds
Started Jun 04 03:01:17 PM PDT 24
Finished Jun 04 03:01:24 PM PDT 24
Peak memory 242184 kb
Host smart-0aa309b8-f00b-467f-981f-4eaea94f930a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770822563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.3770822563
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.2282749709
Short name T159
Test name
Test status
Simulation time 20704643121 ps
CPU time 150.77 seconds
Started Jun 04 03:01:28 PM PDT 24
Finished Jun 04 03:04:00 PM PDT 24
Peak memory 247876 kb
Host smart-5e7c16bc-9f1d-48ba-afeb-fcb0ea4621d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282749709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.2282749709
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.2179316033
Short name T947
Test name
Test status
Simulation time 92308685066 ps
CPU time 2533.1 seconds
Started Jun 04 03:01:18 PM PDT 24
Finished Jun 04 03:43:33 PM PDT 24
Peak memory 427504 kb
Host smart-a556c703-cb01-4e0a-9c32-3551579c83b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179316033 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.2179316033
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.3763672921
Short name T1168
Test name
Test status
Simulation time 1593549650 ps
CPU time 24.26 seconds
Started Jun 04 03:01:18 PM PDT 24
Finished Jun 04 03:01:44 PM PDT 24
Peak memory 242192 kb
Host smart-d6466626-7b94-4d5f-872a-ebfa0ed9bf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763672921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.3763672921
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.210323374
Short name T602
Test name
Test status
Simulation time 254540933 ps
CPU time 4.95 seconds
Started Jun 04 03:04:43 PM PDT 24
Finished Jun 04 03:04:49 PM PDT 24
Peak memory 242580 kb
Host smart-5a42465b-2e24-4b26-9736-6512c7a1f578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210323374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.210323374
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.2323748832
Short name T1188
Test name
Test status
Simulation time 168493868 ps
CPU time 4.73 seconds
Started Jun 04 03:04:40 PM PDT 24
Finished Jun 04 03:04:46 PM PDT 24
Peak memory 242420 kb
Host smart-02f01f2e-f5b4-4c21-9270-0860129275ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323748832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.2323748832
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.1456127695
Short name T495
Test name
Test status
Simulation time 1853934726 ps
CPU time 5.99 seconds
Started Jun 04 03:04:42 PM PDT 24
Finished Jun 04 03:04:49 PM PDT 24
Peak memory 242324 kb
Host smart-597600e5-18d3-48a9-83cd-cc76ead5987d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456127695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.1456127695
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.3590624472
Short name T696
Test name
Test status
Simulation time 234732618 ps
CPU time 3.14 seconds
Started Jun 04 03:04:41 PM PDT 24
Finished Jun 04 03:04:45 PM PDT 24
Peak memory 242380 kb
Host smart-4e96462c-8d8e-4bca-8867-10cf8109d30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590624472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.3590624472
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.1702408757
Short name T124
Test name
Test status
Simulation time 215700853 ps
CPU time 4.37 seconds
Started Jun 04 03:04:43 PM PDT 24
Finished Jun 04 03:04:48 PM PDT 24
Peak memory 242312 kb
Host smart-cd48d0c1-3009-4cf9-9354-db296d1f959f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702408757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.1702408757
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.649840089
Short name T1083
Test name
Test status
Simulation time 394097701 ps
CPU time 5.24 seconds
Started Jun 04 03:04:40 PM PDT 24
Finished Jun 04 03:04:46 PM PDT 24
Peak memory 242252 kb
Host smart-42713eaa-a8db-4fa3-9031-3064addae839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649840089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.649840089
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.1159882541
Short name T1119
Test name
Test status
Simulation time 408692944 ps
CPU time 4.22 seconds
Started Jun 04 03:04:48 PM PDT 24
Finished Jun 04 03:04:54 PM PDT 24
Peak memory 242276 kb
Host smart-aa9f86eb-e4e6-4ed2-baa0-261fb12f4d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159882541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.1159882541
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.761971726
Short name T152
Test name
Test status
Simulation time 247073822 ps
CPU time 4.33 seconds
Started Jun 04 03:04:49 PM PDT 24
Finished Jun 04 03:04:54 PM PDT 24
Peak memory 242640 kb
Host smart-da543666-5e22-44d0-a292-e37697aaf9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761971726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.761971726
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.373897221
Short name T895
Test name
Test status
Simulation time 178251228 ps
CPU time 3.53 seconds
Started Jun 04 03:04:49 PM PDT 24
Finished Jun 04 03:04:54 PM PDT 24
Peak memory 242348 kb
Host smart-5581d5a8-a940-40c3-ae39-140e1f72887b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373897221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.373897221
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.527958624
Short name T499
Test name
Test status
Simulation time 157105126 ps
CPU time 1.91 seconds
Started Jun 04 03:01:31 PM PDT 24
Finished Jun 04 03:01:34 PM PDT 24
Peak memory 240828 kb
Host smart-811c251c-3baa-466c-9f9e-60309cd956ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527958624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.527958624
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.373500268
Short name T56
Test name
Test status
Simulation time 1514533235 ps
CPU time 29.22 seconds
Started Jun 04 03:01:30 PM PDT 24
Finished Jun 04 03:02:00 PM PDT 24
Peak memory 248988 kb
Host smart-2b4f9378-ac60-4063-9a99-e7e6f4776615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373500268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.373500268
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.1693795571
Short name T755
Test name
Test status
Simulation time 212450918 ps
CPU time 10.51 seconds
Started Jun 04 03:01:38 PM PDT 24
Finished Jun 04 03:01:49 PM PDT 24
Peak memory 242468 kb
Host smart-fe470893-8012-4f9a-bb8a-238662ee8efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693795571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.1693795571
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.3067253254
Short name T1004
Test name
Test status
Simulation time 12613304958 ps
CPU time 40.53 seconds
Started Jun 04 03:01:36 PM PDT 24
Finished Jun 04 03:02:18 PM PDT 24
Peak memory 242552 kb
Host smart-db3aa5b7-9622-497d-b5d3-ed5fcfdee671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067253254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.3067253254
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.2613878313
Short name T1176
Test name
Test status
Simulation time 1748284017 ps
CPU time 7.14 seconds
Started Jun 04 03:01:17 PM PDT 24
Finished Jun 04 03:01:25 PM PDT 24
Peak memory 242732 kb
Host smart-68b254a9-898e-4ac6-9d79-1e9e882cae1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613878313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.2613878313
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.3048512461
Short name T726
Test name
Test status
Simulation time 2205364526 ps
CPU time 16.47 seconds
Started Jun 04 03:01:30 PM PDT 24
Finished Jun 04 03:01:47 PM PDT 24
Peak memory 249064 kb
Host smart-dc836493-1ebe-44a2-8298-360f1342ab59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048512461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.3048512461
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.1735840869
Short name T93
Test name
Test status
Simulation time 2528012450 ps
CPU time 52.71 seconds
Started Jun 04 03:01:37 PM PDT 24
Finished Jun 04 03:02:30 PM PDT 24
Peak memory 242264 kb
Host smart-ad086b12-4d27-4ff7-bde2-43c48a7e24c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735840869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.1735840869
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.375415870
Short name T674
Test name
Test status
Simulation time 1559652839 ps
CPU time 3.73 seconds
Started Jun 04 03:01:30 PM PDT 24
Finished Jun 04 03:01:34 PM PDT 24
Peak memory 242408 kb
Host smart-88d62fe6-4f58-4173-a733-46b56b2ba98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375415870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.375415870
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.1388371798
Short name T972
Test name
Test status
Simulation time 428354985 ps
CPU time 12.61 seconds
Started Jun 04 03:01:36 PM PDT 24
Finished Jun 04 03:01:50 PM PDT 24
Peak memory 248780 kb
Host smart-bab35ccb-43ed-4c0f-ba79-859c5e225afc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388371798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.1388371798
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.2038503803
Short name T963
Test name
Test status
Simulation time 559565081 ps
CPU time 11.02 seconds
Started Jun 04 03:01:36 PM PDT 24
Finished Jun 04 03:01:48 PM PDT 24
Peak memory 242268 kb
Host smart-ec0f3e17-1325-4b35-9302-e6ca9ed6896e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2038503803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.2038503803
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.1567714673
Short name T1177
Test name
Test status
Simulation time 2024583036 ps
CPU time 6.36 seconds
Started Jun 04 03:01:17 PM PDT 24
Finished Jun 04 03:01:24 PM PDT 24
Peak memory 242284 kb
Host smart-0400aecb-181e-41d7-869e-b6fce9ea4189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567714673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.1567714673
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.1194130438
Short name T19
Test name
Test status
Simulation time 143146913797 ps
CPU time 1318.78 seconds
Started Jun 04 03:01:30 PM PDT 24
Finished Jun 04 03:23:30 PM PDT 24
Peak memory 412476 kb
Host smart-12af9f8a-e4bb-4568-9a64-d6456d7e83ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194130438 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.1194130438
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.88273677
Short name T694
Test name
Test status
Simulation time 14136608196 ps
CPU time 23.59 seconds
Started Jun 04 03:01:36 PM PDT 24
Finished Jun 04 03:02:00 PM PDT 24
Peak memory 243336 kb
Host smart-3e8273c4-7470-48ee-8a11-4cfd15238177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88273677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.88273677
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.59831862
Short name T915
Test name
Test status
Simulation time 172303662 ps
CPU time 4.83 seconds
Started Jun 04 03:04:55 PM PDT 24
Finished Jun 04 03:05:00 PM PDT 24
Peak memory 242336 kb
Host smart-708d24cc-adbf-4931-8333-868f6d25aad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59831862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.59831862
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.2735266373
Short name T627
Test name
Test status
Simulation time 2536864656 ps
CPU time 7.54 seconds
Started Jun 04 03:04:51 PM PDT 24
Finished Jun 04 03:04:59 PM PDT 24
Peak memory 242452 kb
Host smart-e8049d81-2d23-4310-bcb2-fcad8b62432b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735266373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.2735266373
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.3779322103
Short name T988
Test name
Test status
Simulation time 124672220 ps
CPU time 3.62 seconds
Started Jun 04 03:04:49 PM PDT 24
Finished Jun 04 03:04:54 PM PDT 24
Peak memory 242436 kb
Host smart-c59b0a18-1e80-49c9-89ed-756e5a605792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779322103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.3779322103
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.2827754560
Short name T515
Test name
Test status
Simulation time 146010456 ps
CPU time 4.44 seconds
Started Jun 04 03:04:48 PM PDT 24
Finished Jun 04 03:04:54 PM PDT 24
Peak memory 242376 kb
Host smart-4da03095-14a0-46a0-b9ce-3a3a5a8019a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827754560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.2827754560
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.938744850
Short name T677
Test name
Test status
Simulation time 303831868 ps
CPU time 4.69 seconds
Started Jun 04 03:04:52 PM PDT 24
Finished Jun 04 03:04:58 PM PDT 24
Peak memory 242232 kb
Host smart-209040ca-57b9-4152-b5d6-dcc51476ff97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938744850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.938744850
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.3799166897
Short name T782
Test name
Test status
Simulation time 1689854650 ps
CPU time 4.67 seconds
Started Jun 04 03:04:51 PM PDT 24
Finished Jun 04 03:04:57 PM PDT 24
Peak memory 242452 kb
Host smart-d52de523-c4a6-4ebf-ad77-78e923384f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799166897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.3799166897
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.1062182250
Short name T129
Test name
Test status
Simulation time 348353093 ps
CPU time 4.29 seconds
Started Jun 04 03:04:52 PM PDT 24
Finished Jun 04 03:04:57 PM PDT 24
Peak memory 242484 kb
Host smart-bc799db6-8f25-4fc1-ad90-9b5c888233d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062182250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.1062182250
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.3602278704
Short name T801
Test name
Test status
Simulation time 1831202643 ps
CPU time 7.08 seconds
Started Jun 04 03:04:49 PM PDT 24
Finished Jun 04 03:04:57 PM PDT 24
Peak memory 242676 kb
Host smart-2f56212d-4e32-408c-be4a-5178c2f0a40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602278704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.3602278704
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.3399558733
Short name T1193
Test name
Test status
Simulation time 130347709 ps
CPU time 4.43 seconds
Started Jun 04 03:04:52 PM PDT 24
Finished Jun 04 03:04:57 PM PDT 24
Peak memory 242352 kb
Host smart-fe61c658-9c4e-4b5e-a185-4f5164a2f024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399558733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.3399558733
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.2221913821
Short name T513
Test name
Test status
Simulation time 77021778 ps
CPU time 1.54 seconds
Started Jun 04 03:01:39 PM PDT 24
Finished Jun 04 03:01:41 PM PDT 24
Peak memory 240748 kb
Host smart-76e42881-d2e2-48f3-a145-93a57012cbe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221913821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.2221913821
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.2679119213
Short name T673
Test name
Test status
Simulation time 623094310 ps
CPU time 10.84 seconds
Started Jun 04 03:01:41 PM PDT 24
Finished Jun 04 03:01:53 PM PDT 24
Peak memory 242744 kb
Host smart-89147920-22ff-4648-9965-ae34c2e24bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679119213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.2679119213
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.3425392502
Short name T1154
Test name
Test status
Simulation time 16820348941 ps
CPU time 59.53 seconds
Started Jun 04 03:01:42 PM PDT 24
Finished Jun 04 03:02:43 PM PDT 24
Peak memory 249736 kb
Host smart-efca7d34-864c-41b0-9bc5-b9e962579cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425392502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.3425392502
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.3881243365
Short name T1023
Test name
Test status
Simulation time 8681657956 ps
CPU time 16.9 seconds
Started Jun 04 03:01:41 PM PDT 24
Finished Jun 04 03:01:59 PM PDT 24
Peak memory 242824 kb
Host smart-49c2b3a6-c50c-433c-abd2-ac0d0ead4dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881243365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.3881243365
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.2966840858
Short name T343
Test name
Test status
Simulation time 486688990 ps
CPU time 5.28 seconds
Started Jun 04 03:01:30 PM PDT 24
Finished Jun 04 03:01:36 PM PDT 24
Peak memory 242348 kb
Host smart-2e1dc67c-bfc6-454d-bb57-339dc8f19a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966840858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.2966840858
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.3137596050
Short name T930
Test name
Test status
Simulation time 550621230 ps
CPU time 12.8 seconds
Started Jun 04 03:01:39 PM PDT 24
Finished Jun 04 03:01:53 PM PDT 24
Peak memory 242284 kb
Host smart-f9d5ee03-0911-4300-883f-c40223de88f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137596050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.3137596050
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.692208120
Short name T709
Test name
Test status
Simulation time 592757547 ps
CPU time 16.34 seconds
Started Jun 04 03:01:37 PM PDT 24
Finished Jun 04 03:01:54 PM PDT 24
Peak memory 242584 kb
Host smart-420449dd-3979-4d37-ad3e-e1a8a41390fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692208120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.692208120
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.3716173447
Short name T148
Test name
Test status
Simulation time 1471065337 ps
CPU time 25.79 seconds
Started Jun 04 03:01:32 PM PDT 24
Finished Jun 04 03:01:59 PM PDT 24
Peak memory 248740 kb
Host smart-1e1c1301-049f-4f14-ad19-97fade6eae74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3716173447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.3716173447
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.2090285962
Short name T608
Test name
Test status
Simulation time 2228750088 ps
CPU time 7.97 seconds
Started Jun 04 03:01:38 PM PDT 24
Finished Jun 04 03:01:47 PM PDT 24
Peak memory 242372 kb
Host smart-e67053ef-afff-4e90-aa48-b5fa152479c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2090285962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.2090285962
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.1452735652
Short name T394
Test name
Test status
Simulation time 263449870 ps
CPU time 7.44 seconds
Started Jun 04 03:01:31 PM PDT 24
Finished Jun 04 03:01:39 PM PDT 24
Peak memory 248096 kb
Host smart-9ab59950-3c11-46e7-8dad-1f907f695ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452735652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.1452735652
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.2561922718
Short name T576
Test name
Test status
Simulation time 19207712995 ps
CPU time 111.9 seconds
Started Jun 04 03:01:45 PM PDT 24
Finished Jun 04 03:03:37 PM PDT 24
Peak memory 270824 kb
Host smart-39d92aee-f046-451f-b06c-3cb2047aae29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561922718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.2561922718
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.2821397962
Short name T154
Test name
Test status
Simulation time 683013886033 ps
CPU time 881.77 seconds
Started Jun 04 03:01:42 PM PDT 24
Finished Jun 04 03:16:25 PM PDT 24
Peak memory 295448 kb
Host smart-68210beb-4a64-42e3-b9f8-897ff8d1c80c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821397962 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.2821397962
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.4294918200
Short name T188
Test name
Test status
Simulation time 455976824 ps
CPU time 17.98 seconds
Started Jun 04 03:01:39 PM PDT 24
Finished Jun 04 03:01:58 PM PDT 24
Peak memory 242332 kb
Host smart-cdf576c1-c3f5-4a03-97ae-3e6549f69d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294918200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.4294918200
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.1749686993
Short name T983
Test name
Test status
Simulation time 101399864 ps
CPU time 3.77 seconds
Started Jun 04 03:04:49 PM PDT 24
Finished Jun 04 03:04:53 PM PDT 24
Peak memory 242328 kb
Host smart-92c9ed17-da89-4beb-a3fe-20ac0242806e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749686993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.1749686993
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.197885744
Short name T172
Test name
Test status
Simulation time 315416599 ps
CPU time 4.45 seconds
Started Jun 04 03:04:49 PM PDT 24
Finished Jun 04 03:04:54 PM PDT 24
Peak memory 242636 kb
Host smart-5c7bbf40-d5ed-486a-b111-61868bec4cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197885744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.197885744
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.1311261383
Short name T444
Test name
Test status
Simulation time 326179860 ps
CPU time 3.17 seconds
Started Jun 04 03:04:51 PM PDT 24
Finished Jun 04 03:04:54 PM PDT 24
Peak memory 242672 kb
Host smart-534d4489-7d8c-4363-b8e5-5fc0ce4f952e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311261383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.1311261383
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.3472976497
Short name T917
Test name
Test status
Simulation time 559885920 ps
CPU time 4.83 seconds
Started Jun 04 03:04:49 PM PDT 24
Finished Jun 04 03:04:55 PM PDT 24
Peak memory 242488 kb
Host smart-2f77051a-1327-477d-bb6b-e59a980640cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472976497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.3472976497
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.2577670376
Short name T250
Test name
Test status
Simulation time 1627500044 ps
CPU time 5.63 seconds
Started Jun 04 03:04:55 PM PDT 24
Finished Jun 04 03:05:01 PM PDT 24
Peak memory 242608 kb
Host smart-2caa7180-cdc4-4165-bed6-5a7d32b371c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577670376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.2577670376
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.3985190336
Short name T1094
Test name
Test status
Simulation time 471326180 ps
CPU time 4.04 seconds
Started Jun 04 03:04:49 PM PDT 24
Finished Jun 04 03:04:54 PM PDT 24
Peak memory 242688 kb
Host smart-4ce844b8-4e6c-48e7-beee-fdd8cba4df03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985190336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.3985190336
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.87029361
Short name T452
Test name
Test status
Simulation time 113618217 ps
CPU time 4.32 seconds
Started Jun 04 03:04:50 PM PDT 24
Finished Jun 04 03:04:55 PM PDT 24
Peak memory 242736 kb
Host smart-59118241-74fb-4e5b-b428-1743efcbaca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87029361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.87029361
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.3219472547
Short name T437
Test name
Test status
Simulation time 259092694 ps
CPU time 4.73 seconds
Started Jun 04 03:04:51 PM PDT 24
Finished Jun 04 03:04:56 PM PDT 24
Peak memory 242692 kb
Host smart-eefe66f7-8da8-429a-80ff-ec5713a86088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219472547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.3219472547
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.1226021573
Short name T1071
Test name
Test status
Simulation time 119765882 ps
CPU time 3.16 seconds
Started Jun 04 03:04:50 PM PDT 24
Finished Jun 04 03:04:54 PM PDT 24
Peak memory 242580 kb
Host smart-dccc561a-fd83-48a7-a4c5-6f286000da93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226021573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.1226021573
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.337739197
Short name T115
Test name
Test status
Simulation time 269771137 ps
CPU time 3.98 seconds
Started Jun 04 03:04:52 PM PDT 24
Finished Jun 04 03:04:57 PM PDT 24
Peak memory 242432 kb
Host smart-5a75e44c-e5a6-442d-bd4a-afd72b805d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337739197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.337739197
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.469764500
Short name T1194
Test name
Test status
Simulation time 269379848 ps
CPU time 2.36 seconds
Started Jun 04 02:59:29 PM PDT 24
Finished Jun 04 02:59:32 PM PDT 24
Peak memory 241036 kb
Host smart-a7929cba-0913-4eca-8d3d-506f44579ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469764500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.469764500
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.4109306672
Short name T676
Test name
Test status
Simulation time 2007257677 ps
CPU time 12.07 seconds
Started Jun 04 02:59:18 PM PDT 24
Finished Jun 04 02:59:30 PM PDT 24
Peak memory 242472 kb
Host smart-b3e838cb-2bbd-4a23-9728-32853bca19e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109306672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.4109306672
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.2917491895
Short name T41
Test name
Test status
Simulation time 1019756254 ps
CPU time 15.83 seconds
Started Jun 04 02:59:14 PM PDT 24
Finished Jun 04 02:59:31 PM PDT 24
Peak memory 242344 kb
Host smart-4d02001c-6c5a-491d-b6fb-65f3b4c33207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917491895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.2917491895
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.3046898659
Short name T354
Test name
Test status
Simulation time 8944000396 ps
CPU time 28.17 seconds
Started Jun 04 02:59:15 PM PDT 24
Finished Jun 04 02:59:44 PM PDT 24
Peak memory 242404 kb
Host smart-9f7d96ff-423d-416f-9c61-fe35a8d53a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046898659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.3046898659
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.4165313536
Short name T925
Test name
Test status
Simulation time 1174361571 ps
CPU time 7.44 seconds
Started Jun 04 02:59:15 PM PDT 24
Finished Jun 04 02:59:22 PM PDT 24
Peak memory 242532 kb
Host smart-0c379357-7ce9-4f12-9b23-60e06c291bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165313536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.4165313536
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.783866500
Short name T43
Test name
Test status
Simulation time 516996374 ps
CPU time 5.32 seconds
Started Jun 04 02:59:15 PM PDT 24
Finished Jun 04 02:59:21 PM PDT 24
Peak memory 242704 kb
Host smart-40722d72-ec74-4ea9-89c3-74ef9470f177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783866500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.783866500
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.838323978
Short name T1097
Test name
Test status
Simulation time 5826402625 ps
CPU time 63.2 seconds
Started Jun 04 02:59:14 PM PDT 24
Finished Jun 04 03:00:18 PM PDT 24
Peak memory 248976 kb
Host smart-088b2678-05f3-48f4-8d00-57676f6f0d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838323978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.838323978
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.595943628
Short name T89
Test name
Test status
Simulation time 1555900738 ps
CPU time 22.96 seconds
Started Jun 04 02:59:15 PM PDT 24
Finished Jun 04 02:59:39 PM PDT 24
Peak memory 242556 kb
Host smart-f128414c-599e-4335-92b6-0b60cbff6748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595943628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.595943628
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.1314565613
Short name T474
Test name
Test status
Simulation time 2421170353 ps
CPU time 12.29 seconds
Started Jun 04 02:59:15 PM PDT 24
Finished Jun 04 02:59:27 PM PDT 24
Peak memory 242576 kb
Host smart-9f13bf9c-d5dd-4fca-a706-262fac3d67d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314565613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.1314565613
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.972402711
Short name T643
Test name
Test status
Simulation time 8362782529 ps
CPU time 21.04 seconds
Started Jun 04 02:59:16 PM PDT 24
Finished Jun 04 02:59:37 PM PDT 24
Peak memory 242272 kb
Host smart-0facf9cb-088c-4803-a51f-d48e92cd2d3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=972402711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.972402711
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.2498717698
Short name T552
Test name
Test status
Simulation time 130017748 ps
CPU time 3.83 seconds
Started Jun 04 02:59:19 PM PDT 24
Finished Jun 04 02:59:23 PM PDT 24
Peak memory 242320 kb
Host smart-b45c0199-5a68-4326-9728-6088e6faa875
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2498717698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.2498717698
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.4005930352
Short name T615
Test name
Test status
Simulation time 843285252 ps
CPU time 4.58 seconds
Started Jun 04 02:59:16 PM PDT 24
Finished Jun 04 02:59:22 PM PDT 24
Peak memory 248208 kb
Host smart-88a549a5-b744-4a97-875e-e1c9185415d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005930352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.4005930352
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.2044321140
Short name T263
Test name
Test status
Simulation time 87018171128 ps
CPU time 297.31 seconds
Started Jun 04 02:59:16 PM PDT 24
Finished Jun 04 03:04:14 PM PDT 24
Peak memory 261372 kb
Host smart-7d990d13-8244-4e53-a3cf-7c8e5661ccdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044321140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.
2044321140
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.758877952
Short name T13
Test name
Test status
Simulation time 39318811242 ps
CPU time 455.88 seconds
Started Jun 04 02:59:15 PM PDT 24
Finished Jun 04 03:06:52 PM PDT 24
Peak memory 330736 kb
Host smart-eedb7739-f4dd-4165-a25d-45fb6ea1745e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758877952 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.758877952
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.47213597
Short name T1146
Test name
Test status
Simulation time 206013203 ps
CPU time 5.24 seconds
Started Jun 04 02:59:18 PM PDT 24
Finished Jun 04 02:59:24 PM PDT 24
Peak memory 242384 kb
Host smart-4ce677df-e373-4155-8cbf-59b235e052c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47213597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.47213597
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.684533579
Short name T533
Test name
Test status
Simulation time 295186047 ps
CPU time 2.13 seconds
Started Jun 04 03:01:45 PM PDT 24
Finished Jun 04 03:01:47 PM PDT 24
Peak memory 241028 kb
Host smart-9022908b-aab7-47e5-93c1-de9cd938b527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684533579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.684533579
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.1264993510
Short name T59
Test name
Test status
Simulation time 12415635581 ps
CPU time 24.6 seconds
Started Jun 04 03:01:41 PM PDT 24
Finished Jun 04 03:02:06 PM PDT 24
Peak memory 249044 kb
Host smart-c9c368a7-93f7-43ca-9c8a-da7ed98c4394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264993510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.1264993510
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.762812973
Short name T489
Test name
Test status
Simulation time 499493299 ps
CPU time 20.03 seconds
Started Jun 04 03:01:41 PM PDT 24
Finished Jun 04 03:02:02 PM PDT 24
Peak memory 242256 kb
Host smart-7df30663-1dcb-4bc3-b78c-0893deb5f554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762812973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.762812973
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.3149819995
Short name T756
Test name
Test status
Simulation time 14567272677 ps
CPU time 51.32 seconds
Started Jun 04 03:01:41 PM PDT 24
Finished Jun 04 03:02:33 PM PDT 24
Peak memory 243464 kb
Host smart-3000a6de-c627-401d-a95a-ed4ff02c1084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149819995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.3149819995
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.548266240
Short name T981
Test name
Test status
Simulation time 159359261 ps
CPU time 4.54 seconds
Started Jun 04 03:01:57 PM PDT 24
Finished Jun 04 03:02:03 PM PDT 24
Peak memory 242520 kb
Host smart-4d85a9d3-89b1-4335-b5b1-e964c3d9203e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548266240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.548266240
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.1768633610
Short name T142
Test name
Test status
Simulation time 1940379816 ps
CPU time 11.28 seconds
Started Jun 04 03:01:41 PM PDT 24
Finished Jun 04 03:01:53 PM PDT 24
Peak memory 242864 kb
Host smart-ef9a0100-50de-445a-9985-7bed0a62017b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768633610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.1768633610
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.1641381730
Short name T490
Test name
Test status
Simulation time 478784750 ps
CPU time 19.04 seconds
Started Jun 04 03:01:41 PM PDT 24
Finished Jun 04 03:02:01 PM PDT 24
Peak memory 242264 kb
Host smart-1a89a33c-ee5b-4c5f-b518-dea07a886e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641381730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.1641381730
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.2557429736
Short name T429
Test name
Test status
Simulation time 428307452 ps
CPU time 11.9 seconds
Started Jun 04 03:01:41 PM PDT 24
Finished Jun 04 03:01:54 PM PDT 24
Peak memory 242260 kb
Host smart-b640513e-5859-43a2-8ff3-4663fa7a3e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557429736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.2557429736
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.3211072588
Short name T572
Test name
Test status
Simulation time 393368706 ps
CPU time 10.39 seconds
Started Jun 04 03:01:39 PM PDT 24
Finished Jun 04 03:01:51 PM PDT 24
Peak memory 242208 kb
Host smart-01f181d3-d9de-4b7e-bc48-49b6fd4f8616
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3211072588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.3211072588
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.125852835
Short name T370
Test name
Test status
Simulation time 464374409 ps
CPU time 7.11 seconds
Started Jun 04 03:01:44 PM PDT 24
Finished Jun 04 03:01:52 PM PDT 24
Peak memory 242184 kb
Host smart-08269c60-39cc-4327-93be-84dbda31dfe1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=125852835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.125852835
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.2467026841
Short name T758
Test name
Test status
Simulation time 741676929 ps
CPU time 11.56 seconds
Started Jun 04 03:01:38 PM PDT 24
Finished Jun 04 03:01:50 PM PDT 24
Peak memory 242144 kb
Host smart-4014af07-8ad4-46f4-9ef4-d32080c4bbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467026841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.2467026841
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.2744021291
Short name T385
Test name
Test status
Simulation time 219657343 ps
CPU time 9.07 seconds
Started Jun 04 03:01:38 PM PDT 24
Finished Jun 04 03:01:47 PM PDT 24
Peak memory 242232 kb
Host smart-5f0f3a11-bdc9-48fb-8a4c-94d8044852de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744021291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all
.2744021291
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.2888673613
Short name T1115
Test name
Test status
Simulation time 11943394067 ps
CPU time 395.15 seconds
Started Jun 04 03:01:41 PM PDT 24
Finished Jun 04 03:08:17 PM PDT 24
Peak memory 330748 kb
Host smart-9935532f-9f7d-4da3-aaaf-e7b979d53fe3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888673613 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.2888673613
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.4085053037
Short name T1159
Test name
Test status
Simulation time 4296959019 ps
CPU time 23.79 seconds
Started Jun 04 03:01:41 PM PDT 24
Finished Jun 04 03:02:06 PM PDT 24
Peak memory 248952 kb
Host smart-1a7e05bd-7ade-4ba6-8b13-2816619f2242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085053037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.4085053037
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.1242564397
Short name T516
Test name
Test status
Simulation time 914283035 ps
CPU time 3.14 seconds
Started Jun 04 03:01:43 PM PDT 24
Finished Jun 04 03:01:47 PM PDT 24
Peak memory 240748 kb
Host smart-75ecce93-6c03-42f0-a27d-e57da0075a8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242564397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.1242564397
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.2771502292
Short name T107
Test name
Test status
Simulation time 1602218057 ps
CPU time 28.86 seconds
Started Jun 04 03:01:58 PM PDT 24
Finished Jun 04 03:02:27 PM PDT 24
Peak memory 249080 kb
Host smart-0ffca379-4fd2-41eb-b18b-401806760c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771502292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.2771502292
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.562935182
Short name T520
Test name
Test status
Simulation time 10055395190 ps
CPU time 17.02 seconds
Started Jun 04 03:01:46 PM PDT 24
Finished Jun 04 03:02:04 PM PDT 24
Peak memory 242600 kb
Host smart-1ae2a57e-383d-40da-82ed-608d854ee07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562935182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.562935182
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.1777575277
Short name T958
Test name
Test status
Simulation time 1115570676 ps
CPU time 10.16 seconds
Started Jun 04 03:01:46 PM PDT 24
Finished Jun 04 03:01:57 PM PDT 24
Peak memory 242348 kb
Host smart-07127b93-4d9d-4823-8d76-a32d76f00f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777575277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.1777575277
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.913455439
Short name T61
Test name
Test status
Simulation time 181500876 ps
CPU time 5.17 seconds
Started Jun 04 03:01:48 PM PDT 24
Finished Jun 04 03:01:55 PM PDT 24
Peak memory 242412 kb
Host smart-3c111743-6408-454c-9cf7-2adb9310ca7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913455439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.913455439
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.2729951625
Short name T521
Test name
Test status
Simulation time 3425486362 ps
CPU time 44.08 seconds
Started Jun 04 03:01:38 PM PDT 24
Finished Jun 04 03:02:23 PM PDT 24
Peak memory 257408 kb
Host smart-b8dd8cd7-8c91-492c-8d3f-881a78238c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729951625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.2729951625
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.4000752664
Short name T1114
Test name
Test status
Simulation time 1103715443 ps
CPU time 36.52 seconds
Started Jun 04 03:01:39 PM PDT 24
Finished Jun 04 03:02:17 PM PDT 24
Peak memory 242620 kb
Host smart-019f7751-8260-4a85-8c6b-978099edcd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000752664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.4000752664
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.446697677
Short name T522
Test name
Test status
Simulation time 118644133 ps
CPU time 3.53 seconds
Started Jun 04 03:01:44 PM PDT 24
Finished Jun 04 03:01:48 PM PDT 24
Peak memory 242104 kb
Host smart-285938da-2f39-4c3a-a0f9-906f525ab2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446697677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.446697677
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.3090959176
Short name T1063
Test name
Test status
Simulation time 6014109405 ps
CPU time 18.86 seconds
Started Jun 04 03:01:44 PM PDT 24
Finished Jun 04 03:02:04 PM PDT 24
Peak memory 242308 kb
Host smart-1c21fa98-d97e-4117-9517-cfa67df3ef0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3090959176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.3090959176
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.2485367335
Short name T373
Test name
Test status
Simulation time 1097443775 ps
CPU time 11.86 seconds
Started Jun 04 03:01:40 PM PDT 24
Finished Jun 04 03:01:53 PM PDT 24
Peak memory 242464 kb
Host smart-5d9c1b98-b448-48c8-942d-3c5c6acf6fc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2485367335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.2485367335
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.3823194919
Short name T1112
Test name
Test status
Simulation time 229134339 ps
CPU time 7.03 seconds
Started Jun 04 03:01:42 PM PDT 24
Finished Jun 04 03:01:50 PM PDT 24
Peak memory 242448 kb
Host smart-3768b140-71e5-444b-8b4d-e8e087e20404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823194919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.3823194919
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.3172460166
Short name T1133
Test name
Test status
Simulation time 19607023873 ps
CPU time 123.22 seconds
Started Jun 04 03:01:43 PM PDT 24
Finished Jun 04 03:03:47 PM PDT 24
Peak memory 257156 kb
Host smart-6072e79a-8339-4ba6-8e4a-067c4042f59b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172460166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.3172460166
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.2107483764
Short name T120
Test name
Test status
Simulation time 46272434274 ps
CPU time 1420.59 seconds
Started Jun 04 03:01:43 PM PDT 24
Finished Jun 04 03:25:25 PM PDT 24
Peak memory 414000 kb
Host smart-f8de4750-10fc-475e-97f5-9c273f5b8257
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107483764 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.2107483764
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.4189689141
Short name T215
Test name
Test status
Simulation time 4148257107 ps
CPU time 30.75 seconds
Started Jun 04 03:01:43 PM PDT 24
Finished Jun 04 03:02:15 PM PDT 24
Peak memory 242548 kb
Host smart-dc798eb1-5a7f-4314-95cd-15aea4241f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189689141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.4189689141
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.3722789496
Short name T767
Test name
Test status
Simulation time 113920169 ps
CPU time 1.64 seconds
Started Jun 04 03:01:47 PM PDT 24
Finished Jun 04 03:01:50 PM PDT 24
Peak memory 240748 kb
Host smart-e3d76e8e-6e6b-46e8-a6ae-fa39e2b7f30e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722789496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.3722789496
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.1288363704
Short name T728
Test name
Test status
Simulation time 1878155222 ps
CPU time 5.82 seconds
Started Jun 04 03:01:48 PM PDT 24
Finished Jun 04 03:01:55 PM PDT 24
Peak memory 242624 kb
Host smart-4a4e642f-215e-4349-accb-c293434bdec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288363704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.1288363704
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.1972290736
Short name T711
Test name
Test status
Simulation time 10590503088 ps
CPU time 23.74 seconds
Started Jun 04 03:01:49 PM PDT 24
Finished Jun 04 03:02:13 PM PDT 24
Peak memory 242340 kb
Host smart-7fd03822-786a-4c0e-8207-8a0f5e2e2ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972290736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.1972290736
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.2946609424
Short name T399
Test name
Test status
Simulation time 4035194201 ps
CPU time 12.7 seconds
Started Jun 04 03:01:40 PM PDT 24
Finished Jun 04 03:01:53 PM PDT 24
Peak memory 242584 kb
Host smart-ca8538f8-8b2f-4bfc-a4f9-e53224213304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946609424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.2946609424
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.3604394007
Short name T1082
Test name
Test status
Simulation time 333511067 ps
CPU time 4.81 seconds
Started Jun 04 03:01:46 PM PDT 24
Finished Jun 04 03:01:51 PM PDT 24
Peak memory 242424 kb
Host smart-2ff51209-40eb-4af4-8074-1ef4f5ff3dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604394007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.3604394007
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.2165030171
Short name T1014
Test name
Test status
Simulation time 14422010009 ps
CPU time 35.51 seconds
Started Jun 04 03:01:40 PM PDT 24
Finished Jun 04 03:02:16 PM PDT 24
Peak memory 246244 kb
Host smart-c76b2582-4080-4280-8b0a-dd82e3634b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165030171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.2165030171
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.1262168955
Short name T969
Test name
Test status
Simulation time 1702506261 ps
CPU time 20.79 seconds
Started Jun 04 03:01:43 PM PDT 24
Finished Jun 04 03:02:05 PM PDT 24
Peak memory 248888 kb
Host smart-30bfd4c8-7c62-415f-ad5c-2bc71b58e3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262168955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.1262168955
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.583533481
Short name T811
Test name
Test status
Simulation time 838940303 ps
CPU time 13.24 seconds
Started Jun 04 03:01:43 PM PDT 24
Finished Jun 04 03:01:57 PM PDT 24
Peak memory 242376 kb
Host smart-012de9f4-7c7d-4d79-925d-22dbfd0d0566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583533481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.583533481
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.3427654362
Short name T432
Test name
Test status
Simulation time 229901412 ps
CPU time 6.43 seconds
Started Jun 04 03:01:40 PM PDT 24
Finished Jun 04 03:01:48 PM PDT 24
Peak memory 242180 kb
Host smart-1e2a2dcd-6aee-4d94-b320-e6caa4793121
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3427654362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.3427654362
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.1136896465
Short name T1033
Test name
Test status
Simulation time 2462171938 ps
CPU time 6.79 seconds
Started Jun 04 03:01:43 PM PDT 24
Finished Jun 04 03:01:50 PM PDT 24
Peak memory 242328 kb
Host smart-77b360cd-63a2-4344-a530-428c4a2699a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1136896465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.1136896465
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.2179060986
Short name T665
Test name
Test status
Simulation time 145296581 ps
CPU time 6.49 seconds
Started Jun 04 03:01:42 PM PDT 24
Finished Jun 04 03:01:50 PM PDT 24
Peak memory 242284 kb
Host smart-bda48ef4-9e0d-4f5a-954e-8fa710f81ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179060986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.2179060986
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.903606483
Short name T243
Test name
Test status
Simulation time 11735889247 ps
CPU time 78.24 seconds
Started Jun 04 03:01:47 PM PDT 24
Finished Jun 04 03:03:06 PM PDT 24
Peak memory 258748 kb
Host smart-2f97b3f5-45dd-47b7-ad15-ba72792c55c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903606483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.
903606483
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.2671967578
Short name T1072
Test name
Test status
Simulation time 943595902152 ps
CPU time 2691.78 seconds
Started Jun 04 03:01:49 PM PDT 24
Finished Jun 04 03:46:43 PM PDT 24
Peak memory 447872 kb
Host smart-199a61e1-645e-4d57-b477-4fe589c8f8ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671967578 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.2671967578
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.1382167214
Short name T923
Test name
Test status
Simulation time 554850311 ps
CPU time 1.99 seconds
Started Jun 04 03:01:50 PM PDT 24
Finished Jun 04 03:01:53 PM PDT 24
Peak memory 240776 kb
Host smart-a47df238-d9d2-4baa-8311-aeac6e69026e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382167214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.1382167214
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.86293143
Short name T966
Test name
Test status
Simulation time 1902802365 ps
CPU time 19.05 seconds
Started Jun 04 03:01:50 PM PDT 24
Finished Jun 04 03:02:10 PM PDT 24
Peak memory 248960 kb
Host smart-e0ba3599-b05a-4c45-903e-21f2cf8df59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86293143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.86293143
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.2472658866
Short name T1158
Test name
Test status
Simulation time 212367446 ps
CPU time 13.46 seconds
Started Jun 04 03:01:48 PM PDT 24
Finished Jun 04 03:02:02 PM PDT 24
Peak memory 242304 kb
Host smart-8265a985-677f-469b-99bc-eb010fc46209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472658866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.2472658866
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.3385871165
Short name T894
Test name
Test status
Simulation time 7539891923 ps
CPU time 26.83 seconds
Started Jun 04 03:01:49 PM PDT 24
Finished Jun 04 03:02:17 PM PDT 24
Peak memory 248852 kb
Host smart-2f57abb1-3716-4913-aef1-246526596833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385871165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.3385871165
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.3140349758
Short name T935
Test name
Test status
Simulation time 276838692 ps
CPU time 3.99 seconds
Started Jun 04 03:01:48 PM PDT 24
Finished Jun 04 03:01:53 PM PDT 24
Peak memory 242392 kb
Host smart-46bf5fcd-94d5-4880-844a-5ba939346e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140349758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.3140349758
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.1751967292
Short name T735
Test name
Test status
Simulation time 6563036690 ps
CPU time 14.81 seconds
Started Jun 04 03:01:50 PM PDT 24
Finished Jun 04 03:02:06 PM PDT 24
Peak memory 242688 kb
Host smart-6ef7ae4f-46e5-4be9-9bbd-872776eacbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751967292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.1751967292
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.271385682
Short name T609
Test name
Test status
Simulation time 3058419199 ps
CPU time 7.23 seconds
Started Jun 04 03:01:49 PM PDT 24
Finished Jun 04 03:01:57 PM PDT 24
Peak memory 242628 kb
Host smart-2d413957-3ede-4e4f-a1db-b90021c64422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271385682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.271385682
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.3079692213
Short name T508
Test name
Test status
Simulation time 1011101740 ps
CPU time 19.44 seconds
Started Jun 04 03:01:48 PM PDT 24
Finished Jun 04 03:02:09 PM PDT 24
Peak memory 242584 kb
Host smart-867221b5-22fd-48ab-8b6f-3984bea98f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079692213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.3079692213
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.2048573543
Short name T529
Test name
Test status
Simulation time 973950198 ps
CPU time 17.02 seconds
Started Jun 04 03:01:47 PM PDT 24
Finished Jun 04 03:02:06 PM PDT 24
Peak memory 248864 kb
Host smart-d2296e30-5467-496e-aa33-bf5259dfa14f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2048573543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.2048573543
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.236887490
Short name T770
Test name
Test status
Simulation time 551347909 ps
CPU time 4.79 seconds
Started Jun 04 03:01:47 PM PDT 24
Finished Jun 04 03:01:53 PM PDT 24
Peak memory 242636 kb
Host smart-3f9f459f-ca2d-4fab-98b0-5e531cbc6427
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=236887490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.236887490
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.3148132163
Short name T712
Test name
Test status
Simulation time 184037183 ps
CPU time 4.96 seconds
Started Jun 04 03:01:48 PM PDT 24
Finished Jun 04 03:01:55 PM PDT 24
Peak memory 242420 kb
Host smart-f54f2cd8-77e6-4916-b014-4078303eb79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148132163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.3148132163
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.3720907672
Short name T920
Test name
Test status
Simulation time 49667366170 ps
CPU time 233.96 seconds
Started Jun 04 03:01:51 PM PDT 24
Finished Jun 04 03:05:46 PM PDT 24
Peak memory 262048 kb
Host smart-5899ac47-cbb9-4128-a2c3-573e0cf7496f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720907672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.3720907672
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.267433050
Short name T337
Test name
Test status
Simulation time 490975856082 ps
CPU time 1561.43 seconds
Started Jun 04 03:01:49 PM PDT 24
Finished Jun 04 03:27:52 PM PDT 24
Peak memory 281712 kb
Host smart-f8516afe-735d-48e6-ae43-fe4ccf041bed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267433050 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.267433050
Directory /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.2058243484
Short name T413
Test name
Test status
Simulation time 449712533 ps
CPU time 9.39 seconds
Started Jun 04 03:01:48 PM PDT 24
Finished Jun 04 03:01:58 PM PDT 24
Peak memory 248900 kb
Host smart-d5e7fb80-f3f5-4177-b23d-66de2d63b53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058243484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.2058243484
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.2051433907
Short name T1093
Test name
Test status
Simulation time 3013616730 ps
CPU time 8.96 seconds
Started Jun 04 03:01:48 PM PDT 24
Finished Jun 04 03:01:58 PM PDT 24
Peak memory 242448 kb
Host smart-567f7491-f94e-4a1d-9462-dd7a44d12028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051433907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.2051433907
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.697011651
Short name T352
Test name
Test status
Simulation time 1684507425 ps
CPU time 33.79 seconds
Started Jun 04 03:01:50 PM PDT 24
Finished Jun 04 03:02:24 PM PDT 24
Peak memory 245888 kb
Host smart-001b6ef6-6bb3-4f53-b8dc-435b95561181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697011651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.697011651
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.3604623197
Short name T918
Test name
Test status
Simulation time 672524179 ps
CPU time 4.97 seconds
Started Jun 04 03:01:47 PM PDT 24
Finished Jun 04 03:01:53 PM PDT 24
Peak memory 242148 kb
Host smart-7dee7510-f159-40cc-9b2b-f1c4dfe1b84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604623197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.3604623197
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.3044378379
Short name T136
Test name
Test status
Simulation time 1645322253 ps
CPU time 33.9 seconds
Started Jun 04 03:01:51 PM PDT 24
Finished Jun 04 03:02:25 PM PDT 24
Peak memory 242776 kb
Host smart-825f8329-c23d-4a96-b729-9dd8a3a9aeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044378379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.3044378379
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.2646838580
Short name T177
Test name
Test status
Simulation time 892839601 ps
CPU time 36.55 seconds
Started Jun 04 03:01:52 PM PDT 24
Finished Jun 04 03:02:29 PM PDT 24
Peak memory 242228 kb
Host smart-d24e039e-f433-436e-a780-f794cd790f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646838580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.2646838580
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.2678077045
Short name T868
Test name
Test status
Simulation time 239090066 ps
CPU time 4.84 seconds
Started Jun 04 03:01:48 PM PDT 24
Finished Jun 04 03:01:54 PM PDT 24
Peak memory 242388 kb
Host smart-be9ba9a6-bec1-4a09-9370-608100dd1fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678077045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.2678077045
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.2112956674
Short name T472
Test name
Test status
Simulation time 315011959 ps
CPU time 5.85 seconds
Started Jun 04 03:01:59 PM PDT 24
Finished Jun 04 03:02:06 PM PDT 24
Peak memory 242316 kb
Host smart-0bdbb5f4-1889-47b6-a21e-0dd565a616f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112956674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.2112956674
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.1909178708
Short name T559
Test name
Test status
Simulation time 85680959 ps
CPU time 3.1 seconds
Started Jun 04 03:01:47 PM PDT 24
Finished Jun 04 03:01:51 PM PDT 24
Peak memory 242532 kb
Host smart-0536b77e-73a3-4925-94f7-bcfc0e61c627
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1909178708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.1909178708
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.1410648668
Short name T992
Test name
Test status
Simulation time 1805827859 ps
CPU time 8.73 seconds
Started Jun 04 03:01:48 PM PDT 24
Finished Jun 04 03:01:58 PM PDT 24
Peak memory 248780 kb
Host smart-0776c08c-2b26-451a-ac34-e9a504981799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410648668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.1410648668
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.4214502933
Short name T942
Test name
Test status
Simulation time 34310358553 ps
CPU time 218.95 seconds
Started Jun 04 03:01:50 PM PDT 24
Finished Jun 04 03:05:30 PM PDT 24
Peak memory 259224 kb
Host smart-369ad91a-a8a7-4744-bc8e-156f0bcfe049
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214502933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.4214502933
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.2244122727
Short name T303
Test name
Test status
Simulation time 594840014 ps
CPU time 5.64 seconds
Started Jun 04 03:01:52 PM PDT 24
Finished Jun 04 03:01:58 PM PDT 24
Peak memory 242324 kb
Host smart-87ffa580-e03d-455e-ae5f-cce7629df445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244122727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.2244122727
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.1673561296
Short name T1204
Test name
Test status
Simulation time 58854181 ps
CPU time 1.81 seconds
Started Jun 04 03:01:59 PM PDT 24
Finished Jun 04 03:02:02 PM PDT 24
Peak memory 241056 kb
Host smart-e4e2d57c-c474-4cd4-bb50-96b5ec2be3e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673561296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.1673561296
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.2639999629
Short name T80
Test name
Test status
Simulation time 2032143898 ps
CPU time 24.6 seconds
Started Jun 04 03:02:00 PM PDT 24
Finished Jun 04 03:02:25 PM PDT 24
Peak memory 248900 kb
Host smart-36eb09f1-d1fe-4c6d-9ef3-84695812c3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639999629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.2639999629
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.738765331
Short name T1200
Test name
Test status
Simulation time 1946596084 ps
CPU time 43.6 seconds
Started Jun 04 03:02:02 PM PDT 24
Finished Jun 04 03:02:47 PM PDT 24
Peak memory 246756 kb
Host smart-185e5f89-bb3d-4dd0-ad71-6f1f5cea4e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738765331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.738765331
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.1665853471
Short name T577
Test name
Test status
Simulation time 3479777993 ps
CPU time 33.51 seconds
Started Jun 04 03:02:02 PM PDT 24
Finished Jun 04 03:02:36 PM PDT 24
Peak memory 242552 kb
Host smart-f8b61639-2f9f-40b1-93b5-35e6ca74a042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665853471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.1665853471
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.1928613546
Short name T75
Test name
Test status
Simulation time 658578424 ps
CPU time 5 seconds
Started Jun 04 03:01:48 PM PDT 24
Finished Jun 04 03:01:54 PM PDT 24
Peak memory 242684 kb
Host smart-201f6538-a5c2-4fd4-81e4-874aa81da491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928613546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.1928613546
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.2828369784
Short name T169
Test name
Test status
Simulation time 5957636335 ps
CPU time 42.32 seconds
Started Jun 04 03:02:01 PM PDT 24
Finished Jun 04 03:02:45 PM PDT 24
Peak memory 247844 kb
Host smart-8ef13bf2-537a-4f38-b619-65ec1491efea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828369784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.2828369784
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.1511352666
Short name T491
Test name
Test status
Simulation time 306992640 ps
CPU time 9.86 seconds
Started Jun 04 03:01:58 PM PDT 24
Finished Jun 04 03:02:09 PM PDT 24
Peak memory 242252 kb
Host smart-90723b59-234d-40c4-8cac-40f51d5408be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511352666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1511352666
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.4257501687
Short name T857
Test name
Test status
Simulation time 348362621 ps
CPU time 7.31 seconds
Started Jun 04 03:01:58 PM PDT 24
Finished Jun 04 03:02:06 PM PDT 24
Peak memory 242340 kb
Host smart-5ff78c54-a97c-4b6f-bfe1-fbf8a104e041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257501687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.4257501687
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.2837013847
Short name T914
Test name
Test status
Simulation time 909092255 ps
CPU time 21.58 seconds
Started Jun 04 03:01:49 PM PDT 24
Finished Jun 04 03:02:12 PM PDT 24
Peak memory 248844 kb
Host smart-e4ef2ab3-a9ea-44c4-8798-d22865cd6f73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2837013847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.2837013847
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.358716298
Short name T1134
Test name
Test status
Simulation time 551868534 ps
CPU time 5.81 seconds
Started Jun 04 03:01:56 PM PDT 24
Finished Jun 04 03:02:02 PM PDT 24
Peak memory 242568 kb
Host smart-8b2d069b-0e82-4d6d-b9da-8be9c722392e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=358716298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.358716298
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.3486317279
Short name T253
Test name
Test status
Simulation time 2295519032 ps
CPU time 7.5 seconds
Started Jun 04 03:01:50 PM PDT 24
Finished Jun 04 03:01:58 PM PDT 24
Peak memory 242516 kb
Host smart-736dfb25-f226-4378-a88a-b7c2ee48a921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486317279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.3486317279
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.3127897984
Short name T238
Test name
Test status
Simulation time 2024603817 ps
CPU time 76.64 seconds
Started Jun 04 03:01:58 PM PDT 24
Finished Jun 04 03:03:16 PM PDT 24
Peak memory 245260 kb
Host smart-74a3e1fb-9e08-43d7-9546-4d9ba6a32789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127897984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all
.3127897984
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.3822128077
Short name T1028
Test name
Test status
Simulation time 43844952853 ps
CPU time 1257.53 seconds
Started Jun 04 03:02:01 PM PDT 24
Finished Jun 04 03:22:59 PM PDT 24
Peak memory 314704 kb
Host smart-f6eb7796-ea32-4c5a-8982-7085456bcc69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822128077 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.3822128077
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.1701232924
Short name T1077
Test name
Test status
Simulation time 2938400040 ps
CPU time 35.13 seconds
Started Jun 04 03:02:03 PM PDT 24
Finished Jun 04 03:02:39 PM PDT 24
Peak memory 242540 kb
Host smart-d45fff3b-a425-45c5-8ee4-8ed67baaa50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701232924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.1701232924
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.551562694
Short name T889
Test name
Test status
Simulation time 75937542 ps
CPU time 2.05 seconds
Started Jun 04 03:02:02 PM PDT 24
Finished Jun 04 03:02:05 PM PDT 24
Peak memory 240792 kb
Host smart-7de64d37-0120-44ef-bba8-22234b9448c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551562694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.551562694
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.1127067493
Short name T1178
Test name
Test status
Simulation time 940659280 ps
CPU time 5.15 seconds
Started Jun 04 03:01:59 PM PDT 24
Finished Jun 04 03:02:05 PM PDT 24
Peak memory 242408 kb
Host smart-33ca8399-e793-4296-a4c1-6c311d2d3ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127067493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.1127067493
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.91868334
Short name T463
Test name
Test status
Simulation time 715851336 ps
CPU time 23.07 seconds
Started Jun 04 03:02:00 PM PDT 24
Finished Jun 04 03:02:24 PM PDT 24
Peak memory 242604 kb
Host smart-7d3c6c48-dbb4-4945-98b1-0ebe02f53dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91868334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.91868334
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.3081534923
Short name T589
Test name
Test status
Simulation time 171060728 ps
CPU time 5.28 seconds
Started Jun 04 03:01:58 PM PDT 24
Finished Jun 04 03:02:05 PM PDT 24
Peak memory 248828 kb
Host smart-b635bab2-e339-4f6f-b243-1370395007bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081534923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.3081534923
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.2844260082
Short name T561
Test name
Test status
Simulation time 404950954 ps
CPU time 3.62 seconds
Started Jun 04 03:02:02 PM PDT 24
Finished Jun 04 03:02:07 PM PDT 24
Peak memory 242416 kb
Host smart-a0dd3848-0569-429a-b827-9a352dc631c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844260082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.2844260082
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.4229949895
Short name T827
Test name
Test status
Simulation time 803401848 ps
CPU time 12.82 seconds
Started Jun 04 03:02:01 PM PDT 24
Finished Jun 04 03:02:14 PM PDT 24
Peak memory 242772 kb
Host smart-b3845af6-e458-47b5-b4fa-947527d28dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229949895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.4229949895
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.2184385359
Short name T511
Test name
Test status
Simulation time 1103243813 ps
CPU time 17.61 seconds
Started Jun 04 03:01:57 PM PDT 24
Finished Jun 04 03:02:16 PM PDT 24
Peak memory 242364 kb
Host smart-173ac29c-5c1f-4139-86ec-df89f6f072a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184385359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.2184385359
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.1643552167
Short name T690
Test name
Test status
Simulation time 483521206 ps
CPU time 6.86 seconds
Started Jun 04 03:02:00 PM PDT 24
Finished Jun 04 03:02:08 PM PDT 24
Peak memory 242408 kb
Host smart-edd64ebb-f6de-418a-8028-0bed6370efb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643552167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.1643552167
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.2265867093
Short name T1042
Test name
Test status
Simulation time 6890447289 ps
CPU time 21.64 seconds
Started Jun 04 03:01:58 PM PDT 24
Finished Jun 04 03:02:21 PM PDT 24
Peak memory 242316 kb
Host smart-98a8c0e6-62a9-49eb-9583-21d874c74f20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2265867093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.2265867093
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.4062112943
Short name T1062
Test name
Test status
Simulation time 2009975725 ps
CPU time 6.15 seconds
Started Jun 04 03:02:00 PM PDT 24
Finished Jun 04 03:02:07 PM PDT 24
Peak memory 242180 kb
Host smart-b228263c-5d08-473a-b3a3-4ab3b254ff96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4062112943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.4062112943
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.1091143206
Short name T729
Test name
Test status
Simulation time 280917571 ps
CPU time 10.13 seconds
Started Jun 04 03:02:02 PM PDT 24
Finished Jun 04 03:02:13 PM PDT 24
Peak memory 242288 kb
Host smart-05e2de01-6a27-4a85-9953-8cc85ed43311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091143206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.1091143206
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.4127831485
Short name T237
Test name
Test status
Simulation time 19744650839 ps
CPU time 113.04 seconds
Started Jun 04 03:02:02 PM PDT 24
Finished Jun 04 03:03:56 PM PDT 24
Peak memory 249008 kb
Host smart-cc31aab4-19d9-41b7-84f7-a8cc8b297f73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127831485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all
.4127831485
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.1767218942
Short name T187
Test name
Test status
Simulation time 44622776342 ps
CPU time 370.46 seconds
Started Jun 04 03:01:58 PM PDT 24
Finished Jun 04 03:08:09 PM PDT 24
Peak memory 292648 kb
Host smart-06ec657e-d4d8-4df4-b357-07e7539cc9a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767218942 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.1767218942
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.3590950614
Short name T421
Test name
Test status
Simulation time 2977324289 ps
CPU time 35.97 seconds
Started Jun 04 03:01:57 PM PDT 24
Finished Jun 04 03:02:34 PM PDT 24
Peak memory 242932 kb
Host smart-0f8d8558-7f0e-4a0f-be01-2ff142e77973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590950614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.3590950614
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.1971924353
Short name T396
Test name
Test status
Simulation time 114126948 ps
CPU time 1.89 seconds
Started Jun 04 03:02:11 PM PDT 24
Finished Jun 04 03:02:14 PM PDT 24
Peak memory 241036 kb
Host smart-066ce005-17d9-4fb5-8ff0-4111d1f15809
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971924353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.1971924353
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.4082889022
Short name T995
Test name
Test status
Simulation time 1305065104 ps
CPU time 13.59 seconds
Started Jun 04 03:02:03 PM PDT 24
Finished Jun 04 03:02:17 PM PDT 24
Peak memory 242444 kb
Host smart-6acb0cd9-a350-4742-8b7f-a63fb5a99772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082889022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.4082889022
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.763975893
Short name T1087
Test name
Test status
Simulation time 2563859097 ps
CPU time 38.94 seconds
Started Jun 04 03:02:01 PM PDT 24
Finished Jun 04 03:02:41 PM PDT 24
Peak memory 251492 kb
Host smart-7358a58a-98f7-452e-856a-9cd785ee34c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763975893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.763975893
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.1782369691
Short name T117
Test name
Test status
Simulation time 976540623 ps
CPU time 22.18 seconds
Started Jun 04 03:01:58 PM PDT 24
Finished Jun 04 03:02:21 PM PDT 24
Peak memory 248852 kb
Host smart-4feb6531-a3ba-46e2-809b-5a420c8eee94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782369691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.1782369691
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.2279597158
Short name T611
Test name
Test status
Simulation time 106314954 ps
CPU time 4.1 seconds
Started Jun 04 03:01:59 PM PDT 24
Finished Jun 04 03:02:04 PM PDT 24
Peak memory 242444 kb
Host smart-69b550eb-423d-4edf-939e-6e5077c11421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279597158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.2279597158
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.479113051
Short name T903
Test name
Test status
Simulation time 830961190 ps
CPU time 23.83 seconds
Started Jun 04 03:02:00 PM PDT 24
Finished Jun 04 03:02:25 PM PDT 24
Peak memory 248988 kb
Host smart-b79f46dd-58ea-41f4-ac41-82e04f38d875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479113051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.479113051
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.1060370907
Short name T1047
Test name
Test status
Simulation time 1947617757 ps
CPU time 36.9 seconds
Started Jun 04 03:02:01 PM PDT 24
Finished Jun 04 03:02:39 PM PDT 24
Peak memory 248876 kb
Host smart-37415042-dba5-42ee-aaf9-906b3c73408e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060370907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.1060370907
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.2043024493
Short name T236
Test name
Test status
Simulation time 2913552684 ps
CPU time 13.16 seconds
Started Jun 04 03:02:00 PM PDT 24
Finished Jun 04 03:02:14 PM PDT 24
Peak memory 242184 kb
Host smart-79262820-3ab3-4655-9b81-002b419440a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043024493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.2043024493
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.488328888
Short name T531
Test name
Test status
Simulation time 689249528 ps
CPU time 20.77 seconds
Started Jun 04 03:01:58 PM PDT 24
Finished Jun 04 03:02:20 PM PDT 24
Peak memory 248888 kb
Host smart-662479a5-edb0-41fe-88ab-c747dfe32422
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=488328888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.488328888
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.3274955997
Short name T763
Test name
Test status
Simulation time 4174369678 ps
CPU time 13.11 seconds
Started Jun 04 03:02:08 PM PDT 24
Finished Jun 04 03:02:22 PM PDT 24
Peak memory 242656 kb
Host smart-b41ab0e5-27fe-471d-9257-d54cada2b37a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3274955997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.3274955997
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.2929755371
Short name T826
Test name
Test status
Simulation time 8437906830 ps
CPU time 18.01 seconds
Started Jun 04 03:02:02 PM PDT 24
Finished Jun 04 03:02:21 PM PDT 24
Peak memory 242572 kb
Host smart-7cbe5442-3015-4b99-9b10-e719079392ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929755371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.2929755371
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.3399087978
Short name T524
Test name
Test status
Simulation time 23664557289 ps
CPU time 196.23 seconds
Started Jun 04 03:02:09 PM PDT 24
Finished Jun 04 03:05:26 PM PDT 24
Peak memory 257612 kb
Host smart-854b880a-dc2e-4bf8-9539-32e2014cc0fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399087978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.3399087978
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.1924281669
Short name T299
Test name
Test status
Simulation time 203852305578 ps
CPU time 2716.14 seconds
Started Jun 04 03:02:11 PM PDT 24
Finished Jun 04 03:47:28 PM PDT 24
Peak memory 293344 kb
Host smart-86394553-b207-4318-b1ee-ee6df14263d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924281669 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.1924281669
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.4048388040
Short name T927
Test name
Test status
Simulation time 2314086912 ps
CPU time 16.21 seconds
Started Jun 04 03:02:13 PM PDT 24
Finished Jun 04 03:02:30 PM PDT 24
Peak memory 242208 kb
Host smart-91a7d364-ac07-4b77-a64e-2f3ca80b123e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048388040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.4048388040
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.702729740
Short name T458
Test name
Test status
Simulation time 769057386 ps
CPU time 2.05 seconds
Started Jun 04 03:02:07 PM PDT 24
Finished Jun 04 03:02:10 PM PDT 24
Peak memory 240816 kb
Host smart-0459ce1c-056c-4bad-b0ca-e2fabad0a11a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702729740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.702729740
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.3243537914
Short name T357
Test name
Test status
Simulation time 2007130227 ps
CPU time 21.09 seconds
Started Jun 04 03:02:13 PM PDT 24
Finished Jun 04 03:02:35 PM PDT 24
Peak memory 242512 kb
Host smart-c46602df-acc4-4921-989f-3d26cd596944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243537914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.3243537914
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.1477069229
Short name T1160
Test name
Test status
Simulation time 6600020872 ps
CPU time 10.53 seconds
Started Jun 04 03:02:07 PM PDT 24
Finished Jun 04 03:02:19 PM PDT 24
Peak memory 242252 kb
Host smart-8b076eb7-e8f3-4c79-8a6d-6d9a60e12950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477069229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.1477069229
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.2626776954
Short name T944
Test name
Test status
Simulation time 735498884 ps
CPU time 5.55 seconds
Started Jun 04 03:02:07 PM PDT 24
Finished Jun 04 03:02:13 PM PDT 24
Peak memory 242560 kb
Host smart-ed6cf3d9-705f-4459-952f-e4546bc57d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626776954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.2626776954
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.4257040250
Short name T198
Test name
Test status
Simulation time 424105347 ps
CPU time 4.55 seconds
Started Jun 04 03:02:09 PM PDT 24
Finished Jun 04 03:02:14 PM PDT 24
Peak memory 242424 kb
Host smart-71280c22-e428-493b-b54d-194cb521eaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257040250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.4257040250
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.956785202
Short name T353
Test name
Test status
Simulation time 2713329783 ps
CPU time 29.06 seconds
Started Jun 04 03:02:09 PM PDT 24
Finished Jun 04 03:02:39 PM PDT 24
Peak memory 249052 kb
Host smart-0ab88292-c212-4730-befc-763c77138c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956785202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.956785202
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.3461317468
Short name T486
Test name
Test status
Simulation time 1949844480 ps
CPU time 21.59 seconds
Started Jun 04 03:02:08 PM PDT 24
Finished Jun 04 03:02:30 PM PDT 24
Peak memory 242252 kb
Host smart-f59463a5-9492-458d-ab14-9128d5033649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461317468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.3461317468
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.250408116
Short name T832
Test name
Test status
Simulation time 532086512 ps
CPU time 7.32 seconds
Started Jun 04 03:02:11 PM PDT 24
Finished Jun 04 03:02:18 PM PDT 24
Peak memory 242440 kb
Host smart-4b78e227-2645-44a0-b96a-62b61cc35df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250408116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.250408116
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.2100622258
Short name T196
Test name
Test status
Simulation time 594270917 ps
CPU time 18.56 seconds
Started Jun 04 03:02:13 PM PDT 24
Finished Jun 04 03:02:32 PM PDT 24
Peak memory 248764 kb
Host smart-137ffadb-cd6c-4883-b7fd-668e2366c247
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2100622258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.2100622258
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.2237330366
Short name T993
Test name
Test status
Simulation time 1707624725 ps
CPU time 5.03 seconds
Started Jun 04 03:02:06 PM PDT 24
Finished Jun 04 03:02:12 PM PDT 24
Peak memory 242232 kb
Host smart-d037e938-0206-4d3b-bc7f-e76ebfa041ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2237330366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.2237330366
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.1113902013
Short name T247
Test name
Test status
Simulation time 596429820 ps
CPU time 11.51 seconds
Started Jun 04 03:02:08 PM PDT 24
Finished Jun 04 03:02:20 PM PDT 24
Peak memory 248784 kb
Host smart-f1d724cb-c849-434d-9874-5b7987701631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113902013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.1113902013
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.2439555355
Short name T461
Test name
Test status
Simulation time 8210225360 ps
CPU time 62.74 seconds
Started Jun 04 03:02:10 PM PDT 24
Finished Jun 04 03:03:14 PM PDT 24
Peak memory 248956 kb
Host smart-203915ae-9cc5-45c6-ae25-cf4abe23ccf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439555355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.2439555355
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.992322300
Short name T6
Test name
Test status
Simulation time 13548528120 ps
CPU time 292.53 seconds
Started Jun 04 03:02:08 PM PDT 24
Finished Jun 04 03:07:01 PM PDT 24
Peak memory 265324 kb
Host smart-2c6b9de6-d49d-4069-8545-c999141ce857
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992322300 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.992322300
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.930342412
Short name T850
Test name
Test status
Simulation time 3779255462 ps
CPU time 6.31 seconds
Started Jun 04 03:02:11 PM PDT 24
Finished Jun 04 03:02:17 PM PDT 24
Peak memory 242364 kb
Host smart-a486a6bf-b19a-4533-ba1e-4c5cfc2bc816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930342412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.930342412
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.3699963639
Short name T1045
Test name
Test status
Simulation time 38825579 ps
CPU time 1.55 seconds
Started Jun 04 03:02:10 PM PDT 24
Finished Jun 04 03:02:12 PM PDT 24
Peak memory 240768 kb
Host smart-c74018d5-ff1a-4ce1-8bc6-54ae0c2319c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699963639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.3699963639
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.1755801372
Short name T807
Test name
Test status
Simulation time 1486718129 ps
CPU time 22.91 seconds
Started Jun 04 03:02:13 PM PDT 24
Finished Jun 04 03:02:36 PM PDT 24
Peak memory 242880 kb
Host smart-df25ff14-6cf7-406c-8915-e1cde073c036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755801372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.1755801372
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.594340533
Short name T419
Test name
Test status
Simulation time 6479804869 ps
CPU time 43.65 seconds
Started Jun 04 03:02:10 PM PDT 24
Finished Jun 04 03:02:55 PM PDT 24
Peak memory 251200 kb
Host smart-691daee6-e85e-4bab-992d-44281fa94632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594340533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.594340533
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.4244840176
Short name T1049
Test name
Test status
Simulation time 7823731071 ps
CPU time 15.37 seconds
Started Jun 04 03:02:11 PM PDT 24
Finished Jun 04 03:02:27 PM PDT 24
Peak memory 243380 kb
Host smart-86dac5ce-d108-4355-8333-1deb4056fef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244840176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.4244840176
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.2343090735
Short name T507
Test name
Test status
Simulation time 258173122 ps
CPU time 4.26 seconds
Started Jun 04 03:02:12 PM PDT 24
Finished Jun 04 03:02:16 PM PDT 24
Peak memory 242428 kb
Host smart-6ab98297-e30c-44d0-afce-f41d9496e179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343090735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.2343090735
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.3463912593
Short name T794
Test name
Test status
Simulation time 25571169661 ps
CPU time 69.19 seconds
Started Jun 04 03:02:12 PM PDT 24
Finished Jun 04 03:03:22 PM PDT 24
Peak memory 248936 kb
Host smart-f973a71c-7e13-4c93-ba4b-661448986bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463912593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.3463912593
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.1435582511
Short name T1090
Test name
Test status
Simulation time 2284253612 ps
CPU time 22.89 seconds
Started Jun 04 03:02:07 PM PDT 24
Finished Jun 04 03:02:30 PM PDT 24
Peak memory 248948 kb
Host smart-1ef0b0b2-2d6f-4be5-b150-f3baacd4733e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435582511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.1435582511
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.1999459577
Short name T833
Test name
Test status
Simulation time 695890687 ps
CPU time 9.83 seconds
Started Jun 04 03:02:08 PM PDT 24
Finished Jun 04 03:02:18 PM PDT 24
Peak memory 242400 kb
Host smart-ca47d85c-d03c-4309-902d-b06a386454cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999459577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.1999459577
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.2893351857
Short name T416
Test name
Test status
Simulation time 678910643 ps
CPU time 20.61 seconds
Started Jun 04 03:02:14 PM PDT 24
Finished Jun 04 03:02:35 PM PDT 24
Peak memory 242264 kb
Host smart-0a790c4c-3042-4846-be14-f997d06a8970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2893351857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.2893351857
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.4055073333
Short name T387
Test name
Test status
Simulation time 2776333362 ps
CPU time 8.31 seconds
Started Jun 04 03:02:08 PM PDT 24
Finished Jun 04 03:02:17 PM PDT 24
Peak memory 242500 kb
Host smart-25816895-389a-4edc-b740-09010fab647c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4055073333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.4055073333
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.3633664286
Short name T941
Test name
Test status
Simulation time 608204291 ps
CPU time 9.09 seconds
Started Jun 04 03:02:12 PM PDT 24
Finished Jun 04 03:02:21 PM PDT 24
Peak memory 242280 kb
Host smart-6ffccf01-c4e5-4460-b8f7-92904a93bb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633664286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.3633664286
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.2833529399
Short name T1164
Test name
Test status
Simulation time 35080082615 ps
CPU time 190.78 seconds
Started Jun 04 03:02:13 PM PDT 24
Finished Jun 04 03:05:25 PM PDT 24
Peak memory 259620 kb
Host smart-2521814b-1c6f-43e5-929f-c3233e8c9d70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833529399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.2833529399
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.4147264617
Short name T476
Test name
Test status
Simulation time 157101096 ps
CPU time 2.55 seconds
Started Jun 04 02:59:38 PM PDT 24
Finished Jun 04 02:59:41 PM PDT 24
Peak memory 241104 kb
Host smart-61dd0fcf-5890-4908-9bdc-dfa256cca8e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147264617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.4147264617
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.3517380950
Short name T1009
Test name
Test status
Simulation time 2436819231 ps
CPU time 15.29 seconds
Started Jun 04 02:59:28 PM PDT 24
Finished Jun 04 02:59:44 PM PDT 24
Peak memory 242400 kb
Host smart-f9dbbc2f-3811-4a29-bacd-23d6ac9adb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517380950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.3517380950
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.1917489104
Short name T60
Test name
Test status
Simulation time 8787707571 ps
CPU time 32.59 seconds
Started Jun 04 02:59:29 PM PDT 24
Finished Jun 04 03:00:02 PM PDT 24
Peak memory 248952 kb
Host smart-14c3924a-8cfa-4ad9-bb8b-4bbbf1bf2551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917489104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.1917489104
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.2889652122
Short name T1051
Test name
Test status
Simulation time 1368126369 ps
CPU time 20.03 seconds
Started Jun 04 02:59:30 PM PDT 24
Finished Jun 04 02:59:50 PM PDT 24
Peak memory 242332 kb
Host smart-26ad2163-857c-4861-8405-01fab8766d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889652122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.2889652122
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.1793510492
Short name T921
Test name
Test status
Simulation time 591688420 ps
CPU time 10.33 seconds
Started Jun 04 02:59:28 PM PDT 24
Finished Jun 04 02:59:39 PM PDT 24
Peak memory 242524 kb
Host smart-f3549e80-504d-44a7-b308-eb11705f6697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793510492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.1793510492
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.2837603325
Short name T873
Test name
Test status
Simulation time 2333338019 ps
CPU time 5.17 seconds
Started Jun 04 02:59:32 PM PDT 24
Finished Jun 04 02:59:37 PM PDT 24
Peak memory 242520 kb
Host smart-6f850e4d-b1ea-42bc-bfb0-0cff66438a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837603325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.2837603325
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.2087686921
Short name T622
Test name
Test status
Simulation time 2959010727 ps
CPU time 22.97 seconds
Started Jun 04 02:59:28 PM PDT 24
Finished Jun 04 02:59:51 PM PDT 24
Peak memory 244620 kb
Host smart-c3c25f90-d764-4125-a38b-bc7a92d8e92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087686921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.2087686921
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.3216349068
Short name T528
Test name
Test status
Simulation time 501377273 ps
CPU time 10.47 seconds
Started Jun 04 02:59:31 PM PDT 24
Finished Jun 04 02:59:42 PM PDT 24
Peak memory 242208 kb
Host smart-b0520619-0f3c-4d8c-b340-f02feab989a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216349068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.3216349068
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.286337607
Short name T262
Test name
Test status
Simulation time 173995343 ps
CPU time 4.19 seconds
Started Jun 04 02:59:28 PM PDT 24
Finished Jun 04 02:59:33 PM PDT 24
Peak memory 242384 kb
Host smart-5fbceba1-e2f1-4653-934e-80fdb01de79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286337607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.286337607
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.2082372376
Short name T145
Test name
Test status
Simulation time 765826583 ps
CPU time 16.31 seconds
Started Jun 04 02:59:29 PM PDT 24
Finished Jun 04 02:59:46 PM PDT 24
Peak memory 242252 kb
Host smart-a43d414a-3652-4427-b8d5-9b2a0b24f29b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2082372376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.2082372376
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.3697208833
Short name T270
Test name
Test status
Simulation time 846695291 ps
CPU time 11.5 seconds
Started Jun 04 02:59:32 PM PDT 24
Finished Jun 04 02:59:44 PM PDT 24
Peak memory 242368 kb
Host smart-a8851aa2-2cb8-460d-896a-0140741c8de6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3697208833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.3697208833
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.414821312
Short name T22
Test name
Test status
Simulation time 12658602785 ps
CPU time 186.36 seconds
Started Jun 04 02:59:28 PM PDT 24
Finished Jun 04 03:02:35 PM PDT 24
Peak memory 268536 kb
Host smart-504fce3f-068d-4289-9f71-1ac6e3325286
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414821312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.414821312
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.4078785518
Short name T1197
Test name
Test status
Simulation time 1075662637 ps
CPU time 9.8 seconds
Started Jun 04 02:59:30 PM PDT 24
Finished Jun 04 02:59:40 PM PDT 24
Peak memory 248824 kb
Host smart-6b7e465d-00de-4d70-a3f7-f22c8df43fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078785518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.4078785518
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.2223211029
Short name T216
Test name
Test status
Simulation time 7377554316 ps
CPU time 120.47 seconds
Started Jun 04 02:59:29 PM PDT 24
Finished Jun 04 03:01:30 PM PDT 24
Peak memory 249968 kb
Host smart-839576a0-617b-4dd0-942c-3fab656830c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223211029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.
2223211029
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.1561048388
Short name T265
Test name
Test status
Simulation time 309043745783 ps
CPU time 2389.58 seconds
Started Jun 04 02:59:28 PM PDT 24
Finished Jun 04 03:39:19 PM PDT 24
Peak memory 601420 kb
Host smart-abed8418-f79a-4835-aedd-ddef48a79031
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561048388 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.1561048388
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.1118882164
Short name T913
Test name
Test status
Simulation time 1108386204 ps
CPU time 23.82 seconds
Started Jun 04 02:59:29 PM PDT 24
Finished Jun 04 02:59:54 PM PDT 24
Peak memory 242500 kb
Host smart-dc0d76bc-9dcd-47aa-bc21-3b45bfead9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118882164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.1118882164
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.4062773861
Short name T179
Test name
Test status
Simulation time 182895679 ps
CPU time 1.85 seconds
Started Jun 04 03:02:16 PM PDT 24
Finished Jun 04 03:02:18 PM PDT 24
Peak memory 240880 kb
Host smart-ee392f98-40d8-41b3-bcba-89ba6bc4b37a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062773861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.4062773861
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.2492239106
Short name T603
Test name
Test status
Simulation time 1005093192 ps
CPU time 11.8 seconds
Started Jun 04 03:02:18 PM PDT 24
Finished Jun 04 03:02:31 PM PDT 24
Peak memory 248912 kb
Host smart-d0cffb5f-c3de-4e48-b84b-7d6c2bd1e987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492239106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.2492239106
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.3650302675
Short name T482
Test name
Test status
Simulation time 200919235 ps
CPU time 10.14 seconds
Started Jun 04 03:02:19 PM PDT 24
Finished Jun 04 03:02:30 PM PDT 24
Peak memory 242276 kb
Host smart-d1fa469c-5a0a-4f39-a5ef-91d077313525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650302675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.3650302675
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.1048628976
Short name T1086
Test name
Test status
Simulation time 32389312629 ps
CPU time 71.58 seconds
Started Jun 04 03:02:16 PM PDT 24
Finished Jun 04 03:03:28 PM PDT 24
Peak memory 243532 kb
Host smart-f4c3726a-5f74-45f1-950f-96f2c4875f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048628976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.1048628976
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.1798914896
Short name T199
Test name
Test status
Simulation time 362280437 ps
CPU time 3.37 seconds
Started Jun 04 03:02:09 PM PDT 24
Finished Jun 04 03:02:13 PM PDT 24
Peak memory 242352 kb
Host smart-62ee3045-3777-43c5-9e1b-04332962cc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798914896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.1798914896
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.2133524042
Short name T1167
Test name
Test status
Simulation time 10923310509 ps
CPU time 28.97 seconds
Started Jun 04 03:02:16 PM PDT 24
Finished Jun 04 03:02:45 PM PDT 24
Peak memory 242320 kb
Host smart-a31b7978-6a7a-4317-9fa6-29cb2c59659d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133524042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.2133524042
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.3036770165
Short name T471
Test name
Test status
Simulation time 5519018876 ps
CPU time 42.62 seconds
Started Jun 04 03:02:18 PM PDT 24
Finished Jun 04 03:03:02 PM PDT 24
Peak memory 242384 kb
Host smart-fda1b0ca-7d75-4754-8f81-1af9d9d961df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036770165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.3036770165
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.3494189993
Short name T182
Test name
Test status
Simulation time 275217407 ps
CPU time 6.95 seconds
Started Jun 04 03:02:18 PM PDT 24
Finished Jun 04 03:02:26 PM PDT 24
Peak memory 242288 kb
Host smart-e8a1be76-8e03-4d21-92e3-95cfbf13f2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494189993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.3494189993
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.3856560553
Short name T659
Test name
Test status
Simulation time 570373405 ps
CPU time 16.96 seconds
Started Jun 04 03:02:07 PM PDT 24
Finished Jun 04 03:02:25 PM PDT 24
Peak memory 242120 kb
Host smart-82e5622a-23e9-4d8a-89d5-a82a1a81b975
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856560553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.3856560553
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.3258792146
Short name T366
Test name
Test status
Simulation time 245387701 ps
CPU time 6.16 seconds
Started Jun 04 03:02:17 PM PDT 24
Finished Jun 04 03:02:24 PM PDT 24
Peak memory 248928 kb
Host smart-e50329c4-a0a0-45dc-9bbd-d99847b67d08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258792146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.3258792146
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.987881273
Short name T772
Test name
Test status
Simulation time 244426346 ps
CPU time 4.59 seconds
Started Jun 04 03:02:10 PM PDT 24
Finished Jun 04 03:02:15 PM PDT 24
Peak memory 242284 kb
Host smart-1ee6d186-4e5d-4999-8b46-a56ae2ef1578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987881273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.987881273
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.3585454617
Short name T974
Test name
Test status
Simulation time 56931887621 ps
CPU time 118.95 seconds
Started Jun 04 03:02:18 PM PDT 24
Finished Jun 04 03:04:18 PM PDT 24
Peak memory 245224 kb
Host smart-45ef7621-91de-4956-93da-ee4be8242602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585454617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all
.3585454617
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.3505575258
Short name T1095
Test name
Test status
Simulation time 84675070218 ps
CPU time 1241.67 seconds
Started Jun 04 03:02:14 PM PDT 24
Finished Jun 04 03:22:57 PM PDT 24
Peak memory 299772 kb
Host smart-c1864dcb-cbc0-466d-a595-b7b4cc63e20a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505575258 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.3505575258
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.1196756607
Short name T1021
Test name
Test status
Simulation time 4151742180 ps
CPU time 31.5 seconds
Started Jun 04 03:02:18 PM PDT 24
Finished Jun 04 03:02:51 PM PDT 24
Peak memory 242344 kb
Host smart-844e7125-be21-4e5a-aa96-41f783011ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196756607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.1196756607
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.1551339653
Short name T652
Test name
Test status
Simulation time 101944615 ps
CPU time 1.75 seconds
Started Jun 04 03:02:16 PM PDT 24
Finished Jun 04 03:02:18 PM PDT 24
Peak memory 241216 kb
Host smart-025772ed-48e4-4425-9e46-563fc0975e57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551339653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.1551339653
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.1060367114
Short name T645
Test name
Test status
Simulation time 5940577703 ps
CPU time 14.56 seconds
Started Jun 04 03:02:18 PM PDT 24
Finished Jun 04 03:02:34 PM PDT 24
Peak memory 243144 kb
Host smart-cabb0d40-de97-42da-9915-f653974c9ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060367114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.1060367114
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.3090208766
Short name T864
Test name
Test status
Simulation time 741188200 ps
CPU time 15.27 seconds
Started Jun 04 03:02:14 PM PDT 24
Finished Jun 04 03:02:30 PM PDT 24
Peak memory 248916 kb
Host smart-c2a72ec3-3a6f-4683-9163-810e4a2ffe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090208766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.3090208766
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.565796363
Short name T987
Test name
Test status
Simulation time 3519224084 ps
CPU time 23.21 seconds
Started Jun 04 03:02:15 PM PDT 24
Finished Jun 04 03:02:39 PM PDT 24
Peak memory 242392 kb
Host smart-1577156f-34fa-4256-8ce8-9532f224d604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565796363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.565796363
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.4155726688
Short name T1055
Test name
Test status
Simulation time 162554097 ps
CPU time 4.06 seconds
Started Jun 04 03:02:15 PM PDT 24
Finished Jun 04 03:02:20 PM PDT 24
Peak memory 242652 kb
Host smart-6b680cb1-8efd-4ff4-9d06-42b18620d3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155726688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.4155726688
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.3894312614
Short name T439
Test name
Test status
Simulation time 313949822 ps
CPU time 6.98 seconds
Started Jun 04 03:02:18 PM PDT 24
Finished Jun 04 03:02:26 PM PDT 24
Peak memory 242268 kb
Host smart-bf7c4991-5423-4916-806e-0855e574772f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894312614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.3894312614
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.1943754121
Short name T727
Test name
Test status
Simulation time 637701761 ps
CPU time 5.21 seconds
Started Jun 04 03:02:17 PM PDT 24
Finished Jun 04 03:02:23 PM PDT 24
Peak memory 242164 kb
Host smart-48525751-d5e6-4f22-a769-3c0837c28bdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1943754121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.1943754121
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.1122529982
Short name T1027
Test name
Test status
Simulation time 877435692 ps
CPU time 7.69 seconds
Started Jun 04 03:02:19 PM PDT 24
Finished Jun 04 03:02:28 PM PDT 24
Peak memory 248944 kb
Host smart-ad5cf70e-cecd-4a78-a0a0-4bfad342c83d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1122529982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.1122529982
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.2162504641
Short name T812
Test name
Test status
Simulation time 486359376 ps
CPU time 3.77 seconds
Started Jun 04 03:02:17 PM PDT 24
Finished Jun 04 03:02:21 PM PDT 24
Peak memory 242192 kb
Host smart-8c22fa92-5de3-4db9-b6a0-99eca0dd7d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162504641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.2162504641
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.1981025457
Short name T295
Test name
Test status
Simulation time 120935588858 ps
CPU time 1843.18 seconds
Started Jun 04 03:02:19 PM PDT 24
Finished Jun 04 03:33:04 PM PDT 24
Peak memory 263716 kb
Host smart-ddd0518d-a143-49eb-b2b4-836db40c9fd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981025457 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.1981025457
Directory /workspace/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.2201836963
Short name T293
Test name
Test status
Simulation time 3299256153 ps
CPU time 47.23 seconds
Started Jun 04 03:02:17 PM PDT 24
Finished Jun 04 03:03:05 PM PDT 24
Peak memory 244084 kb
Host smart-dc5657bc-91da-45bd-8dd1-b8dc55f3acaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201836963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.2201836963
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.3051263397
Short name T934
Test name
Test status
Simulation time 120559349 ps
CPU time 2.06 seconds
Started Jun 04 03:02:24 PM PDT 24
Finished Jun 04 03:02:27 PM PDT 24
Peak memory 241016 kb
Host smart-49529491-96c3-4526-98d9-7893e9ba1c3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051263397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.3051263397
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.2861656401
Short name T1147
Test name
Test status
Simulation time 3971569817 ps
CPU time 27.48 seconds
Started Jun 04 03:02:21 PM PDT 24
Finished Jun 04 03:02:49 PM PDT 24
Peak memory 243732 kb
Host smart-4860503c-f6c2-47bb-95f5-2d51aee38df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861656401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.2861656401
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.668647608
Short name T350
Test name
Test status
Simulation time 14679110533 ps
CPU time 37.42 seconds
Started Jun 04 03:02:21 PM PDT 24
Finished Jun 04 03:03:00 PM PDT 24
Peak memory 246952 kb
Host smart-40b5e12d-c36e-4023-95f8-8bdef132e95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668647608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.668647608
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.3587928111
Short name T545
Test name
Test status
Simulation time 523281367 ps
CPU time 7.31 seconds
Started Jun 04 03:02:18 PM PDT 24
Finished Jun 04 03:02:26 PM PDT 24
Peak memory 242592 kb
Host smart-087a0040-d5ee-4e1a-b986-e3e027e60228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587928111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.3587928111
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.1668596288
Short name T496
Test name
Test status
Simulation time 2845795158 ps
CPU time 5.32 seconds
Started Jun 04 03:02:19 PM PDT 24
Finished Jun 04 03:02:25 PM PDT 24
Peak memory 242432 kb
Host smart-14dd0518-c8dd-4843-899a-182fa25694f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668596288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.1668596288
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.685380648
Short name T734
Test name
Test status
Simulation time 389774969 ps
CPU time 5.48 seconds
Started Jun 04 03:02:21 PM PDT 24
Finished Jun 04 03:02:27 PM PDT 24
Peak memory 242208 kb
Host smart-a376c012-2d8d-41c3-a9d6-cdc949ab6308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685380648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.685380648
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.805130268
Short name T743
Test name
Test status
Simulation time 2426209083 ps
CPU time 31.48 seconds
Started Jun 04 03:02:15 PM PDT 24
Finished Jun 04 03:02:47 PM PDT 24
Peak memory 242340 kb
Host smart-212700ef-afe8-48fd-a1e9-520516af3b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805130268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.805130268
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.1233710140
Short name T978
Test name
Test status
Simulation time 498004410 ps
CPU time 12.18 seconds
Started Jun 04 03:02:17 PM PDT 24
Finished Jun 04 03:02:30 PM PDT 24
Peak memory 242268 kb
Host smart-1c3a5a1b-1b4b-48e7-8e76-6a4f8cbee728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233710140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.1233710140
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.1196193661
Short name T885
Test name
Test status
Simulation time 508053885 ps
CPU time 17.22 seconds
Started Jun 04 03:02:21 PM PDT 24
Finished Jun 04 03:02:40 PM PDT 24
Peak memory 242232 kb
Host smart-b6d24780-1ade-4cb8-a404-67fae9556075
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1196193661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.1196193661
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.32827881
Short name T156
Test name
Test status
Simulation time 147700156 ps
CPU time 5.57 seconds
Started Jun 04 03:02:25 PM PDT 24
Finished Jun 04 03:02:31 PM PDT 24
Peak memory 242324 kb
Host smart-cc716426-1df8-4570-a921-87628eb60170
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=32827881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.32827881
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.366400186
Short name T819
Test name
Test status
Simulation time 1088674868 ps
CPU time 6.63 seconds
Started Jun 04 03:02:16 PM PDT 24
Finished Jun 04 03:02:23 PM PDT 24
Peak memory 242544 kb
Host smart-c560cd78-b5a1-48be-9d1c-d1dbcbb93277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366400186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.366400186
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.3901642993
Short name T1141
Test name
Test status
Simulation time 2946954779 ps
CPU time 19.93 seconds
Started Jun 04 03:02:26 PM PDT 24
Finished Jun 04 03:02:47 PM PDT 24
Peak memory 242000 kb
Host smart-5cc2b693-41f9-4843-8d82-00bb7d800dc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901642993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all
.3901642993
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.574636035
Short name T739
Test name
Test status
Simulation time 7655781906 ps
CPU time 17.7 seconds
Started Jun 04 03:02:24 PM PDT 24
Finished Jun 04 03:02:43 PM PDT 24
Peak memory 242508 kb
Host smart-89bd6fe5-f1cf-42dd-bff3-b027c1bc9986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574636035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.574636035
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.903930503
Short name T210
Test name
Test status
Simulation time 78866086 ps
CPU time 1.65 seconds
Started Jun 04 03:02:34 PM PDT 24
Finished Jun 04 03:02:37 PM PDT 24
Peak memory 241304 kb
Host smart-636ef376-e1c0-4ca4-bac8-54c1e78c0c82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903930503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.903930503
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.3692006613
Short name T77
Test name
Test status
Simulation time 1731713965 ps
CPU time 25.14 seconds
Started Jun 04 03:02:33 PM PDT 24
Finished Jun 04 03:02:59 PM PDT 24
Peak memory 244452 kb
Host smart-56dbebd0-c7e0-4fbd-9bd2-7d81bf552b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692006613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.3692006613
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.3842365288
Short name T996
Test name
Test status
Simulation time 1003123098 ps
CPU time 32.47 seconds
Started Jun 04 03:02:26 PM PDT 24
Finished Jun 04 03:02:59 PM PDT 24
Peak memory 245172 kb
Host smart-552a308d-9a9d-45b0-aacb-fdb452d952d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842365288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.3842365288
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.3897198376
Short name T837
Test name
Test status
Simulation time 3083334892 ps
CPU time 24.1 seconds
Started Jun 04 03:02:23 PM PDT 24
Finished Jun 04 03:02:48 PM PDT 24
Peak memory 242452 kb
Host smart-4919bddb-d519-4cde-af52-92e145cac9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897198376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.3897198376
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.3958779139
Short name T691
Test name
Test status
Simulation time 496103957 ps
CPU time 4.38 seconds
Started Jun 04 03:02:24 PM PDT 24
Finished Jun 04 03:02:29 PM PDT 24
Peak memory 242756 kb
Host smart-bd8d546e-b8eb-4360-a646-5e8a853ce7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958779139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.3958779139
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.691044478
Short name T749
Test name
Test status
Simulation time 1436829799 ps
CPU time 37.41 seconds
Started Jun 04 03:02:35 PM PDT 24
Finished Jun 04 03:03:13 PM PDT 24
Peak memory 244240 kb
Host smart-60566c4e-6968-4ce1-aadd-523ef883b8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691044478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.691044478
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.4230032371
Short name T457
Test name
Test status
Simulation time 458611816 ps
CPU time 6.36 seconds
Started Jun 04 03:02:33 PM PDT 24
Finished Jun 04 03:02:40 PM PDT 24
Peak memory 242220 kb
Host smart-191bd7e4-8749-4533-9f93-6086ec3aa800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230032371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.4230032371
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.2572167351
Short name T1061
Test name
Test status
Simulation time 2940332981 ps
CPU time 10.16 seconds
Started Jun 04 03:02:23 PM PDT 24
Finished Jun 04 03:02:34 PM PDT 24
Peak memory 242396 kb
Host smart-7c32f7a9-1ab4-4622-a71e-ca3ff1a55863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572167351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.2572167351
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.270685986
Short name T487
Test name
Test status
Simulation time 2096088625 ps
CPU time 22.58 seconds
Started Jun 04 03:02:24 PM PDT 24
Finished Jun 04 03:02:47 PM PDT 24
Peak memory 242364 kb
Host smart-c9a3a8c8-dffb-4798-902a-3d3aed9a5d02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=270685986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.270685986
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.2249308832
Short name T1039
Test name
Test status
Simulation time 225293030 ps
CPU time 3.87 seconds
Started Jun 04 03:02:34 PM PDT 24
Finished Jun 04 03:02:39 PM PDT 24
Peak memory 242164 kb
Host smart-1bfd8e2d-4559-4a30-85a8-50411eb212a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2249308832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.2249308832
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.4191134230
Short name T649
Test name
Test status
Simulation time 3980064910 ps
CPU time 10.29 seconds
Started Jun 04 03:02:25 PM PDT 24
Finished Jun 04 03:02:36 PM PDT 24
Peak memory 249020 kb
Host smart-9ebdabd8-04f5-4ce0-9f6b-20fcb1bfac09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191134230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.4191134230
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.1403467288
Short name T351
Test name
Test status
Simulation time 3854215081 ps
CPU time 100.47 seconds
Started Jun 04 03:02:33 PM PDT 24
Finished Jun 04 03:04:15 PM PDT 24
Peak memory 247740 kb
Host smart-f17552fc-8e8a-4fb1-886d-d48b5dfaced4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403467288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.1403467288
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.2430380159
Short name T600
Test name
Test status
Simulation time 31166746224 ps
CPU time 904.48 seconds
Started Jun 04 03:02:32 PM PDT 24
Finished Jun 04 03:17:38 PM PDT 24
Peak memory 289424 kb
Host smart-83168ea0-0d9a-434d-b3ea-bf73d63d9a30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430380159 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.2430380159
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.551218090
Short name T523
Test name
Test status
Simulation time 382550382 ps
CPU time 7.18 seconds
Started Jun 04 03:02:34 PM PDT 24
Finished Jun 04 03:02:43 PM PDT 24
Peak memory 242232 kb
Host smart-f8bcd1b4-d114-411f-80b0-22abdd202013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551218090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.551218090
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.3292753274
Short name T979
Test name
Test status
Simulation time 219252322 ps
CPU time 2.15 seconds
Started Jun 04 03:02:34 PM PDT 24
Finished Jun 04 03:02:38 PM PDT 24
Peak memory 240844 kb
Host smart-a5566511-923c-477c-a4dd-471568cfdbcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292753274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.3292753274
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.4207024337
Short name T55
Test name
Test status
Simulation time 28223158140 ps
CPU time 57.78 seconds
Started Jun 04 03:02:35 PM PDT 24
Finished Jun 04 03:03:34 PM PDT 24
Peak memory 246612 kb
Host smart-ccbf8176-5c64-4359-ab20-7aa680bc91f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207024337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.4207024337
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.1588024889
Short name T713
Test name
Test status
Simulation time 18842098803 ps
CPU time 46.56 seconds
Started Jun 04 03:02:32 PM PDT 24
Finished Jun 04 03:03:19 PM PDT 24
Peak memory 248352 kb
Host smart-5bf11840-1afa-4e6b-820c-b46a979e3a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588024889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.1588024889
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.3805316067
Short name T682
Test name
Test status
Simulation time 8249663993 ps
CPU time 48.92 seconds
Started Jun 04 03:02:33 PM PDT 24
Finished Jun 04 03:03:23 PM PDT 24
Peak memory 248976 kb
Host smart-210de199-53ab-4d4c-bc6e-e92483d943a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805316067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.3805316067
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.425066466
Short name T904
Test name
Test status
Simulation time 328187875 ps
CPU time 4.68 seconds
Started Jun 04 03:02:34 PM PDT 24
Finished Jun 04 03:02:40 PM PDT 24
Peak memory 242420 kb
Host smart-3a05effa-69ae-47ec-9980-4fdf62e2b32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425066466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.425066466
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.2122371271
Short name T1136
Test name
Test status
Simulation time 3621570507 ps
CPU time 30.2 seconds
Started Jun 04 03:02:33 PM PDT 24
Finished Jun 04 03:03:04 PM PDT 24
Peak memory 246332 kb
Host smart-b65e2118-4d4a-4cb8-b9d1-daa0ba748113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122371271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.2122371271
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.681674692
Short name T1153
Test name
Test status
Simulation time 899094549 ps
CPU time 22.57 seconds
Started Jun 04 03:02:35 PM PDT 24
Finished Jun 04 03:02:59 PM PDT 24
Peak memory 242500 kb
Host smart-d33b3584-6b77-47a1-81f7-129d6f753d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681674692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.681674692
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.4123146607
Short name T861
Test name
Test status
Simulation time 389911767 ps
CPU time 11.17 seconds
Started Jun 04 03:02:33 PM PDT 24
Finished Jun 04 03:02:45 PM PDT 24
Peak memory 242308 kb
Host smart-0263997e-4b38-4bf7-a64d-47bb0792b601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123146607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.4123146607
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.3447656243
Short name T786
Test name
Test status
Simulation time 275939764 ps
CPU time 4.85 seconds
Started Jun 04 03:02:34 PM PDT 24
Finished Jun 04 03:02:40 PM PDT 24
Peak memory 248520 kb
Host smart-9e6a5269-d495-4da5-8089-c22bab251769
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3447656243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.3447656243
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.1896281105
Short name T957
Test name
Test status
Simulation time 118006245 ps
CPU time 3.82 seconds
Started Jun 04 03:02:34 PM PDT 24
Finished Jun 04 03:02:39 PM PDT 24
Peak memory 248296 kb
Host smart-4150368d-19c5-44d3-a887-de12f079d168
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1896281105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.1896281105
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.1597109219
Short name T750
Test name
Test status
Simulation time 538145226 ps
CPU time 4.46 seconds
Started Jun 04 03:02:33 PM PDT 24
Finished Jun 04 03:02:38 PM PDT 24
Peak memory 242168 kb
Host smart-036cd8d6-2a3b-4a84-86ba-080f5e1008a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597109219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.1597109219
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.502543525
Short name T753
Test name
Test status
Simulation time 1191849476 ps
CPU time 20.35 seconds
Started Jun 04 03:02:34 PM PDT 24
Finished Jun 04 03:02:56 PM PDT 24
Peak memory 242304 kb
Host smart-05a2e942-beab-4b67-8d4e-8539393e8059
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502543525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.
502543525
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.808831963
Short name T334
Test name
Test status
Simulation time 229394994970 ps
CPU time 2856.26 seconds
Started Jun 04 03:02:34 PM PDT 24
Finished Jun 04 03:50:11 PM PDT 24
Peak memory 283036 kb
Host smart-88c3d5f8-e81f-4709-9fc8-18dbab17ee10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808831963 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.808831963
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.4002794423
Short name T95
Test name
Test status
Simulation time 1668826743 ps
CPU time 33.6 seconds
Started Jun 04 03:02:34 PM PDT 24
Finished Jun 04 03:03:09 PM PDT 24
Peak memory 242264 kb
Host smart-ff203a8f-b810-455d-a12f-68b39d2daf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002794423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.4002794423
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.3273860688
Short name T438
Test name
Test status
Simulation time 67312982 ps
CPU time 1.91 seconds
Started Jun 04 03:02:34 PM PDT 24
Finished Jun 04 03:02:37 PM PDT 24
Peak memory 240884 kb
Host smart-553c08c3-4a41-4652-8554-5ca63aa40687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273860688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.3273860688
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.4096779995
Short name T138
Test name
Test status
Simulation time 1574113082 ps
CPU time 18.83 seconds
Started Jun 04 03:02:35 PM PDT 24
Finished Jun 04 03:02:55 PM PDT 24
Peak memory 242344 kb
Host smart-a234e312-474a-4874-8a42-f3238d76a55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096779995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.4096779995
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.4153727442
Short name T532
Test name
Test status
Simulation time 311557192 ps
CPU time 12.41 seconds
Started Jun 04 03:02:33 PM PDT 24
Finished Jun 04 03:02:46 PM PDT 24
Peak memory 242264 kb
Host smart-ce008886-1bb8-497f-91f3-d3915d3ec354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153727442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.4153727442
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.2067327445
Short name T382
Test name
Test status
Simulation time 4205584590 ps
CPU time 18.25 seconds
Started Jun 04 03:02:36 PM PDT 24
Finished Jun 04 03:02:55 PM PDT 24
Peak memory 242188 kb
Host smart-fb378802-eb2b-47e9-b9c1-afafb6aa456d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067327445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.2067327445
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.2323209037
Short name T1132
Test name
Test status
Simulation time 149679294 ps
CPU time 4.15 seconds
Started Jun 04 03:02:33 PM PDT 24
Finished Jun 04 03:02:38 PM PDT 24
Peak memory 242436 kb
Host smart-f66c2ea7-5e11-48a8-97ef-5ed136ed6846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323209037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.2323209037
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.3791396841
Short name T174
Test name
Test status
Simulation time 2318100885 ps
CPU time 54.97 seconds
Started Jun 04 03:02:32 PM PDT 24
Finished Jun 04 03:03:27 PM PDT 24
Peak memory 253208 kb
Host smart-0dee0666-48f7-41ad-ae21-39dbd251a31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791396841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.3791396841
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.4141567232
Short name T1076
Test name
Test status
Simulation time 1145966167 ps
CPU time 17.39 seconds
Started Jun 04 03:02:32 PM PDT 24
Finished Jun 04 03:02:50 PM PDT 24
Peak memory 242244 kb
Host smart-9f31af6b-28ed-4b39-b631-58ef256250c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141567232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.4141567232
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.584385597
Short name T599
Test name
Test status
Simulation time 564402551 ps
CPU time 5.4 seconds
Started Jun 04 03:02:36 PM PDT 24
Finished Jun 04 03:02:42 PM PDT 24
Peak memory 242240 kb
Host smart-17f49c9b-eb5f-49be-8a93-7d595d61f2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584385597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.584385597
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.2925025713
Short name T799
Test name
Test status
Simulation time 1359869967 ps
CPU time 23.11 seconds
Started Jun 04 03:02:34 PM PDT 24
Finished Jun 04 03:02:59 PM PDT 24
Peak memory 242296 kb
Host smart-3794bae3-d739-44f9-a590-86a1964ebfef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2925025713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.2925025713
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.3482806268
Short name T959
Test name
Test status
Simulation time 184753007 ps
CPU time 4.92 seconds
Started Jun 04 03:02:33 PM PDT 24
Finished Jun 04 03:02:39 PM PDT 24
Peak memory 242204 kb
Host smart-7d6f0ede-0e55-45a4-a05f-e423a78b643d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3482806268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.3482806268
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.2653769708
Short name T392
Test name
Test status
Simulation time 254028623 ps
CPU time 5.14 seconds
Started Jun 04 03:02:36 PM PDT 24
Finished Jun 04 03:02:42 PM PDT 24
Peak memory 242276 kb
Host smart-4f50d49f-a037-4395-b35e-e8681251c6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653769708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.2653769708
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.2755220122
Short name T651
Test name
Test status
Simulation time 51677595946 ps
CPU time 334.33 seconds
Started Jun 04 03:02:34 PM PDT 24
Finished Jun 04 03:08:09 PM PDT 24
Peak memory 265524 kb
Host smart-c2521abe-1040-44e2-ac62-ae754ff0b486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755220122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all
.2755220122
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.3687735522
Short name T15
Test name
Test status
Simulation time 876933093 ps
CPU time 18.9 seconds
Started Jun 04 03:02:35 PM PDT 24
Finished Jun 04 03:02:55 PM PDT 24
Peak memory 242460 kb
Host smart-2c0c6397-0ce0-4f6c-bc90-a160d2c1c2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687735522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.3687735522
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.2798412879
Short name T744
Test name
Test status
Simulation time 92933070 ps
CPU time 1.62 seconds
Started Jun 04 03:02:43 PM PDT 24
Finished Jun 04 03:02:45 PM PDT 24
Peak memory 240852 kb
Host smart-8407fbc3-1850-405a-84cd-cbd63ad7b5f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798412879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.2798412879
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.1689501848
Short name T110
Test name
Test status
Simulation time 566502893 ps
CPU time 9.35 seconds
Started Jun 04 03:02:37 PM PDT 24
Finished Jun 04 03:02:47 PM PDT 24
Peak memory 248204 kb
Host smart-ace31d9e-3e0b-438d-936a-c996ae3bdb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689501848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.1689501848
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.2364741765
Short name T1089
Test name
Test status
Simulation time 814268077 ps
CPU time 25.48 seconds
Started Jun 04 03:02:34 PM PDT 24
Finished Jun 04 03:03:01 PM PDT 24
Peak memory 242492 kb
Host smart-b354ab84-3e43-46c0-a54a-4acdbcccdce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364741765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.2364741765
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.1535519144
Short name T466
Test name
Test status
Simulation time 831616657 ps
CPU time 10.4 seconds
Started Jun 04 03:02:34 PM PDT 24
Finished Jun 04 03:02:46 PM PDT 24
Peak memory 242428 kb
Host smart-813c4585-6685-4a58-974f-81d107d29eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535519144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.1535519144
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.2702979184
Short name T35
Test name
Test status
Simulation time 168273212 ps
CPU time 3.88 seconds
Started Jun 04 03:02:32 PM PDT 24
Finished Jun 04 03:02:36 PM PDT 24
Peak memory 242404 kb
Host smart-d8e652df-2f42-4616-921b-60f268517342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702979184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.2702979184
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.3763595266
Short name T888
Test name
Test status
Simulation time 1309963135 ps
CPU time 31.66 seconds
Started Jun 04 03:02:35 PM PDT 24
Finished Jun 04 03:03:08 PM PDT 24
Peak memory 248936 kb
Host smart-246c56eb-94f4-409d-ba41-323d254aacb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763595266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.3763595266
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.1119574717
Short name T512
Test name
Test status
Simulation time 907466560 ps
CPU time 20.86 seconds
Started Jun 04 03:02:35 PM PDT 24
Finished Jun 04 03:02:57 PM PDT 24
Peak memory 242392 kb
Host smart-f3fb8b20-cb7e-40dc-8bb1-13a05bfb5c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119574717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.1119574717
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.925246228
Short name T180
Test name
Test status
Simulation time 406980328 ps
CPU time 4.46 seconds
Started Jun 04 03:02:34 PM PDT 24
Finished Jun 04 03:02:40 PM PDT 24
Peak memory 242336 kb
Host smart-033ae3ed-d25d-4bc5-81ed-7d8d508cc214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925246228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.925246228
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.243245512
Short name T88
Test name
Test status
Simulation time 2876726591 ps
CPU time 24.98 seconds
Started Jun 04 03:02:34 PM PDT 24
Finished Jun 04 03:02:59 PM PDT 24
Peak memory 242292 kb
Host smart-bf916019-bbf6-4fab-a536-cdfcccc19f14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=243245512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.243245512
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.1699744018
Short name T367
Test name
Test status
Simulation time 2089550760 ps
CPU time 5.57 seconds
Started Jun 04 03:02:37 PM PDT 24
Finished Jun 04 03:02:43 PM PDT 24
Peak memory 242212 kb
Host smart-fdd5f50f-4999-452d-9cb2-a1fde00c862d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1699744018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.1699744018
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.192599307
Short name T403
Test name
Test status
Simulation time 5566678573 ps
CPU time 10.63 seconds
Started Jun 04 03:02:32 PM PDT 24
Finished Jun 04 03:02:44 PM PDT 24
Peak memory 242116 kb
Host smart-57e250b0-98a7-41a7-acb3-3521489fac8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192599307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.192599307
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.2861706934
Short name T856
Test name
Test status
Simulation time 13974020210 ps
CPU time 117.71 seconds
Started Jun 04 03:02:43 PM PDT 24
Finished Jun 04 03:04:42 PM PDT 24
Peak memory 246056 kb
Host smart-e81791f4-42d8-4e01-8691-812815c7adb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861706934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all
.2861706934
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.17219055
Short name T887
Test name
Test status
Simulation time 194123360892 ps
CPU time 565.76 seconds
Started Jun 04 03:02:46 PM PDT 24
Finished Jun 04 03:12:12 PM PDT 24
Peak memory 257272 kb
Host smart-3feef094-54f2-4bfa-aba3-b5b39b4e9f57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17219055 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.17219055
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.4145937988
Short name T1142
Test name
Test status
Simulation time 2455513639 ps
CPU time 6.75 seconds
Started Jun 04 03:02:36 PM PDT 24
Finished Jun 04 03:02:44 PM PDT 24
Peak memory 242380 kb
Host smart-32d55068-ac67-4cb4-a516-ef5dcd3f313e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145937988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.4145937988
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.2401498716
Short name T1135
Test name
Test status
Simulation time 53235783 ps
CPU time 1.78 seconds
Started Jun 04 03:02:44 PM PDT 24
Finished Jun 04 03:02:47 PM PDT 24
Peak memory 240764 kb
Host smart-e9c771f9-edcf-48dd-9224-411e73cc880b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401498716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.2401498716
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.1748102478
Short name T1052
Test name
Test status
Simulation time 2921999043 ps
CPU time 23.59 seconds
Started Jun 04 03:02:43 PM PDT 24
Finished Jun 04 03:03:07 PM PDT 24
Peak memory 242736 kb
Host smart-35e40340-ae78-41aa-9332-c50d80afa994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748102478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.1748102478
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.3195411575
Short name T1070
Test name
Test status
Simulation time 4865614891 ps
CPU time 27.26 seconds
Started Jun 04 03:02:43 PM PDT 24
Finished Jun 04 03:03:11 PM PDT 24
Peak memory 242812 kb
Host smart-63b490c4-76fb-4312-ada0-56c7e229669d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195411575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.3195411575
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.3675084592
Short name T31
Test name
Test status
Simulation time 179206345 ps
CPU time 4.44 seconds
Started Jun 04 03:02:44 PM PDT 24
Finished Jun 04 03:02:49 PM PDT 24
Peak memory 242456 kb
Host smart-365ebf4c-4a4c-4e10-93d2-24828e4a61e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675084592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.3675084592
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.3690932566
Short name T1096
Test name
Test status
Simulation time 528948232 ps
CPU time 6.57 seconds
Started Jun 04 03:02:42 PM PDT 24
Finished Jun 04 03:02:49 PM PDT 24
Peak memory 242744 kb
Host smart-609f825d-164e-4cd1-9e1d-d6a16e81d2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690932566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.3690932566
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.3871853452
Short name T190
Test name
Test status
Simulation time 9576659525 ps
CPU time 19.61 seconds
Started Jun 04 03:02:42 PM PDT 24
Finished Jun 04 03:03:02 PM PDT 24
Peak memory 248976 kb
Host smart-7a79484e-d988-48c6-a24f-e7b5650c789d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871853452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.3871853452
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.2454439043
Short name T748
Test name
Test status
Simulation time 241202796 ps
CPU time 8.85 seconds
Started Jun 04 03:02:43 PM PDT 24
Finished Jun 04 03:02:52 PM PDT 24
Peak memory 242160 kb
Host smart-7459db42-cdd5-4c22-b846-f096aa1b51ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454439043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.2454439043
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.2413405452
Short name T306
Test name
Test status
Simulation time 1274997043 ps
CPU time 17.75 seconds
Started Jun 04 03:02:43 PM PDT 24
Finished Jun 04 03:03:02 PM PDT 24
Peak memory 242452 kb
Host smart-d57ad384-b910-48e3-b0c4-fb8e69417b7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2413405452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.2413405452
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.2011452105
Short name T192
Test name
Test status
Simulation time 393866624 ps
CPU time 7 seconds
Started Jun 04 03:02:41 PM PDT 24
Finished Jun 04 03:02:49 PM PDT 24
Peak memory 242508 kb
Host smart-fd521dec-b007-4b44-a5b7-e20bf76565a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2011452105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.2011452105
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.3975711861
Short name T534
Test name
Test status
Simulation time 5083343176 ps
CPU time 12.39 seconds
Started Jun 04 03:02:47 PM PDT 24
Finished Jun 04 03:03:00 PM PDT 24
Peak memory 242596 kb
Host smart-0b0ae01f-caad-4cbe-b2a7-7db5dbe6ac45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975711861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.3975711861
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.3259735204
Short name T897
Test name
Test status
Simulation time 10420368243 ps
CPU time 119.31 seconds
Started Jun 04 03:02:46 PM PDT 24
Finished Jun 04 03:04:46 PM PDT 24
Peak memory 245912 kb
Host smart-c422bfdb-4a22-4bf6-a50b-00341bc89d83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259735204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all
.3259735204
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.1162635137
Short name T153
Test name
Test status
Simulation time 11647967229 ps
CPU time 24.16 seconds
Started Jun 04 03:02:44 PM PDT 24
Finished Jun 04 03:03:09 PM PDT 24
Peak memory 248952 kb
Host smart-e4ddb30e-d279-4b8c-b85e-4caaaa56748c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162635137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.1162635137
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.3152730157
Short name T1041
Test name
Test status
Simulation time 69007011 ps
CPU time 1.86 seconds
Started Jun 04 03:02:45 PM PDT 24
Finished Jun 04 03:02:47 PM PDT 24
Peak memory 240820 kb
Host smart-c45d08cd-399d-4505-8620-6cd5cd52dd89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152730157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.3152730157
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.1765964203
Short name T484
Test name
Test status
Simulation time 324507235 ps
CPU time 18.81 seconds
Started Jun 04 03:02:43 PM PDT 24
Finished Jun 04 03:03:02 PM PDT 24
Peak memory 242344 kb
Host smart-55362e78-8239-4f49-82de-069837805e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765964203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.1765964203
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.2641923998
Short name T1169
Test name
Test status
Simulation time 1514451407 ps
CPU time 27.64 seconds
Started Jun 04 03:02:43 PM PDT 24
Finished Jun 04 03:03:11 PM PDT 24
Peak memory 242516 kb
Host smart-11d73df9-5e2d-4954-a25a-b8d08b2e0435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641923998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.2641923998
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.2194954248
Short name T781
Test name
Test status
Simulation time 513267496 ps
CPU time 4.07 seconds
Started Jun 04 03:02:43 PM PDT 24
Finished Jun 04 03:02:48 PM PDT 24
Peak memory 242432 kb
Host smart-850d480d-bd7d-4242-9e93-d691587d4ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194954248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.2194954248
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.2309054285
Short name T668
Test name
Test status
Simulation time 1704481327 ps
CPU time 12.88 seconds
Started Jun 04 03:02:46 PM PDT 24
Finished Jun 04 03:03:00 PM PDT 24
Peak memory 244952 kb
Host smart-7ac96cca-456f-4636-a5e8-0317608526bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309054285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.2309054285
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.4124727843
Short name T379
Test name
Test status
Simulation time 1311632655 ps
CPU time 18.52 seconds
Started Jun 04 03:02:47 PM PDT 24
Finished Jun 04 03:03:06 PM PDT 24
Peak memory 242516 kb
Host smart-e046f0ae-51c3-4911-af48-5055d94d6eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124727843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.4124727843
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.114965866
Short name T853
Test name
Test status
Simulation time 866144294 ps
CPU time 11.78 seconds
Started Jun 04 03:02:40 PM PDT 24
Finished Jun 04 03:02:52 PM PDT 24
Peak memory 242252 kb
Host smart-734f8b29-f3ce-45a4-af7e-366f70487cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114965866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.114965866
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.3569138352
Short name T616
Test name
Test status
Simulation time 860311800 ps
CPU time 21.29 seconds
Started Jun 04 03:02:43 PM PDT 24
Finished Jun 04 03:03:06 PM PDT 24
Peak memory 248840 kb
Host smart-3dae0cde-0ef1-4256-9212-ad4b7ee0c7f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3569138352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.3569138352
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.3880846792
Short name T1118
Test name
Test status
Simulation time 518586987 ps
CPU time 9.57 seconds
Started Jun 04 03:02:41 PM PDT 24
Finished Jun 04 03:02:51 PM PDT 24
Peak memory 242252 kb
Host smart-5df2dc9e-09b9-4ef1-967b-5472b5cbaa3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3880846792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.3880846792
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.1606463839
Short name T834
Test name
Test status
Simulation time 859217122 ps
CPU time 10.31 seconds
Started Jun 04 03:02:43 PM PDT 24
Finished Jun 04 03:02:54 PM PDT 24
Peak memory 248768 kb
Host smart-2ecc1481-c19a-4375-bda2-d576c06d49da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606463839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.1606463839
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.520632258
Short name T968
Test name
Test status
Simulation time 15279931422 ps
CPU time 178.44 seconds
Started Jun 04 03:02:43 PM PDT 24
Finished Jun 04 03:05:42 PM PDT 24
Peak memory 244936 kb
Host smart-2e62f44f-14ca-4091-bebf-090af899c540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520632258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.
520632258
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.888274139
Short name T568
Test name
Test status
Simulation time 151465049272 ps
CPU time 1015.89 seconds
Started Jun 04 03:02:46 PM PDT 24
Finished Jun 04 03:19:43 PM PDT 24
Peak memory 265628 kb
Host smart-07a88bb6-19d2-4267-85cd-878ba1dba5f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888274139 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.888274139
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.1279803035
Short name T866
Test name
Test status
Simulation time 1943873839 ps
CPU time 23.2 seconds
Started Jun 04 03:02:43 PM PDT 24
Finished Jun 04 03:03:07 PM PDT 24
Peak memory 242188 kb
Host smart-ad505e77-95c5-4514-99d4-237d85ada75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279803035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.1279803035
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.4202989765
Short name T1
Test name
Test status
Simulation time 181703434 ps
CPU time 3.07 seconds
Started Jun 04 03:02:55 PM PDT 24
Finished Jun 04 03:02:59 PM PDT 24
Peak memory 240792 kb
Host smart-528b2de4-7ef8-4c32-91a8-577c3e96c39e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202989765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.4202989765
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.3832746313
Short name T1161
Test name
Test status
Simulation time 9005489373 ps
CPU time 31.53 seconds
Started Jun 04 03:02:52 PM PDT 24
Finished Jun 04 03:03:24 PM PDT 24
Peak memory 248996 kb
Host smart-8591e9d9-bce6-4e73-be4c-b02a75402e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832746313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.3832746313
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.2279190053
Short name T725
Test name
Test status
Simulation time 11478062680 ps
CPU time 34.8 seconds
Started Jun 04 03:02:52 PM PDT 24
Finished Jun 04 03:03:28 PM PDT 24
Peak memory 243588 kb
Host smart-3d994e30-c7e9-41d8-a71d-7f02472269af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279190053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.2279190053
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.3143450557
Short name T776
Test name
Test status
Simulation time 829484558 ps
CPU time 5.68 seconds
Started Jun 04 03:02:50 PM PDT 24
Finished Jun 04 03:02:56 PM PDT 24
Peak memory 242136 kb
Host smart-3d5d6762-720b-4735-9108-4a3db8bf99bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143450557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.3143450557
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.3129287708
Short name T133
Test name
Test status
Simulation time 160625546 ps
CPU time 3.78 seconds
Started Jun 04 03:02:52 PM PDT 24
Finished Jun 04 03:02:57 PM PDT 24
Peak memory 242392 kb
Host smart-c821ab68-bdce-4053-9b58-51885fe9dfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129287708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.3129287708
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.2762380145
Short name T245
Test name
Test status
Simulation time 207883745 ps
CPU time 3 seconds
Started Jun 04 03:02:52 PM PDT 24
Finished Jun 04 03:02:56 PM PDT 24
Peak memory 247124 kb
Host smart-02d66b99-74c7-4903-bb3a-f6b9fc54c535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762380145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.2762380145
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.2131466618
Short name T3
Test name
Test status
Simulation time 1886607660 ps
CPU time 11.99 seconds
Started Jun 04 03:02:51 PM PDT 24
Finished Jun 04 03:03:03 PM PDT 24
Peak memory 242456 kb
Host smart-fd0366eb-c6d7-4430-87e6-a4ad08487963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131466618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.2131466618
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.2692051468
Short name T806
Test name
Test status
Simulation time 349656006 ps
CPU time 9.01 seconds
Started Jun 04 03:02:51 PM PDT 24
Finished Jun 04 03:03:01 PM PDT 24
Peak memory 242416 kb
Host smart-341a049d-3ca4-4e48-a77a-d8c4dc7ce07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692051468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.2692051468
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.2880631972
Short name T835
Test name
Test status
Simulation time 1124344203 ps
CPU time 18.56 seconds
Started Jun 04 03:02:54 PM PDT 24
Finished Jun 04 03:03:13 PM PDT 24
Peak memory 242500 kb
Host smart-f84bb9e7-41f8-4583-89ce-bb6d7dd41a3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2880631972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.2880631972
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.2863892574
Short name T816
Test name
Test status
Simulation time 196424718 ps
CPU time 3.88 seconds
Started Jun 04 03:02:53 PM PDT 24
Finished Jun 04 03:02:57 PM PDT 24
Peak memory 242312 kb
Host smart-53605868-e144-45f8-8b2e-6f00bf341fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863892574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.2863892574
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.517853703
Short name T297
Test name
Test status
Simulation time 112164819140 ps
CPU time 254.46 seconds
Started Jun 04 03:02:58 PM PDT 24
Finished Jun 04 03:07:13 PM PDT 24
Peak memory 258516 kb
Host smart-a8581dc6-3828-4211-be4e-20b266545bca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517853703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.
517853703
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.1888993716
Short name T256
Test name
Test status
Simulation time 185103364099 ps
CPU time 2419.37 seconds
Started Jun 04 03:02:52 PM PDT 24
Finished Jun 04 03:43:12 PM PDT 24
Peak memory 328116 kb
Host smart-97e4261d-b146-4968-8755-a909550c4f99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888993716 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.1888993716
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.4028998404
Short name T667
Test name
Test status
Simulation time 1770277679 ps
CPU time 32.69 seconds
Started Jun 04 03:02:53 PM PDT 24
Finished Jun 04 03:03:26 PM PDT 24
Peak memory 242272 kb
Host smart-e2264226-62af-4380-a988-9b20f35bfcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028998404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.4028998404
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.3316994339
Short name T672
Test name
Test status
Simulation time 57247699 ps
CPU time 1.82 seconds
Started Jun 04 02:59:43 PM PDT 24
Finished Jun 04 02:59:45 PM PDT 24
Peak memory 241272 kb
Host smart-daf7fede-69e0-40e6-9c8e-4b17ecd42d61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316994339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.3316994339
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.1759145762
Short name T789
Test name
Test status
Simulation time 2539645000 ps
CPU time 14.86 seconds
Started Jun 04 02:59:39 PM PDT 24
Finished Jun 04 02:59:54 PM PDT 24
Peak memory 242708 kb
Host smart-e70b1165-5bb1-419d-8ab3-8e21ed14b854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759145762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.1759145762
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.838956068
Short name T26
Test name
Test status
Simulation time 12395750530 ps
CPU time 30.69 seconds
Started Jun 04 02:59:39 PM PDT 24
Finished Jun 04 03:00:10 PM PDT 24
Peak memory 243340 kb
Host smart-806b2ddc-a058-4eda-abff-e9bcd37c76e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838956068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.838956068
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.3641313372
Short name T485
Test name
Test status
Simulation time 1143073351 ps
CPU time 32.21 seconds
Started Jun 04 02:59:39 PM PDT 24
Finished Jun 04 03:00:12 PM PDT 24
Peak memory 242452 kb
Host smart-fce6440e-cf0a-4b10-ba62-0185c4145f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641313372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.3641313372
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.2598446392
Short name T197
Test name
Test status
Simulation time 2771433187 ps
CPU time 7.07 seconds
Started Jun 04 02:59:38 PM PDT 24
Finished Jun 04 02:59:45 PM PDT 24
Peak memory 242540 kb
Host smart-4bf87ccd-1e83-490a-9778-59772c72cd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598446392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.2598446392
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.1314370917
Short name T454
Test name
Test status
Simulation time 1637643360 ps
CPU time 5.19 seconds
Started Jun 04 02:59:42 PM PDT 24
Finished Jun 04 02:59:48 PM PDT 24
Peak memory 242632 kb
Host smart-397dd408-e34b-45d4-b119-991c47cdcae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314370917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.1314370917
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.2279201712
Short name T143
Test name
Test status
Simulation time 3427029402 ps
CPU time 22.34 seconds
Started Jun 04 02:59:39 PM PDT 24
Finished Jun 04 03:00:02 PM PDT 24
Peak memory 249008 kb
Host smart-b6a59faf-aaf1-4114-880e-ec01b29903c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279201712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.2279201712
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.1791092729
Short name T675
Test name
Test status
Simulation time 207577354 ps
CPU time 8.53 seconds
Started Jun 04 02:59:40 PM PDT 24
Finished Jun 04 02:59:49 PM PDT 24
Peak memory 242260 kb
Host smart-fa472b70-d0ac-44ff-815a-0133ff826a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791092729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.1791092729
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.1494944284
Short name T111
Test name
Test status
Simulation time 3281630943 ps
CPU time 10.11 seconds
Started Jun 04 02:59:38 PM PDT 24
Finished Jun 04 02:59:49 PM PDT 24
Peak memory 248868 kb
Host smart-53980067-9fac-4952-b574-30352a9fbaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494944284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.1494944284
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.1863384315
Short name T252
Test name
Test status
Simulation time 454207618 ps
CPU time 4.03 seconds
Started Jun 04 02:59:41 PM PDT 24
Finished Jun 04 02:59:46 PM PDT 24
Peak memory 248556 kb
Host smart-993608e0-5b08-4b86-98b2-b988cf04b2dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1863384315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.1863384315
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.1351979923
Short name T251
Test name
Test status
Simulation time 198488950 ps
CPU time 3.64 seconds
Started Jun 04 02:59:39 PM PDT 24
Finished Jun 04 02:59:43 PM PDT 24
Peak memory 248564 kb
Host smart-8b7e770d-1372-4d66-bec7-c50e321efc46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1351979923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.1351979923
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.1420865117
Short name T1129
Test name
Test status
Simulation time 235446306 ps
CPU time 4.62 seconds
Started Jun 04 02:59:38 PM PDT 24
Finished Jun 04 02:59:43 PM PDT 24
Peak memory 242376 kb
Host smart-899f812a-0b88-4a2e-8d05-9b35e93e883c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420865117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.1420865117
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.1043726123
Short name T1100
Test name
Test status
Simulation time 4201595621 ps
CPU time 54.62 seconds
Started Jun 04 02:59:43 PM PDT 24
Finished Jun 04 03:00:38 PM PDT 24
Peak memory 261320 kb
Host smart-699ffcfb-7423-4176-b4d5-5a65e2aa2f34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043726123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.
1043726123
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.4186193829
Short name T301
Test name
Test status
Simulation time 43327010599 ps
CPU time 636.62 seconds
Started Jun 04 02:59:40 PM PDT 24
Finished Jun 04 03:10:18 PM PDT 24
Peak memory 363404 kb
Host smart-3cf66486-728f-40d0-b4ca-bf758d224e01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186193829 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.4186193829
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.3050445563
Short name T302
Test name
Test status
Simulation time 980232992 ps
CPU time 20.72 seconds
Started Jun 04 02:59:38 PM PDT 24
Finished Jun 04 02:59:59 PM PDT 24
Peak memory 248832 kb
Host smart-71469ada-b677-4270-93f6-44ad29d4c508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050445563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.3050445563
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.4138307214
Short name T825
Test name
Test status
Simulation time 333846518 ps
CPU time 4.34 seconds
Started Jun 04 03:02:53 PM PDT 24
Finished Jun 04 03:02:58 PM PDT 24
Peak memory 242684 kb
Host smart-cfa1efac-f7ac-4eda-b2b3-c6d58c074914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138307214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.4138307214
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.3998462867
Short name T964
Test name
Test status
Simulation time 222035901 ps
CPU time 3.07 seconds
Started Jun 04 03:02:58 PM PDT 24
Finished Jun 04 03:03:02 PM PDT 24
Peak memory 242204 kb
Host smart-c6816ab8-1dae-4bac-adc2-45fbb1371e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998462867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.3998462867
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.533580443
Short name T708
Test name
Test status
Simulation time 285011328 ps
CPU time 4.53 seconds
Started Jun 04 03:02:57 PM PDT 24
Finished Jun 04 03:03:02 PM PDT 24
Peak memory 242492 kb
Host smart-2ee3c57b-b1c3-4997-b0b6-7207d2eeef8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533580443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.533580443
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.1774509486
Short name T181
Test name
Test status
Simulation time 140281962 ps
CPU time 3.94 seconds
Started Jun 04 03:02:51 PM PDT 24
Finished Jun 04 03:02:56 PM PDT 24
Peak memory 242220 kb
Host smart-b18f2e29-f14b-43ca-8a66-ad89bb65486c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774509486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.1774509486
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.4046391467
Short name T296
Test name
Test status
Simulation time 52441858552 ps
CPU time 1167.54 seconds
Started Jun 04 03:02:51 PM PDT 24
Finished Jun 04 03:22:19 PM PDT 24
Peak memory 265488 kb
Host smart-227f4cd7-c6ea-4ac7-8ba5-259d9b4ef11c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046391467 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.4046391467
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.3036017878
Short name T137
Test name
Test status
Simulation time 194754836 ps
CPU time 3.73 seconds
Started Jun 04 03:02:52 PM PDT 24
Finished Jun 04 03:02:57 PM PDT 24
Peak memory 242432 kb
Host smart-47b38d2e-160e-47c8-80b8-8c58e51f4e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036017878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.3036017878
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.3427256967
Short name T795
Test name
Test status
Simulation time 163544784 ps
CPU time 4.03 seconds
Started Jun 04 03:02:55 PM PDT 24
Finished Jun 04 03:03:00 PM PDT 24
Peak memory 242292 kb
Host smart-fb5c770e-6af0-443f-8f5a-f4708590a94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427256967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.3427256967
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.1227448415
Short name T390
Test name
Test status
Simulation time 32620712192 ps
CPU time 851.17 seconds
Started Jun 04 03:02:52 PM PDT 24
Finished Jun 04 03:17:05 PM PDT 24
Peak memory 313648 kb
Host smart-c40fb145-5ebc-4d73-880c-c031aa2771af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227448415 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.1227448415
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.3261269232
Short name T128
Test name
Test status
Simulation time 2250579238 ps
CPU time 4.88 seconds
Started Jun 04 03:02:57 PM PDT 24
Finished Jun 04 03:03:03 PM PDT 24
Peak memory 242488 kb
Host smart-abdfa05d-f047-498d-a1e4-0c09b4545573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261269232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.3261269232
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.1450615612
Short name T501
Test name
Test status
Simulation time 150357030 ps
CPU time 6.58 seconds
Started Jun 04 03:02:51 PM PDT 24
Finished Jun 04 03:02:58 PM PDT 24
Peak memory 242556 kb
Host smart-2e84c4ea-eed6-434a-937a-33e4fe7a5fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450615612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.1450615612
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.2131572051
Short name T1035
Test name
Test status
Simulation time 245657201 ps
CPU time 3.3 seconds
Started Jun 04 03:02:54 PM PDT 24
Finished Jun 04 03:02:58 PM PDT 24
Peak memory 242652 kb
Host smart-ea58e667-ee21-4eac-95b1-9a1a72e23ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131572051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.2131572051
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.3010794260
Short name T435
Test name
Test status
Simulation time 1089097589 ps
CPU time 8.35 seconds
Started Jun 04 03:02:52 PM PDT 24
Finished Jun 04 03:03:01 PM PDT 24
Peak memory 242272 kb
Host smart-c71f4be5-7bec-47a4-b5ad-06d550899992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010794260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.3010794260
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.3607574988
Short name T638
Test name
Test status
Simulation time 237034877 ps
CPU time 7.08 seconds
Started Jun 04 03:03:00 PM PDT 24
Finished Jun 04 03:03:08 PM PDT 24
Peak memory 242596 kb
Host smart-46f21f85-557f-4c3e-a845-e8979bec69a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607574988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.3607574988
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.1745371485
Short name T223
Test name
Test status
Simulation time 289254205811 ps
CPU time 2002.4 seconds
Started Jun 04 03:03:00 PM PDT 24
Finished Jun 04 03:36:25 PM PDT 24
Peak memory 475448 kb
Host smart-8d7320db-02ea-4681-b34b-d6a2239fedb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745371485 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.1745371485
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.1426157176
Short name T737
Test name
Test status
Simulation time 147397295 ps
CPU time 4.06 seconds
Started Jun 04 03:03:00 PM PDT 24
Finished Jun 04 03:03:06 PM PDT 24
Peak memory 242392 kb
Host smart-ebbce809-1c20-4ee8-9d11-8ad3c00b72c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426157176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.1426157176
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.4262718145
Short name T644
Test name
Test status
Simulation time 741432188 ps
CPU time 6.45 seconds
Started Jun 04 03:03:03 PM PDT 24
Finished Jun 04 03:03:11 PM PDT 24
Peak memory 242436 kb
Host smart-99854e06-dedd-46b7-aa16-9f9f099cc46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262718145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.4262718145
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.1444262934
Short name T388
Test name
Test status
Simulation time 250344678980 ps
CPU time 1736.35 seconds
Started Jun 04 03:03:00 PM PDT 24
Finished Jun 04 03:31:57 PM PDT 24
Peak memory 300040 kb
Host smart-796197d1-be86-428f-b59d-5e3cba369bcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444262934 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.1444262934
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.1542170967
Short name T213
Test name
Test status
Simulation time 122823109 ps
CPU time 4.86 seconds
Started Jun 04 03:03:05 PM PDT 24
Finished Jun 04 03:03:11 PM PDT 24
Peak memory 242432 kb
Host smart-5a5191dd-31f9-4f59-bcf6-cbe538dad59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542170967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.1542170967
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.1726321905
Short name T71
Test name
Test status
Simulation time 816696275 ps
CPU time 10.32 seconds
Started Jun 04 03:03:03 PM PDT 24
Finished Jun 04 03:03:14 PM PDT 24
Peak memory 242340 kb
Host smart-69210c08-e912-4482-bc0a-f9b457af071c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726321905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.1726321905
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.807898877
Short name T425
Test name
Test status
Simulation time 49599432162 ps
CPU time 812.01 seconds
Started Jun 04 03:03:01 PM PDT 24
Finished Jun 04 03:16:35 PM PDT 24
Peak memory 307952 kb
Host smart-f16dc077-2dcd-410d-80b5-0e75e00b459b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807898877 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.807898877
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.1390491854
Short name T1150
Test name
Test status
Simulation time 533961144 ps
CPU time 4.14 seconds
Started Jun 04 03:02:58 PM PDT 24
Finished Jun 04 03:03:03 PM PDT 24
Peak memory 242328 kb
Host smart-1268ba2f-bb8f-48e9-98aa-8b1953e2ffc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390491854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.1390491854
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.1050740818
Short name T590
Test name
Test status
Simulation time 741692981 ps
CPU time 9.36 seconds
Started Jun 04 03:03:00 PM PDT 24
Finished Jun 04 03:03:11 PM PDT 24
Peak memory 242380 kb
Host smart-59bc578e-3c21-491e-81ec-f2656384398e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050740818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.1050740818
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.976374495
Short name T468
Test name
Test status
Simulation time 837695466347 ps
CPU time 2768.21 seconds
Started Jun 04 03:03:05 PM PDT 24
Finished Jun 04 03:49:15 PM PDT 24
Peak memory 405716 kb
Host smart-31a0bd79-b697-418d-b2f2-78c3227d54c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976374495 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.976374495
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.655765347
Short name T583
Test name
Test status
Simulation time 332011963 ps
CPU time 4.6 seconds
Started Jun 04 03:03:01 PM PDT 24
Finished Jun 04 03:03:07 PM PDT 24
Peak memory 242272 kb
Host smart-ab806d3f-6da1-48ec-aa29-dcc5eeb48d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655765347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.655765347
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.2572677914
Short name T191
Test name
Test status
Simulation time 1846402657 ps
CPU time 4.23 seconds
Started Jun 04 03:03:00 PM PDT 24
Finished Jun 04 03:03:05 PM PDT 24
Peak memory 248500 kb
Host smart-8142b535-54a8-44f8-9556-f5e08c2c6f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572677914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.2572677914
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.3447110449
Short name T341
Test name
Test status
Simulation time 49356193744 ps
CPU time 1041.77 seconds
Started Jun 04 03:03:02 PM PDT 24
Finished Jun 04 03:20:25 PM PDT 24
Peak memory 446752 kb
Host smart-7d3ab259-8406-487d-ab2b-ae61faf89df8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447110449 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.3447110449
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.856348921
Short name T940
Test name
Test status
Simulation time 64564144 ps
CPU time 1.89 seconds
Started Jun 04 02:59:39 PM PDT 24
Finished Jun 04 02:59:42 PM PDT 24
Peak memory 240800 kb
Host smart-2d946189-6c67-4f19-b87f-a194d5a1535e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856348921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.856348921
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.1870705362
Short name T619
Test name
Test status
Simulation time 2434670746 ps
CPU time 22.78 seconds
Started Jun 04 02:59:39 PM PDT 24
Finished Jun 04 03:00:03 PM PDT 24
Peak memory 242424 kb
Host smart-cc145a18-b981-4e88-80b6-62af7628e07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870705362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.1870705362
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.63313056
Short name T103
Test name
Test status
Simulation time 3963764538 ps
CPU time 34.49 seconds
Started Jun 04 02:59:41 PM PDT 24
Finished Jun 04 03:00:16 PM PDT 24
Peak memory 242484 kb
Host smart-d494cbfb-14d9-44b5-af1e-b3bf57266f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63313056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.63313056
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.3709901179
Short name T879
Test name
Test status
Simulation time 915752560 ps
CPU time 22.84 seconds
Started Jun 04 02:59:42 PM PDT 24
Finished Jun 04 03:00:06 PM PDT 24
Peak memory 242420 kb
Host smart-abf43cfe-1627-4d77-922c-a4b6f0d3a05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709901179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.3709901179
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.1052535863
Short name T565
Test name
Test status
Simulation time 13296801119 ps
CPU time 22.69 seconds
Started Jun 04 02:59:39 PM PDT 24
Finished Jun 04 03:00:03 PM PDT 24
Peak memory 242572 kb
Host smart-bae58e59-a9e9-4109-b07c-d1e74a1147c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052535863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.1052535863
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.2487477979
Short name T202
Test name
Test status
Simulation time 216874460 ps
CPU time 4.48 seconds
Started Jun 04 02:59:38 PM PDT 24
Finished Jun 04 02:59:43 PM PDT 24
Peak memory 242368 kb
Host smart-763e62af-640c-490d-bd7f-d43aa201c17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487477979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.2487477979
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.1368769053
Short name T475
Test name
Test status
Simulation time 1557632157 ps
CPU time 15.69 seconds
Started Jun 04 02:59:36 PM PDT 24
Finished Jun 04 02:59:52 PM PDT 24
Peak memory 248948 kb
Host smart-9d7123c9-44f3-46de-9a62-14ab1e909981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368769053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.1368769053
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.2798770978
Short name T554
Test name
Test status
Simulation time 3099801527 ps
CPU time 39.49 seconds
Started Jun 04 02:59:39 PM PDT 24
Finished Jun 04 03:00:19 PM PDT 24
Peak memory 242588 kb
Host smart-be7f1402-4ad3-43c9-be72-e0595d441139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798770978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.2798770978
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.914797205
Short name T99
Test name
Test status
Simulation time 160269120 ps
CPU time 4.2 seconds
Started Jun 04 02:59:41 PM PDT 24
Finished Jun 04 02:59:46 PM PDT 24
Peak memory 242272 kb
Host smart-8ac9fa26-5329-47b3-8ed0-bfb6253651aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914797205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.914797205
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.3528391448
Short name T780
Test name
Test status
Simulation time 7356956095 ps
CPU time 17.56 seconds
Started Jun 04 02:59:38 PM PDT 24
Finished Jun 04 02:59:56 PM PDT 24
Peak memory 242240 kb
Host smart-93ca3a52-b7e1-408a-a5b4-76c00b09556e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3528391448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.3528391448
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.1429441995
Short name T698
Test name
Test status
Simulation time 639395740 ps
CPU time 8.79 seconds
Started Jun 04 02:59:41 PM PDT 24
Finished Jun 04 02:59:51 PM PDT 24
Peak memory 242560 kb
Host smart-e7ca3ccb-0eee-4f9a-a882-ecb2744e947f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1429441995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.1429441995
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.2181625251
Short name T391
Test name
Test status
Simulation time 3140052290 ps
CPU time 9.24 seconds
Started Jun 04 02:59:39 PM PDT 24
Finished Jun 04 02:59:49 PM PDT 24
Peak memory 242292 kb
Host smart-b7785c5d-b170-4b56-85ea-09e1aa53fd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181625251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.2181625251
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.3321198376
Short name T381
Test name
Test status
Simulation time 133421316104 ps
CPU time 227.06 seconds
Started Jun 04 02:59:39 PM PDT 24
Finished Jun 04 03:03:27 PM PDT 24
Peak memory 265260 kb
Host smart-67667012-7668-47a9-bd51-7a015c89f81c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321198376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.
3321198376
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.289576300
Short name T298
Test name
Test status
Simulation time 57306885894 ps
CPU time 1494.48 seconds
Started Jun 04 02:59:40 PM PDT 24
Finished Jun 04 03:24:35 PM PDT 24
Peak memory 469604 kb
Host smart-693fa01c-b1c0-4d98-8765-ecc2f319574a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289576300 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.289576300
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.676620898
Short name T971
Test name
Test status
Simulation time 1013230291 ps
CPU time 36.06 seconds
Started Jun 04 02:59:39 PM PDT 24
Finished Jun 04 03:00:16 PM PDT 24
Peak memory 242476 kb
Host smart-8bb57410-7dcb-4b37-9693-265afc448ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676620898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.676620898
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.1540357526
Short name T212
Test name
Test status
Simulation time 601490029 ps
CPU time 4.96 seconds
Started Jun 04 03:03:02 PM PDT 24
Finished Jun 04 03:03:08 PM PDT 24
Peak memory 242712 kb
Host smart-960f52bb-209e-42ae-a1a7-4a994492254a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540357526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.1540357526
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.2120690621
Short name T241
Test name
Test status
Simulation time 2203969381 ps
CPU time 27.8 seconds
Started Jun 04 03:03:00 PM PDT 24
Finished Jun 04 03:03:29 PM PDT 24
Peak memory 242608 kb
Host smart-fdd186a3-800e-4385-a794-d3b746631d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120690621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.2120690621
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.1104556963
Short name T693
Test name
Test status
Simulation time 175021540811 ps
CPU time 1441.75 seconds
Started Jun 04 03:03:02 PM PDT 24
Finished Jun 04 03:27:05 PM PDT 24
Peak memory 363768 kb
Host smart-d67f2bb0-eb46-4746-956f-477fc2249967
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104556963 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.1104556963
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.1270143055
Short name T462
Test name
Test status
Simulation time 142910082 ps
CPU time 3.7 seconds
Started Jun 04 03:03:01 PM PDT 24
Finished Jun 04 03:03:06 PM PDT 24
Peak memory 242368 kb
Host smart-011ab06d-10a2-4ab9-9d4e-e3b1651047d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270143055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.1270143055
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.1974004319
Short name T751
Test name
Test status
Simulation time 2440265226 ps
CPU time 7.07 seconds
Started Jun 04 03:03:00 PM PDT 24
Finished Jun 04 03:03:09 PM PDT 24
Peak memory 242480 kb
Host smart-e858e41d-8d78-4814-b6b5-c08f84e82c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974004319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.1974004319
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.2879427800
Short name T308
Test name
Test status
Simulation time 194351278195 ps
CPU time 624.82 seconds
Started Jun 04 03:03:02 PM PDT 24
Finished Jun 04 03:13:29 PM PDT 24
Peak memory 318472 kb
Host smart-80273afa-359c-46d6-a66d-4844e2335c61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879427800 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.2879427800
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.997324214
Short name T623
Test name
Test status
Simulation time 575865547 ps
CPU time 4.07 seconds
Started Jun 04 03:03:03 PM PDT 24
Finished Jun 04 03:03:08 PM PDT 24
Peak memory 242576 kb
Host smart-659b7097-aad6-4615-a8ff-4b26310116cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997324214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.997324214
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.195755668
Short name T637
Test name
Test status
Simulation time 2403100756 ps
CPU time 22.35 seconds
Started Jun 04 03:03:04 PM PDT 24
Finished Jun 04 03:03:27 PM PDT 24
Peak memory 242644 kb
Host smart-baf4b5c1-5a03-4abf-9e4d-79317766fa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195755668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.195755668
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.3705027418
Short name T1018
Test name
Test status
Simulation time 561722151 ps
CPU time 4.07 seconds
Started Jun 04 03:03:01 PM PDT 24
Finished Jun 04 03:03:06 PM PDT 24
Peak memory 242716 kb
Host smart-41fabd66-d900-4fa1-ab60-9b328019e6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705027418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.3705027418
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.4152965558
Short name T445
Test name
Test status
Simulation time 157958071 ps
CPU time 4.07 seconds
Started Jun 04 03:02:59 PM PDT 24
Finished Jun 04 03:03:04 PM PDT 24
Peak memory 242132 kb
Host smart-69142323-720b-4857-904d-332f7625988e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152965558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.4152965558
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.765641659
Short name T702
Test name
Test status
Simulation time 453603186 ps
CPU time 3.59 seconds
Started Jun 04 03:03:02 PM PDT 24
Finished Jun 04 03:03:07 PM PDT 24
Peak memory 242324 kb
Host smart-7f229e73-638e-42b4-975b-47130cd5b461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765641659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.765641659
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.630285353
Short name T233
Test name
Test status
Simulation time 2221815660 ps
CPU time 5.26 seconds
Started Jun 04 03:03:01 PM PDT 24
Finished Jun 04 03:03:08 PM PDT 24
Peak memory 242208 kb
Host smart-149e8116-a0be-450e-8954-8804278d7295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630285353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.630285353
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.3901947804
Short name T1151
Test name
Test status
Simulation time 124546930202 ps
CPU time 1528.46 seconds
Started Jun 04 03:03:01 PM PDT 24
Finished Jun 04 03:28:32 PM PDT 24
Peak memory 323968 kb
Host smart-59a13b94-da2f-455c-aa24-9e6ed7d2b05e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901947804 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.3901947804
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.2577119721
Short name T538
Test name
Test status
Simulation time 116969459 ps
CPU time 3.3 seconds
Started Jun 04 03:03:03 PM PDT 24
Finished Jun 04 03:03:07 PM PDT 24
Peak memory 242360 kb
Host smart-cd7a314f-f4e4-43aa-9c2b-b886857e4169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577119721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.2577119721
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.3561829065
Short name T1103
Test name
Test status
Simulation time 1042547898 ps
CPU time 15.87 seconds
Started Jun 04 03:03:01 PM PDT 24
Finished Jun 04 03:03:18 PM PDT 24
Peak memory 242596 kb
Host smart-96a3d218-139b-41e7-9f97-cbe3ba3c951e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561829065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.3561829065
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.3755378289
Short name T268
Test name
Test status
Simulation time 480405736315 ps
CPU time 1740.03 seconds
Started Jun 04 03:03:01 PM PDT 24
Finished Jun 04 03:32:03 PM PDT 24
Peak memory 388448 kb
Host smart-be49b2fe-5680-4778-aa09-63e716b19b46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755378289 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.3755378289
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.2103179427
Short name T785
Test name
Test status
Simulation time 136416571 ps
CPU time 3.32 seconds
Started Jun 04 03:03:00 PM PDT 24
Finished Jun 04 03:03:05 PM PDT 24
Peak memory 242636 kb
Host smart-86cf4a8f-1f5d-4939-8e5c-80455ed3fde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103179427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.2103179427
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.2013344166
Short name T549
Test name
Test status
Simulation time 170593735 ps
CPU time 3.99 seconds
Started Jun 04 03:03:01 PM PDT 24
Finished Jun 04 03:03:07 PM PDT 24
Peak memory 242284 kb
Host smart-acd225d4-4f0b-41a6-8303-10d5282aa953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013344166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.2013344166
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.2484910711
Short name T823
Test name
Test status
Simulation time 299017794 ps
CPU time 3.64 seconds
Started Jun 04 03:03:03 PM PDT 24
Finished Jun 04 03:03:08 PM PDT 24
Peak memory 242716 kb
Host smart-808910f7-9db3-487f-80d6-4932ce2981c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484910711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.2484910711
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.3676606458
Short name T272
Test name
Test status
Simulation time 1054877275 ps
CPU time 16.18 seconds
Started Jun 04 03:03:13 PM PDT 24
Finished Jun 04 03:03:30 PM PDT 24
Peak memory 242588 kb
Host smart-d74bf2a9-80b6-4b85-a727-f9d31db03be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676606458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.3676606458
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.3248744819
Short name T909
Test name
Test status
Simulation time 1238293416442 ps
CPU time 2278.12 seconds
Started Jun 04 03:03:07 PM PDT 24
Finished Jun 04 03:41:07 PM PDT 24
Peak memory 398956 kb
Host smart-ff10564c-32c5-4846-af7e-788d3aba34ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248744819 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.3248744819
Directory /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.2867661189
Short name T587
Test name
Test status
Simulation time 124141471 ps
CPU time 4.42 seconds
Started Jun 04 03:03:07 PM PDT 24
Finished Jun 04 03:03:13 PM PDT 24
Peak memory 242336 kb
Host smart-5e9e6271-e489-4a7b-880f-542d43d6a9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867661189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.2867661189
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.1087896895
Short name T738
Test name
Test status
Simulation time 346834177 ps
CPU time 6.5 seconds
Started Jun 04 03:03:10 PM PDT 24
Finished Jun 04 03:03:17 PM PDT 24
Peak memory 242340 kb
Host smart-c183996c-9783-4dc4-887f-e33be259aea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087896895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.1087896895
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.3652832730
Short name T1190
Test name
Test status
Simulation time 50967681 ps
CPU time 1.84 seconds
Started Jun 04 02:59:46 PM PDT 24
Finished Jun 04 02:59:48 PM PDT 24
Peak memory 240836 kb
Host smart-7f75cb80-15f6-4fb3-b315-7546cef6a5b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652832730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.3652832730
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.862060396
Short name T109
Test name
Test status
Simulation time 6011539240 ps
CPU time 36.13 seconds
Started Jun 04 02:59:38 PM PDT 24
Finished Jun 04 03:00:15 PM PDT 24
Peak memory 242624 kb
Host smart-a789af25-23f3-4b99-b9ed-08208900acac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862060396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.862060396
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.1412927342
Short name T632
Test name
Test status
Simulation time 661158158 ps
CPU time 15.59 seconds
Started Jun 04 02:59:39 PM PDT 24
Finished Jun 04 02:59:56 PM PDT 24
Peak memory 242192 kb
Host smart-73ebe531-c168-49ac-9d9d-72bc713bb1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412927342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.1412927342
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.1859161679
Short name T459
Test name
Test status
Simulation time 2110031331 ps
CPU time 27.33 seconds
Started Jun 04 02:59:39 PM PDT 24
Finished Jun 04 03:00:07 PM PDT 24
Peak memory 242224 kb
Host smart-8f9b9b17-a5e6-463c-ae64-60dd44b46ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859161679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.1859161679
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.1176284643
Short name T784
Test name
Test status
Simulation time 103371638 ps
CPU time 3.99 seconds
Started Jun 04 02:59:39 PM PDT 24
Finished Jun 04 02:59:44 PM PDT 24
Peak memory 242436 kb
Host smart-1c320e7c-507f-4c05-975d-9f8b692bfe61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176284643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.1176284643
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.1939674361
Short name T707
Test name
Test status
Simulation time 11081781109 ps
CPU time 25.45 seconds
Started Jun 04 02:59:48 PM PDT 24
Finished Jun 04 03:00:14 PM PDT 24
Peak memory 244912 kb
Host smart-3bc35d53-6f7a-4d96-9010-0aac641cb248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939674361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.1939674361
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.1958301535
Short name T900
Test name
Test status
Simulation time 644802309 ps
CPU time 28.25 seconds
Started Jun 04 02:59:47 PM PDT 24
Finished Jun 04 03:00:16 PM PDT 24
Peak memory 242592 kb
Host smart-a01c8a94-201f-4120-8316-3be8273bf96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958301535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.1958301535
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.2669678449
Short name T1102
Test name
Test status
Simulation time 408533798 ps
CPU time 4.42 seconds
Started Jun 04 02:59:42 PM PDT 24
Finished Jun 04 02:59:47 PM PDT 24
Peak memory 242276 kb
Host smart-0167c288-c0da-4eaa-b4d7-00ae3477aeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669678449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.2669678449
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.998450090
Short name T564
Test name
Test status
Simulation time 1280959639 ps
CPU time 20.22 seconds
Started Jun 04 02:59:39 PM PDT 24
Finished Jun 04 03:00:01 PM PDT 24
Peak memory 242332 kb
Host smart-581ed7bc-438e-400e-b2d1-d63872b25033
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=998450090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.998450090
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.2853059885
Short name T938
Test name
Test status
Simulation time 4483007249 ps
CPU time 12.47 seconds
Started Jun 04 02:59:49 PM PDT 24
Finished Jun 04 03:00:02 PM PDT 24
Peak memory 248984 kb
Host smart-292ea525-c88a-4d45-9444-eaf5f6b12329
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2853059885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.2853059885
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.1343296039
Short name T420
Test name
Test status
Simulation time 1207522434 ps
CPU time 13.15 seconds
Started Jun 04 02:59:37 PM PDT 24
Finished Jun 04 02:59:51 PM PDT 24
Peak memory 242212 kb
Host smart-9f3416e1-738d-4c59-89bb-a43fc9e1fb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343296039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.1343296039
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.2769332231
Short name T294
Test name
Test status
Simulation time 1123104281727 ps
CPU time 2698.9 seconds
Started Jun 04 02:59:49 PM PDT 24
Finished Jun 04 03:44:49 PM PDT 24
Peak memory 298320 kb
Host smart-d39073a7-360f-4362-967d-1fc00983feca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769332231 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.2769332231
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.2521229650
Short name T824
Test name
Test status
Simulation time 1055104977 ps
CPU time 27.33 seconds
Started Jun 04 02:59:49 PM PDT 24
Finished Jun 04 03:00:17 PM PDT 24
Peak memory 242752 kb
Host smart-9bfa811a-18ae-4a7c-b4a3-0eccf49aa001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521229650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2521229650
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.619773433
Short name T905
Test name
Test status
Simulation time 304201853 ps
CPU time 4.35 seconds
Started Jun 04 03:03:08 PM PDT 24
Finished Jun 04 03:03:13 PM PDT 24
Peak memory 242416 kb
Host smart-4ba81fc2-bde2-4032-abec-90485d71b480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619773433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.619773433
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.746339443
Short name T962
Test name
Test status
Simulation time 431108737 ps
CPU time 6.66 seconds
Started Jun 04 03:03:08 PM PDT 24
Finished Jun 04 03:03:16 PM PDT 24
Peak memory 242304 kb
Host smart-096f7804-b503-47ce-9663-a29e7e6c9ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746339443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.746339443
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.1176178605
Short name T906
Test name
Test status
Simulation time 535514873172 ps
CPU time 1320.44 seconds
Started Jun 04 03:03:08 PM PDT 24
Finished Jun 04 03:25:10 PM PDT 24
Peak memory 331144 kb
Host smart-88f05195-8170-4783-b5e6-8a89a8dcdb14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176178605 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.1176178605
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.803042176
Short name T955
Test name
Test status
Simulation time 442107738 ps
CPU time 3.17 seconds
Started Jun 04 03:03:11 PM PDT 24
Finished Jun 04 03:03:15 PM PDT 24
Peak memory 242320 kb
Host smart-0ddfdf2f-4da5-4f95-b601-07f0028a7409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803042176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.803042176
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.1644266993
Short name T859
Test name
Test status
Simulation time 151678027 ps
CPU time 7.61 seconds
Started Jun 04 03:03:11 PM PDT 24
Finished Jun 04 03:03:19 PM PDT 24
Peak memory 242588 kb
Host smart-c37f58a7-8465-40f7-852d-8bfa512b3b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644266993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.1644266993
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.2901864440
Short name T1179
Test name
Test status
Simulation time 100491932812 ps
CPU time 1461.13 seconds
Started Jun 04 03:03:12 PM PDT 24
Finished Jun 04 03:27:34 PM PDT 24
Peak memory 260792 kb
Host smart-737bf807-bd0d-41c3-8389-ac90a3d1e811
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901864440 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.2901864440
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.2099559998
Short name T566
Test name
Test status
Simulation time 2163677655 ps
CPU time 5.05 seconds
Started Jun 04 03:03:10 PM PDT 24
Finished Jun 04 03:03:16 PM PDT 24
Peak memory 242460 kb
Host smart-9d5a1b78-5d81-4c26-9925-5232e51a3dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099559998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.2099559998
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.3680762049
Short name T119
Test name
Test status
Simulation time 2711794709 ps
CPU time 7.05 seconds
Started Jun 04 03:03:09 PM PDT 24
Finished Jun 04 03:03:17 PM PDT 24
Peak memory 242356 kb
Host smart-f2e29427-226e-4d45-9d46-83eab0340211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680762049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.3680762049
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.366318710
Short name T950
Test name
Test status
Simulation time 19021702585 ps
CPU time 265.43 seconds
Started Jun 04 03:03:11 PM PDT 24
Finished Jun 04 03:07:38 PM PDT 24
Peak memory 257224 kb
Host smart-ed39ccab-7c63-4022-af5a-4bd81ac55c1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366318710 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.366318710
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.1399528722
Short name T757
Test name
Test status
Simulation time 463077277 ps
CPU time 4.84 seconds
Started Jun 04 03:03:12 PM PDT 24
Finished Jun 04 03:03:18 PM PDT 24
Peak memory 242356 kb
Host smart-fcfef21f-0a77-4163-bfdb-62348d983f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399528722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.1399528722
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.345974862
Short name T731
Test name
Test status
Simulation time 972090479 ps
CPU time 25.24 seconds
Started Jun 04 03:03:09 PM PDT 24
Finished Jun 04 03:03:36 PM PDT 24
Peak memory 242268 kb
Host smart-73004173-77cb-4e2f-b533-d8f8619af46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345974862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.345974862
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.556002615
Short name T597
Test name
Test status
Simulation time 52672584223 ps
CPU time 700.19 seconds
Started Jun 04 03:03:11 PM PDT 24
Finished Jun 04 03:14:52 PM PDT 24
Peak memory 275512 kb
Host smart-981bbb29-3cfa-45bb-8c81-7490dc69e0fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556002615 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.556002615
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.3811725454
Short name T845
Test name
Test status
Simulation time 282455017 ps
CPU time 3.79 seconds
Started Jun 04 03:03:11 PM PDT 24
Finished Jun 04 03:03:15 PM PDT 24
Peak memory 242456 kb
Host smart-6d24a298-066e-4250-bc85-0e85257165b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811725454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.3811725454
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.1310623009
Short name T7
Test name
Test status
Simulation time 17065242398 ps
CPU time 298.47 seconds
Started Jun 04 03:03:11 PM PDT 24
Finished Jun 04 03:08:11 PM PDT 24
Peak memory 306748 kb
Host smart-73eda730-dd79-4608-ae24-917d632c7ca0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310623009 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.1310623009
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.1824226998
Short name T149
Test name
Test status
Simulation time 466030992 ps
CPU time 4.07 seconds
Started Jun 04 03:03:11 PM PDT 24
Finished Jun 04 03:03:16 PM PDT 24
Peak memory 242488 kb
Host smart-4ebaa7d9-0f2e-4f22-b4be-d42defe27e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824226998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.1824226998
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.3679069572
Short name T228
Test name
Test status
Simulation time 438266705 ps
CPU time 5.2 seconds
Started Jun 04 03:03:13 PM PDT 24
Finished Jun 04 03:03:19 PM PDT 24
Peak memory 242592 kb
Host smart-dbd73837-cd2c-4ec9-bbd6-28ac4c26d265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679069572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.3679069572
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.3818919349
Short name T803
Test name
Test status
Simulation time 122118663107 ps
CPU time 401.04 seconds
Started Jun 04 03:03:10 PM PDT 24
Finished Jun 04 03:09:52 PM PDT 24
Peak memory 262472 kb
Host smart-af50a962-75a2-4079-9bca-7170975f8da8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818919349 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.3818919349
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.2413535324
Short name T945
Test name
Test status
Simulation time 283043208 ps
CPU time 4.13 seconds
Started Jun 04 03:03:09 PM PDT 24
Finished Jun 04 03:03:14 PM PDT 24
Peak memory 242392 kb
Host smart-94e70c74-a386-44d2-944a-dfc3514a0597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413535324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.2413535324
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.2437545432
Short name T1201
Test name
Test status
Simulation time 13170373238 ps
CPU time 25.95 seconds
Started Jun 04 03:03:10 PM PDT 24
Finished Jun 04 03:03:37 PM PDT 24
Peak memory 242420 kb
Host smart-51162f12-41ea-4df4-8e1c-1afa6efbc703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437545432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.2437545432
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.2528022052
Short name T258
Test name
Test status
Simulation time 136343450415 ps
CPU time 2195.35 seconds
Started Jun 04 03:03:08 PM PDT 24
Finished Jun 04 03:39:44 PM PDT 24
Peak memory 324364 kb
Host smart-4df7cb24-68a9-47b8-beb0-5d689d683968
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528022052 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.2528022052
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.1366420001
Short name T492
Test name
Test status
Simulation time 195163725 ps
CPU time 3.8 seconds
Started Jun 04 03:03:09 PM PDT 24
Finished Jun 04 03:03:14 PM PDT 24
Peak memory 242372 kb
Host smart-14bb6e93-17d3-4d5e-bbab-a81c484b234a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366420001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.1366420001
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.3137298739
Short name T601
Test name
Test status
Simulation time 523839856 ps
CPU time 7.33 seconds
Started Jun 04 03:03:10 PM PDT 24
Finished Jun 04 03:03:18 PM PDT 24
Peak memory 242504 kb
Host smart-e0d9bda3-c41e-47e3-86fe-f7b95a7c26bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137298739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.3137298739
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.2780744875
Short name T1037
Test name
Test status
Simulation time 120497653125 ps
CPU time 2040.71 seconds
Started Jun 04 03:03:08 PM PDT 24
Finished Jun 04 03:37:10 PM PDT 24
Peak memory 314664 kb
Host smart-adf0a1bc-7ce5-44b3-9428-171cbd615402
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780744875 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.2780744875
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.2903788142
Short name T74
Test name
Test status
Simulation time 2512050044 ps
CPU time 6.77 seconds
Started Jun 04 03:03:09 PM PDT 24
Finished Jun 04 03:03:17 PM PDT 24
Peak memory 242416 kb
Host smart-11aba5e9-0a59-4192-8460-7c84959a8e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903788142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.2903788142
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.2076733131
Short name T977
Test name
Test status
Simulation time 119734149 ps
CPU time 5.31 seconds
Started Jun 04 03:03:09 PM PDT 24
Finished Jun 04 03:03:15 PM PDT 24
Peak memory 242336 kb
Host smart-c428fec8-10fa-4d17-95b7-f961fe65a7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076733131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.2076733131
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.2018082476
Short name T717
Test name
Test status
Simulation time 18674347975 ps
CPU time 169.97 seconds
Started Jun 04 03:03:10 PM PDT 24
Finished Jun 04 03:06:01 PM PDT 24
Peak memory 257308 kb
Host smart-e7aceb2e-3956-4004-a1ae-114ad2da877d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018082476 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.2018082476
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.1325027707
Short name T168
Test name
Test status
Simulation time 648210938 ps
CPU time 4.24 seconds
Started Jun 04 03:03:11 PM PDT 24
Finished Jun 04 03:03:16 PM PDT 24
Peak memory 242380 kb
Host smart-ca3d0af0-89c0-49d1-a242-75c45a2e7106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325027707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.1325027707
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.236457186
Short name T1149
Test name
Test status
Simulation time 526704245 ps
CPU time 12.38 seconds
Started Jun 04 03:03:20 PM PDT 24
Finished Jun 04 03:03:34 PM PDT 24
Peak memory 242320 kb
Host smart-03256889-4c3f-4024-8bc6-b840dc691fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236457186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.236457186
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.207158688
Short name T716
Test name
Test status
Simulation time 124545425585 ps
CPU time 634.35 seconds
Started Jun 04 03:03:19 PM PDT 24
Finished Jun 04 03:13:55 PM PDT 24
Peak memory 265252 kb
Host smart-d5a150e9-fef7-46ab-aa17-5fab989b2c05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207158688 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.207158688
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.3434018697
Short name T1005
Test name
Test status
Simulation time 226775679 ps
CPU time 2 seconds
Started Jun 04 02:59:50 PM PDT 24
Finished Jun 04 02:59:53 PM PDT 24
Peak memory 240872 kb
Host smart-60a77ff6-91a5-4c8a-920a-4c0b9ce26bdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434018697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.3434018697
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.1974613993
Short name T509
Test name
Test status
Simulation time 4993416904 ps
CPU time 34.2 seconds
Started Jun 04 02:59:50 PM PDT 24
Finished Jun 04 03:00:25 PM PDT 24
Peak memory 242624 kb
Host smart-4d3136ae-3f5d-4319-87e9-da48b216a6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974613993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.1974613993
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.340709870
Short name T81
Test name
Test status
Simulation time 5586139419 ps
CPU time 11.39 seconds
Started Jun 04 02:59:50 PM PDT 24
Finished Jun 04 03:00:02 PM PDT 24
Peak memory 242404 kb
Host smart-5f76a919-f36c-4cbc-a4ce-fc5c43c8fa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340709870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.340709870
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.1922966374
Short name T569
Test name
Test status
Simulation time 368389514 ps
CPU time 17.19 seconds
Started Jun 04 02:59:49 PM PDT 24
Finished Jun 04 03:00:07 PM PDT 24
Peak memory 242240 kb
Host smart-0c252a41-3c75-4999-8261-195a8fd7c3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922966374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.1922966374
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.452980107
Short name T804
Test name
Test status
Simulation time 13213755550 ps
CPU time 24.78 seconds
Started Jun 04 02:59:49 PM PDT 24
Finished Jun 04 03:00:14 PM PDT 24
Peak memory 242292 kb
Host smart-c579b17e-a365-43bc-b889-e99a9a03f72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452980107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.452980107
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.2410397796
Short name T787
Test name
Test status
Simulation time 305526510 ps
CPU time 4.43 seconds
Started Jun 04 02:59:50 PM PDT 24
Finished Jun 04 02:59:55 PM PDT 24
Peak memory 242576 kb
Host smart-1730287e-54e3-41b0-b737-f7ac79ecd613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410397796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.2410397796
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.764282690
Short name T663
Test name
Test status
Simulation time 2824527967 ps
CPU time 20.1 seconds
Started Jun 04 02:59:54 PM PDT 24
Finished Jun 04 03:00:14 PM PDT 24
Peak memory 243536 kb
Host smart-5ffb7267-8484-4a3a-ad90-8a259f1b9bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764282690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.764282690
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.3219625219
Short name T1180
Test name
Test status
Simulation time 605114772 ps
CPU time 14.2 seconds
Started Jun 04 02:59:50 PM PDT 24
Finished Jun 04 03:00:05 PM PDT 24
Peak memory 242268 kb
Host smart-562b9e8b-b0f6-480e-bbe3-279f517b04fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219625219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.3219625219
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.4238367301
Short name T820
Test name
Test status
Simulation time 640372251 ps
CPU time 8.53 seconds
Started Jun 04 02:59:50 PM PDT 24
Finished Jun 04 03:00:00 PM PDT 24
Peak memory 242372 kb
Host smart-1a054818-6fe8-4aec-834a-eeb632d649d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238367301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.4238367301
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.2314457830
Short name T208
Test name
Test status
Simulation time 1463759383 ps
CPU time 11.85 seconds
Started Jun 04 02:59:50 PM PDT 24
Finished Jun 04 03:00:03 PM PDT 24
Peak memory 242248 kb
Host smart-f11aad26-d3e4-4c08-8a3a-70b7275cb11b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2314457830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.2314457830
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.2879833976
Short name T943
Test name
Test status
Simulation time 195624955 ps
CPU time 4.85 seconds
Started Jun 04 02:59:47 PM PDT 24
Finished Jun 04 02:59:52 PM PDT 24
Peak memory 242568 kb
Host smart-d12a3b5c-8a0d-43af-b692-1b7360250a9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2879833976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.2879833976
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.1921314933
Short name T741
Test name
Test status
Simulation time 647554706 ps
CPU time 6.28 seconds
Started Jun 04 02:59:47 PM PDT 24
Finished Jun 04 02:59:54 PM PDT 24
Peak memory 248596 kb
Host smart-0a508d37-190b-4bd0-b921-1db725a7e171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921314933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.1921314933
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.1221431282
Short name T802
Test name
Test status
Simulation time 21186835371 ps
CPU time 195.45 seconds
Started Jun 04 02:59:49 PM PDT 24
Finished Jun 04 03:03:05 PM PDT 24
Peak memory 260464 kb
Host smart-8f262868-85f0-4ba8-95e1-ba163fedf5f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221431282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.
1221431282
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.3212734114
Short name T430
Test name
Test status
Simulation time 2864095635 ps
CPU time 17.56 seconds
Started Jun 04 02:59:47 PM PDT 24
Finished Jun 04 03:00:06 PM PDT 24
Peak memory 242600 kb
Host smart-2dc1b206-340e-4862-a38c-f33031e734f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212734114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.3212734114
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.2358772070
Short name T621
Test name
Test status
Simulation time 488830362 ps
CPU time 3.72 seconds
Started Jun 04 03:03:18 PM PDT 24
Finished Jun 04 03:03:23 PM PDT 24
Peak memory 242364 kb
Host smart-640f1fa9-852d-4b11-b673-e9a78f4c005c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358772070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.2358772070
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.4046119350
Short name T239
Test name
Test status
Simulation time 230142644 ps
CPU time 7.3 seconds
Started Jun 04 03:03:18 PM PDT 24
Finished Jun 04 03:03:27 PM PDT 24
Peak memory 242116 kb
Host smart-d866bcb1-da15-47c2-8c3d-54b0c1418876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046119350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.4046119350
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.3363952305
Short name T340
Test name
Test status
Simulation time 469861784290 ps
CPU time 978.11 seconds
Started Jun 04 03:03:20 PM PDT 24
Finished Jun 04 03:19:40 PM PDT 24
Peak memory 366300 kb
Host smart-c3765efb-c363-4d97-8070-c2c80f536312
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363952305 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.3363952305
Directory /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.3514812516
Short name T1173
Test name
Test status
Simulation time 464027937 ps
CPU time 12.42 seconds
Started Jun 04 03:03:19 PM PDT 24
Finished Jun 04 03:03:33 PM PDT 24
Peak memory 242540 kb
Host smart-53f2101e-58d1-4f7f-ae80-7e614e05fb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514812516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.3514812516
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.2953747907
Short name T229
Test name
Test status
Simulation time 53788368317 ps
CPU time 903.9 seconds
Started Jun 04 03:03:18 PM PDT 24
Finished Jun 04 03:18:23 PM PDT 24
Peak memory 399072 kb
Host smart-d8e25919-c696-4b02-af00-d155b92cfb5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953747907 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.2953747907
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.3356287559
Short name T951
Test name
Test status
Simulation time 513591879 ps
CPU time 3.78 seconds
Started Jun 04 03:03:22 PM PDT 24
Finished Jun 04 03:03:27 PM PDT 24
Peak memory 242636 kb
Host smart-bf2f1835-6cda-46b7-abe1-38940ba1beba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356287559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.3356287559
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.3593747705
Short name T1001
Test name
Test status
Simulation time 10033229214 ps
CPU time 22.17 seconds
Started Jun 04 03:03:17 PM PDT 24
Finished Jun 04 03:03:41 PM PDT 24
Peak memory 242676 kb
Host smart-b08dc073-bf30-4060-95d2-e8ba81d480da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593747705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.3593747705
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.3428107366
Short name T1171
Test name
Test status
Simulation time 310395709668 ps
CPU time 2808.44 seconds
Started Jun 04 03:03:16 PM PDT 24
Finished Jun 04 03:50:06 PM PDT 24
Peak memory 352404 kb
Host smart-15386f7e-02d5-4755-8de8-5ac8d1754fba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428107366 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.3428107366
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.1775650674
Short name T166
Test name
Test status
Simulation time 2166422750 ps
CPU time 5.81 seconds
Started Jun 04 03:03:20 PM PDT 24
Finished Jun 04 03:03:27 PM PDT 24
Peak memory 242448 kb
Host smart-1d617b48-ba83-4b3a-8a79-89eda7fd06e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775650674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.1775650674
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.237367790
Short name T402
Test name
Test status
Simulation time 1573571060 ps
CPU time 14.94 seconds
Started Jun 04 03:03:20 PM PDT 24
Finished Jun 04 03:03:36 PM PDT 24
Peak memory 242628 kb
Host smart-298787e3-fbf9-4dd7-9de0-e826e359807c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237367790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.237367790
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.3539407767
Short name T338
Test name
Test status
Simulation time 456656712984 ps
CPU time 3186.08 seconds
Started Jun 04 03:03:19 PM PDT 24
Finished Jun 04 03:56:27 PM PDT 24
Peak memory 636512 kb
Host smart-bf9c5e73-224f-4823-92d2-6b1d91a113c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539407767 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.3539407767
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.1825092038
Short name T582
Test name
Test status
Simulation time 637158337 ps
CPU time 4.64 seconds
Started Jun 04 03:03:22 PM PDT 24
Finished Jun 04 03:03:27 PM PDT 24
Peak memory 242312 kb
Host smart-8e190250-485f-4aab-8cfb-f1244e8b9665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825092038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.1825092038
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.1465144257
Short name T273
Test name
Test status
Simulation time 1073240394 ps
CPU time 8.86 seconds
Started Jun 04 03:03:17 PM PDT 24
Finished Jun 04 03:03:27 PM PDT 24
Peak memory 247624 kb
Host smart-039b1284-9bb6-4249-8ae9-f29cc930e307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465144257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.1465144257
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.2806552853
Short name T1148
Test name
Test status
Simulation time 363215385604 ps
CPU time 1693.64 seconds
Started Jun 04 03:03:21 PM PDT 24
Finished Jun 04 03:31:36 PM PDT 24
Peak memory 415792 kb
Host smart-2bd6ad4a-efbc-4be9-a36f-744ac6218ac5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806552853 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.2806552853
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.4153209708
Short name T535
Test name
Test status
Simulation time 90875946 ps
CPU time 3.29 seconds
Started Jun 04 03:03:19 PM PDT 24
Finished Jun 04 03:03:24 PM PDT 24
Peak memory 242744 kb
Host smart-52552e43-8f8a-4c96-9422-21fc6541cdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153209708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.4153209708
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.3867003094
Short name T1162
Test name
Test status
Simulation time 401509143 ps
CPU time 9.77 seconds
Started Jun 04 03:03:18 PM PDT 24
Finished Jun 04 03:03:30 PM PDT 24
Peak memory 242232 kb
Host smart-cee2d81d-00d8-40fd-82a2-5eef7c589ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867003094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.3867003094
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.353357895
Short name T547
Test name
Test status
Simulation time 63674181026 ps
CPU time 630.05 seconds
Started Jun 04 03:03:18 PM PDT 24
Finished Jun 04 03:13:49 PM PDT 24
Peak memory 261132 kb
Host smart-d0701e3f-11fe-4ac7-a4fc-ed4b06452331
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353357895 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.353357895
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.116593256
Short name T1043
Test name
Test status
Simulation time 487975339 ps
CPU time 3.84 seconds
Started Jun 04 03:03:22 PM PDT 24
Finished Jun 04 03:03:27 PM PDT 24
Peak memory 242628 kb
Host smart-3435292e-e58e-4e69-a2b9-72b2d71dbec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116593256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.116593256
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.1081242433
Short name T1184
Test name
Test status
Simulation time 180783250 ps
CPU time 4.83 seconds
Started Jun 04 03:03:18 PM PDT 24
Finished Jun 04 03:03:25 PM PDT 24
Peak memory 242208 kb
Host smart-26d6cf95-b248-41f0-ac6b-d62daa238806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081242433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.1081242433
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.1847955594
Short name T300
Test name
Test status
Simulation time 243795911084 ps
CPU time 1489.84 seconds
Started Jun 04 03:03:20 PM PDT 24
Finished Jun 04 03:28:11 PM PDT 24
Peak memory 390660 kb
Host smart-c3d29312-7de0-4e0a-beca-8fe6bbe8c593
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847955594 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.1847955594
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.4289991088
Short name T456
Test name
Test status
Simulation time 267780417 ps
CPU time 4.52 seconds
Started Jun 04 03:03:18 PM PDT 24
Finished Jun 04 03:03:25 PM PDT 24
Peak memory 242288 kb
Host smart-382c706e-b6c9-481b-9a74-27eb84dfc502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289991088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.4289991088
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.1185145497
Short name T760
Test name
Test status
Simulation time 1342994052 ps
CPU time 17.44 seconds
Started Jun 04 03:03:18 PM PDT 24
Finished Jun 04 03:03:36 PM PDT 24
Peak memory 242520 kb
Host smart-2b3c97b7-0ba6-47c8-929f-0e6219ae7c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185145497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.1185145497
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.2228357023
Short name T203
Test name
Test status
Simulation time 722122340 ps
CPU time 4.76 seconds
Started Jun 04 03:03:20 PM PDT 24
Finished Jun 04 03:03:26 PM PDT 24
Peak memory 242260 kb
Host smart-9c804175-3bb8-46bd-a691-e5847f513056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228357023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.2228357023
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.2314808717
Short name T126
Test name
Test status
Simulation time 218822534 ps
CPU time 2.97 seconds
Started Jun 04 03:03:20 PM PDT 24
Finished Jun 04 03:03:24 PM PDT 24
Peak memory 242288 kb
Host smart-0f32ca8f-3fc5-476a-860b-803c26876c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314808717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.2314808717
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.817977315
Short name T924
Test name
Test status
Simulation time 788866068377 ps
CPU time 2939.21 seconds
Started Jun 04 03:03:32 PM PDT 24
Finished Jun 04 03:52:32 PM PDT 24
Peak memory 553788 kb
Host smart-15292b04-6ca8-4a3d-901b-63cf51aa4ba1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817977315 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.817977315
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.1725111412
Short name T45
Test name
Test status
Simulation time 526665304 ps
CPU time 4.1 seconds
Started Jun 04 03:03:19 PM PDT 24
Finished Jun 04 03:03:25 PM PDT 24
Peak memory 242668 kb
Host smart-fe6d74ea-4fdb-4716-8535-5d862015d3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725111412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.1725111412
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.3259300024
Short name T681
Test name
Test status
Simulation time 2760680704 ps
CPU time 9.72 seconds
Started Jun 04 03:03:18 PM PDT 24
Finished Jun 04 03:03:29 PM PDT 24
Peak memory 242320 kb
Host smart-2e6f7da8-8912-488f-a6d7-6f2a3124440c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259300024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.3259300024
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.187768240
Short name T344
Test name
Test status
Simulation time 133660191440 ps
CPU time 1133.85 seconds
Started Jun 04 03:03:28 PM PDT 24
Finished Jun 04 03:22:23 PM PDT 24
Peak memory 381904 kb
Host smart-5815d97d-ac78-4026-8e53-82d959ef2e53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187768240 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.187768240
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.797828310
Short name T1144
Test name
Test status
Simulation time 353102969 ps
CPU time 4.1 seconds
Started Jun 04 03:00:01 PM PDT 24
Finished Jun 04 03:00:06 PM PDT 24
Peak memory 241120 kb
Host smart-7d4dade7-ea25-4dd0-9278-46ac5fa466f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797828310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.797828310
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.1766921068
Short name T655
Test name
Test status
Simulation time 960806994 ps
CPU time 9.8 seconds
Started Jun 04 02:59:50 PM PDT 24
Finished Jun 04 03:00:00 PM PDT 24
Peak memory 242296 kb
Host smart-7270d7a2-5262-4d13-bb6c-e5a50b1ac095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766921068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.1766921068
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.618388834
Short name T1002
Test name
Test status
Simulation time 198168270 ps
CPU time 6.71 seconds
Started Jun 04 03:00:00 PM PDT 24
Finished Jun 04 03:00:07 PM PDT 24
Peak memory 248976 kb
Host smart-61816ced-f061-4cca-89fa-c76eaf39f09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618388834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.618388834
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.1548176271
Short name T407
Test name
Test status
Simulation time 8490141312 ps
CPU time 21.28 seconds
Started Jun 04 02:59:48 PM PDT 24
Finished Jun 04 03:00:10 PM PDT 24
Peak memory 242540 kb
Host smart-1786fe69-3cae-4c53-a373-2575dacb71b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548176271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.1548176271
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.3714018826
Short name T933
Test name
Test status
Simulation time 2497290248 ps
CPU time 29.12 seconds
Started Jun 04 02:59:50 PM PDT 24
Finished Jun 04 03:00:20 PM PDT 24
Peak memory 242476 kb
Host smart-ab976ec8-aa6e-4c28-bb60-0b5066eaa46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714018826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.3714018826
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.289812302
Short name T526
Test name
Test status
Simulation time 3168758390 ps
CPU time 23 seconds
Started Jun 04 02:59:59 PM PDT 24
Finished Jun 04 03:00:22 PM PDT 24
Peak memory 244160 kb
Host smart-dee17789-df20-49c3-8e30-e4125f9e24f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289812302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.289812302
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.3151178191
Short name T480
Test name
Test status
Simulation time 739008818 ps
CPU time 31.02 seconds
Started Jun 04 02:59:59 PM PDT 24
Finished Jun 04 03:00:31 PM PDT 24
Peak memory 242576 kb
Host smart-8fc1d004-d1b1-4256-bde4-3ed5f66079d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151178191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.3151178191
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.1788377042
Short name T1079
Test name
Test status
Simulation time 525503709 ps
CPU time 13.23 seconds
Started Jun 04 02:59:51 PM PDT 24
Finished Jun 04 03:00:05 PM PDT 24
Peak memory 242524 kb
Host smart-59dd4f2c-13aa-48cf-8ec1-99160f8f2385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788377042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.1788377042
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.3709635437
Short name T860
Test name
Test status
Simulation time 10798884884 ps
CPU time 24.42 seconds
Started Jun 04 02:59:50 PM PDT 24
Finished Jun 04 03:00:15 PM PDT 24
Peak memory 242388 kb
Host smart-a51e84ec-0b6c-464d-ad4d-a44492e6e718
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3709635437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.3709635437
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.3633907508
Short name T797
Test name
Test status
Simulation time 158112539 ps
CPU time 5.65 seconds
Started Jun 04 02:59:59 PM PDT 24
Finished Jun 04 03:00:05 PM PDT 24
Peak memory 242320 kb
Host smart-ef9d8d58-2fdd-4ca4-a1f9-a41ddf6ecef2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3633907508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.3633907508
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.58006054
Short name T648
Test name
Test status
Simulation time 374867133 ps
CPU time 6.99 seconds
Started Jun 04 02:59:51 PM PDT 24
Finished Jun 04 02:59:58 PM PDT 24
Peak memory 242152 kb
Host smart-ff99ca0c-4edd-406a-87ad-b9a2405ea63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58006054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.58006054
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.1362841456
Short name T339
Test name
Test status
Simulation time 170192856518 ps
CPU time 1219.32 seconds
Started Jun 04 03:00:02 PM PDT 24
Finished Jun 04 03:20:23 PM PDT 24
Peak memory 393948 kb
Host smart-5956e6a5-9949-480f-92eb-015e51159d0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362841456 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.1362841456
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.1347316990
Short name T899
Test name
Test status
Simulation time 3002507943 ps
CPU time 16.6 seconds
Started Jun 04 03:00:01 PM PDT 24
Finished Jun 04 03:00:19 PM PDT 24
Peak memory 242600 kb
Host smart-d7229d78-f7d2-41e9-8375-e94b82a3fbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347316990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.1347316990
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.965863561
Short name T796
Test name
Test status
Simulation time 214359389 ps
CPU time 3.56 seconds
Started Jun 04 03:03:30 PM PDT 24
Finished Jun 04 03:03:34 PM PDT 24
Peak memory 242660 kb
Host smart-c666ff82-c5a0-4962-ba9f-0467f204af66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965863561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.965863561
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.3890448941
Short name T309
Test name
Test status
Simulation time 173361558 ps
CPU time 8.86 seconds
Started Jun 04 03:03:27 PM PDT 24
Finished Jun 04 03:03:37 PM PDT 24
Peak memory 242080 kb
Host smart-8a5856fa-5ccc-4081-bfce-387c60be829f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890448941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.3890448941
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.233796182
Short name T389
Test name
Test status
Simulation time 129416534419 ps
CPU time 2999.72 seconds
Started Jun 04 03:03:27 PM PDT 24
Finished Jun 04 03:53:29 PM PDT 24
Peak memory 363860 kb
Host smart-032a8fcb-6541-46a2-a1a3-6e998483977d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233796182 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.233796182
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.3465592302
Short name T882
Test name
Test status
Simulation time 152730302 ps
CPU time 4.09 seconds
Started Jun 04 03:03:29 PM PDT 24
Finished Jun 04 03:03:35 PM PDT 24
Peak memory 242536 kb
Host smart-b5378acb-b256-4820-836e-18f05eaaf610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465592302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.3465592302
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.1964732903
Short name T641
Test name
Test status
Simulation time 110820962 ps
CPU time 3.37 seconds
Started Jun 04 03:03:26 PM PDT 24
Finished Jun 04 03:03:30 PM PDT 24
Peak memory 242116 kb
Host smart-85e63cca-d861-44ff-a64e-f2228653fd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964732903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.1964732903
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.1445934994
Short name T64
Test name
Test status
Simulation time 55849716863 ps
CPU time 453.01 seconds
Started Jun 04 03:03:26 PM PDT 24
Finished Jun 04 03:11:00 PM PDT 24
Peak memory 281824 kb
Host smart-1b50776c-1564-451a-b7fa-9195c3817e13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445934994 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.1445934994
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.2384905442
Short name T478
Test name
Test status
Simulation time 126138196 ps
CPU time 3.12 seconds
Started Jun 04 03:03:28 PM PDT 24
Finished Jun 04 03:03:32 PM PDT 24
Peak memory 242376 kb
Host smart-78f59df1-db1f-4a9d-adcc-5ab6812c7f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384905442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.2384905442
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.2636454865
Short name T542
Test name
Test status
Simulation time 253130667 ps
CPU time 6.4 seconds
Started Jun 04 03:03:29 PM PDT 24
Finished Jun 04 03:03:36 PM PDT 24
Peak memory 242528 kb
Host smart-5b6bfea6-f6ae-45ff-83ac-2f36cde76e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636454865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.2636454865
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.3924749520
Short name T16
Test name
Test status
Simulation time 70299530614 ps
CPU time 1247.67 seconds
Started Jun 04 03:03:28 PM PDT 24
Finished Jun 04 03:24:17 PM PDT 24
Peak memory 393280 kb
Host smart-3e7190d3-ffd1-4f85-9422-83fb5ff8cf7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924749520 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.3924749520
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.2233678313
Short name T715
Test name
Test status
Simulation time 1434775964 ps
CPU time 3.91 seconds
Started Jun 04 03:03:29 PM PDT 24
Finished Jun 04 03:03:34 PM PDT 24
Peak memory 242284 kb
Host smart-a1719836-6387-407a-8e74-0c48317367b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233678313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.2233678313
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.2037751881
Short name T931
Test name
Test status
Simulation time 1359297627 ps
CPU time 35.12 seconds
Started Jun 04 03:03:29 PM PDT 24
Finished Jun 04 03:04:05 PM PDT 24
Peak memory 242720 kb
Host smart-d2204dcb-2201-4723-91de-81b84a78bd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037751881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.2037751881
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.3792275070
Short name T704
Test name
Test status
Simulation time 164100313432 ps
CPU time 424.58 seconds
Started Jun 04 03:03:29 PM PDT 24
Finished Jun 04 03:10:35 PM PDT 24
Peak memory 314152 kb
Host smart-7e7da18c-17cc-4bf1-838a-58b3890bdc76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792275070 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.3792275070
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.1848964745
Short name T85
Test name
Test status
Simulation time 411107980 ps
CPU time 3.99 seconds
Started Jun 04 03:03:27 PM PDT 24
Finished Jun 04 03:03:32 PM PDT 24
Peak memory 242728 kb
Host smart-89bfa879-5df5-4b9d-b81a-778243a5f964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848964745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.1848964745
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.2022198304
Short name T70
Test name
Test status
Simulation time 519125815 ps
CPU time 14.39 seconds
Started Jun 04 03:03:28 PM PDT 24
Finished Jun 04 03:03:44 PM PDT 24
Peak memory 242212 kb
Host smart-b990dc3b-ebea-4b54-a621-356134cabade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022198304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.2022198304
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.1707804337
Short name T948
Test name
Test status
Simulation time 881262716920 ps
CPU time 1440.55 seconds
Started Jun 04 03:03:30 PM PDT 24
Finished Jun 04 03:27:32 PM PDT 24
Peak memory 313560 kb
Host smart-aa69e0e0-27df-43dd-bb0d-319c090cad3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707804337 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.1707804337
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.2184126669
Short name T1182
Test name
Test status
Simulation time 143907860 ps
CPU time 4.29 seconds
Started Jun 04 03:03:28 PM PDT 24
Finished Jun 04 03:03:33 PM PDT 24
Peak memory 242344 kb
Host smart-26c61e67-f4aa-444e-a0a1-cca0bfd777a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184126669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.2184126669
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.4053647754
Short name T1130
Test name
Test status
Simulation time 5797083468 ps
CPU time 20.93 seconds
Started Jun 04 03:03:30 PM PDT 24
Finished Jun 04 03:03:52 PM PDT 24
Peak memory 242264 kb
Host smart-26585657-d867-48bd-81bf-db47f5b31481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053647754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.4053647754
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.1826925314
Short name T1088
Test name
Test status
Simulation time 147230517 ps
CPU time 4.15 seconds
Started Jun 04 03:03:27 PM PDT 24
Finished Jun 04 03:03:33 PM PDT 24
Peak memory 242436 kb
Host smart-817d27a5-2d70-4c07-bb67-e99ea87a22dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826925314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.1826925314
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.1518749156
Short name T1017
Test name
Test status
Simulation time 381357690 ps
CPU time 4.83 seconds
Started Jun 04 03:03:26 PM PDT 24
Finished Jun 04 03:03:32 PM PDT 24
Peak memory 242264 kb
Host smart-b03a2d13-8ea8-4032-92f8-a815d5c1da6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518749156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.1518749156
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.889958489
Short name T1066
Test name
Test status
Simulation time 799772184503 ps
CPU time 2012.29 seconds
Started Jun 04 03:03:27 PM PDT 24
Finished Jun 04 03:37:01 PM PDT 24
Peak memory 265512 kb
Host smart-ab166191-a69b-406e-8e6d-cab72526bccb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889958489 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.889958489
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.2063331416
Short name T52
Test name
Test status
Simulation time 353469222 ps
CPU time 4.2 seconds
Started Jun 04 03:03:27 PM PDT 24
Finished Jun 04 03:03:32 PM PDT 24
Peak memory 242396 kb
Host smart-10e0ea50-af90-473c-be4a-476c586260a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063331416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.2063331416
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.2018153367
Short name T150
Test name
Test status
Simulation time 492334835 ps
CPU time 6.68 seconds
Started Jun 04 03:03:33 PM PDT 24
Finished Jun 04 03:03:40 PM PDT 24
Peak memory 242564 kb
Host smart-e538e488-4375-4993-8ee9-37e08af7875b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018153367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.2018153367
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.2854592512
Short name T244
Test name
Test status
Simulation time 34900816062 ps
CPU time 404.14 seconds
Started Jun 04 03:03:27 PM PDT 24
Finished Jun 04 03:10:13 PM PDT 24
Peak memory 265512 kb
Host smart-1de32d45-fa5d-4518-9254-d0fcb05b10f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854592512 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.2854592512
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.4188413047
Short name T579
Test name
Test status
Simulation time 250262620 ps
CPU time 3.67 seconds
Started Jun 04 03:03:29 PM PDT 24
Finished Jun 04 03:03:34 PM PDT 24
Peak memory 242484 kb
Host smart-6ce8f365-bb7e-4262-b43c-d6fe9c32f01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188413047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.4188413047
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.3178532455
Short name T896
Test name
Test status
Simulation time 366778543 ps
CPU time 15.96 seconds
Started Jun 04 03:03:27 PM PDT 24
Finished Jun 04 03:03:45 PM PDT 24
Peak memory 242180 kb
Host smart-2b9af04d-6996-402d-b59d-b717cf161e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178532455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.3178532455
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.1719325748
Short name T151
Test name
Test status
Simulation time 153046159231 ps
CPU time 2709.49 seconds
Started Jun 04 03:03:27 PM PDT 24
Finished Jun 04 03:48:38 PM PDT 24
Peak memory 315504 kb
Host smart-bf7dfc5b-558b-4f9d-b708-f1ee2ae1044b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719325748 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.1719325748
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.1923268220
Short name T595
Test name
Test status
Simulation time 339963355 ps
CPU time 3.73 seconds
Started Jun 04 03:03:28 PM PDT 24
Finished Jun 04 03:03:33 PM PDT 24
Peak memory 242672 kb
Host smart-c0c7cd03-51f8-4454-80f1-60b2e87b926e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923268220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.1923268220
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.3844996126
Short name T342
Test name
Test status
Simulation time 219286153 ps
CPU time 2.97 seconds
Started Jun 04 03:03:25 PM PDT 24
Finished Jun 04 03:03:29 PM PDT 24
Peak memory 242532 kb
Host smart-fc239765-59c6-4838-ad0e-452706b4a1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844996126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.3844996126
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.1452281183
Short name T18
Test name
Test status
Simulation time 29888031545 ps
CPU time 380.87 seconds
Started Jun 04 03:03:26 PM PDT 24
Finished Jun 04 03:09:48 PM PDT 24
Peak memory 257312 kb
Host smart-80489665-b6de-43d3-beba-b9a8d57ded16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452281183 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.1452281183
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
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