Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
sram_0_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
sram_0_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
sram_0_req_during_lc_esc	2	0	2	100.00	100	1	1	0
sram_0_req_during_otbn_req	2	0	2	100.00	100	1	1	2
sram_0_req_during_otp_idle	2	0	2	100.00	100	1	1	2
sram_0_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable sram_0_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_0_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12149

1

T1

8

T2

2

T4

134

auto[1]

703

1

T4

22

T5

6

T101

5

---

Summary for Variable sram_0_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_0_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12087

1

T1

8

T2

2

T4

136

auto[1]

765

1

T4

20

T5

2

T101

2

---

Summary for Variable sram_0_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sram_0_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

12817

1

T1

8

T2

2

T4

156

lc_esc_on

35

1

T216

1

T16

1

T395

1

---

Summary for Variable sram_0_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_0_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12086

1

T1

8

T2

2

T4

134

auto[1]

766

1

T4

22

T5

2

T101

3

---

Summary for Variable sram_0_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_0_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1995

1

T4

10

T5

7

T10

7

auto[1]

10857

1

T1

8

T2

2

T4

146

---

Summary for Variable sram_0_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_0_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10677

1

T1

4

T2

1

T4

81

auto[1]

2175

1

T1

4

T2

1

T4

75