Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
176917 |
1 |
|
|
T1 |
48 |
|
T2 |
39 |
|
T3 |
48 |
all_pins[1] |
176917 |
1 |
|
|
T1 |
48 |
|
T2 |
39 |
|
T3 |
48 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
295567 |
1 |
|
|
T1 |
80 |
|
T2 |
40 |
|
T3 |
48 |
values[0x1] |
58267 |
1 |
|
|
T1 |
16 |
|
T2 |
38 |
|
T3 |
48 |
transitions[0x0=>0x1] |
42893 |
1 |
|
|
T1 |
16 |
|
T2 |
38 |
|
T3 |
48 |
transitions[0x1=>0x0] |
42816 |
1 |
|
|
T1 |
16 |
|
T2 |
38 |
|
T3 |
47 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
134711 |
1 |
|
|
T1 |
38 |
|
T2 |
1 |
|
T4 |
944 |
all_pins[0] |
values[0x1] |
42206 |
1 |
|
|
T1 |
10 |
|
T2 |
38 |
|
T3 |
48 |
all_pins[0] |
transitions[0x0=>0x1] |
34573 |
1 |
|
|
T1 |
10 |
|
T2 |
38 |
|
T3 |
48 |
all_pins[0] |
transitions[0x1=>0x0] |
8428 |
1 |
|
|
T1 |
6 |
|
T4 |
109 |
|
T5 |
22 |
all_pins[1] |
values[0x0] |
160856 |
1 |
|
|
T1 |
42 |
|
T2 |
39 |
|
T3 |
48 |
all_pins[1] |
values[0x1] |
16061 |
1 |
|
|
T1 |
6 |
|
T4 |
197 |
|
T5 |
46 |
all_pins[1] |
transitions[0x0=>0x1] |
8320 |
1 |
|
|
T1 |
6 |
|
T4 |
108 |
|
T5 |
22 |
all_pins[1] |
transitions[0x1=>0x0] |
34388 |
1 |
|
|
T1 |
10 |
|
T2 |
38 |
|
T3 |
47 |