SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 47678 | 1 | T1 | 17 | T9 | 21 | T12 | 39 | ||||
access_err | 60483 | 1 | T1 | 13 | T2 | 10 | T4 | 577 | ||||
write_blank_err | 460 | 1 | T4 | 11 | T6 | 1 | T13 | 1 | ||||
ecc_uncorr_err | 70673 | 1 | T4 | 754 | T12 | 121 | T6 | 499 | ||||
ecc_corr_err | 1283 | 1 | T1 | 1 | T12 | 2 | T129 | 1 | ||||
no_err | 90786 | 1 | T1 | 15 | T2 | 34 | T4 | 734 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 828 | 1 | T4 | 15 | T6 | 6 | T13 | 16 | ||||
secret2 | 23602 | 1 | T1 | 3 | T2 | 3 | T4 | 133 | ||||
secret1 | 28244 | 1 | T1 | 1 | T2 | 4 | T4 | 106 | ||||
secret0 | 36954 | 1 | T1 | 10 | T2 | 5 | T4 | 101 | ||||
hw_cfg1 | 40606 | 1 | T1 | 5 | T2 | 3 | T4 | 661 | ||||
hw_cfg0 | 24473 | 1 | T2 | 9 | T4 | 320 | T5 | 19 | ||||
rot_creator_auth_state | 21970 | 1 | T4 | 122 | T5 | 24 | T9 | 2 | ||||
rot_creator_auth_codesign | 20720 | 1 | T2 | 4 | T4 | 160 | T5 | 29 | ||||
owner_sw_cfg | 20669 | 1 | T2 | 6 | T4 | 162 | T5 | 28 | ||||
creator_sw_cfg | 21553 | 1 | T1 | 2 | T2 | 5 | T4 | 146 | ||||
vendor_test | 31744 | 1 | T1 | 25 | T2 | 5 | T4 | 150 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 2414 | 1 | T177 | 1 | T218 | 166 | T63 | 210 | ||||
fsm_err | secret1 | 3882 | 1 | T215 | 256 | T139 | 6 | T17 | 165 | ||||
fsm_err | secret0 | 3219 | 1 | T153 | 54 | T135 | 344 | T142 | 60 | ||||
fsm_err | hw_cfg1 | 4980 | 1 | T216 | 401 | T136 | 226 | T334 | 137 | ||||
fsm_err | hw_cfg0 | 4939 | 1 | T188 | 392 | T335 | 141 | T336 | 237 | ||||
fsm_err | rot_creator_auth_state | 3031 | 1 | T12 | 18 | T89 | 44 | T241 | 45 | ||||
fsm_err | rot_creator_auth_codesign | 3278 | 1 | T337 | 202 | T245 | 161 | T89 | 49 | ||||
fsm_err | owner_sw_cfg | 3459 | 1 | T12 | 21 | T176 | 34 | T192 | 61 | ||||
fsm_err | creator_sw_cfg | 3993 | 1 | T244 | 411 | T338 | 135 | T134 | 439 | ||||
fsm_err | vendor_test | 14483 | 1 | T1 | 17 | T9 | 21 | T45 | 136 | ||||
access_err | life_cycle | 828 | 1 | T4 | 15 | T6 | 6 | T13 | 16 | ||||
access_err | secret2 | 10723 | 1 | T1 | 2 | T4 | 70 | T5 | 28 | ||||
access_err | secret1 | 5585 | 1 | T1 | 1 | T2 | 2 | T4 | 56 | ||||
access_err | secret0 | 4403 | 1 | T1 | 8 | T2 | 2 | T4 | 57 | ||||
access_err | hw_cfg1 | 1268 | 1 | T1 | 2 | T2 | 1 | T4 | 15 | ||||
access_err | hw_cfg0 | 2036 | 1 | T2 | 4 | T4 | 21 | T5 | 6 | ||||
access_err | rot_creator_auth_state | 5841 | 1 | T4 | 66 | T5 | 7 | T10 | 1 | ||||
access_err | rot_creator_auth_codesign | 7752 | 1 | T4 | 65 | T5 | 9 | T10 | 2 | ||||
access_err | owner_sw_cfg | 6901 | 1 | T4 | 46 | T5 | 21 | T10 | 3 | ||||
access_err | creator_sw_cfg | 7927 | 1 | T2 | 1 | T4 | 82 | T5 | 8 | ||||
access_err | vendor_test | 7219 | 1 | T4 | 84 | T5 | 9 | T10 | 3 | ||||
write_blank_err | secret2 | 13 | 1 | T14 | 1 | T339 | 1 | T198 | 1 | ||||
write_blank_err | secret1 | 26 | 1 | T6 | 1 | T13 | 1 | T16 | 1 | ||||
write_blank_err | secret0 | 58 | 1 | T16 | 1 | T66 | 1 | T338 | 1 | ||||
write_blank_err | hw_cfg1 | 74 | 1 | T4 | 2 | T132 | 1 | T157 | 1 | ||||
write_blank_err | hw_cfg0 | 17 | 1 | T4 | 1 | T340 | 1 | T341 | 1 | ||||
write_blank_err | rot_creator_auth_state | 162 | 1 | T4 | 6 | T14 | 8 | T16 | 2 | ||||
write_blank_err | rot_creator_auth_codesign | 53 | 1 | T14 | 3 | T16 | 3 | T338 | 4 | ||||
write_blank_err | owner_sw_cfg | 15 | 1 | T4 | 1 | T198 | 3 | T342 | 1 | ||||
write_blank_err | creator_sw_cfg | 12 | 1 | T211 | 1 | T343 | 1 | T344 | 1 | ||||
write_blank_err | vendor_test | 30 | 1 | T4 | 1 | T14 | 1 | T338 | 1 | ||||
ecc_uncorr_err | secret2 | 5118 | 1 | T12 | 18 | T14 | 396 | T89 | 46 | ||||
ecc_uncorr_err | secret1 | 9533 | 1 | T6 | 499 | T129 | 62 | T13 | 467 | ||||
ecc_uncorr_err | secret0 | 20533 | 1 | T16 | 673 | T156 | 39 | T66 | 95 | ||||
ecc_uncorr_err | hw_cfg1 | 23279 | 1 | T4 | 559 | T132 | 87 | T157 | 294 | ||||
ecc_uncorr_err | hw_cfg0 | 5171 | 1 | T4 | 195 | T12 | 22 | T89 | 44 | ||||
ecc_uncorr_err | rot_creator_auth_state | 4399 | 1 | T217 | 198 | T153 | 57 | T166 | 7 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 681 | 1 | T129 | 72 | T166 | 5 | T89 | 48 | ||||
ecc_uncorr_err | owner_sw_cfg | 860 | 1 | T12 | 44 | T156 | 38 | T195 | 56 | ||||
ecc_uncorr_err | creator_sw_cfg | 1099 | 1 | T12 | 37 | T89 | 51 | T199 | 10 | ||||
ecc_corr_err | secret2 | 68 | 1 | T38 | 2 | T345 | 1 | T346 | 5 | ||||
ecc_corr_err | secret1 | 131 | 1 | T129 | 1 | T45 | 2 | T105 | 1 | ||||
ecc_corr_err | secret0 | 93 | 1 | T153 | 3 | T345 | 1 | T347 | 1 | ||||
ecc_corr_err | hw_cfg1 | 302 | 1 | T1 | 1 | T45 | 9 | T105 | 11 | ||||
ecc_corr_err | hw_cfg0 | 270 | 1 | T45 | 10 | T105 | 2 | T38 | 5 | ||||
ecc_corr_err | rot_creator_auth_state | 94 | 1 | T45 | 1 | T105 | 2 | T38 | 2 | ||||
ecc_corr_err | rot_creator_auth_codesign | 107 | 1 | T12 | 1 | T105 | 1 | T38 | 12 | ||||
ecc_corr_err | owner_sw_cfg | 103 | 1 | T12 | 1 | T105 | 2 | T38 | 5 | ||||
ecc_corr_err | creator_sw_cfg | 115 | 1 | T45 | 3 | T105 | 5 | T38 | 8 | ||||
no_err | secret2 | 5266 | 1 | T1 | 1 | T2 | 3 | T4 | 63 | ||||
no_err | secret1 | 9087 | 1 | T2 | 2 | T4 | 50 | T5 | 5 | ||||
no_err | secret0 | 8648 | 1 | T1 | 2 | T2 | 3 | T4 | 44 | ||||
no_err | hw_cfg1 | 10703 | 1 | T1 | 2 | T2 | 2 | T4 | 85 | ||||
no_err | hw_cfg0 | 12040 | 1 | T2 | 5 | T4 | 103 | T5 | 13 | ||||
no_err | rot_creator_auth_state | 8443 | 1 | T4 | 50 | T5 | 17 | T9 | 2 | ||||
no_err | rot_creator_auth_codesign | 8849 | 1 | T2 | 4 | T4 | 95 | T5 | 20 | ||||
no_err | owner_sw_cfg | 9331 | 1 | T2 | 6 | T4 | 115 | T5 | 7 | ||||
no_err | creator_sw_cfg | 8407 | 1 | T1 | 2 | T2 | 4 | T4 | 64 | ||||
no_err | vendor_test | 10012 | 1 | T1 | 8 | T2 | 5 | T4 | 65 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |