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Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 14039 1 T1 4 T2 20 T3 32


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 14039 1 T1 4 T2 20 T3 32


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 10042 1 T1 2 T2 12 T3 23
true 16380 1 T1 4 T2 20 T3 34


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 10926 1 T1 2 T2 14 T3 25
true 16440 1 T1 4 T2 20 T3 34


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 100 1 T59 2 T192 2 T412 2
others[1] 128 1 T26 2 T91 2 T98 2
others[2] 108 1 T2 2 T59 2 T300 2
others[3] 94 1 T3 2 T91 2 T94 2
others[4] 60 1 T2 2 T92 2 T413 2
others[5] 96 1 T26 2 T68 2 T95 2
others[6] 54 1 T3 2 T26 2 T91 2
others[7] 116 1 T2 2 T3 2 T4 2
false 14039 1 T1 4 T2 20 T3 32


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 76 1 T93 2 T95 2 T190 2
others[1] 80 1 T2 2 T51 2 T300 4
others[2] 96 1 T92 2 T101 2 T234 2
others[3] 78 1 T65 2 T93 2 T223 2
others[4] 96 1 T3 2 T26 2 T96 2
others[5] 84 1 T3 2 T98 2 T191 2
others[6] 94 1 T91 2 T97 2 T101 2
others[7] 100 1 T3 2 T99 2 T235 2
false 14039 1 T1 4 T2 20 T3 32


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 80 1 T26 2 T91 2 T92 2
others[1] 68 1 T26 2 T65 2 T192 2
others[2] 104 1 T2 2 T9 2 T93 4
others[3] 92 1 T9 2 T12 2 T26 2
others[4] 98 1 T26 2 T96 2 T76 2
others[5] 74 1 T101 2 T223 2 T51 2
others[6] 98 1 T223 2 T300 2 T192 2
others[7] 100 1 T26 2 T96 2 T193 4
false 14039 1 T1 4 T2 20 T3 32


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 60 1 T51 2 T192 2 T193 2
others[1] 46 1 T414 4 T205 2 T413 2
others[2] 58 1 T415 2 T205 2 T416 2
others[3] 40 1 T192 2 T413 2 T417 2
others[4] 56 1 T92 2 T211 2 T415 2
others[5] 52 1 T91 2 T415 2 T418 2
others[6] 48 1 T91 2 T190 2 T195 2
others[7] 60 1 T191 2 T193 2 T194 2
false 14039 1 T1 4 T2 20 T3 32


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 64 1 T192 2 T413 2 T43 2
others[1] 92 1 T2 2 T99 2 T192 2
others[2] 76 1 T98 2 T416 4 T419 2
others[3] 68 1 T92 2 T98 2 T101 2
others[4] 98 1 T59 2 T95 2 T99 2
others[5] 82 1 T96 2 T223 2 T302 2
others[6] 94 1 T96 4 T99 2 T51 2
others[7] 108 1 T95 2 T101 4 T224 2
false 14039 1 T1 4 T2 20 T3 32


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 34 1 T26 2 T99 2 T61 2
others[1] 38 1 T96 2 T101 4 T224 2
others[2] 50 1 T26 4 T59 2 T236 2
others[3] 44 1 T99 2 T224 2 T236 2
others[4] 30 1 T96 2 T236 2 T420 2
others[5] 46 1 T96 2 T235 2 T420 2
others[6] 32 1 T258 2 T120 2 T421 2
others[7] 46 1 T98 2 T234 2 T422 2
false 14039 1 T1 4 T2 20 T3 32


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 96 1 T91 2 T59 2 T101 2
others[1] 76 1 T234 2 T236 2 T195 4
others[2] 100 1 T92 4 T93 2 T94 2
others[3] 104 1 T300 2 T235 2 T236 4
others[4] 80 1 T26 2 T93 2 T101 2
others[5] 80 1 T224 2 T192 2 T236 4
others[6] 86 1 T3 2 T224 2 T302 2
others[7] 116 1 T12 2 T95 2 T101 4
false 14039 1 T1 4 T2 20 T3 32


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 88 1 T101 4 T300 2 T302 2
others[1] 108 1 T101 2 T51 2 T423 2
others[2] 94 1 T92 2 T235 2 T236 6
others[3] 106 1 T98 2 T93 2 T95 2
others[4] 118 1 T95 2 T101 2 T224 2
others[5] 76 1 T59 2 T97 2 T223 2
others[6] 94 1 T3 2 T26 2 T59 2
others[7] 116 1 T3 2 T12 2 T26 2
false 14039 1 T1 4 T2 20 T3 32


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 82 1 T2 2 T300 2 T302 2
others[1] 90 1 T3 2 T91 2 T96 2
others[2] 88 1 T3 2 T26 2 T93 2
others[3] 106 1 T101 2 T223 2 T301 2
others[4] 106 1 T2 2 T26 2 T235 2
others[5] 102 1 T191 2 T193 2 T236 2
others[6] 94 1 T2 2 T4 2 T95 2
others[7] 114 1 T2 2 T26 2 T91 2
false 14039 1 T1 4 T2 20 T3 32


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 100 1 T4 2 T234 2 T300 2
others[1] 70 1 T2 2 T65 2 T59 2
others[2] 94 1 T2 2 T95 2 T51 2
others[3] 110 1 T3 2 T92 2 T99 2
others[4] 98 1 T2 2 T91 2 T93 2
others[5] 64 1 T101 2 T300 4 T302 2
others[6] 92 1 T3 2 T4 2 T96 2
others[7] 122 1 T91 2 T101 2 T193 2
false 14039 1 T1 4 T2 20 T3 32


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 68 1 T26 2 T190 2 T97 2
others[1] 76 1 T94 2 T97 2 T223 2
others[2] 104 1 T2 2 T3 2 T99 2
others[3] 96 1 T3 2 T26 2 T101 4
others[4] 100 1 T96 2 T224 2 T424 2
others[5] 58 1 T101 2 T425 2 T414 2
others[6] 86 1 T26 2 T92 2 T94 2
others[7] 128 1 T2 2 T101 2 T191 2
false 14039 1 T1 4 T2 20 T3 32


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 35 1 T5 1 T139 1 T113 2
others[1] 20 1 T5 1 T139 2 T422 2
others[2] 40 1 T5 1 T6 1 T113 1
others[3] 31 1 T5 2 T6 2 T111 1
others[4] 33 1 T13 1 T113 1 T111 1
others[5] 31 1 T6 1 T266 2 T155 2
others[6] 24 1 T5 2 T16 1 T137 1
others[7] 25 1 T5 3 T94 2 T270 1
false 14039 1 T1 4 T2 20 T3 32
true 2197 1 T2 8 T3 6 T4 2


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 29 1 T5 3 T139 1 T113 1
others[1] 31 1 T5 1 T113 1 T137 1
others[2] 31 1 T6 2 T270 1 T267 1
others[3] 33 1 T5 2 T13 1 T255 1
others[4] 25 1 T5 2 T6 1 T254 1
others[5] 31 1 T5 1 T139 1 T94 2
others[6] 31 1 T5 1 T111 2 T266 2
others[7] 28 1 T6 1 T16 1 T139 1
false 11425 1 T1 3 T2 16 T3 25
true 18613 1 T1 5 T2 28 T3 39


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 76 1 T91 4 T235 2 T425 2
others[1] 110 1 T2 2 T3 2 T193 2
others[2] 76 1 T3 2 T26 2 T96 2
others[3] 104 1 T3 2 T26 2 T68 2
others[4] 96 1 T4 2 T59 2 T101 2
others[5] 88 1 T91 2 T92 2 T101 2
others[6] 102 1 T2 2 T95 2 T190 2
others[7] 104 1 T2 2 T26 2 T59 2
false 7753 1 T1 3 T2 2 T3 13
true 16492 1 T1 5 T2 20 T3 34


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 92 1 T3 4 T26 2 T92 2
others[1] 88 1 T65 2 T99 2 T234 2
others[2] 100 1 T98 2 T93 2 T101 2
others[3] 66 1 T91 2 T101 2 T235 2
others[4] 82 1 T96 2 T101 2 T223 2
others[5] 96 1 T93 2 T101 2 T191 2
others[6] 80 1 T2 2 T101 2 T412 2
others[7] 100 1 T3 2 T95 2 T190 2
false 6815 1 T1 2 T2 3 T3 9
true 16265 1 T1 4 T2 20 T3 34


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 100 1 T26 2 T101 2 T223 2
others[1] 96 1 T2 2 T26 2 T93 2
others[2] 90 1 T26 4 T234 2 T300 4
others[3] 76 1 T65 2 T93 2 T95 2
others[4] 72 1 T26 2 T192 2 T422 2
others[5] 84 1 T91 2 T92 2 T93 2
others[6] 92 1 T9 4 T93 2 T96 2
others[7] 104 1 T12 2 T192 2 T325 2
false 7252 1 T1 2 T2 4 T3 10
true 16284 1 T1 4 T2 20 T3 34


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 24 1 T5 1 T13 1 T139 2
others[1] 23 1 T5 1 T16 1 T113 1
others[2] 18 1 T6 1 T113 1 T111 1
others[3] 43 1 T6 1 T111 1 T254 2
others[4] 30 1 T5 1 T16 1 T113 2
others[5] 23 1 T6 1 T113 2 T239 1
others[6] 26 1 T5 1 T101 2 T137 2
others[7] 37 1 T5 3 T13 1 T139 1
false 11358 1 T1 3 T2 15 T3 25
true 18572 1 T1 5 T2 25 T3 40


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 46 1 T191 2 T415 2 T155 2
others[1] 52 1 T51 2 T192 2 T194 2
others[2] 60 1 T92 2 T414 2 T258 4
others[3] 48 1 T91 4 T415 2 T416 2
others[4] 66 1 T193 2 T414 2 T418 2
others[5] 38 1 T192 2 T415 2 T414 2
others[6] 56 1 T193 2 T415 4 T414 2
others[7] 54 1 T190 2 T211 2 T414 4
false 9080 1 T1 3 T2 15 T3 14
true 16491 1 T1 5 T2 20 T3 34


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 28 1 T266 1 T270 1 T422 2
others[1] 38 1 T5 1 T6 1 T113 2
others[2] 23 1 T5 1 T59 2 T111 1
others[3] 39 1 T2 2 T5 1 T113 1
others[4] 42 1 T5 3 T6 1 T139 1
others[5] 25 1 T224 2 T270 1 T256 2
others[6] 30 1 T5 3 T6 1 T16 1
others[7] 33 1 T139 1 T59 2 T267 1
false 11309 1 T1 3 T2 14 T3 25
true 18569 1 T1 5 T2 27 T3 38


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 78 1 T96 2 T415 2 T418 2
others[1] 86 1 T98 2 T99 2 T101 2
others[2] 58 1 T98 2 T95 2 T99 2
others[3] 92 1 T2 2 T95 2 T235 2
others[4] 98 1 T92 2 T300 2 T302 2
others[5] 96 1 T96 2 T99 2 T223 2
others[6] 66 1 T96 2 T101 2 T300 2
others[7] 108 1 T59 2 T224 2 T51 2
false 7767 1 T1 3 T2 2 T3 13
true 16424 1 T1 5 T2 20 T3 34


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 38 1 T2 2 T5 2 T13 1
others[1] 30 1 T5 2 T139 1 T113 2
others[2] 24 1 T16 1 T139 1 T113 1
others[3] 30 1 T5 2 T26 2 T6 1
others[4] 28 1 T5 2 T139 1 T113 3
others[5] 29 1 T5 3 T224 2 T51 2
others[6] 23 1 T2 2 T16 1 T139 1
others[7] 32 1 T113 2 T266 1 T267 1
false 11267 1 T1 3 T2 14 T3 25
true 18460 1 T1 5 T2 27 T3 38


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 38 1 T98 2 T99 2 T234 2
others[1] 36 1 T26 2 T99 2 T236 2
others[2] 38 1 T96 2 T101 2 T422 2
others[3] 48 1 T59 2 T224 2 T36 2
others[4] 30 1 T26 2 T224 2 T420 2
others[5] 40 1 T101 2 T234 2 T235 2
others[6] 36 1 T96 2 T420 2 T242 2
others[7] 54 1 T26 2 T96 2 T235 2
false 9636 1 T1 3 T2 2 T3 24
true 16454 1 T1 5 T2 20 T3 34


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 94 1 T92 2 T93 2 T234 2
others[1] 86 1 T101 2 T224 2 T144 2
others[2] 96 1 T12 2 T93 2 T235 2
others[3] 96 1 T59 2 T101 4 T424 2
others[4] 94 1 T26 2 T92 2 T94 2
others[5] 80 1 T95 2 T236 2 T325 2
others[6] 88 1 T97 2 T301 2 T236 2
others[7] 104 1 T3 2 T91 2 T300 2
false 6977 1 T1 2 T2 12 T3 9
true 16262 1 T1 4 T2 20 T3 34


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 98 1 T59 2 T97 2 T223 2
others[1] 80 1 T12 2 T26 2 T101 2
others[2] 114 1 T26 2 T93 2 T302 2
others[3] 94 1 T3 2 T95 2 T97 2
others[4] 96 1 T95 2 T97 2 T51 2
others[5] 94 1 T92 2 T101 2 T224 4
others[6] 94 1 T59 2 T223 2 T300 2
others[7] 130 1 T3 2 T98 2 T99 2
false 6977 1 T1 2 T2 12 T3 9
true 16262 1 T1 4 T2 20 T3 34


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T91 2 T144 2 T300 2
others[1] 98 1 T3 2 T91 2 T93 2
others[2] 116 1 T2 2 T59 2 T97 2
others[3] 76 1 T2 2 T101 2 T301 2
others[4] 110 1 T2 2 T26 2 T302 2
others[5] 74 1 T96 2 T300 2 T236 2
others[6] 106 1 T3 2 T4 2 T26 4
others[7] 112 1 T2 2 T92 2 T95 2
false 6328 1 T1 1 T2 2 T3 7
true 16250 1 T1 4 T2 20 T3 34


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 100 1 T92 2 T96 4 T99 2
others[1] 72 1 T59 2 T93 2 T51 2
others[2] 68 1 T101 2 T300 2 T301 2
others[3] 90 1 T2 4 T101 2 T300 2
others[4] 80 1 T3 2 T91 2 T420 2
others[5] 92 1 T51 2 T302 2 T36 2
others[6] 136 1 T2 2 T3 2 T4 4
others[7] 112 1 T91 2 T95 2 T101 4
false 6328 1 T1 1 T2 2 T3 7
true 16250 1 T1 4 T2 20 T3 34


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 66 1 T98 2 T93 4 T223 2
others[1] 68 1 T26 2 T92 2 T235 2
others[2] 66 1 T2 2 T93 2 T94 2
others[3] 70 1 T234 2 T272 2 T209 2
others[4] 54 1 T93 2 T101 2 T51 2
others[5] 74 1 T4 2 T26 2 T101 2
others[6] 90 1 T92 2 T101 2 T223 2
others[7] 94 1 T3 2 T4 2 T26 2
false 6767 1 T1 1 T2 1 T3 14
true 17549 1 T1 4 T2 20 T3 43


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 66 1 T2 2 T92 2 T101 2
others[1] 70 1 T91 2 T101 2 T235 2
others[2] 56 1 T2 2 T26 2 T101 2
others[3] 66 1 T2 2 T91 2 T101 4
others[4] 68 1 T65 2 T101 2 T300 2
others[5] 58 1 T92 2 T93 2 T223 2
others[6] 74 1 T97 2 T51 2 T192 2
others[7] 76 1 T26 4 T98 2 T101 2
false 6767 1 T1 1 T2 1 T3 14
true 17549 1 T1 4 T2 20 T3 43


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 29 1 T139 1 T113 2 T111 2
others[1] 28 1 T5 1 T13 2 T139 1
others[2] 35 1 T5 3 T113 1 T254 1
others[3] 30 1 T5 2 T6 1 T13 1
others[4] 35 1 T5 2 T96 2 T137 1
others[5] 43 1 T5 2 T6 1 T13 1
others[6] 36 1 T139 1 T113 1 T137 1
others[7] 38 1 T5 1 T13 1 T139 1
false 11504 1 T1 3 T2 16 T3 25
true 18725 1 T1 5 T2 28 T3 38


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 112 1 T2 4 T26 4 T94 2
others[1] 112 1 T3 2 T94 2 T101 2
others[2] 74 1 T236 2 T155 2 T426 2
others[3] 62 1 T96 2 T97 2 T427 2
others[4] 80 1 T3 2 T97 2 T101 2
others[5] 86 1 T26 2 T101 2 T223 2
others[6] 76 1 T96 2 T99 2 T101 2
others[7] 114 1 T92 2 T190 2 T300 2
false 7754 1 T1 3 T2 2 T3 13
true 16447 1 T1 5 T2 20 T3 34


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 41 1 T5 1 T13 1 T113 2
others[1] 24 1 T6 1 T16 1 T113 1
others[2] 23 1 T5 2 T113 1 T137 2
others[3] 33 1 T5 1 T16 1 T113 2
others[4] 26 1 T137 1 T368 1 T17 1
others[5] 28 1 T113 2 T367 1 T323 1
others[6] 13 1 T5 1 T13 1 T139 1
others[7] 37 1 T5 2 T6 2 T139 2
false 14039 1 T1 4 T2 20 T3 32
true 2209 1 T2 5 T3 6 T4 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%