Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	2	0	2	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	8	0	8	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr_pin

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_pins[0]

163198

1

T1

73

T2

171

T3

446

all_pins[1]

163198

1

T1

73

T2

171

T3

446

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	267812	1			T1	146		T2	249		T3	756
values[0x1]	58584	1			T2	93		T3	136		T4	48
transitions[0x0=>0x1]	43145	1			T2	46		T3	96		T4	28
transitions[0x1=>0x0]	43079	1			T2	46		T3	96		T4	28

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	120804	1			T1	73		T2	119		T3	341
all_pins[0]	values[0x1]	42394	1			T2	52		T3	105		T4	32
all_pins[0]	transitions[0x0=>0x1]	34724	1			T2	28		T3	85		T4	22
all_pins[0]	transitions[0x1=>0x0]	8520	1			T2	17		T3	11		T4	6
all_pins[1]	values[0x0]	147008	1			T1	73		T2	130		T3	415
all_pins[1]	values[0x1]	16190	1			T2	41		T3	31		T4	16
all_pins[1]	transitions[0x0=>0x1]	8421	1			T2	18		T3	11		T4	6
all_pins[1]	transitions[0x1=>0x0]	34559	1			T2	29		T3	85		T4	22