Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_csr_rd_after_alert_cg_wrap::csr_rd_after_alert_cg

Group : otp_ctrl_env_pkg::otp_ctrl_csr_rd_after_alert_cg_wrap::csr_rd_after_alert_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

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Summary for Group otp_ctrl_env_pkg::otp_ctrl_csr_rd_after_alert_cg_wrap::csr_rd_after_alert_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group otp_ctrl_env_pkg::otp_ctrl_csr_rd_after_alert_cg_wrap::csr_rd_after_alert_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
read_csr_after_alert_issued	6	0	6	100.00	100	1	1	0

Summary for Variable read_csr_after_alert_issued

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for read_csr_after_alert_issued

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
error_code	1383703	1			T3	9568		T72	8		T100	4914
status	385955	1			T3	751		T72	228		T100	326
direct_access_rdata	53866	1			T3	342		T72	113		T100	178
secret_digests	14040	1			T3	96		T100	66		T87	12
hw_digests	9360	1			T3	64		T100	44		T87	8
unbuffered_digests	23400	1			T3	160		T100	110		T87	20