Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv



Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 0 5 100.00
Crosses 6 0 6 100.00


Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
dai_access_cmd 3 0 3 100.00 100 1 1 0
lc_creator_seed_sw_rw_en 2 0 2 100.00 100 1 1 2


Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
dai_access_secret2 6 0 6 100.00 100 1 1 0


Summary for Variable dai_access_cmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for dai_access_cmd

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
dai_digest 2338 1 T2 8 T3 9 T4 4
dai_wr 3928 1 T1 6 T2 7 T3 10
dai_rd 6748 1 T1 9 T2 9 T3 9



Summary for Variable lc_creator_seed_sw_rw_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_creator_seed_sw_rw_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5622 1 T2 8 T3 20 T4 12
auto[1] 7392 1 T1 15 T2 16 T3 8



Summary for Cross dai_access_secret2

Samples crossed: lc_creator_seed_sw_rw_en dai_access_cmd
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 0 6 100.00


Automatically Generated Cross Bins for dai_access_secret2

Bins
lc_creator_seed_sw_rw_endai_access_cmdCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] dai_digest 1257 1 T2 4 T3 7 T4 2
auto[0] dai_wr 1334 1 T2 2 T3 8 T4 3
auto[0] dai_rd 3031 1 T2 2 T3 5 T4 7
auto[1] dai_digest 1081 1 T2 4 T3 2 T4 2
auto[1] dai_wr 2594 1 T1 6 T2 5 T3 2
auto[1] dai_rd 3717 1 T1 9 T2 7 T3 4

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