Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	48217	1			T3	319		T100	378		T87	10
access_err	58440	1			T2	119		T3	33		T4	30
write_blank_err	356	1			T3	1		T6	3		T7	1
ecc_uncorr_err	58218	1			T3	417		T87	59		T6	954
ecc_corr_err	1594	1			T87	1		T75	9		T65	30
no_err	85118	1			T2	114		T3	105		T4	40

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	555	1			T6	12		T7	2		T14	8
secret2	24305	1			T2	28		T3	338		T4	9
secret1	22526	1			T2	25		T3	7		T4	2
secret0	35751	1			T2	21		T3	452		T4	3
hw_cfg1	35294	1			T2	21		T3	8		T4	5
hw_cfg0	20859	1			T2	11		T3	10		T4	6
rot_creator_auth_state	20827	1			T2	22		T3	23		T4	9
rot_creator_auth_codesign	21282	1			T2	28		T3	10		T4	5
owner_sw_cfg	17991	1			T2	28		T3	18		T4	4
creator_sw_cfg	18829	1			T2	23		T3	3		T4	13
vendor_test	33724	1			T2	26		T3	6		T4	14

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	5113	1			T3	319		T100	378		T6	513
fsm_err	secret1	1963	1			T323	2		T372	322		T373	298
fsm_err	secret0	6204	1			T264	34		T374	540		T127	138
fsm_err	hw_cfg1	3550	1			T261	541		T270	332		T267	277
fsm_err	hw_cfg0	4044	1			T90	604		T111	167		T266	150
fsm_err	rot_creator_auth_state	2369	1			T89	2		T92	30		T225	59
fsm_err	rot_creator_auth_codesign	2913	1			T92	127		T204	36		T375	457
fsm_err	owner_sw_cfg	2322	1			T239	411		T201	14		T202	9
fsm_err	creator_sw_cfg	2465	1			T87	10		T265	70		T137	223
fsm_err	vendor_test	17274	1			T75	72		T92	520		T16	118
access_err	life_cycle	555	1			T6	12		T7	2		T14	8
access_err	secret2	10273	1			T2	23		T3	15		T4	7
access_err	secret1	5807	1			T2	22		T3	3		T4	2
access_err	secret0	4513	1			T2	1		T3	7		T5	1
access_err	hw_cfg1	1184	1			T2	3		T3	4		T5	6
access_err	hw_cfg0	1980	1			T26	2		T91	1		T6	1
access_err	rot_creator_auth_state	5468	1			T2	19		T3	3		T4	3
access_err	rot_creator_auth_codesign	7805	1			T2	19		T4	4		T5	162
access_err	owner_sw_cfg	6310	1			T4	2		T5	114		T26	4
access_err	creator_sw_cfg	7575	1			T2	17		T4	8		T5	136
access_err	vendor_test	6970	1			T2	15		T3	1		T4	4
write_blank_err	secret2	9	1			T266	1		T376	1		T377	1
write_blank_err	secret1	18	1			T378	1		T195	1		T323	1
write_blank_err	secret0	42	1			T3	1		T6	1		T7	1
write_blank_err	hw_cfg1	68	1			T14	1		T101	1		T111	1
write_blank_err	hw_cfg0	12	1			T379	1		T323	1		T286	1
write_blank_err	rot_creator_auth_state	120	1			T6	1		T143	1		T101	3
write_blank_err	rot_creator_auth_codesign	37	1			T6	1		T380	2		T381	4
write_blank_err	owner_sw_cfg	18	1			T145	1		T368	3		T323	1
write_blank_err	creator_sw_cfg	17	1			T258	2		T382	1		T383	3
write_blank_err	vendor_test	15	1			T142	1		T236	1		T240	1
ecc_uncorr_err	secret2	3758	1			T266	441		T376	109		T377	496
ecc_uncorr_err	secret1	6172	1			T87	15		T153	31		T378	410
ecc_uncorr_err	secret0	16760	1			T3	417		T87	16		T6	429
ecc_uncorr_err	hw_cfg1	20249	1			T14	115		T144	3		T111	27
ecc_uncorr_err	hw_cfg0	3274	1			T144	4		T379	550		T225	58
ecc_uncorr_err	rot_creator_auth_state	4704	1			T143	548		T101	450		T225	122
ecc_uncorr_err	rot_creator_auth_codesign	2036	1			T87	13		T6	525		T380	482
ecc_uncorr_err	owner_sw_cfg	611	1			T153	32		T201	61		T212	53
ecc_uncorr_err	creator_sw_cfg	654	1			T87	15		T153	21		T202	19
ecc_corr_err	secret2	87	1			T59	8		T191	1		T51	2
ecc_corr_err	secret1	138	1			T75	2		T65	1		T59	5
ecc_corr_err	secret0	179	1			T59	6		T76	4		T51	5
ecc_corr_err	hw_cfg1	292	1			T75	1		T65	13		T59	19
ecc_corr_err	hw_cfg0	310	1			T75	6		T65	5		T59	24
ecc_corr_err	rot_creator_auth_state	141	1			T59	4		T101	1		T51	1
ecc_corr_err	rot_creator_auth_codesign	151	1			T65	3		T59	3		T76	1
ecc_corr_err	owner_sw_cfg	147	1			T65	3		T59	6		T76	1
ecc_corr_err	creator_sw_cfg	149	1			T87	1		T65	5		T59	2
no_err	secret2	5065	1			T2	5		T3	4		T4	2
no_err	secret1	8428	1			T2	3		T3	4		T5	171
no_err	secret0	8053	1			T2	20		T3	27		T4	3
no_err	hw_cfg1	9951	1			T2	18		T3	4		T4	5
no_err	hw_cfg0	11239	1			T2	11		T3	10		T4	6
no_err	rot_creator_auth_state	8025	1			T2	3		T3	20		T4	6
no_err	rot_creator_auth_codesign	8340	1			T2	9		T3	10		T4	1
no_err	owner_sw_cfg	8583	1			T2	28		T3	18		T4	2
no_err	creator_sw_cfg	7969	1			T2	6		T3	3		T4	5
no_err	vendor_test	9465	1			T2	11		T3	5		T4	10

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded