SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
read_csr_after_alert_issued | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
error_code | 1436814 | 1 | T72 | 4537 | T8 | 9659 | T112 | 2158 | ||||
status | 393302 | 1 | T3 | 378 | T72 | 367 | T8 | 829 | ||||
direct_access_rdata | 54629 | 1 | T3 | 204 | T72 | 121 | T8 | 321 | ||||
secret_digests | 14298 | 1 | T3 | 66 | T72 | 18 | T8 | 12 | ||||
hw_digests | 9532 | 1 | T3 | 44 | T72 | 12 | T8 | 8 | ||||
unbuffered_digests | 23830 | 1 | T3 | 110 | T72 | 30 | T8 | 20 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |