Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
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Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv



Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 0 5 100.00
Crosses 6 0 6 100.00


Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
dai_access_cmd 3 0 3 100.00 100 1 1 0
lc_creator_seed_sw_rw_en 2 0 2 100.00 100 1 1 2


Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
dai_access_secret2 6 0 6 100.00 100 1 1 0


Summary for Variable dai_access_cmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for dai_access_cmd

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
dai_digest 2248 1 T4 1 T6 12 T7 1
dai_wr 4107 1 T1 2 T2 3 T4 2
dai_rd 7057 1 T1 3 T2 4 T4 6



Summary for Variable lc_creator_seed_sw_rw_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_creator_seed_sw_rw_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6118 1 T6 17 T72 2 T8 9
auto[1] 7294 1 T1 5 T2 7 T4 9



Summary for Cross dai_access_secret2

Samples crossed: lc_creator_seed_sw_rw_en dai_access_cmd
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 0 6 100.00


Automatically Generated Cross Bins for dai_access_secret2

Bins
lc_creator_seed_sw_rw_endai_access_cmdCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] dai_digest 1227 1 T6 11 T8 2 T70 1
auto[0] dai_wr 1525 1 T6 4 T8 3 T9 6
auto[0] dai_rd 3366 1 T6 2 T72 2 T8 4
auto[1] dai_digest 1021 1 T4 1 T6 1 T7 1
auto[1] dai_wr 2582 1 T1 2 T2 3 T4 2
auto[1] dai_rd 3691 1 T1 3 T2 4 T4 6

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