Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	51314	1			T72	136		T70	77		T113	107
access_err	59518	1			T6	93		T72	3		T8	152
write_blank_err	382	1			T8	2		T112	3		T9	3
ecc_uncorr_err	59207	1			T72	213		T8	743		T112	166
ecc_corr_err	1229	1			T72	7		T112	5		T70	33
no_err	88706	1			T4	74		T6	197		T7	57

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	575	1			T8	8		T9	3		T14	5
secret2	20842	1			T4	12		T6	41		T7	3
secret1	30636	1			T4	8		T6	25		T7	11
secret0	32128	1			T4	11		T6	26		T7	7
hw_cfg1	38011	1			T4	10		T6	14		T7	6
hw_cfg0	27891	1			T4	7		T6	19		T7	1
rot_creator_auth_state	19887	1			T4	10		T6	34		T7	4
rot_creator_auth_codesign	20262	1			T4	3		T6	27		T7	7
owner_sw_cfg	18693	1			T4	5		T6	38		T7	2
creator_sw_cfg	20589	1			T6	38		T7	4		T12	8
vendor_test	30842	1			T4	8		T6	28		T7	12

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2812	1			T267	55		T127	108		T241	427
fsm_err	secret1	6575	1			T13	651		T299	128		T365	594
fsm_err	secret0	3230	1			T190	97		T264	51		T231	32
fsm_err	hw_cfg1	5174	1			T105	72		T366	87		T41	153
fsm_err	hw_cfg0	6811	1			T113	107		T14	301		T265	69
fsm_err	rot_creator_auth_state	3291	1			T72	29		T32	4		T143	27
fsm_err	rot_creator_auth_codesign	3170	1			T72	31		T367	197		T20	244
fsm_err	owner_sw_cfg	2190	1			T72	38		T277	365		T368	101
fsm_err	creator_sw_cfg	3857	1			T32	3		T182	2		T369	34
fsm_err	vendor_test	14204	1			T72	38		T70	77		T16	72
access_err	life_cycle	575	1			T8	8		T9	3		T14	5
access_err	secret2	10726	1			T6	29		T72	3		T8	28
access_err	secret1	5668	1			T8	16		T70	2		T31	8
access_err	secret0	4382	1			T8	19		T70	3		T42	10
access_err	hw_cfg1	1244	1			T8	3		T70	5		T113	2
access_err	hw_cfg0	2122	1			T70	5		T113	1		T18	16
access_err	rot_creator_auth_state	5651	1			T6	15		T8	14		T113	1
access_err	rot_creator_auth_codesign	7503	1			T6	12		T8	11		T112	2
access_err	owner_sw_cfg	6825	1			T6	15		T8	11		T70	7
access_err	creator_sw_cfg	7824	1			T6	13		T8	26		T112	3
access_err	vendor_test	6998	1			T6	9		T8	16		T112	7
write_blank_err	secret2	6	1			T297	1		T370	1		T261	1
write_blank_err	secret1	25	1			T9	1		T14	1		T19	1
write_blank_err	secret0	46	1			T112	1		T14	1		T246	1
write_blank_err	hw_cfg1	60	1			T8	2		T112	1		T14	1
write_blank_err	hw_cfg0	21	1			T127	1		T23	1		T141	2
write_blank_err	rot_creator_auth_state	126	1			T364	1		T127	1		T163	1
write_blank_err	rot_creator_auth_codesign	41	1			T9	2		T14	2		T102	1
write_blank_err	owner_sw_cfg	25	1			T14	1		T127	3		T23	1
write_blank_err	creator_sw_cfg	12	1			T364	1		T102	1		T371	1
write_blank_err	vendor_test	20	1			T112	1		T14	1		T127	2
ecc_uncorr_err	secret2	2019	1			T32	3		T191	46		T297	257
ecc_uncorr_err	secret1	9411	1			T72	40		T9	391		T14	175
ecc_uncorr_err	secret0	15985	1			T72	35		T14	423		T246	314
ecc_uncorr_err	hw_cfg1	20842	1			T8	743		T112	166		T13	688
ecc_uncorr_err	hw_cfg0	6759	1			T158	19		T372	129		T182	7
ecc_uncorr_err	rot_creator_auth_state	2327	1			T72	37		T32	5		T372	61
ecc_uncorr_err	rot_creator_auth_codesign	774	1			T72	38		T158	44		T372	65
ecc_uncorr_err	owner_sw_cfg	607	1			T72	63		T191	48		T217	17
ecc_uncorr_err	creator_sw_cfg	483	1			T191	63		T158	43		T210	14
ecc_corr_err	secret2	74	1			T70	4		T66	1		T372	2
ecc_corr_err	secret1	101	1			T70	2		T32	1		T66	3
ecc_corr_err	secret0	148	1			T72	1		T112	5		T70	2
ecc_corr_err	hw_cfg1	238	1			T70	4		T32	1		T158	8
ecc_corr_err	hw_cfg0	189	1			T72	1		T70	3		T66	8
ecc_corr_err	rot_creator_auth_state	108	1			T32	1		T191	4		T67	3
ecc_corr_err	rot_creator_auth_codesign	139	1			T72	1		T70	3		T32	3
ecc_corr_err	owner_sw_cfg	137	1			T72	4		T70	13		T32	1
ecc_corr_err	creator_sw_cfg	95	1			T70	2		T118	2		T158	3
no_err	secret2	5205	1			T4	12		T6	12		T7	3
no_err	secret1	8856	1			T4	8		T6	25		T7	11
no_err	secret0	8337	1			T4	11		T6	26		T7	7
no_err	hw_cfg1	10453	1			T4	10		T6	14		T7	6
no_err	hw_cfg0	11989	1			T4	7		T6	19		T7	1
no_err	rot_creator_auth_state	8384	1			T4	10		T6	19		T7	4
no_err	rot_creator_auth_codesign	8635	1			T4	3		T6	15		T7	7
no_err	owner_sw_cfg	8909	1			T4	5		T6	23		T7	2
no_err	creator_sw_cfg	8318	1			T6	25		T7	4		T12	8
no_err	vendor_test	9620	1			T4	8		T6	19		T7	12

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded