Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
852 |
1 |
|
|
T8 |
4 |
|
T14 |
11 |
|
T19 |
15 |
all_values[1] |
852 |
1 |
|
|
T8 |
4 |
|
T14 |
11 |
|
T19 |
15 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
914 |
1 |
|
|
T8 |
3 |
|
T14 |
14 |
|
T19 |
23 |
auto[1] |
790 |
1 |
|
|
T8 |
5 |
|
T14 |
8 |
|
T19 |
7 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
693 |
1 |
|
|
T8 |
3 |
|
T14 |
5 |
|
T19 |
12 |
auto[1] |
1011 |
1 |
|
|
T8 |
5 |
|
T14 |
17 |
|
T19 |
18 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1015 |
1 |
|
|
T8 |
5 |
|
T14 |
10 |
|
T19 |
18 |
auto[1] |
689 |
1 |
|
|
T8 |
3 |
|
T14 |
12 |
|
T19 |
12 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
12 |
0 |
12 |
100.00 |
|
Automatically Generated Cross Bins |
12 |
0 |
12 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
198 |
1 |
|
|
T14 |
2 |
|
T19 |
6 |
|
T127 |
1 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
82 |
1 |
|
|
T14 |
2 |
|
T19 |
2 |
|
T260 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
149 |
1 |
|
|
T14 |
2 |
|
T19 |
3 |
|
T127 |
4 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
80 |
1 |
|
|
T8 |
2 |
|
T260 |
1 |
|
T127 |
2 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
184 |
1 |
|
|
T14 |
2 |
|
T19 |
4 |
|
T260 |
4 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
159 |
1 |
|
|
T8 |
2 |
|
T14 |
3 |
|
T260 |
1 |
all_values[1] |
auto[0] |
auto[0] |
auto[0] |
190 |
1 |
|
|
T8 |
2 |
|
T19 |
3 |
|
T260 |
2 |
all_values[1] |
auto[0] |
auto[0] |
auto[1] |
71 |
1 |
|
|
T14 |
1 |
|
T19 |
2 |
|
T127 |
2 |
all_values[1] |
auto[0] |
auto[1] |
auto[0] |
156 |
1 |
|
|
T8 |
1 |
|
T14 |
1 |
|
T260 |
2 |
all_values[1] |
auto[0] |
auto[1] |
auto[1] |
89 |
1 |
|
|
T14 |
2 |
|
T19 |
2 |
|
T260 |
1 |
all_values[1] |
auto[1] |
auto[0] |
auto[1] |
189 |
1 |
|
|
T8 |
1 |
|
T14 |
7 |
|
T19 |
6 |
all_values[1] |
auto[1] |
auto[1] |
auto[1] |
157 |
1 |
|
|
T19 |
2 |
|
T260 |
1 |
|
T127 |
4 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |