Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	49132	1			T1	376		T13	51		T105	11
access_err	63752	1			T2	168		T4	5		T5	72
write_blank_err	507	1			T6	1		T107	1		T14	4
ecc_uncorr_err	68621	1			T6	132		T107	383		T14	596
ecc_corr_err	1339	1			T2	37		T13	8		T15	6
no_err	95792	1			T2	91		T4	6		T5	95

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	848	1			T6	5		T14	13		T15	20
secret2	26891	1			T1	376		T2	30		T5	6
secret1	28042	1			T2	44		T4	1		T5	20
secret0	37597	1			T2	20		T4	5		T5	13
hw_cfg1	38549	1			T2	17		T5	22		T12	20
hw_cfg0	24322	1			T2	32		T4	2		T5	18
rot_creator_auth_state	25289	1			T2	47		T5	23		T10	2
rot_creator_auth_codesign	22736	1			T2	33		T5	21		T12	23
owner_sw_cfg	20129	1			T2	18		T4	1		T5	11
creator_sw_cfg	21370	1			T2	27		T4	1		T5	12
vendor_test	33370	1			T2	28		T4	1		T5	21

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	4342	1			T1	376		T114	70		T328	491
fsm_err	secret1	4259	1			T16	334		T110	159		T149	52
fsm_err	secret0	3859	1			T329	312		T254	485		T143	6
fsm_err	hw_cfg1	3923	1			T106	44		T136	155		T15	130
fsm_err	hw_cfg0	4186	1			T105	11		T93	24		T33	181
fsm_err	rot_creator_auth_state	3678	1			T235	17		T236	150		T330	268
fsm_err	rot_creator_auth_codesign	3764	1			T202	220		T244	25		T168	14
fsm_err	owner_sw_cfg	2303	1			T164	57		T251	415		T253	403
fsm_err	creator_sw_cfg	3645	1			T165	64		T331	407		T255	193
fsm_err	vendor_test	15173	1			T13	51		T15	22		T332	245
access_err	life_cycle	848	1			T6	5		T14	13		T15	20
access_err	secret2	11390	1			T2	26		T5	2		T12	6
access_err	secret1	5769	1			T2	29		T5	15		T12	26
access_err	secret0	4690	1			T2	2		T4	5		T12	16
access_err	hw_cfg1	1308	1			T2	8		T5	2		T12	4
access_err	hw_cfg0	2336	1			T2	1		T5	5		T12	5
access_err	rot_creator_auth_state	6296	1			T2	38		T5	11		T12	10
access_err	rot_creator_auth_codesign	8116	1			T2	23		T5	13		T12	18
access_err	owner_sw_cfg	7209	1			T2	5		T5	4		T12	5
access_err	creator_sw_cfg	8021	1			T2	23		T5	7		T12	4
access_err	vendor_test	7769	1			T2	13		T5	13		T12	15
write_blank_err	secret2	17	1			T116	1		T333	1		T325	1
write_blank_err	secret1	22	1			T15	1		T63	1		T334	1
write_blank_err	secret0	53	1			T6	1		T107	1		T15	2
write_blank_err	hw_cfg1	73	1			T14	1		T15	1		T63	1
write_blank_err	hw_cfg0	20	1			T327	1		T142	1		T248	1
write_blank_err	rot_creator_auth_state	173	1			T15	2		T154	6		T334	4
write_blank_err	rot_creator_auth_codesign	60	1			T15	1		T63	1		T155	2
write_blank_err	owner_sw_cfg	39	1			T15	1		T123	3		T131	3
write_blank_err	creator_sw_cfg	18	1			T14	1		T102	2		T335	1
write_blank_err	vendor_test	32	1			T14	2		T63	2		T156	1
ecc_uncorr_err	secret2	5160	1			T164	58		T116	612		T336	10
ecc_uncorr_err	secret1	8256	1			T63	577		T149	54		T334	257
ecc_uncorr_err	secret0	19668	1			T6	132		T107	383		T15	228
ecc_uncorr_err	hw_cfg1	21673	1			T14	596		T15	574		T155	529
ecc_uncorr_err	hw_cfg0	4962	1			T149	55		T164	57		T160	56
ecc_uncorr_err	rot_creator_auth_state	6089	1			T154	643		T160	57		T168	18
ecc_uncorr_err	rot_creator_auth_codesign	1293	1			T164	52		T160	124		T165	31
ecc_uncorr_err	owner_sw_cfg	768	1			T165	29		T337	39		T212	85
ecc_uncorr_err	creator_sw_cfg	752	1			T149	62		T335	250		T168	35
ecc_corr_err	secret2	84	1			T2	3		T338	1		T43	1
ecc_corr_err	secret1	145	1			T2	4		T13	5		T15	1
ecc_corr_err	secret0	138	1			T2	11		T13	1		T15	5
ecc_corr_err	hw_cfg1	228	1			T2	1		T13	1		T63	1
ecc_corr_err	hw_cfg0	249	1			T2	7		T13	1		T164	1
ecc_corr_err	rot_creator_auth_state	136	1			T2	1		T149	1		T164	1
ecc_corr_err	rot_creator_auth_codesign	109	1			T2	2		T69	2		T55	1
ecc_corr_err	owner_sw_cfg	110	1			T2	5		T149	1		T69	2
ecc_corr_err	creator_sw_cfg	140	1			T2	3		T164	5		T160	1
no_err	secret2	5898	1			T2	1		T5	4		T10	1
no_err	secret1	9591	1			T2	11		T4	1		T5	5
no_err	secret0	9189	1			T2	7		T5	13		T12	6
no_err	hw_cfg1	11344	1			T2	8		T5	20		T12	16
no_err	hw_cfg0	12569	1			T2	24		T4	2		T5	13
no_err	rot_creator_auth_state	8917	1			T2	8		T5	12		T10	2
no_err	rot_creator_auth_codesign	9394	1			T2	8		T5	8		T12	5
no_err	owner_sw_cfg	9700	1			T2	8		T4	1		T5	7
no_err	creator_sw_cfg	8794	1			T2	1		T4	1		T5	5
no_err	vendor_test	10396	1			T2	15		T4	1		T5	8

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded