Group : tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg
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Group : tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 0 14 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
lc_esc_during_flash_addr_req 2 0 2 100.00 100 1 1 2
lc_esc_during_flash_data_req 2 0 2 100.00 100 1 1 2
lc_esc_during_lc_otp_prog_req 2 0 2 100.00 100 1 1 2
lc_esc_during_otbn_req 2 0 2 100.00 100 1 1 2
lc_esc_during_otp_idle 2 0 2 100.00 100 1 1 2
lc_esc_during_sram_0_req 2 0 2 100.00 100 1 1 2
lc_esc_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable lc_esc_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 335 1 T3 1 T6 1 T7 4
auto[1] 47 1 T3 1 T6 1 T154 1



Summary for Variable lc_esc_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 345 1 T3 2 T6 2 T7 3
auto[1] 37 1 T7 1 T147 1 T344 1



Summary for Variable lc_esc_during_lc_otp_prog_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_lc_otp_prog_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 344 1 T3 2 T6 2 T7 4
auto[1] 38 1 T60 1 T399 1 T164 1



Summary for Variable lc_esc_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 335 1 T3 2 T6 2 T7 3
auto[1] 47 1 T7 1 T98 1 T235 1



Summary for Variable lc_esc_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 34 1 T7 1 T154 1 T60 1
auto[1] 348 1 T3 2 T6 2 T7 3



Summary for Variable lc_esc_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 336 1 T3 2 T6 2 T7 4
auto[1] 46 1 T180 1 T60 2 T248 1



Summary for Variable lc_esc_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 332 1 T3 2 T6 2 T7 4
auto[1] 50 1 T180 2 T60 2 T248 2

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