Group : tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg
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Group : tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
sram_0_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
sram_0_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
sram_0_req_during_lc_esc 2 0 2 100.00 100 1 1 0
sram_0_req_during_otbn_req 2 0 2 100.00 100 1 1 2
sram_0_req_during_otp_idle 2 0 2 100.00 100 1 1 2
sram_0_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable sram_0_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12373 1 T1 4 T4 2 T5 40
auto[1] 873 1 T6 11 T9 88 T7 3



Summary for Variable sram_0_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12189 1 T1 4 T4 2 T5 40
auto[1] 1057 1 T6 9 T9 86 T7 4



Summary for Variable sram_0_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for sram_0_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 13218 1 T1 4 T4 2 T5 40
lc_esc_on 28 1 T180 1 T60 2 T248 1



Summary for Variable sram_0_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12438 1 T1 4 T4 2 T5 40
auto[1] 808 1 T6 10 T7 4 T60 2



Summary for Variable sram_0_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2159 1 T6 20 T9 165 T7 10
auto[1] 11087 1 T1 4 T4 2 T5 40



Summary for Variable sram_0_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_0_req_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11490 1 T1 2 T4 2 T5 39
auto[1] 1756 1 T1 2 T5 1 T8 1

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