Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	48253	1			T3	319		T6	141		T11	17
access_err	60106	1			T3	1		T4	2		T5	190
write_blank_err	396	1			T5	4		T6	5		T7	2
ecc_uncorr_err	66041	1			T5	569		T6	676		T7	361
ecc_corr_err	919	1			T5	1		T11	3		T104	4
no_err	91235	1			T1	48		T3	2		T4	10

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	640	1			T5	6		T6	4		T7	12
secret2	22095	1			T1	7		T4	1		T5	56
secret1	24574	1			T1	7		T3	2		T4	2
secret0	44276	1			T1	1		T4	2		T5	60
hw_cfg1	37282	1			T1	2		T5	46		T8	10
hw_cfg0	20854	1			T1	6		T5	41		T8	2
rot_creator_auth_state	22211	1			T1	8		T5	41		T8	5
rot_creator_auth_codesign	21965	1			T1	2		T4	2		T5	55
owner_sw_cfg	19779	1			T1	2		T4	2		T5	36
creator_sw_cfg	21489	1			T1	7		T3	320		T4	2
vendor_test	31785	1			T1	6		T4	1		T5	72

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3560	1			T212	490		T164	23		T342	118
fsm_err	secret1	3268	1			T6	108		T108	138		T60	391
fsm_err	secret0	4653	1			T147	73		T12	364		T26	177
fsm_err	hw_cfg1	4847	1			T343	124		T245	282		T246	60
fsm_err	hw_cfg0	3831	1			T60	98		T341	256		T163	148
fsm_err	rot_creator_auth_state	3021	1			T104	29		T344	331		T155	69
fsm_err	rot_creator_auth_codesign	3790	1			T6	33		T104	34		T98	531
fsm_err	owner_sw_cfg	2733	1			T7	498		T345	560		T189	27
fsm_err	creator_sw_cfg	4143	1			T3	319		T60	27		T248	23
fsm_err	vendor_test	14407	1			T11	17		T7	88		T180	231
access_err	life_cycle	640	1			T5	6		T6	4		T7	12
access_err	secret2	10384	1			T5	50		T6	96		T11	2
access_err	secret1	5530	1			T6	109		T11	4		T7	14
access_err	secret0	4564	1			T4	2		T5	13		T6	69
access_err	hw_cfg1	1195	1			T5	3		T6	30		T7	5
access_err	hw_cfg0	2047	1			T6	23		T7	7		T31	7
access_err	rot_creator_auth_state	5976	1			T5	25		T6	52		T7	14
access_err	rot_creator_auth_codesign	7876	1			T5	19		T6	105		T7	9
access_err	owner_sw_cfg	6953	1			T5	14		T6	86		T7	13
access_err	creator_sw_cfg	7428	1			T3	1		T5	28		T6	72
access_err	vendor_test	7513	1			T5	32		T6	120		T7	15
write_blank_err	secret2	11	1			T60	1		T216	1		T124	1
write_blank_err	secret1	21	1			T5	1		T7	1		T346	1
write_blank_err	secret0	67	1			T6	1		T7	1		T206	2
write_blank_err	hw_cfg1	76	1			T5	1		T181	1		T340	2
write_blank_err	hw_cfg0	9	1			T212	1		T272	1		T347	1
write_blank_err	rot_creator_auth_state	110	1			T340	2		T212	6		T128	1
write_blank_err	rot_creator_auth_codesign	44	1			T6	3		T271	5		T212	2
write_blank_err	owner_sw_cfg	16	1			T212	1		T124	4		T348	1
write_blank_err	creator_sw_cfg	10	1			T244	1		T128	2		T295	1
write_blank_err	vendor_test	32	1			T5	2		T6	1		T346	2
ecc_uncorr_err	secret2	2845	1			T60	275		T140	28		T141	50
ecc_uncorr_err	secret1	6508	1			T5	569		T7	226		T141	111
ecc_uncorr_err	secret0	26203	1			T6	676		T7	135		T206	515
ecc_uncorr_err	hw_cfg1	20122	1			T181	485		T140	86		T145	102
ecc_uncorr_err	hw_cfg0	2462	1			T140	43		T162	88		T272	154
ecc_uncorr_err	rot_creator_auth_state	4563	1			T140	43		T155	68		T156	69
ecc_uncorr_err	rot_creator_auth_codesign	1110	1			T104	34		T140	39		T141	44
ecc_uncorr_err	owner_sw_cfg	756	1			T104	63		T186	23		T140	43
ecc_uncorr_err	creator_sw_cfg	1472	1			T104	30		T140	42		T145	102
ecc_corr_err	secret2	50	1			T44	3		T32	3		T67	6
ecc_corr_err	secret1	88	1			T104	1		T44	4		T140	1
ecc_corr_err	secret0	117	1			T11	1		T104	1		T206	3
ecc_corr_err	hw_cfg1	174	1			T5	1		T44	4		T32	2
ecc_corr_err	hw_cfg0	187	1			T104	1		T44	5		T32	2
ecc_corr_err	rot_creator_auth_state	76	1			T11	1		T104	1		T44	4
ecc_corr_err	rot_creator_auth_codesign	62	1			T11	1		T44	1		T186	1
ecc_corr_err	owner_sw_cfg	105	1			T44	1		T32	1		T141	1
ecc_corr_err	creator_sw_cfg	60	1			T44	2		T32	1		T145	2
no_err	secret2	5245	1			T1	7		T4	1		T5	6
no_err	secret1	9159	1			T1	7		T3	2		T4	2
no_err	secret0	8672	1			T1	1		T5	47		T6	58
no_err	hw_cfg1	10868	1			T1	2		T5	41		T8	10
no_err	hw_cfg0	12318	1			T1	6		T5	41		T8	2
no_err	rot_creator_auth_state	8465	1			T1	8		T5	16		T8	5
no_err	rot_creator_auth_codesign	9083	1			T1	2		T4	2		T5	36
no_err	owner_sw_cfg	9216	1			T1	2		T4	2		T5	22
no_err	creator_sw_cfg	8376	1			T1	7		T4	2		T5	16
no_err	vendor_test	9833	1			T1	6		T4	1		T5	38

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded