Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv



Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
secret1_lock 2 0 2 100.00 100 1 1 2
sram_index 4 0 4 100.00 100 1 1 0


Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sram_req_lock_cross 8 0 8 100.00 100 1 1 0


Summary for Variable secret1_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for secret1_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1656 1 T6 24 T11 6 T104 16
auto[1] 1100 1 T6 36 T11 19 T31 11



Summary for Variable sram_index

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for sram_index

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sram_key[0x0] 125 1 T6 6 T128 2 T16 13
sram_key[0x1] 853 1 T6 18 T11 7 T104 7
sram_key[0x2] 903 1 T6 23 T11 9 T104 7
sram_key[0x3] 875 1 T6 13 T11 9 T104 2



Summary for Cross sram_req_lock_cross

Samples crossed: sram_index secret1_lock
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for sram_req_lock_cross

Bins
sram_indexsecret1_lockCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sram_key[0x0] auto[0] 82 1 T6 1 T128 2 T16 13
sram_key[0x0] auto[1] 43 1 T6 5 T391 1 T395 1
sram_key[0x1] auto[0] 512 1 T6 8 T11 2 T104 7
sram_key[0x1] auto[1] 341 1 T6 10 T11 5 T98 6
sram_key[0x2] auto[0] 543 1 T6 9 T11 2 T104 7
sram_key[0x2] auto[1] 360 1 T6 14 T11 7 T31 5
sram_key[0x3] auto[0] 519 1 T6 6 T11 2 T104 2
sram_key[0x3] auto[1] 356 1 T6 7 T11 7 T31 6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%