Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.08 93.89 96.62 96.07 92.12 97.24 96.33 93.28


Total test records in report: 1321
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T268 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2403315536 Jun 10 07:44:31 PM PDT 24 Jun 10 07:44:46 PM PDT 24 981507989 ps
T1265 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.1691070044 Jun 10 07:44:29 PM PDT 24 Jun 10 07:44:32 PM PDT 24 47009059 ps
T1266 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.1783698417 Jun 10 07:44:29 PM PDT 24 Jun 10 07:44:32 PM PDT 24 547991182 ps
T1267 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.2084213689 Jun 10 07:44:16 PM PDT 24 Jun 10 07:44:23 PM PDT 24 88457686 ps
T1268 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.662249717 Jun 10 07:44:30 PM PDT 24 Jun 10 07:44:35 PM PDT 24 115298081 ps
T1269 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.380106490 Jun 10 07:44:37 PM PDT 24 Jun 10 07:44:43 PM PDT 24 39508734 ps
T304 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.4197117451 Jun 10 07:44:11 PM PDT 24 Jun 10 07:44:20 PM PDT 24 156897560 ps
T1270 /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.456261975 Jun 10 07:44:39 PM PDT 24 Jun 10 07:44:45 PM PDT 24 74943000 ps
T1271 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.1672123814 Jun 10 07:44:38 PM PDT 24 Jun 10 07:44:44 PM PDT 24 39468770 ps
T1272 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2256569384 Jun 10 07:44:10 PM PDT 24 Jun 10 07:44:16 PM PDT 24 92314892 ps
T1273 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.4074188300 Jun 10 07:44:10 PM PDT 24 Jun 10 07:44:15 PM PDT 24 48840079 ps
T1274 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.440938987 Jun 10 07:44:09 PM PDT 24 Jun 10 07:44:13 PM PDT 24 134439161 ps
T1275 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1552756483 Jun 10 07:44:20 PM PDT 24 Jun 10 07:44:24 PM PDT 24 513939714 ps
T1276 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2682938587 Jun 10 07:44:16 PM PDT 24 Jun 10 07:44:22 PM PDT 24 137917094 ps
T305 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.1977085741 Jun 10 07:44:32 PM PDT 24 Jun 10 07:44:37 PM PDT 24 143113337 ps
T1277 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3882142575 Jun 10 07:44:31 PM PDT 24 Jun 10 07:44:37 PM PDT 24 1471818746 ps
T1278 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.3832090966 Jun 10 07:44:32 PM PDT 24 Jun 10 07:44:41 PM PDT 24 78043661 ps
T1279 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2865754809 Jun 10 07:44:11 PM PDT 24 Jun 10 07:44:22 PM PDT 24 3725054375 ps
T350 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1311982707 Jun 10 07:44:32 PM PDT 24 Jun 10 07:44:45 PM PDT 24 667908128 ps
T1280 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3771396126 Jun 10 07:44:28 PM PDT 24 Jun 10 07:44:30 PM PDT 24 49240546 ps
T1281 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3867492945 Jun 10 07:44:32 PM PDT 24 Jun 10 07:44:37 PM PDT 24 67605415 ps
T1282 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2729872195 Jun 10 07:44:17 PM PDT 24 Jun 10 07:44:22 PM PDT 24 578424230 ps
T1283 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.503688089 Jun 10 07:44:11 PM PDT 24 Jun 10 07:44:15 PM PDT 24 554119495 ps
T1284 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.3733598394 Jun 10 07:44:31 PM PDT 24 Jun 10 07:44:36 PM PDT 24 559923595 ps
T351 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2351669561 Jun 10 07:44:16 PM PDT 24 Jun 10 07:44:39 PM PDT 24 1310846983 ps
T1285 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.997128389 Jun 10 07:44:15 PM PDT 24 Jun 10 07:44:22 PM PDT 24 119552707 ps
T1286 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.1122426268 Jun 10 07:44:08 PM PDT 24 Jun 10 07:44:15 PM PDT 24 1334925171 ps
T1287 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.763219709 Jun 10 07:44:07 PM PDT 24 Jun 10 07:44:11 PM PDT 24 38191604 ps
T1288 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.103370971 Jun 10 07:44:39 PM PDT 24 Jun 10 07:44:45 PM PDT 24 43139536 ps
T1289 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.3016033793 Jun 10 07:44:19 PM PDT 24 Jun 10 07:44:25 PM PDT 24 215599607 ps
T357 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1803624272 Jun 10 07:44:17 PM PDT 24 Jun 10 07:44:33 PM PDT 24 2477155367 ps
T306 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.712414671 Jun 10 07:44:08 PM PDT 24 Jun 10 07:44:15 PM PDT 24 866437448 ps
T307 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1397075208 Jun 10 07:44:19 PM PDT 24 Jun 10 07:44:25 PM PDT 24 1045557050 ps
T1290 /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2538131426 Jun 10 07:44:17 PM PDT 24 Jun 10 07:44:23 PM PDT 24 85856099 ps
T1291 /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.805579245 Jun 10 07:44:33 PM PDT 24 Jun 10 07:44:38 PM PDT 24 137029817 ps
T1292 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.957117394 Jun 10 07:44:30 PM PDT 24 Jun 10 07:44:35 PM PDT 24 72982623 ps
T1293 /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.2611790224 Jun 10 07:44:17 PM PDT 24 Jun 10 07:44:22 PM PDT 24 595917087 ps
T1294 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.3502301531 Jun 10 07:44:32 PM PDT 24 Jun 10 07:44:38 PM PDT 24 52600660 ps
T1295 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2571410882 Jun 10 07:44:03 PM PDT 24 Jun 10 07:44:13 PM PDT 24 101837641 ps
T1296 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.3068116932 Jun 10 07:44:33 PM PDT 24 Jun 10 07:44:38 PM PDT 24 38894515 ps
T1297 /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.973534615 Jun 10 07:44:29 PM PDT 24 Jun 10 07:44:32 PM PDT 24 69618811 ps
T1298 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.992093050 Jun 10 07:44:30 PM PDT 24 Jun 10 07:44:35 PM PDT 24 84990082 ps
T354 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.1259978486 Jun 10 07:44:18 PM PDT 24 Jun 10 07:44:45 PM PDT 24 4569419172 ps
T1299 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.3188361693 Jun 10 07:44:11 PM PDT 24 Jun 10 07:44:25 PM PDT 24 933785567 ps
T1300 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2742439249 Jun 10 07:44:32 PM PDT 24 Jun 10 07:44:38 PM PDT 24 69271051 ps
T1301 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1473695797 Jun 10 07:44:10 PM PDT 24 Jun 10 07:44:32 PM PDT 24 2496106476 ps
T1302 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2980918609 Jun 10 07:44:32 PM PDT 24 Jun 10 07:44:40 PM PDT 24 230059923 ps
T1303 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2049622527 Jun 10 07:44:32 PM PDT 24 Jun 10 07:44:38 PM PDT 24 538049138 ps
T316 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1026843919 Jun 10 07:44:28 PM PDT 24 Jun 10 07:44:31 PM PDT 24 86664508 ps
T1304 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.26253310 Jun 10 07:44:11 PM PDT 24 Jun 10 07:44:17 PM PDT 24 519000138 ps
T1305 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.1253100896 Jun 10 07:44:12 PM PDT 24 Jun 10 07:44:16 PM PDT 24 64949689 ps
T359 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.3962852574 Jun 10 07:44:19 PM PDT 24 Jun 10 07:44:31 PM PDT 24 628038569 ps
T1306 /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.893044442 Jun 10 07:44:34 PM PDT 24 Jun 10 07:44:40 PM PDT 24 41420492 ps
T1307 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2354461614 Jun 10 07:44:31 PM PDT 24 Jun 10 07:44:41 PM PDT 24 617786179 ps
T323 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.3613382853 Jun 10 07:44:11 PM PDT 24 Jun 10 07:44:18 PM PDT 24 1551543822 ps
T1308 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.385583533 Jun 10 07:44:16 PM PDT 24 Jun 10 07:44:21 PM PDT 24 152752193 ps
T1309 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.1060508069 Jun 10 07:44:32 PM PDT 24 Jun 10 07:44:37 PM PDT 24 40072715 ps
T1310 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3101232317 Jun 10 07:44:18 PM PDT 24 Jun 10 07:44:25 PM PDT 24 122114890 ps
T1311 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3556858662 Jun 10 07:44:31 PM PDT 24 Jun 10 07:44:37 PM PDT 24 261432853 ps
T1312 /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.2255492308 Jun 10 07:44:28 PM PDT 24 Jun 10 07:44:31 PM PDT 24 72330114 ps
T1313 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3314127132 Jun 10 07:44:11 PM PDT 24 Jun 10 07:44:16 PM PDT 24 68969653 ps
T1314 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.543804196 Jun 10 07:44:19 PM PDT 24 Jun 10 07:44:23 PM PDT 24 139897494 ps
T358 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.1372053395 Jun 10 07:44:32 PM PDT 24 Jun 10 07:44:55 PM PDT 24 1338225520 ps
T1315 /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.3744930053 Jun 10 07:44:31 PM PDT 24 Jun 10 07:44:38 PM PDT 24 688366926 ps
T1316 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.734087898 Jun 10 07:44:36 PM PDT 24 Jun 10 07:44:43 PM PDT 24 70645753 ps
T1317 /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.486371413 Jun 10 07:44:38 PM PDT 24 Jun 10 07:44:44 PM PDT 24 141167420 ps
T1318 /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1762891836 Jun 10 07:44:31 PM PDT 24 Jun 10 07:44:36 PM PDT 24 158466229 ps
T1319 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.680779276 Jun 10 07:44:17 PM PDT 24 Jun 10 07:44:23 PM PDT 24 236754099 ps
T1320 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3212599030 Jun 10 07:44:17 PM PDT 24 Jun 10 07:44:22 PM PDT 24 80108864 ps
T321 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3308541338 Jun 10 07:44:29 PM PDT 24 Jun 10 07:44:33 PM PDT 24 51582203 ps
T1321 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1408540987 Jun 10 07:44:07 PM PDT 24 Jun 10 07:44:16 PM PDT 24 260667023 ps

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.2716532319
Short name T6
Test name
Test status
Simulation time 84232251310 ps
CPU time 386.32 seconds
Started Jun 10 07:50:31 PM PDT 24
Finished Jun 10 07:57:00 PM PDT 24
Peak memory 265384 kb
Host smart-4cea6f5d-f2e6-4e8c-86ae-64f87a14ff61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716532319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.2716532319
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.3503631305
Short name T5
Test name
Test status
Simulation time 293625568365 ps
CPU time 861.38 seconds
Started Jun 10 07:51:06 PM PDT 24
Finished Jun 10 08:05:30 PM PDT 24
Peak memory 293436 kb
Host smart-75443cf8-6984-4830-ac67-8929f31eb0ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503631305 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.3503631305
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.2794483893
Short name T60
Test name
Test status
Simulation time 32782957218 ps
CPU time 223.15 seconds
Started Jun 10 07:51:42 PM PDT 24
Finished Jun 10 07:55:29 PM PDT 24
Peak memory 262668 kb
Host smart-24e92616-05d4-46cf-8a83-35f9f9707859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794483893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all
.2794483893
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.676040701
Short name T164
Test name
Test status
Simulation time 27892034087 ps
CPU time 226.27 seconds
Started Jun 10 07:50:42 PM PDT 24
Finished Jun 10 07:54:31 PM PDT 24
Peak memory 247792 kb
Host smart-ad36be9a-dc90-4010-bd44-de97e85bb9a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676040701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.
676040701
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.2435835948
Short name T9
Test name
Test status
Simulation time 11517210271 ps
CPU time 190.03 seconds
Started Jun 10 07:49:52 PM PDT 24
Finished Jun 10 07:53:06 PM PDT 24
Peak memory 279000 kb
Host smart-e97a991d-4cfc-46e5-b4d9-dd1d0a199493
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435835948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.2435835948
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.2007759678
Short name T142
Test name
Test status
Simulation time 418430891 ps
CPU time 3.91 seconds
Started Jun 10 07:52:47 PM PDT 24
Finished Jun 10 07:52:54 PM PDT 24
Peak memory 242376 kb
Host smart-e16a32ac-aa30-4e0d-94a7-8e19a8b46a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007759678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2007759678
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.2438470734
Short name T45
Test name
Test status
Simulation time 12141537988 ps
CPU time 16.06 seconds
Started Jun 10 07:50:41 PM PDT 24
Finished Jun 10 07:50:59 PM PDT 24
Peak memory 249180 kb
Host smart-256834ea-24dd-4153-bf36-24ca46243f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438470734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.2438470734
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.313296472
Short name T65
Test name
Test status
Simulation time 191689105469 ps
CPU time 2488.21 seconds
Started Jun 10 07:52:00 PM PDT 24
Finished Jun 10 08:33:32 PM PDT 24
Peak memory 322892 kb
Host smart-1f725e81-f262-4008-9ef7-5f6e86167241
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313296472 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.313296472
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.2840028164
Short name T155
Test name
Test status
Simulation time 34489602150 ps
CPU time 76.6 seconds
Started Jun 10 07:50:53 PM PDT 24
Finished Jun 10 07:52:11 PM PDT 24
Peak memory 256488 kb
Host smart-a98d8372-c6fb-4a04-9855-91ffc74aabdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840028164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.2840028164
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.3388903659
Short name T124
Test name
Test status
Simulation time 21338969688 ps
CPU time 256.82 seconds
Started Jun 10 07:50:34 PM PDT 24
Finished Jun 10 07:54:53 PM PDT 24
Peak memory 257412 kb
Host smart-88ec82c3-0469-431e-b8d4-1aa9a8508ef6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388903659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.3388903659
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.516583849
Short name T38
Test name
Test status
Simulation time 294343407 ps
CPU time 3.95 seconds
Started Jun 10 07:52:33 PM PDT 24
Finished Jun 10 07:52:40 PM PDT 24
Peak memory 242504 kb
Host smart-f876f592-bb0f-4fc3-9080-8e65be195057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516583849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.516583849
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.2123121245
Short name T258
Test name
Test status
Simulation time 1253746972 ps
CPU time 18.99 seconds
Started Jun 10 07:44:11 PM PDT 24
Finished Jun 10 07:44:34 PM PDT 24
Peak memory 238640 kb
Host smart-be6ebf7e-c0f5-40ff-8f2c-06733906e7ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123121245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.2123121245
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.292898671
Short name T24
Test name
Test status
Simulation time 422817114 ps
CPU time 4.49 seconds
Started Jun 10 07:52:20 PM PDT 24
Finished Jun 10 07:52:27 PM PDT 24
Peak memory 242128 kb
Host smart-80fd58ba-c01c-40d9-aee5-4d5074574df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292898671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.292898671
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.1917756881
Short name T63
Test name
Test status
Simulation time 239034469 ps
CPU time 4.61 seconds
Started Jun 10 07:51:56 PM PDT 24
Finished Jun 10 07:52:03 PM PDT 24
Peak memory 242288 kb
Host smart-2fe61a84-c176-4841-8b07-403e9f7edccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917756881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.1917756881
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.2400923212
Short name T153
Test name
Test status
Simulation time 130900305 ps
CPU time 3.73 seconds
Started Jun 10 07:50:14 PM PDT 24
Finished Jun 10 07:50:19 PM PDT 24
Peak memory 242352 kb
Host smart-1be7b718-0e0a-46fa-907d-2e1f293815d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400923212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.2400923212
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.3087251236
Short name T12
Test name
Test status
Simulation time 139701813797 ps
CPU time 1952.01 seconds
Started Jun 10 07:50:16 PM PDT 24
Finished Jun 10 08:22:50 PM PDT 24
Peak memory 319132 kb
Host smart-a55ed569-c7b9-4c78-a1ba-0cf6fc6f6e97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087251236 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.3087251236
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.730494313
Short name T14
Test name
Test status
Simulation time 7674231030 ps
CPU time 176.58 seconds
Started Jun 10 07:50:04 PM PDT 24
Finished Jun 10 07:53:03 PM PDT 24
Peak memory 257436 kb
Host smart-4009d303-01c6-46b6-a60e-5b32a7e7bc68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730494313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.730494313
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.3220159648
Short name T10
Test name
Test status
Simulation time 325744399 ps
CPU time 4.64 seconds
Started Jun 10 07:53:08 PM PDT 24
Finished Jun 10 07:53:16 PM PDT 24
Peak memory 242512 kb
Host smart-a06d5cc7-c52c-46aa-9b12-c78413ecb3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220159648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.3220159648
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.2002479226
Short name T212
Test name
Test status
Simulation time 131923890343 ps
CPU time 296.11 seconds
Started Jun 10 07:51:45 PM PDT 24
Finished Jun 10 07:56:45 PM PDT 24
Peak memory 290220 kb
Host smart-5b409387-6204-447c-b9b1-0a4353e76831
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002479226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.2002479226
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.1430376672
Short name T55
Test name
Test status
Simulation time 4671485690 ps
CPU time 35.72 seconds
Started Jun 10 07:50:16 PM PDT 24
Finished Jun 10 07:50:54 PM PDT 24
Peak memory 244480 kb
Host smart-5a6c82be-cad9-4f80-9156-2855ae76e89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430376672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.1430376672
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.3074220602
Short name T57
Test name
Test status
Simulation time 133680324 ps
CPU time 4.88 seconds
Started Jun 10 07:53:27 PM PDT 24
Finished Jun 10 07:53:33 PM PDT 24
Peak memory 242436 kb
Host smart-6c70a860-0747-4aad-bf33-25cc567d6ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074220602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.3074220602
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2843238995
Short name T264
Test name
Test status
Simulation time 44816008 ps
CPU time 1.61 seconds
Started Jun 10 07:44:19 PM PDT 24
Finished Jun 10 07:44:23 PM PDT 24
Peak memory 240724 kb
Host smart-1cc1910c-71f7-4b05-91b2-74c5887972b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843238995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.2843238995
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.3798532050
Short name T612
Test name
Test status
Simulation time 331112000 ps
CPU time 4.59 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:52:53 PM PDT 24
Peak memory 242160 kb
Host smart-1993c703-48ee-4418-abac-174e7fe05bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798532050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.3798532050
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.266758275
Short name T139
Test name
Test status
Simulation time 137001753 ps
CPU time 4.06 seconds
Started Jun 10 07:52:11 PM PDT 24
Finished Jun 10 07:52:17 PM PDT 24
Peak memory 242208 kb
Host smart-c28da53e-51c3-4bfb-abd0-3c2ee3454000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266758275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.266758275
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.2188838592
Short name T19
Test name
Test status
Simulation time 1445875270011 ps
CPU time 1537.55 seconds
Started Jun 10 07:51:08 PM PDT 24
Finished Jun 10 08:16:47 PM PDT 24
Peak memory 359904 kb
Host smart-9ab04f77-4ea5-42c2-94bf-3b6334f118ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188838592 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.2188838592
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.31013416
Short name T49
Test name
Test status
Simulation time 116662952 ps
CPU time 4.29 seconds
Started Jun 10 07:53:18 PM PDT 24
Finished Jun 10 07:53:25 PM PDT 24
Peak memory 242256 kb
Host smart-6021f37d-6950-4839-aefe-7ca386ef8b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31013416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.31013416
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.3114109637
Short name T62
Test name
Test status
Simulation time 278130104 ps
CPU time 4.23 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:52:52 PM PDT 24
Peak memory 242468 kb
Host smart-827431fe-4bbd-4bd3-b453-358eb149c955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114109637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.3114109637
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.1785921414
Short name T244
Test name
Test status
Simulation time 479550594412 ps
CPU time 1434.2 seconds
Started Jun 10 07:52:13 PM PDT 24
Finished Jun 10 08:16:09 PM PDT 24
Peak memory 317588 kb
Host smart-10aabee1-2b7d-4710-9677-2e0deb907942
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785921414 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.1785921414
Directory /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.267139837
Short name T35
Test name
Test status
Simulation time 2080172300 ps
CPU time 5.69 seconds
Started Jun 10 07:52:58 PM PDT 24
Finished Jun 10 07:53:07 PM PDT 24
Peak memory 242252 kb
Host smart-d4044186-2938-4ad4-b7ec-ec0238785475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267139837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.267139837
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.1187530627
Short name T53
Test name
Test status
Simulation time 181923438 ps
CPU time 4.61 seconds
Started Jun 10 07:52:01 PM PDT 24
Finished Jun 10 07:52:09 PM PDT 24
Peak memory 242516 kb
Host smart-500e0999-c02f-4805-b84b-df391345f3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187530627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.1187530627
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.617652789
Short name T30
Test name
Test status
Simulation time 571667961 ps
CPU time 4.52 seconds
Started Jun 10 07:52:59 PM PDT 24
Finished Jun 10 07:53:07 PM PDT 24
Peak memory 242412 kb
Host smart-918b31ad-d704-4b13-83a6-5b2bc6542fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617652789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.617652789
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.3227725141
Short name T389
Test name
Test status
Simulation time 60550338470 ps
CPU time 325.48 seconds
Started Jun 10 07:51:40 PM PDT 24
Finished Jun 10 07:57:08 PM PDT 24
Peak memory 281992 kb
Host smart-832f37b3-add4-439e-9360-535a1d912ce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227725141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.3227725141
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.1506888110
Short name T403
Test name
Test status
Simulation time 48553984 ps
CPU time 1.66 seconds
Started Jun 10 07:50:14 PM PDT 24
Finished Jun 10 07:50:17 PM PDT 24
Peak memory 240780 kb
Host smart-c3737df5-fcfb-41b3-a5c5-4082589bcbbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506888110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.1506888110
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.1222167716
Short name T22
Test name
Test status
Simulation time 20014853693 ps
CPU time 171.35 seconds
Started Jun 10 07:49:55 PM PDT 24
Finished Jun 10 07:52:49 PM PDT 24
Peak memory 264296 kb
Host smart-edfb31f4-4b7f-4418-a520-624a5f6d4af3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222167716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.1222167716
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.2235404472
Short name T256
Test name
Test status
Simulation time 1063936113 ps
CPU time 17.87 seconds
Started Jun 10 07:52:59 PM PDT 24
Finished Jun 10 07:53:20 PM PDT 24
Peak memory 242316 kb
Host smart-2106e5d2-4832-47f1-9ccf-a5ec86980129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235404472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.2235404472
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.534853898
Short name T118
Test name
Test status
Simulation time 14856902683 ps
CPU time 262.16 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:55:54 PM PDT 24
Peak memory 258128 kb
Host smart-004b7532-bc29-414e-b9a3-38e2defd15f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534853898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.
534853898
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.3425845643
Short name T515
Test name
Test status
Simulation time 5080164455 ps
CPU time 15.1 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:51:47 PM PDT 24
Peak memory 242672 kb
Host smart-3cb6f555-f9ae-4ea1-bc26-f323dcda0814
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3425845643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.3425845643
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.2030575180
Short name T27
Test name
Test status
Simulation time 20053096102 ps
CPU time 46.75 seconds
Started Jun 10 07:50:04 PM PDT 24
Finished Jun 10 07:50:52 PM PDT 24
Peak memory 245164 kb
Host smart-e74e4167-54fc-4fec-8ce2-92a244bcd86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030575180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.2030575180
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.1848646079
Short name T189
Test name
Test status
Simulation time 2225960393 ps
CPU time 11.4 seconds
Started Jun 10 07:51:28 PM PDT 24
Finished Jun 10 07:51:41 PM PDT 24
Peak memory 242520 kb
Host smart-8f60ed2c-000c-4aa3-84c2-b06b9c542148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848646079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.1848646079
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.3523581726
Short name T44
Test name
Test status
Simulation time 415869179 ps
CPU time 13.39 seconds
Started Jun 10 07:51:34 PM PDT 24
Finished Jun 10 07:51:50 PM PDT 24
Peak memory 243164 kb
Host smart-8ec229b3-2c9f-40ea-a2ee-8c1f40d1cc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523581726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.3523581726
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.1362334598
Short name T276
Test name
Test status
Simulation time 267703279836 ps
CPU time 1174.91 seconds
Started Jun 10 07:52:15 PM PDT 24
Finished Jun 10 08:11:52 PM PDT 24
Peak memory 352288 kb
Host smart-62f9444a-272f-4ab6-9f21-4c42cc6efe91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362334598 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.1362334598
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.80867842
Short name T220
Test name
Test status
Simulation time 1382798801 ps
CPU time 18.57 seconds
Started Jun 10 07:52:26 PM PDT 24
Finished Jun 10 07:52:47 PM PDT 24
Peak memory 242472 kb
Host smart-403c1f1e-1201-4487-9254-4d924d578485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80867842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.80867842
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.4199041487
Short name T108
Test name
Test status
Simulation time 2394697894 ps
CPU time 8.51 seconds
Started Jun 10 07:52:12 PM PDT 24
Finished Jun 10 07:52:22 PM PDT 24
Peak memory 242124 kb
Host smart-927ae02a-0208-447e-aafd-716a2c26621b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199041487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.4199041487
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.611184584
Short name T214
Test name
Test status
Simulation time 19517834472 ps
CPU time 239.07 seconds
Started Jun 10 07:49:56 PM PDT 24
Finished Jun 10 07:53:58 PM PDT 24
Peak memory 263464 kb
Host smart-88917e17-5de4-4460-a001-ae70be5faf19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611184584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.611184584
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2272769477
Short name T257
Test name
Test status
Simulation time 1203500362 ps
CPU time 11.26 seconds
Started Jun 10 07:44:33 PM PDT 24
Finished Jun 10 07:44:48 PM PDT 24
Peak memory 238568 kb
Host smart-bd85fa53-a933-4644-b386-dec97fe0508b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272769477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.2272769477
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.969053731
Short name T218
Test name
Test status
Simulation time 585680871 ps
CPU time 7.12 seconds
Started Jun 10 07:52:34 PM PDT 24
Finished Jun 10 07:52:44 PM PDT 24
Peak memory 242140 kb
Host smart-28a59a37-75c8-41a8-9f5d-f307738292ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969053731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.969053731
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.1081732137
Short name T37
Test name
Test status
Simulation time 293014219 ps
CPU time 4.27 seconds
Started Jun 10 07:52:44 PM PDT 24
Finished Jun 10 07:52:51 PM PDT 24
Peak memory 242328 kb
Host smart-8eb97c86-7ce7-49e0-8642-67fe6372a8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081732137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.1081732137
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.1910033777
Short name T233
Test name
Test status
Simulation time 338207493 ps
CPU time 8.35 seconds
Started Jun 10 07:50:55 PM PDT 24
Finished Jun 10 07:51:07 PM PDT 24
Peak memory 242004 kb
Host smart-fcd8dcdc-0fa2-49be-ad2e-fa59ee5281e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910033777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.1910033777
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.1707705326
Short name T254
Test name
Test status
Simulation time 2162048057 ps
CPU time 27.26 seconds
Started Jun 10 07:50:53 PM PDT 24
Finished Jun 10 07:51:23 PM PDT 24
Peak memory 241964 kb
Host smart-97c5291e-d881-4aca-9e0b-4e7c90223990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707705326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.1707705326
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.1605209332
Short name T127
Test name
Test status
Simulation time 125342871320 ps
CPU time 1785.97 seconds
Started Jun 10 07:52:25 PM PDT 24
Finished Jun 10 08:22:14 PM PDT 24
Peak memory 345768 kb
Host smart-154e75ab-8969-4e48-b89a-d3177207c13c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605209332 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.1605209332
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.2969163740
Short name T187
Test name
Test status
Simulation time 411025564 ps
CPU time 6.01 seconds
Started Jun 10 07:52:24 PM PDT 24
Finished Jun 10 07:52:33 PM PDT 24
Peak memory 242240 kb
Host smart-4658812e-783e-4429-888b-900b698bc2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969163740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.2969163740
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.731689282
Short name T222
Test name
Test status
Simulation time 596439880142 ps
CPU time 3369.32 seconds
Started Jun 10 07:52:22 PM PDT 24
Finished Jun 10 08:48:36 PM PDT 24
Peak memory 397484 kb
Host smart-e3e6a0b7-d8cd-47b6-8d99-bc5d1224c0e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731689282 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.731689282
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.3477271150
Short name T1152
Test name
Test status
Simulation time 918560080 ps
CPU time 22.59 seconds
Started Jun 10 07:50:32 PM PDT 24
Finished Jun 10 07:50:56 PM PDT 24
Peak memory 249092 kb
Host smart-edc4e059-ce74-4a33-b018-57682d46663a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477271150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.3477271150
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.2300033292
Short name T365
Test name
Test status
Simulation time 221706005 ps
CPU time 7.44 seconds
Started Jun 10 07:50:19 PM PDT 24
Finished Jun 10 07:50:28 PM PDT 24
Peak memory 241752 kb
Host smart-9d5d12fb-e3f5-4dde-904b-bda7d8232008
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2300033292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.2300033292
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.1878063962
Short name T39
Test name
Test status
Simulation time 3802131147 ps
CPU time 39.29 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:52:10 PM PDT 24
Peak memory 244084 kb
Host smart-7342de7f-868e-4820-99e8-d5bbda06b02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878063962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.1878063962
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.891259200
Short name T83
Test name
Test status
Simulation time 329793848 ps
CPU time 4.19 seconds
Started Jun 10 07:53:16 PM PDT 24
Finished Jun 10 07:53:22 PM PDT 24
Peak memory 242504 kb
Host smart-4e15fdd6-05ef-420d-a821-7e23227bc183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891259200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.891259200
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.1372053395
Short name T358
Test name
Test status
Simulation time 1338225520 ps
CPU time 19.7 seconds
Started Jun 10 07:44:32 PM PDT 24
Finished Jun 10 07:44:55 PM PDT 24
Peak memory 238568 kb
Host smart-a8c5c032-970a-43e8-83dd-0110bb1ad311
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372053395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.1372053395
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.1259978486
Short name T354
Test name
Test status
Simulation time 4569419172 ps
CPU time 23.65 seconds
Started Jun 10 07:44:18 PM PDT 24
Finished Jun 10 07:44:45 PM PDT 24
Peak memory 238664 kb
Host smart-863023c9-c745-41b6-9c97-66fcbafe1ded
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259978486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.1259978486
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.468281763
Short name T253
Test name
Test status
Simulation time 366401586 ps
CPU time 12.12 seconds
Started Jun 10 07:49:44 PM PDT 24
Finished Jun 10 07:49:59 PM PDT 24
Peak memory 242336 kb
Host smart-5e13e729-9314-438d-a69c-c7c1c6f5019f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=468281763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.468281763
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.2286099498
Short name T670
Test name
Test status
Simulation time 3601157062 ps
CPU time 47.49 seconds
Started Jun 10 07:51:15 PM PDT 24
Finished Jun 10 07:52:04 PM PDT 24
Peak memory 257344 kb
Host smart-19bce56e-0319-49f5-b711-5f78c5742fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286099498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.2286099498
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.681536509
Short name T656
Test name
Test status
Simulation time 24508750777 ps
CPU time 260.33 seconds
Started Jun 10 07:51:16 PM PDT 24
Finished Jun 10 07:55:39 PM PDT 24
Peak memory 257536 kb
Host smart-1e8fb80b-ae45-4562-a944-e5425697534a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681536509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.
681536509
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.1900891754
Short name T87
Test name
Test status
Simulation time 539410591 ps
CPU time 4.84 seconds
Started Jun 10 07:52:21 PM PDT 24
Finished Jun 10 07:52:29 PM PDT 24
Peak memory 242152 kb
Host smart-3e9b430e-267d-4cf8-a1b9-d4ec1485ebb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900891754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.1900891754
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.3627295022
Short name T250
Test name
Test status
Simulation time 147488121 ps
CPU time 3.96 seconds
Started Jun 10 07:53:18 PM PDT 24
Finished Jun 10 07:53:25 PM PDT 24
Peak memory 242604 kb
Host smart-696fcdab-3094-4b1d-8f9c-158ca88a759c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627295022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.3627295022
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.212246918
Short name T248
Test name
Test status
Simulation time 299410270 ps
CPU time 4.18 seconds
Started Jun 10 07:52:58 PM PDT 24
Finished Jun 10 07:53:05 PM PDT 24
Peak memory 242152 kb
Host smart-7b940cef-39c6-40a8-8dd0-4b0b293fcc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212246918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.212246918
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.2506895503
Short name T51
Test name
Test status
Simulation time 1086860938 ps
CPU time 13.02 seconds
Started Jun 10 07:51:15 PM PDT 24
Finished Jun 10 07:51:30 PM PDT 24
Peak memory 242828 kb
Host smart-d2428848-b200-4bda-b0a9-431340551a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506895503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.2506895503
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.1106233719
Short name T210
Test name
Test status
Simulation time 144599226 ps
CPU time 3.63 seconds
Started Jun 10 07:52:34 PM PDT 24
Finished Jun 10 07:52:40 PM PDT 24
Peak memory 242352 kb
Host smart-44493882-6d70-4575-9af5-5e8be4d6d565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106233719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.1106233719
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.3257437281
Short name T125
Test name
Test status
Simulation time 322857826 ps
CPU time 4.69 seconds
Started Jun 10 07:52:35 PM PDT 24
Finished Jun 10 07:52:42 PM PDT 24
Peak memory 242504 kb
Host smart-8c4bf323-bea4-41be-8f4f-ac80d62703cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257437281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.3257437281
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.436103307
Short name T151
Test name
Test status
Simulation time 114341347 ps
CPU time 3.57 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:52:52 PM PDT 24
Peak memory 242348 kb
Host smart-965ea9e0-2711-44c2-a2d2-0ff87a410771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436103307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.436103307
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.3787285216
Short name T349
Test name
Test status
Simulation time 2489660746 ps
CPU time 13.87 seconds
Started Jun 10 07:44:32 PM PDT 24
Finished Jun 10 07:44:49 PM PDT 24
Peak memory 243536 kb
Host smart-ced7c864-1297-47f1-bead-3e135b05ce42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787285216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.3787285216
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.2636888545
Short name T372
Test name
Test status
Simulation time 4315289417 ps
CPU time 12.25 seconds
Started Jun 10 07:49:54 PM PDT 24
Finished Jun 10 07:50:09 PM PDT 24
Peak memory 242320 kb
Host smart-7b9cfe0e-1e43-44f7-a4c3-c22a1ca281a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2636888545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.2636888545
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.1303296577
Short name T400
Test name
Test status
Simulation time 92366457288 ps
CPU time 1381.41 seconds
Started Jun 10 07:52:20 PM PDT 24
Finished Jun 10 08:15:25 PM PDT 24
Peak memory 271476 kb
Host smart-e731d45c-405d-4dab-b8cb-0e48e6683ffd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303296577 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.1303296577
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.2246803587
Short name T238
Test name
Test status
Simulation time 103771469 ps
CPU time 1.74 seconds
Started Jun 10 07:49:44 PM PDT 24
Finished Jun 10 07:49:50 PM PDT 24
Peak memory 240728 kb
Host smart-ad9824e8-9c81-48a9-b8d6-7bad26c0393b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2246803587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.2246803587
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.117341542
Short name T397
Test name
Test status
Simulation time 32788956948 ps
CPU time 241.42 seconds
Started Jun 10 07:50:33 PM PDT 24
Finished Jun 10 07:54:36 PM PDT 24
Peak memory 257400 kb
Host smart-a8628a41-7033-4bca-a90c-b02fca2ca49f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117341542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.
117341542
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.3190621650
Short name T216
Test name
Test status
Simulation time 322652468301 ps
CPU time 1166.72 seconds
Started Jun 10 07:51:34 PM PDT 24
Finished Jun 10 08:11:04 PM PDT 24
Peak memory 265708 kb
Host smart-39e3411c-83e8-4368-a26d-751316909c09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190621650 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.3190621650
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.3295385857
Short name T116
Test name
Test status
Simulation time 1863377195 ps
CPU time 17.51 seconds
Started Jun 10 07:50:26 PM PDT 24
Finished Jun 10 07:50:46 PM PDT 24
Peak memory 242516 kb
Host smart-07a5a3e6-0cec-43a1-8883-1edf1ecb3961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295385857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.3295385857
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3994112514
Short name T267
Test name
Test status
Simulation time 1280299372 ps
CPU time 20.79 seconds
Started Jun 10 07:44:30 PM PDT 24
Finished Jun 10 07:44:54 PM PDT 24
Peak memory 243480 kb
Host smart-1919bc82-05d3-435a-b465-d503d06e8598
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994112514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.3994112514
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2403315536
Short name T268
Test name
Test status
Simulation time 981507989 ps
CPU time 11.76 seconds
Started Jun 10 07:44:31 PM PDT 24
Finished Jun 10 07:44:46 PM PDT 24
Peak memory 243280 kb
Host smart-cff9e764-1c2f-4c84-965f-40379722791f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403315536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.2403315536
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.1950780472
Short name T102
Test name
Test status
Simulation time 5369229277 ps
CPU time 30.87 seconds
Started Jun 10 07:50:42 PM PDT 24
Finished Jun 10 07:51:15 PM PDT 24
Peak memory 242640 kb
Host smart-0dcb2bae-cfbb-4c73-8f15-0e5369f9b6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950780472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.1950780472
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.3523089089
Short name T77
Test name
Test status
Simulation time 293633893 ps
CPU time 4.24 seconds
Started Jun 10 07:53:18 PM PDT 24
Finished Jun 10 07:53:24 PM PDT 24
Peak memory 242636 kb
Host smart-c611c46b-1ce0-4584-8a59-91ec24e9f7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523089089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.3523089089
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.3810827673
Short name T969
Test name
Test status
Simulation time 10881361146 ps
CPU time 26.28 seconds
Started Jun 10 07:50:31 PM PDT 24
Finished Jun 10 07:50:59 PM PDT 24
Peak memory 243316 kb
Host smart-de35787a-ba1d-4b71-9abe-d378cc7c9010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810827673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.3810827673
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.1648887817
Short name T76
Test name
Test status
Simulation time 191766878 ps
CPU time 4.42 seconds
Started Jun 10 07:52:28 PM PDT 24
Finished Jun 10 07:52:34 PM PDT 24
Peak memory 242152 kb
Host smart-91e2b8b0-68ab-49d4-b4db-42f489a1ea26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648887817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.1648887817
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.1450825648
Short name T383
Test name
Test status
Simulation time 1049314661 ps
CPU time 14.71 seconds
Started Jun 10 07:49:53 PM PDT 24
Finished Jun 10 07:50:11 PM PDT 24
Peak memory 242108 kb
Host smart-35660825-8e20-483e-ad88-fd0b994204bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1450825648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.1450825648
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.3441905076
Short name T477
Test name
Test status
Simulation time 15208822474 ps
CPU time 35.43 seconds
Started Jun 10 07:51:09 PM PDT 24
Finished Jun 10 07:51:46 PM PDT 24
Peak memory 249064 kb
Host smart-022d0c56-893b-4af3-98eb-0664bec70c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441905076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.3441905076
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.590289072
Short name T1245
Test name
Test status
Simulation time 1588033134 ps
CPU time 4.55 seconds
Started Jun 10 07:44:10 PM PDT 24
Finished Jun 10 07:44:17 PM PDT 24
Peak memory 238484 kb
Host smart-cc96e6a4-f65e-4ac8-ab05-1d8df2ad97b6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590289072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alias
ing.590289072
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2488768534
Short name T262
Test name
Test status
Simulation time 745151712 ps
CPU time 6.14 seconds
Started Jun 10 07:44:08 PM PDT 24
Finished Jun 10 07:44:17 PM PDT 24
Peak memory 240060 kb
Host smart-08b1b15f-2988-4db8-99a9-f66da90cffbe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488768534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.2488768534
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1934561250
Short name T1212
Test name
Test status
Simulation time 76148394 ps
CPU time 1.95 seconds
Started Jun 10 07:44:16 PM PDT 24
Finished Jun 10 07:44:21 PM PDT 24
Peak memory 240248 kb
Host smart-ae8e7699-a66b-41f6-8388-48290ea16be9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934561250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r
eset.1934561250
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.32265559
Short name T1205
Test name
Test status
Simulation time 192469521 ps
CPU time 3.48 seconds
Started Jun 10 07:44:07 PM PDT 24
Finished Jun 10 07:44:14 PM PDT 24
Peak memory 246756 kb
Host smart-8a81e6d2-5a89-4bf5-a49e-81c4dad3a68c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32265559 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.32265559
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1160133859
Short name T1252
Test name
Test status
Simulation time 157874726 ps
CPU time 1.56 seconds
Started Jun 10 07:44:10 PM PDT 24
Finished Jun 10 07:44:15 PM PDT 24
Peak memory 240548 kb
Host smart-0c9eed0b-3db3-4e2a-af33-c3f61ec8165e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160133859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.1160133859
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2111049455
Short name T1214
Test name
Test status
Simulation time 115687026 ps
CPU time 1.47 seconds
Started Jun 10 07:44:09 PM PDT 24
Finished Jun 10 07:44:14 PM PDT 24
Peak memory 229560 kb
Host smart-e59411c6-0ad1-4c9f-bfec-7866e1eed566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111049455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.2111049455
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.256201123
Short name T1221
Test name
Test status
Simulation time 39071545 ps
CPU time 1.32 seconds
Started Jun 10 07:44:16 PM PDT 24
Finished Jun 10 07:44:20 PM PDT 24
Peak memory 229352 kb
Host smart-0f3412b1-708a-4617-8a95-47b16969c69d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256201123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl
_mem_partial_access.256201123
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.248739963
Short name T1222
Test name
Test status
Simulation time 70316194 ps
CPU time 1.38 seconds
Started Jun 10 07:44:10 PM PDT 24
Finished Jun 10 07:44:15 PM PDT 24
Peak memory 229316 kb
Host smart-6b7a7418-8107-411f-be8e-91b0355be07e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248739963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.
248739963
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.2827786368
Short name T325
Test name
Test status
Simulation time 98561778 ps
CPU time 1.99 seconds
Started Jun 10 07:44:17 PM PDT 24
Finished Jun 10 07:44:22 PM PDT 24
Peak memory 238572 kb
Host smart-1dc56ce6-e732-40d5-b33d-58d86007800a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827786368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.2827786368
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2571410882
Short name T1295
Test name
Test status
Simulation time 101837641 ps
CPU time 5.62 seconds
Started Jun 10 07:44:03 PM PDT 24
Finished Jun 10 07:44:13 PM PDT 24
Peak memory 245712 kb
Host smart-09390884-72db-4a91-bee2-71b867422132
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571410882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.2571410882
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1473695797
Short name T1301
Test name
Test status
Simulation time 2496106476 ps
CPU time 19.16 seconds
Started Jun 10 07:44:10 PM PDT 24
Finished Jun 10 07:44:32 PM PDT 24
Peak memory 238640 kb
Host smart-a66af5b6-79c8-4503-804d-753111a0dc83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473695797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.1473695797
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.3613382853
Short name T323
Test name
Test status
Simulation time 1551543822 ps
CPU time 4.66 seconds
Started Jun 10 07:44:11 PM PDT 24
Finished Jun 10 07:44:18 PM PDT 24
Peak memory 238432 kb
Host smart-d2d65221-d110-4f06-987b-ba22f3b58651
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613382853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia
sing.3613382853
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2566511847
Short name T260
Test name
Test status
Simulation time 1975475393 ps
CPU time 9.21 seconds
Started Jun 10 07:44:17 PM PDT 24
Finished Jun 10 07:44:30 PM PDT 24
Peak memory 238468 kb
Host smart-4c7d3f2a-4777-47cd-b82f-16ea051ac82c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566511847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_
bash.2566511847
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.835943347
Short name T1203
Test name
Test status
Simulation time 267077808 ps
CPU time 2.05 seconds
Started Jun 10 07:44:08 PM PDT 24
Finished Jun 10 07:44:14 PM PDT 24
Peak memory 240268 kb
Host smart-e0fd7b2e-f29f-4420-8471-28001f254638
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835943347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_re
set.835943347
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.2219027019
Short name T1199
Test name
Test status
Simulation time 67951069 ps
CPU time 2.05 seconds
Started Jun 10 07:44:05 PM PDT 24
Finished Jun 10 07:44:11 PM PDT 24
Peak memory 244648 kb
Host smart-b45f0e0b-9a2f-49ff-9695-9004fcfaba86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219027019 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.2219027019
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2896313127
Short name T1238
Test name
Test status
Simulation time 140527230 ps
CPU time 1.52 seconds
Started Jun 10 07:44:17 PM PDT 24
Finished Jun 10 07:44:21 PM PDT 24
Peak memory 240032 kb
Host smart-87c7ec06-7a7e-4726-8a8f-40eab9dc7ddc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896313127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.2896313127
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.2672302925
Short name T1209
Test name
Test status
Simulation time 80837404 ps
CPU time 1.51 seconds
Started Jun 10 07:44:08 PM PDT 24
Finished Jun 10 07:44:13 PM PDT 24
Peak memory 230336 kb
Host smart-05d467ba-4064-455d-86a5-fd185930f81b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672302925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.2672302925
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.763219709
Short name T1287
Test name
Test status
Simulation time 38191604 ps
CPU time 1.36 seconds
Started Jun 10 07:44:07 PM PDT 24
Finished Jun 10 07:44:11 PM PDT 24
Peak memory 229320 kb
Host smart-6a19dff1-f4ea-4dd1-b812-3e02e8fb1377
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763219709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl
_mem_partial_access.763219709
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.1253100896
Short name T1305
Test name
Test status
Simulation time 64949689 ps
CPU time 1.39 seconds
Started Jun 10 07:44:12 PM PDT 24
Finished Jun 10 07:44:16 PM PDT 24
Peak memory 230224 kb
Host smart-381896fb-4cf8-49af-be0f-24dbcf115f15
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253100896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.1253100896
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.3434639008
Short name T324
Test name
Test status
Simulation time 694039337 ps
CPU time 1.9 seconds
Started Jun 10 07:44:16 PM PDT 24
Finished Jun 10 07:44:21 PM PDT 24
Peak memory 241476 kb
Host smart-15d81d2d-4b54-4410-9e7c-0b21c59987ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434639008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.3434639008
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2682938587
Short name T1276
Test name
Test status
Simulation time 137917094 ps
CPU time 3.22 seconds
Started Jun 10 07:44:16 PM PDT 24
Finished Jun 10 07:44:22 PM PDT 24
Peak memory 245656 kb
Host smart-7e596b6b-97be-40a0-8a51-32522f046340
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682938587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.2682938587
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2575520438
Short name T265
Test name
Test status
Simulation time 94153742 ps
CPU time 2.97 seconds
Started Jun 10 07:44:31 PM PDT 24
Finished Jun 10 07:44:38 PM PDT 24
Peak memory 246844 kb
Host smart-f21fbad1-55ea-47bd-b636-7c9a730505f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575520438 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.2575520438
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.721303204
Short name T315
Test name
Test status
Simulation time 81754621 ps
CPU time 1.63 seconds
Started Jun 10 07:44:32 PM PDT 24
Finished Jun 10 07:44:38 PM PDT 24
Peak memory 240140 kb
Host smart-cf4cac5f-a070-4cce-918c-436c4f12f043
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721303204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.721303204
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.2264110875
Short name T1257
Test name
Test status
Simulation time 130452420 ps
CPU time 1.41 seconds
Started Jun 10 07:44:29 PM PDT 24
Finished Jun 10 07:44:33 PM PDT 24
Peak memory 229920 kb
Host smart-0c7e25b5-ff5f-4bf9-97f7-b3ad14ba2f2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264110875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.2264110875
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1953519963
Short name T1260
Test name
Test status
Simulation time 274949732 ps
CPU time 3.46 seconds
Started Jun 10 07:44:30 PM PDT 24
Finished Jun 10 07:44:36 PM PDT 24
Peak memory 238656 kb
Host smart-4c24f1a8-e297-4ea4-803f-6cad375463cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953519963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.1953519963
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3910572362
Short name T1258
Test name
Test status
Simulation time 110457271 ps
CPU time 3.21 seconds
Started Jun 10 07:44:28 PM PDT 24
Finished Jun 10 07:44:32 PM PDT 24
Peak memory 245480 kb
Host smart-c0a86e36-d363-498a-8aa1-369b583476da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910572362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.3910572362
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2017557224
Short name T1259
Test name
Test status
Simulation time 1295230014 ps
CPU time 20.03 seconds
Started Jun 10 07:44:30 PM PDT 24
Finished Jun 10 07:44:52 PM PDT 24
Peak memory 238524 kb
Host smart-6bda745a-5ea3-4254-97ed-34ec133ebc75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017557224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.2017557224
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1235867139
Short name T1244
Test name
Test status
Simulation time 428182738 ps
CPU time 2.84 seconds
Started Jun 10 07:44:33 PM PDT 24
Finished Jun 10 07:44:40 PM PDT 24
Peak memory 246748 kb
Host smart-e950847a-f2fe-42c3-b9c0-647d65c03689
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235867139 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.1235867139
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.992093050
Short name T1298
Test name
Test status
Simulation time 84990082 ps
CPU time 1.8 seconds
Started Jun 10 07:44:30 PM PDT 24
Finished Jun 10 07:44:35 PM PDT 24
Peak memory 238508 kb
Host smart-9f666918-6b2d-48ee-812a-79c7a54d6e63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992093050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.992093050
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.973534615
Short name T1297
Test name
Test status
Simulation time 69618811 ps
CPU time 1.46 seconds
Started Jun 10 07:44:29 PM PDT 24
Finished Jun 10 07:44:32 PM PDT 24
Peak memory 229884 kb
Host smart-28a81705-aad3-4bf0-a227-1cac0661f714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973534615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.973534615
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.83045015
Short name T1235
Test name
Test status
Simulation time 1917717386 ps
CPU time 4.04 seconds
Started Jun 10 07:44:30 PM PDT 24
Finished Jun 10 07:44:36 PM PDT 24
Peak memory 241624 kb
Host smart-79a2c4bf-af50-4d2d-b4b1-8f52b072c598
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83045015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ct
rl_same_csr_outstanding.83045015
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3699288596
Short name T1220
Test name
Test status
Simulation time 258292998 ps
CPU time 5.22 seconds
Started Jun 10 07:44:28 PM PDT 24
Finished Jun 10 07:44:35 PM PDT 24
Peak memory 246512 kb
Host smart-1739ee2e-6318-4037-8745-a9897c75f37d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699288596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.3699288596
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.823485548
Short name T1201
Test name
Test status
Simulation time 1693209605 ps
CPU time 7.17 seconds
Started Jun 10 07:44:29 PM PDT 24
Finished Jun 10 07:44:39 PM PDT 24
Peak memory 246784 kb
Host smart-7fec9f19-8db3-4a2a-9053-93e9f1afba5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823485548 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.823485548
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1026843919
Short name T316
Test name
Test status
Simulation time 86664508 ps
CPU time 1.7 seconds
Started Jun 10 07:44:28 PM PDT 24
Finished Jun 10 07:44:31 PM PDT 24
Peak memory 240568 kb
Host smart-1ff849ac-3ffb-4be1-b917-68b447988ccc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026843919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.1026843919
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2371364687
Short name T1195
Test name
Test status
Simulation time 68139360 ps
CPU time 1.45 seconds
Started Jun 10 07:44:27 PM PDT 24
Finished Jun 10 07:44:29 PM PDT 24
Peak memory 229656 kb
Host smart-fddc0cbc-a252-4736-ba1a-bcdaa35d93e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371364687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.2371364687
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.3020988819
Short name T1241
Test name
Test status
Simulation time 228918501 ps
CPU time 3.08 seconds
Started Jun 10 07:44:31 PM PDT 24
Finished Jun 10 07:44:37 PM PDT 24
Peak memory 238488 kb
Host smart-a4fc4c2e-4646-484a-bf11-f7822754e8f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020988819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.3020988819
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3823030825
Short name T1228
Test name
Test status
Simulation time 133957462 ps
CPU time 5.47 seconds
Started Jun 10 07:44:32 PM PDT 24
Finished Jun 10 07:44:41 PM PDT 24
Peak memory 245552 kb
Host smart-0f1da3ed-f0c4-4865-821c-b5dc520149c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823030825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.3823030825
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.90951913
Short name T319
Test name
Test status
Simulation time 48941627 ps
CPU time 1.63 seconds
Started Jun 10 07:44:34 PM PDT 24
Finished Jun 10 07:44:39 PM PDT 24
Peak memory 238572 kb
Host smart-bb04a355-a58b-497f-a6c9-7f0c4e0d12b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90951913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.90951913
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.1276249733
Short name T1254
Test name
Test status
Simulation time 41762012 ps
CPU time 1.44 seconds
Started Jun 10 07:44:29 PM PDT 24
Finished Jun 10 07:44:33 PM PDT 24
Peak memory 229864 kb
Host smart-6daebb8e-5003-483f-8b1a-a412be98bfb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276249733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.1276249733
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1762891836
Short name T1318
Test name
Test status
Simulation time 158466229 ps
CPU time 2.66 seconds
Started Jun 10 07:44:31 PM PDT 24
Finished Jun 10 07:44:36 PM PDT 24
Peak memory 238604 kb
Host smart-8512f389-cf3b-44f8-a95d-2dfab41f29e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762891836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.1762891836
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2354461614
Short name T1307
Test name
Test status
Simulation time 617786179 ps
CPU time 5.64 seconds
Started Jun 10 07:44:31 PM PDT 24
Finished Jun 10 07:44:41 PM PDT 24
Peak memory 245548 kb
Host smart-13ea4a3d-5fca-4e3c-977c-9871f27ff6b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354461614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.2354461614
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.2835954782
Short name T356
Test name
Test status
Simulation time 5041532911 ps
CPU time 20.15 seconds
Started Jun 10 07:44:28 PM PDT 24
Finished Jun 10 07:44:50 PM PDT 24
Peak memory 244240 kb
Host smart-3abbd638-fea1-4b1c-9d6e-fb32a9bb44ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835954782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.2835954782
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2980918609
Short name T1302
Test name
Test status
Simulation time 230059923 ps
CPU time 3.6 seconds
Started Jun 10 07:44:32 PM PDT 24
Finished Jun 10 07:44:40 PM PDT 24
Peak memory 246832 kb
Host smart-7f5ad091-1dbe-4078-9146-c33ab1c0cb45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980918609 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.2980918609
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1097555676
Short name T318
Test name
Test status
Simulation time 104229195 ps
CPU time 1.68 seconds
Started Jun 10 07:44:31 PM PDT 24
Finished Jun 10 07:44:36 PM PDT 24
Peak memory 240760 kb
Host smart-854f4f15-5a8e-4a1b-9e13-1725562a56e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097555676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.1097555676
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2703640578
Short name T1219
Test name
Test status
Simulation time 43562851 ps
CPU time 1.55 seconds
Started Jun 10 07:44:31 PM PDT 24
Finished Jun 10 07:44:36 PM PDT 24
Peak memory 229544 kb
Host smart-698ce517-80ec-4e86-9666-d97c5a7d93ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703640578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.2703640578
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.3744930053
Short name T1315
Test name
Test status
Simulation time 688366926 ps
CPU time 2.78 seconds
Started Jun 10 07:44:31 PM PDT 24
Finished Jun 10 07:44:38 PM PDT 24
Peak memory 241432 kb
Host smart-b260f51e-219b-436d-8d6c-41275795128e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744930053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.3744930053
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3882142575
Short name T1277
Test name
Test status
Simulation time 1471818746 ps
CPU time 3.54 seconds
Started Jun 10 07:44:31 PM PDT 24
Finished Jun 10 07:44:37 PM PDT 24
Peak memory 245300 kb
Host smart-eed678f1-d961-45d5-b707-fd388e9fcba3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882142575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.3882142575
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3503131829
Short name T263
Test name
Test status
Simulation time 97826170 ps
CPU time 3.25 seconds
Started Jun 10 07:44:31 PM PDT 24
Finished Jun 10 07:44:37 PM PDT 24
Peak memory 246872 kb
Host smart-87dc74d6-dea8-4c37-8f88-14dfc35f5b5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503131829 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.3503131829
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3308541338
Short name T321
Test name
Test status
Simulation time 51582203 ps
CPU time 1.73 seconds
Started Jun 10 07:44:29 PM PDT 24
Finished Jun 10 07:44:33 PM PDT 24
Peak memory 238484 kb
Host smart-554c983e-19c0-4dc9-8588-7f5f506e1096
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308541338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.3308541338
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.2757634093
Short name T1218
Test name
Test status
Simulation time 511985840 ps
CPU time 1.98 seconds
Started Jun 10 07:44:31 PM PDT 24
Finished Jun 10 07:44:36 PM PDT 24
Peak memory 229628 kb
Host smart-abd1a8c3-0aac-418c-a510-1319dc2c4e83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757634093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.2757634093
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.997153936
Short name T330
Test name
Test status
Simulation time 233481634 ps
CPU time 2.32 seconds
Started Jun 10 07:44:31 PM PDT 24
Finished Jun 10 07:44:36 PM PDT 24
Peak memory 238532 kb
Host smart-44592aea-b75d-4da6-a73a-41a2145bb3ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997153936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_c
trl_same_csr_outstanding.997153936
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1854157020
Short name T1224
Test name
Test status
Simulation time 91442632 ps
CPU time 5.06 seconds
Started Jun 10 07:44:30 PM PDT 24
Finished Jun 10 07:44:37 PM PDT 24
Peak memory 245752 kb
Host smart-b1522a4b-2a0f-42ab-b603-6f89793c3a8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854157020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.1854157020
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2669097660
Short name T1264
Test name
Test status
Simulation time 2586130958 ps
CPU time 12.58 seconds
Started Jun 10 07:44:29 PM PDT 24
Finished Jun 10 07:44:43 PM PDT 24
Peak memory 243652 kb
Host smart-07a82d30-cd76-420e-a5f2-625f70afb960
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669097660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i
ntg_err.2669097660
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.4264407707
Short name T1253
Test name
Test status
Simulation time 199058287 ps
CPU time 3.54 seconds
Started Jun 10 07:44:33 PM PDT 24
Finished Jun 10 07:44:41 PM PDT 24
Peak memory 246780 kb
Host smart-98fdbeb0-2d50-443f-b638-a18d8e728882
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264407707 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.4264407707
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3771396126
Short name T1280
Test name
Test status
Simulation time 49240546 ps
CPU time 1.57 seconds
Started Jun 10 07:44:28 PM PDT 24
Finished Jun 10 07:44:30 PM PDT 24
Peak memory 240220 kb
Host smart-1700a7fa-3325-4d87-95c6-e0182975bebc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771396126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.3771396126
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.1691070044
Short name T1265
Test name
Test status
Simulation time 47009059 ps
CPU time 1.46 seconds
Started Jun 10 07:44:29 PM PDT 24
Finished Jun 10 07:44:32 PM PDT 24
Peak memory 229524 kb
Host smart-d9b22bb0-a588-4eaa-b75f-4d37630cf410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691070044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.1691070044
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.2055779080
Short name T1246
Test name
Test status
Simulation time 111412694 ps
CPU time 2.92 seconds
Started Jun 10 07:44:29 PM PDT 24
Finished Jun 10 07:44:34 PM PDT 24
Peak memory 238540 kb
Host smart-8d8662e4-fba7-49fd-9a44-a6cb31df8ee6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055779080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_
ctrl_same_csr_outstanding.2055779080
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.162954541
Short name T1211
Test name
Test status
Simulation time 146318472 ps
CPU time 5.22 seconds
Started Jun 10 07:44:27 PM PDT 24
Finished Jun 10 07:44:33 PM PDT 24
Peak memory 245756 kb
Host smart-eab0128e-e3d3-4216-82ad-c592e7f639b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162954541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.162954541
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3556858662
Short name T1311
Test name
Test status
Simulation time 261432853 ps
CPU time 2.25 seconds
Started Jun 10 07:44:31 PM PDT 24
Finished Jun 10 07:44:37 PM PDT 24
Peak memory 244412 kb
Host smart-407e544f-6405-419d-84d7-195d6ac2ec25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556858662 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.3556858662
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.1977085741
Short name T305
Test name
Test status
Simulation time 143113337 ps
CPU time 1.56 seconds
Started Jun 10 07:44:32 PM PDT 24
Finished Jun 10 07:44:37 PM PDT 24
Peak memory 240600 kb
Host smart-fca09313-1ffc-4fba-9f18-3bb1909b338b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977085741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.1977085741
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2049622527
Short name T1303
Test name
Test status
Simulation time 538049138 ps
CPU time 1.49 seconds
Started Jun 10 07:44:32 PM PDT 24
Finished Jun 10 07:44:38 PM PDT 24
Peak memory 229564 kb
Host smart-bd7ae00c-9361-4c7e-8dac-ed60bfe9580c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049622527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.2049622527
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.2181254566
Short name T1240
Test name
Test status
Simulation time 1022507067 ps
CPU time 2.48 seconds
Started Jun 10 07:44:32 PM PDT 24
Finished Jun 10 07:44:39 PM PDT 24
Peak memory 238652 kb
Host smart-7802a7f2-05d8-4bb8-bb51-9a3b47b4057c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181254566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.2181254566
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.3832090966
Short name T1278
Test name
Test status
Simulation time 78043661 ps
CPU time 5.75 seconds
Started Jun 10 07:44:32 PM PDT 24
Finished Jun 10 07:44:41 PM PDT 24
Peak memory 245816 kb
Host smart-21dcd3f8-e402-4bda-8f90-96a51b27397b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832090966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.3832090966
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1638824359
Short name T1200
Test name
Test status
Simulation time 308554530 ps
CPU time 3.18 seconds
Started Jun 10 07:44:31 PM PDT 24
Finished Jun 10 07:44:38 PM PDT 24
Peak memory 246832 kb
Host smart-47b96bcf-cd2d-4003-b76e-f6f5c235c5e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638824359 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.1638824359
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.1612362957
Short name T317
Test name
Test status
Simulation time 170640687 ps
CPU time 1.7 seconds
Started Jun 10 07:44:33 PM PDT 24
Finished Jun 10 07:44:39 PM PDT 24
Peak memory 240700 kb
Host smart-b4603c94-53e8-49ce-9321-1000a6a39b81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612362957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.1612362957
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.1783698417
Short name T1266
Test name
Test status
Simulation time 547991182 ps
CPU time 1.57 seconds
Started Jun 10 07:44:29 PM PDT 24
Finished Jun 10 07:44:32 PM PDT 24
Peak memory 229836 kb
Host smart-50f7031a-48d8-4382-9bc5-0895cc2a67ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783698417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.1783698417
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.2370325729
Short name T1251
Test name
Test status
Simulation time 98542791 ps
CPU time 2.31 seconds
Started Jun 10 07:44:30 PM PDT 24
Finished Jun 10 07:44:35 PM PDT 24
Peak memory 241572 kb
Host smart-d4fc52d3-a2fe-4a9c-8bd4-747f092a7619
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370325729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.2370325729
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3591397061
Short name T1206
Test name
Test status
Simulation time 194616514 ps
CPU time 3.85 seconds
Started Jun 10 07:44:31 PM PDT 24
Finished Jun 10 07:44:39 PM PDT 24
Peak memory 245476 kb
Host smart-fef70715-4d9b-4e21-8334-b19e68c128ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591397061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.3591397061
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3360288119
Short name T355
Test name
Test status
Simulation time 1291804044 ps
CPU time 19.56 seconds
Started Jun 10 07:44:32 PM PDT 24
Finished Jun 10 07:44:56 PM PDT 24
Peak memory 243512 kb
Host smart-eee7e755-2177-413f-a37f-860ad8b424c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360288119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.3360288119
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.906150656
Short name T1242
Test name
Test status
Simulation time 200985193 ps
CPU time 2.91 seconds
Started Jun 10 07:44:33 PM PDT 24
Finished Jun 10 07:44:40 PM PDT 24
Peak memory 246704 kb
Host smart-fb3a6b2b-64e0-4a0b-a9d9-8a4b7a7c7701
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906150656 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.906150656
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.662249717
Short name T1268
Test name
Test status
Simulation time 115298081 ps
CPU time 1.59 seconds
Started Jun 10 07:44:30 PM PDT 24
Finished Jun 10 07:44:35 PM PDT 24
Peak memory 239904 kb
Host smart-b73a1f0c-e3bb-452a-83cf-4714240370b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662249717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.662249717
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3867492945
Short name T1281
Test name
Test status
Simulation time 67605415 ps
CPU time 1.39 seconds
Started Jun 10 07:44:32 PM PDT 24
Finished Jun 10 07:44:37 PM PDT 24
Peak memory 229600 kb
Host smart-0befb415-4061-4360-97ab-a5f5906b7c9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867492945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.3867492945
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3444302527
Short name T326
Test name
Test status
Simulation time 1063620971 ps
CPU time 4.09 seconds
Started Jun 10 07:44:29 PM PDT 24
Finished Jun 10 07:44:36 PM PDT 24
Peak memory 241376 kb
Host smart-7ddc280d-44fd-440a-9dc1-515a33ce1a6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444302527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.3444302527
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1099085938
Short name T1194
Test name
Test status
Simulation time 49016597 ps
CPU time 2.53 seconds
Started Jun 10 07:44:32 PM PDT 24
Finished Jun 10 07:44:38 PM PDT 24
Peak memory 238656 kb
Host smart-dd4d9829-4c05-4f2f-8f7d-394ea8932036
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099085938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.1099085938
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1311982707
Short name T350
Test name
Test status
Simulation time 667908128 ps
CPU time 10.05 seconds
Started Jun 10 07:44:32 PM PDT 24
Finished Jun 10 07:44:45 PM PDT 24
Peak memory 243232 kb
Host smart-743ba084-4a4f-4dce-bb35-c04b1b0d69f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311982707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.1311982707
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.712414671
Short name T306
Test name
Test status
Simulation time 866437448 ps
CPU time 3.99 seconds
Started Jun 10 07:44:08 PM PDT 24
Finished Jun 10 07:44:15 PM PDT 24
Peak memory 230340 kb
Host smart-4b71d772-7261-49a6-98e2-2429ae15fd87
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712414671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alias
ing.712414671
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2865754809
Short name T1279
Test name
Test status
Simulation time 3725054375 ps
CPU time 8.86 seconds
Started Jun 10 07:44:11 PM PDT 24
Finished Jun 10 07:44:22 PM PDT 24
Peak memory 230328 kb
Host smart-e1680b12-8fbe-4817-832a-6a965402a355
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865754809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.2865754809
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.680779276
Short name T1319
Test name
Test status
Simulation time 236754099 ps
CPU time 2.01 seconds
Started Jun 10 07:44:17 PM PDT 24
Finished Jun 10 07:44:23 PM PDT 24
Peak memory 238592 kb
Host smart-4c4c199f-3f49-4f62-97be-0c8b991182c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680779276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_re
set.680779276
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3314127132
Short name T1313
Test name
Test status
Simulation time 68969653 ps
CPU time 2.36 seconds
Started Jun 10 07:44:11 PM PDT 24
Finished Jun 10 07:44:16 PM PDT 24
Peak memory 246776 kb
Host smart-6c4c4c3f-d9ca-4bfc-9f91-7349743fad82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314127132 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.3314127132
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.2723320673
Short name T1247
Test name
Test status
Simulation time 48569181 ps
CPU time 1.74 seconds
Started Jun 10 07:44:09 PM PDT 24
Finished Jun 10 07:44:14 PM PDT 24
Peak memory 238452 kb
Host smart-0c358677-669d-40d6-a587-e0c2fefdde0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723320673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.2723320673
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.503688089
Short name T1283
Test name
Test status
Simulation time 554119495 ps
CPU time 1.66 seconds
Started Jun 10 07:44:11 PM PDT 24
Finished Jun 10 07:44:15 PM PDT 24
Peak memory 229592 kb
Host smart-b60f7b45-c32b-493f-ba45-a37b5ddaa0ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503688089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.503688089
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.26253310
Short name T1304
Test name
Test status
Simulation time 519000138 ps
CPU time 1.96 seconds
Started Jun 10 07:44:11 PM PDT 24
Finished Jun 10 07:44:17 PM PDT 24
Peak memory 229336 kb
Host smart-7e580ba1-516d-4551-b92d-598913f8ef80
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26253310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_
mem_partial_access.26253310
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.4074188300
Short name T1273
Test name
Test status
Simulation time 48840079 ps
CPU time 1.42 seconds
Started Jun 10 07:44:10 PM PDT 24
Finished Jun 10 07:44:15 PM PDT 24
Peak memory 229364 kb
Host smart-73f88c67-c74a-4211-b805-49fd927b5d58
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074188300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.4074188300
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3212599030
Short name T1320
Test name
Test status
Simulation time 80108864 ps
CPU time 2.22 seconds
Started Jun 10 07:44:17 PM PDT 24
Finished Jun 10 07:44:22 PM PDT 24
Peak memory 238516 kb
Host smart-b1ec3693-9055-4570-82d9-990520391a12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212599030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.3212599030
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2256569384
Short name T1272
Test name
Test status
Simulation time 92314892 ps
CPU time 3.01 seconds
Started Jun 10 07:44:10 PM PDT 24
Finished Jun 10 07:44:16 PM PDT 24
Peak memory 244840 kb
Host smart-e28d983d-c90c-4ae1-9570-c4c7911f26ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256569384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.2256569384
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2351669561
Short name T351
Test name
Test status
Simulation time 1310846983 ps
CPU time 19.3 seconds
Started Jun 10 07:44:16 PM PDT 24
Finished Jun 10 07:44:39 PM PDT 24
Peak memory 243576 kb
Host smart-69bf94b4-24b9-431c-ad7c-9420731f8d52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351669561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.2351669561
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.3502301531
Short name T1294
Test name
Test status
Simulation time 52600660 ps
CPU time 1.49 seconds
Started Jun 10 07:44:32 PM PDT 24
Finished Jun 10 07:44:38 PM PDT 24
Peak memory 229512 kb
Host smart-5e901fd7-5854-43e1-bd01-a72f355162c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502301531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.3502301531
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2951257354
Short name T1223
Test name
Test status
Simulation time 38160511 ps
CPU time 1.47 seconds
Started Jun 10 07:44:32 PM PDT 24
Finished Jun 10 07:44:38 PM PDT 24
Peak memory 229344 kb
Host smart-bc268c6b-c7d4-417f-a98a-5006f3be3a56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951257354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.2951257354
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.33863456
Short name T1197
Test name
Test status
Simulation time 42311507 ps
CPU time 1.46 seconds
Started Jun 10 07:44:33 PM PDT 24
Finished Jun 10 07:44:38 PM PDT 24
Peak memory 230328 kb
Host smart-b32de73d-f6df-4a65-8393-a398d485cb50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33863456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.33863456
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.1889355259
Short name T1239
Test name
Test status
Simulation time 45022512 ps
CPU time 1.46 seconds
Started Jun 10 07:44:30 PM PDT 24
Finished Jun 10 07:44:35 PM PDT 24
Peak memory 229552 kb
Host smart-fa9c1937-77a4-4625-b53f-347d34e8bfde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889355259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.1889355259
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.555010925
Short name T1231
Test name
Test status
Simulation time 71714054 ps
CPU time 1.43 seconds
Started Jun 10 07:44:30 PM PDT 24
Finished Jun 10 07:44:34 PM PDT 24
Peak memory 229860 kb
Host smart-58bb621e-64ff-48ac-b24d-24f2df0f59dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555010925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.555010925
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.2255492308
Short name T1312
Test name
Test status
Simulation time 72330114 ps
CPU time 1.46 seconds
Started Jun 10 07:44:28 PM PDT 24
Finished Jun 10 07:44:31 PM PDT 24
Peak memory 229868 kb
Host smart-bb58948e-b5da-4b52-8c4e-ff6de9de7c1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255492308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.2255492308
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.805579245
Short name T1291
Test name
Test status
Simulation time 137029817 ps
CPU time 1.46 seconds
Started Jun 10 07:44:33 PM PDT 24
Finished Jun 10 07:44:38 PM PDT 24
Peak memory 229592 kb
Host smart-5ed15a68-2f33-4f75-8291-8048a0678e4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805579245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.805579245
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.957117394
Short name T1292
Test name
Test status
Simulation time 72982623 ps
CPU time 1.51 seconds
Started Jun 10 07:44:30 PM PDT 24
Finished Jun 10 07:44:35 PM PDT 24
Peak memory 229844 kb
Host smart-a3205985-d0aa-4624-a90b-44ddb29cd06b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957117394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.957117394
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.1060508069
Short name T1309
Test name
Test status
Simulation time 40072715 ps
CPU time 1.41 seconds
Started Jun 10 07:44:32 PM PDT 24
Finished Jun 10 07:44:37 PM PDT 24
Peak memory 229588 kb
Host smart-9d6f1e5e-a31a-4276-b423-52caa38055d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060508069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.1060508069
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2742439249
Short name T1300
Test name
Test status
Simulation time 69271051 ps
CPU time 1.4 seconds
Started Jun 10 07:44:32 PM PDT 24
Finished Jun 10 07:44:38 PM PDT 24
Peak memory 230360 kb
Host smart-c2a2651c-a81a-4781-9489-4e33c96097a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742439249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.2742439249
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.4197117451
Short name T304
Test name
Test status
Simulation time 156897560 ps
CPU time 5.87 seconds
Started Jun 10 07:44:11 PM PDT 24
Finished Jun 10 07:44:20 PM PDT 24
Peak memory 238552 kb
Host smart-f2de8b3d-3717-4fdc-97bd-4d39fea49648
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197117451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.4197117451
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.3188361693
Short name T1299
Test name
Test status
Simulation time 933785567 ps
CPU time 11.35 seconds
Started Jun 10 07:44:11 PM PDT 24
Finished Jun 10 07:44:25 PM PDT 24
Peak memory 230272 kb
Host smart-fae99d37-fbf3-41ef-8566-d8e2197793f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188361693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.3188361693
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.637567475
Short name T1233
Test name
Test status
Simulation time 68378322 ps
CPU time 1.95 seconds
Started Jun 10 07:44:16 PM PDT 24
Finished Jun 10 07:44:22 PM PDT 24
Peak memory 238592 kb
Host smart-34c1ff06-a456-401b-b9f5-c62ba6708c6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637567475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_re
set.637567475
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.3325592206
Short name T1227
Test name
Test status
Simulation time 87043177 ps
CPU time 2.11 seconds
Started Jun 10 07:44:08 PM PDT 24
Finished Jun 10 07:44:13 PM PDT 24
Peak memory 244448 kb
Host smart-e1b06a40-28d1-4823-87aa-4268a7e5ecad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325592206 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.3325592206
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.4198553694
Short name T322
Test name
Test status
Simulation time 605715219 ps
CPU time 1.99 seconds
Started Jun 10 07:44:17 PM PDT 24
Finished Jun 10 07:44:22 PM PDT 24
Peak memory 239844 kb
Host smart-3c3a7f36-fa98-4320-8b9d-e949ce1e21ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198553694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.4198553694
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.2611790224
Short name T1293
Test name
Test status
Simulation time 595917087 ps
CPU time 1.37 seconds
Started Jun 10 07:44:17 PM PDT 24
Finished Jun 10 07:44:22 PM PDT 24
Peak memory 229448 kb
Host smart-6ebe434f-d374-4b2d-94cb-9b22deea96ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611790224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.2611790224
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.440938987
Short name T1274
Test name
Test status
Simulation time 134439161 ps
CPU time 1.43 seconds
Started Jun 10 07:44:09 PM PDT 24
Finished Jun 10 07:44:13 PM PDT 24
Peak memory 230180 kb
Host smart-554afcfd-b854-476d-b776-291552101e22
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440938987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl
_mem_partial_access.440938987
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2487783411
Short name T1243
Test name
Test status
Simulation time 37050697 ps
CPU time 1.38 seconds
Started Jun 10 07:44:08 PM PDT 24
Finished Jun 10 07:44:13 PM PDT 24
Peak memory 229436 kb
Host smart-af66abd7-d387-4aac-b625-f15fe903c074
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487783411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.2487783411
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.31396213
Short name T261
Test name
Test status
Simulation time 1242789064 ps
CPU time 3.49 seconds
Started Jun 10 07:44:09 PM PDT 24
Finished Jun 10 07:44:16 PM PDT 24
Peak memory 238604 kb
Host smart-4078e61c-a5ae-4981-b137-ec1ae76e7b31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31396213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_same_csr_outstanding.31396213
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1408540987
Short name T1321
Test name
Test status
Simulation time 260667023 ps
CPU time 5.86 seconds
Started Jun 10 07:44:07 PM PDT 24
Finished Jun 10 07:44:16 PM PDT 24
Peak memory 246668 kb
Host smart-2e61442d-2a6f-4bbb-8f1c-99072f23a848
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408540987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.1408540987
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.3397204207
Short name T269
Test name
Test status
Simulation time 1403285259 ps
CPU time 20.66 seconds
Started Jun 10 07:44:11 PM PDT 24
Finished Jun 10 07:44:34 PM PDT 24
Peak memory 238556 kb
Host smart-53cfcbbe-896f-4ea9-b154-672b6d2c5e65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397204207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.3397204207
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.757982498
Short name T1202
Test name
Test status
Simulation time 92765892 ps
CPU time 1.54 seconds
Started Jun 10 07:44:30 PM PDT 24
Finished Jun 10 07:44:33 PM PDT 24
Peak memory 230328 kb
Host smart-e723e3f6-93a8-493e-bbd4-18e1cb4b99ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757982498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.757982498
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.3068116932
Short name T1296
Test name
Test status
Simulation time 38894515 ps
CPU time 1.38 seconds
Started Jun 10 07:44:33 PM PDT 24
Finished Jun 10 07:44:38 PM PDT 24
Peak memory 229612 kb
Host smart-80d481cb-a2fc-4d47-889b-dc1f78a7330e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068116932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.3068116932
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.893044442
Short name T1306
Test name
Test status
Simulation time 41420492 ps
CPU time 1.51 seconds
Started Jun 10 07:44:34 PM PDT 24
Finished Jun 10 07:44:40 PM PDT 24
Peak memory 229904 kb
Host smart-0700b173-ac97-4d6c-ba3d-f3e8aa1542f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893044442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.893044442
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.3733598394
Short name T1284
Test name
Test status
Simulation time 559923595 ps
CPU time 1.63 seconds
Started Jun 10 07:44:31 PM PDT 24
Finished Jun 10 07:44:36 PM PDT 24
Peak memory 230392 kb
Host smart-d9c57687-9cdf-4948-9fab-cf840ce36080
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733598394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.3733598394
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.3961185126
Short name T1226
Test name
Test status
Simulation time 579716903 ps
CPU time 1.96 seconds
Started Jun 10 07:44:37 PM PDT 24
Finished Jun 10 07:44:43 PM PDT 24
Peak memory 230324 kb
Host smart-b7ecc355-7d8c-492f-bd0b-bb52f4fd229c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961185126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.3961185126
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.103370971
Short name T1288
Test name
Test status
Simulation time 43139536 ps
CPU time 1.41 seconds
Started Jun 10 07:44:39 PM PDT 24
Finished Jun 10 07:44:45 PM PDT 24
Peak memory 230340 kb
Host smart-5d6fbeba-5804-46c9-88d6-f4c2eb33bb5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103370971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.103370971
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3714150842
Short name T1213
Test name
Test status
Simulation time 561289654 ps
CPU time 2.05 seconds
Started Jun 10 07:44:35 PM PDT 24
Finished Jun 10 07:44:42 PM PDT 24
Peak memory 230368 kb
Host smart-2cbe6199-a488-448e-a678-20d6c1838c75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714150842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.3714150842
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.1672123814
Short name T1271
Test name
Test status
Simulation time 39468770 ps
CPU time 1.44 seconds
Started Jun 10 07:44:38 PM PDT 24
Finished Jun 10 07:44:44 PM PDT 24
Peak memory 229548 kb
Host smart-24e3d096-cebb-4844-87c5-33f6bcc10131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672123814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.1672123814
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.1362442212
Short name T1234
Test name
Test status
Simulation time 61158991 ps
CPU time 1.42 seconds
Started Jun 10 07:44:37 PM PDT 24
Finished Jun 10 07:44:43 PM PDT 24
Peak memory 229596 kb
Host smart-f528e6be-1a35-4c89-952c-022268932343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362442212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.1362442212
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.456261975
Short name T1270
Test name
Test status
Simulation time 74943000 ps
CPU time 1.46 seconds
Started Jun 10 07:44:39 PM PDT 24
Finished Jun 10 07:44:45 PM PDT 24
Peak memory 230296 kb
Host smart-aaca6556-54b2-4972-8be9-eeed5f200bdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456261975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.456261975
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.946715002
Short name T1230
Test name
Test status
Simulation time 199992179 ps
CPU time 3.69 seconds
Started Jun 10 07:44:18 PM PDT 24
Finished Jun 10 07:44:25 PM PDT 24
Peak memory 238464 kb
Host smart-b15bdf8d-2803-4921-908a-37dc8c68b323
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946715002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alias
ing.946715002
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.3875327755
Short name T333
Test name
Test status
Simulation time 1382762702 ps
CPU time 9.76 seconds
Started Jun 10 07:44:16 PM PDT 24
Finished Jun 10 07:44:29 PM PDT 24
Peak memory 230380 kb
Host smart-34c54404-ff39-4481-98bb-fd636645c0ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875327755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_
bash.3875327755
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1397075208
Short name T307
Test name
Test status
Simulation time 1045557050 ps
CPU time 3.05 seconds
Started Jun 10 07:44:19 PM PDT 24
Finished Jun 10 07:44:25 PM PDT 24
Peak memory 240320 kb
Host smart-0b6388c4-0324-435a-a1d2-ba367243d8e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397075208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.1397075208
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3124733434
Short name T1261
Test name
Test status
Simulation time 78785190 ps
CPU time 2.45 seconds
Started Jun 10 07:44:19 PM PDT 24
Finished Jun 10 07:44:24 PM PDT 24
Peak memory 245848 kb
Host smart-ce7c34dd-ef1d-4bcf-ae5d-ea6784b31b39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124733434 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.3124733434
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3388160266
Short name T320
Test name
Test status
Simulation time 45619647 ps
CPU time 1.81 seconds
Started Jun 10 07:44:18 PM PDT 24
Finished Jun 10 07:44:23 PM PDT 24
Peak memory 240832 kb
Host smart-2f687a7d-a0e3-4a49-a9e8-98752bfa4751
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388160266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.3388160266
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.4124956491
Short name T1204
Test name
Test status
Simulation time 38950440 ps
CPU time 1.38 seconds
Started Jun 10 07:44:17 PM PDT 24
Finished Jun 10 07:44:21 PM PDT 24
Peak memory 229584 kb
Host smart-1ec8701d-b8f4-41aa-afb4-446e93dd3621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124956491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.4124956491
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.53853712
Short name T1263
Test name
Test status
Simulation time 126698280 ps
CPU time 1.49 seconds
Started Jun 10 07:44:17 PM PDT 24
Finished Jun 10 07:44:22 PM PDT 24
Peak memory 230240 kb
Host smart-e8996e53-e7f3-430b-a091-67e5ee64e85e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53853712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_
mem_partial_access.53853712
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2097469170
Short name T1248
Test name
Test status
Simulation time 35465442 ps
CPU time 1.37 seconds
Started Jun 10 07:44:18 PM PDT 24
Finished Jun 10 07:44:22 PM PDT 24
Peak memory 229388 kb
Host smart-bde782b0-2f9a-4bc7-ba9a-5972ce412622
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097469170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.2097469170
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.997128389
Short name T1285
Test name
Test status
Simulation time 119552707 ps
CPU time 3.67 seconds
Started Jun 10 07:44:15 PM PDT 24
Finished Jun 10 07:44:22 PM PDT 24
Peak memory 238628 kb
Host smart-b97daf1e-c32b-40a9-a925-91bb238d9d5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997128389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ct
rl_same_csr_outstanding.997128389
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.1122426268
Short name T1286
Test name
Test status
Simulation time 1334925171 ps
CPU time 3.64 seconds
Started Jun 10 07:44:08 PM PDT 24
Finished Jun 10 07:44:15 PM PDT 24
Peak memory 245104 kb
Host smart-a966ed8d-c1fd-41ef-8794-21519dc227e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122426268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.1122426268
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1803624272
Short name T357
Test name
Test status
Simulation time 2477155367 ps
CPU time 13.06 seconds
Started Jun 10 07:44:17 PM PDT 24
Finished Jun 10 07:44:33 PM PDT 24
Peak memory 243536 kb
Host smart-611c214e-0be3-4f42-8c2e-6edc316e1e53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803624272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in
tg_err.1803624272
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.3864728145
Short name T1215
Test name
Test status
Simulation time 136826652 ps
CPU time 1.44 seconds
Started Jun 10 07:44:36 PM PDT 24
Finished Jun 10 07:44:42 PM PDT 24
Peak memory 230296 kb
Host smart-f4b3407d-12f6-444f-8244-883965f6191a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864728145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.3864728145
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.2705871049
Short name T1196
Test name
Test status
Simulation time 557927795 ps
CPU time 1.54 seconds
Started Jun 10 07:44:38 PM PDT 24
Finished Jun 10 07:44:43 PM PDT 24
Peak memory 229628 kb
Host smart-215fd3cf-e0b8-4d30-80e0-6957a04ae0b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705871049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.2705871049
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.3669665718
Short name T1217
Test name
Test status
Simulation time 76168555 ps
CPU time 1.39 seconds
Started Jun 10 07:44:39 PM PDT 24
Finished Jun 10 07:44:45 PM PDT 24
Peak memory 229612 kb
Host smart-005788e3-7b06-4b54-a30f-f5501384bddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669665718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.3669665718
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.1444505663
Short name T1208
Test name
Test status
Simulation time 38940744 ps
CPU time 1.41 seconds
Started Jun 10 07:44:39 PM PDT 24
Finished Jun 10 07:44:45 PM PDT 24
Peak memory 230344 kb
Host smart-43d431f0-9bf8-4ddf-ae9e-769f55ba622d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444505663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.1444505663
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.3725361060
Short name T1216
Test name
Test status
Simulation time 38768654 ps
CPU time 1.46 seconds
Started Jun 10 07:44:38 PM PDT 24
Finished Jun 10 07:44:44 PM PDT 24
Peak memory 229584 kb
Host smart-694975a4-454e-446b-a94a-a149da8e8077
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725361060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.3725361060
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.2772750869
Short name T1198
Test name
Test status
Simulation time 56809479 ps
CPU time 1.59 seconds
Started Jun 10 07:44:39 PM PDT 24
Finished Jun 10 07:44:45 PM PDT 24
Peak memory 229656 kb
Host smart-355674f6-008c-4846-8f02-5fee4b085dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772750869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.2772750869
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.486371413
Short name T1317
Test name
Test status
Simulation time 141167420 ps
CPU time 1.37 seconds
Started Jun 10 07:44:38 PM PDT 24
Finished Jun 10 07:44:44 PM PDT 24
Peak memory 230384 kb
Host smart-dde43957-8a08-454c-98ee-6da8aa5b04d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486371413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.486371413
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.1602599862
Short name T1193
Test name
Test status
Simulation time 73604986 ps
CPU time 1.48 seconds
Started Jun 10 07:44:38 PM PDT 24
Finished Jun 10 07:44:44 PM PDT 24
Peak memory 230348 kb
Host smart-00924707-dab0-4ac0-9232-6fb0e88619de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602599862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.1602599862
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.380106490
Short name T1269
Test name
Test status
Simulation time 39508734 ps
CPU time 1.35 seconds
Started Jun 10 07:44:37 PM PDT 24
Finished Jun 10 07:44:43 PM PDT 24
Peak memory 229600 kb
Host smart-8073f62a-1bf9-4a6a-b871-3f1ddfa099e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380106490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.380106490
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.734087898
Short name T1316
Test name
Test status
Simulation time 70645753 ps
CPU time 1.48 seconds
Started Jun 10 07:44:36 PM PDT 24
Finished Jun 10 07:44:43 PM PDT 24
Peak memory 229552 kb
Host smart-8224f0cb-98d4-4fd2-92e3-edfabbe3f1ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734087898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.734087898
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.3016033793
Short name T1289
Test name
Test status
Simulation time 215599607 ps
CPU time 3.14 seconds
Started Jun 10 07:44:19 PM PDT 24
Finished Jun 10 07:44:25 PM PDT 24
Peak memory 246716 kb
Host smart-9a2e9da9-fa11-4734-a0f0-ba1d1cd34d69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016033793 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.3016033793
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3304237191
Short name T328
Test name
Test status
Simulation time 90474367 ps
CPU time 1.76 seconds
Started Jun 10 07:44:18 PM PDT 24
Finished Jun 10 07:44:22 PM PDT 24
Peak memory 240364 kb
Host smart-a9616f29-1b79-4df8-ab13-d501fd54cde1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304237191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.3304237191
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.1517498938
Short name T1255
Test name
Test status
Simulation time 75596620 ps
CPU time 1.38 seconds
Started Jun 10 07:44:18 PM PDT 24
Finished Jun 10 07:44:22 PM PDT 24
Peak memory 229860 kb
Host smart-69b3ed3c-33ba-42b9-9db3-a0f91f6711c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517498938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.1517498938
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.461700551
Short name T1232
Test name
Test status
Simulation time 1655544711 ps
CPU time 4.62 seconds
Started Jun 10 07:44:18 PM PDT 24
Finished Jun 10 07:44:26 PM PDT 24
Peak memory 238556 kb
Host smart-a88e1fe1-228b-4a57-91ae-0966b26b9aa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461700551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ct
rl_same_csr_outstanding.461700551
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.963289785
Short name T1225
Test name
Test status
Simulation time 206753151 ps
CPU time 3.12 seconds
Started Jun 10 07:44:19 PM PDT 24
Finished Jun 10 07:44:25 PM PDT 24
Peak memory 245316 kb
Host smart-61a99f6b-7825-44a9-9544-1b7dc653903e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963289785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.963289785
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3796367272
Short name T259
Test name
Test status
Simulation time 10304881285 ps
CPU time 22.83 seconds
Started Jun 10 07:44:17 PM PDT 24
Finished Jun 10 07:44:43 PM PDT 24
Peak memory 238748 kb
Host smart-725ff2dd-ffff-48a4-ae00-4b63f1213320
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796367272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.3796367272
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1586004738
Short name T1256
Test name
Test status
Simulation time 1664711000 ps
CPU time 4.11 seconds
Started Jun 10 07:44:18 PM PDT 24
Finished Jun 10 07:44:25 PM PDT 24
Peak memory 246804 kb
Host smart-142c0c8d-97a0-433c-9872-608599c32e83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586004738 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.1586004738
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.1128978991
Short name T1229
Test name
Test status
Simulation time 43275443 ps
CPU time 1.48 seconds
Started Jun 10 07:44:17 PM PDT 24
Finished Jun 10 07:44:22 PM PDT 24
Peak memory 229548 kb
Host smart-89510eca-fbc5-4511-aa00-1d14324a1a4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128978991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.1128978991
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.327006649
Short name T1250
Test name
Test status
Simulation time 707098401 ps
CPU time 2.61 seconds
Started Jun 10 07:44:14 PM PDT 24
Finished Jun 10 07:44:20 PM PDT 24
Peak memory 241652 kb
Host smart-3bfcc676-5829-42f2-88ec-0f2c3e413698
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327006649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ct
rl_same_csr_outstanding.327006649
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.524942377
Short name T1236
Test name
Test status
Simulation time 66357846 ps
CPU time 3.65 seconds
Started Jun 10 07:44:19 PM PDT 24
Finished Jun 10 07:44:26 PM PDT 24
Peak memory 246000 kb
Host smart-dac5734d-06d6-4925-91b0-729c45875b38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524942377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.524942377
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.3962852574
Short name T359
Test name
Test status
Simulation time 628038569 ps
CPU time 9.49 seconds
Started Jun 10 07:44:19 PM PDT 24
Finished Jun 10 07:44:31 PM PDT 24
Peak memory 243192 kb
Host smart-095ebf9c-efce-423d-aff4-497bd3001fd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962852574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.3962852574
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1990366875
Short name T1210
Test name
Test status
Simulation time 158159190 ps
CPU time 2.21 seconds
Started Jun 10 07:44:20 PM PDT 24
Finished Jun 10 07:44:25 PM PDT 24
Peak memory 243984 kb
Host smart-d2c75910-3644-42ee-ab3f-5677d693c07d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990366875 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.1990366875
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.2216643536
Short name T329
Test name
Test status
Simulation time 87944378 ps
CPU time 1.76 seconds
Started Jun 10 07:44:17 PM PDT 24
Finished Jun 10 07:44:22 PM PDT 24
Peak memory 238548 kb
Host smart-249b0025-02ca-4763-a94f-fb875e2ebe94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216643536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.2216643536
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.385022879
Short name T1249
Test name
Test status
Simulation time 73588394 ps
CPU time 1.42 seconds
Started Jun 10 07:44:17 PM PDT 24
Finished Jun 10 07:44:21 PM PDT 24
Peak memory 229580 kb
Host smart-46a3551a-4dd0-4a3e-aa07-427ea4f81fa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385022879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.385022879
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3564089687
Short name T327
Test name
Test status
Simulation time 702023707 ps
CPU time 2.21 seconds
Started Jun 10 07:44:18 PM PDT 24
Finished Jun 10 07:44:23 PM PDT 24
Peak memory 238560 kb
Host smart-d3818f4e-c8eb-4fe6-80a0-7a7648244572
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564089687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c
trl_same_csr_outstanding.3564089687
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.2084213689
Short name T1267
Test name
Test status
Simulation time 88457686 ps
CPU time 4.1 seconds
Started Jun 10 07:44:16 PM PDT 24
Finished Jun 10 07:44:23 PM PDT 24
Peak memory 245444 kb
Host smart-d0e8b863-b565-4fdd-a27e-f103a69f957b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084213689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.2084213689
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3542959970
Short name T353
Test name
Test status
Simulation time 1016168888 ps
CPU time 9.95 seconds
Started Jun 10 07:44:20 PM PDT 24
Finished Jun 10 07:44:33 PM PDT 24
Peak memory 238584 kb
Host smart-96d31bdf-259f-4a47-bdb3-069c7241fa98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542959970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in
tg_err.3542959970
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3146166983
Short name T266
Test name
Test status
Simulation time 1134910596 ps
CPU time 3.89 seconds
Started Jun 10 07:44:18 PM PDT 24
Finished Jun 10 07:44:25 PM PDT 24
Peak memory 245400 kb
Host smart-d6809a1b-5373-4a9a-8833-1d67fc0d2652
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146166983 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.3146166983
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2729872195
Short name T1282
Test name
Test status
Simulation time 578424230 ps
CPU time 1.86 seconds
Started Jun 10 07:44:17 PM PDT 24
Finished Jun 10 07:44:22 PM PDT 24
Peak memory 238512 kb
Host smart-73fe60ac-592c-4257-87c3-d8eca425ddbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729872195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.2729872195
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.543804196
Short name T1314
Test name
Test status
Simulation time 139897494 ps
CPU time 1.62 seconds
Started Jun 10 07:44:19 PM PDT 24
Finished Jun 10 07:44:23 PM PDT 24
Peak memory 229864 kb
Host smart-cf28c16c-e81f-4c78-979c-094345f99bb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543804196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.543804196
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2538131426
Short name T1290
Test name
Test status
Simulation time 85856099 ps
CPU time 2.28 seconds
Started Jun 10 07:44:17 PM PDT 24
Finished Jun 10 07:44:23 PM PDT 24
Peak memory 241528 kb
Host smart-c40da3f2-926c-4bc1-9b3a-1baef50087d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538131426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.2538131426
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.705991989
Short name T1262
Test name
Test status
Simulation time 180389009 ps
CPU time 6.25 seconds
Started Jun 10 07:44:19 PM PDT 24
Finished Jun 10 07:44:28 PM PDT 24
Peak memory 245600 kb
Host smart-f4062b45-ab40-47e9-b8a9-5975c7af1d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705991989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.705991989
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1967099463
Short name T1207
Test name
Test status
Simulation time 132864059 ps
CPU time 2.31 seconds
Started Jun 10 07:44:18 PM PDT 24
Finished Jun 10 07:44:23 PM PDT 24
Peak memory 246752 kb
Host smart-0afad520-0240-435b-80e4-5e3c53961de5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967099463 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.1967099463
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.385583533
Short name T1308
Test name
Test status
Simulation time 152752193 ps
CPU time 1.69 seconds
Started Jun 10 07:44:16 PM PDT 24
Finished Jun 10 07:44:21 PM PDT 24
Peak memory 241100 kb
Host smart-0fdfd5bf-e90e-459a-bba8-805715922231
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385583533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.385583533
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1552756483
Short name T1275
Test name
Test status
Simulation time 513939714 ps
CPU time 2.1 seconds
Started Jun 10 07:44:20 PM PDT 24
Finished Jun 10 07:44:24 PM PDT 24
Peak memory 229544 kb
Host smart-5a4d0304-7c97-4d2e-9ae1-0cb3d2fd92cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552756483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.1552756483
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.131278379
Short name T1237
Test name
Test status
Simulation time 136769982 ps
CPU time 2.24 seconds
Started Jun 10 07:44:18 PM PDT 24
Finished Jun 10 07:44:23 PM PDT 24
Peak memory 238564 kb
Host smart-8f5f2e77-2b9a-4992-9a63-0bd87c13a90e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131278379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ct
rl_same_csr_outstanding.131278379
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3101232317
Short name T1310
Test name
Test status
Simulation time 122114890 ps
CPU time 4.44 seconds
Started Jun 10 07:44:18 PM PDT 24
Finished Jun 10 07:44:25 PM PDT 24
Peak memory 245832 kb
Host smart-cfe50a1f-d1da-4728-9430-d483cd05ad1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101232317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.3101232317
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.2407094409
Short name T352
Test name
Test status
Simulation time 1471804236 ps
CPU time 19.19 seconds
Started Jun 10 07:44:18 PM PDT 24
Finished Jun 10 07:44:40 PM PDT 24
Peak memory 243572 kb
Host smart-420eca39-73eb-4a71-9f9b-56acc611aaf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407094409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.2407094409
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.2921448248
Short name T812
Test name
Test status
Simulation time 90240784 ps
CPU time 2.34 seconds
Started Jun 10 07:49:45 PM PDT 24
Finished Jun 10 07:49:50 PM PDT 24
Peak memory 240656 kb
Host smart-312bb0ce-4a4f-486e-be3f-d4476486ce45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921448248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.2921448248
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.224130627
Short name T1138
Test name
Test status
Simulation time 513001137 ps
CPU time 16.46 seconds
Started Jun 10 07:49:44 PM PDT 24
Finished Jun 10 07:50:04 PM PDT 24
Peak memory 242340 kb
Host smart-7eda58d8-a54d-4c1b-bd24-3bf9e40de8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224130627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.224130627
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.3996564574
Short name T67
Test name
Test status
Simulation time 11301773734 ps
CPU time 32.72 seconds
Started Jun 10 07:49:49 PM PDT 24
Finished Jun 10 07:50:26 PM PDT 24
Peak memory 249192 kb
Host smart-0d92a493-18c7-4ead-a12a-22602f76945e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996564574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.3996564574
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.139018928
Short name T602
Test name
Test status
Simulation time 811192873 ps
CPU time 17.71 seconds
Started Jun 10 07:49:42 PM PDT 24
Finished Jun 10 07:50:03 PM PDT 24
Peak memory 242296 kb
Host smart-f819e185-9ecf-4bda-8886-4e81c326457e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139018928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.139018928
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.3790373088
Short name T725
Test name
Test status
Simulation time 1421144405 ps
CPU time 19.3 seconds
Started Jun 10 07:49:45 PM PDT 24
Finished Jun 10 07:50:08 PM PDT 24
Peak memory 242400 kb
Host smart-b13f99b8-2416-4ee2-bff3-ba5d98ab4047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790373088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.3790373088
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.4170757611
Short name T924
Test name
Test status
Simulation time 116249037 ps
CPU time 3.82 seconds
Started Jun 10 07:49:43 PM PDT 24
Finished Jun 10 07:49:50 PM PDT 24
Peak memory 242488 kb
Host smart-d03f4f6c-94d0-4fd0-9a6a-ebef3969659e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170757611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.4170757611
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.634757630
Short name T700
Test name
Test status
Simulation time 3392997286 ps
CPU time 12.01 seconds
Started Jun 10 07:49:42 PM PDT 24
Finished Jun 10 07:49:58 PM PDT 24
Peak memory 242232 kb
Host smart-6643cc20-fa7e-45ee-aa80-1fcb34e09bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634757630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.634757630
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.3981115694
Short name T593
Test name
Test status
Simulation time 747372201 ps
CPU time 15.42 seconds
Started Jun 10 07:49:44 PM PDT 24
Finished Jun 10 07:50:03 PM PDT 24
Peak memory 243616 kb
Host smart-9cb612dd-dc87-444e-8705-9eddfb43ce37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981115694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.3981115694
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.726827072
Short name T714
Test name
Test status
Simulation time 103901704 ps
CPU time 3.42 seconds
Started Jun 10 07:49:46 PM PDT 24
Finished Jun 10 07:49:54 PM PDT 24
Peak memory 242648 kb
Host smart-670066d2-fd62-4ef9-bf00-3fb0af00de5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726827072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.726827072
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.3248806759
Short name T939
Test name
Test status
Simulation time 1177046121 ps
CPU time 16.86 seconds
Started Jun 10 07:49:48 PM PDT 24
Finished Jun 10 07:50:09 PM PDT 24
Peak memory 242464 kb
Host smart-891b068f-56cd-44eb-be52-040a4416c7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248806759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.3248806759
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.2671705431
Short name T416
Test name
Test status
Simulation time 784425720 ps
CPU time 18.76 seconds
Started Jun 10 07:49:47 PM PDT 24
Finished Jun 10 07:50:10 PM PDT 24
Peak memory 241892 kb
Host smart-9b42eb54-bc0c-4ca9-a14c-e0dc691823b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671705431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.2671705431
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.1173244287
Short name T21
Test name
Test status
Simulation time 38773923388 ps
CPU time 209.22 seconds
Started Jun 10 07:49:46 PM PDT 24
Finished Jun 10 07:53:18 PM PDT 24
Peak memory 268900 kb
Host smart-ab30ee80-327f-4068-9147-340b2eb2c3b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173244287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.1173244287
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.567084215
Short name T666
Test name
Test status
Simulation time 252460294 ps
CPU time 10.27 seconds
Started Jun 10 07:49:54 PM PDT 24
Finished Jun 10 07:50:07 PM PDT 24
Peak memory 242108 kb
Host smart-f16ff58f-402c-44b5-b2b8-cb5a13c1b112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567084215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.567084215
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.1014337948
Short name T849
Test name
Test status
Simulation time 6846271478 ps
CPU time 64.05 seconds
Started Jun 10 07:49:47 PM PDT 24
Finished Jun 10 07:50:55 PM PDT 24
Peak memory 243852 kb
Host smart-cc9e3f74-2404-4160-8b5d-b3e838becdf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014337948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
1014337948
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.2674723845
Short name T275
Test name
Test status
Simulation time 59665153947 ps
CPU time 887.71 seconds
Started Jun 10 07:49:44 PM PDT 24
Finished Jun 10 08:04:35 PM PDT 24
Peak memory 454996 kb
Host smart-502bf7e8-a4e6-4888-8dd7-2cf2eaa9d2cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674723845 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.2674723845
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.2380423314
Short name T101
Test name
Test status
Simulation time 12680884438 ps
CPU time 19.84 seconds
Started Jun 10 07:49:46 PM PDT 24
Finished Jun 10 07:50:10 PM PDT 24
Peak memory 243104 kb
Host smart-9bc16de7-0242-4b97-846b-242399ca4165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380423314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.2380423314
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.3549442983
Short name T1176
Test name
Test status
Simulation time 60857936 ps
CPU time 1.83 seconds
Started Jun 10 07:49:44 PM PDT 24
Finished Jun 10 07:49:49 PM PDT 24
Peak memory 241024 kb
Host smart-8d27bef6-e025-4436-b3e6-444cd14a7f59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549442983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.3549442983
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.2584154925
Short name T793
Test name
Test status
Simulation time 4978900820 ps
CPU time 29.11 seconds
Started Jun 10 07:49:45 PM PDT 24
Finished Jun 10 07:50:17 PM PDT 24
Peak memory 242956 kb
Host smart-9818cde5-3cbf-4b76-a9a0-322ae400a554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584154925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.2584154925
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.932487969
Short name T865
Test name
Test status
Simulation time 3578261744 ps
CPU time 27.63 seconds
Started Jun 10 07:49:44 PM PDT 24
Finished Jun 10 07:50:14 PM PDT 24
Peak memory 249180 kb
Host smart-4f941e9e-090f-4a52-b7d8-92b4d8974a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932487969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.932487969
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.3995126823
Short name T1175
Test name
Test status
Simulation time 2530069430 ps
CPU time 30.65 seconds
Started Jun 10 07:49:43 PM PDT 24
Finished Jun 10 07:50:17 PM PDT 24
Peak memory 242348 kb
Host smart-0aeda195-fde6-4b28-800f-903dbd91fa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995126823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.3995126823
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.1065032192
Short name T565
Test name
Test status
Simulation time 1017666613 ps
CPU time 16.62 seconds
Started Jun 10 07:49:45 PM PDT 24
Finished Jun 10 07:50:05 PM PDT 24
Peak memory 242508 kb
Host smart-08ab82f2-d3d0-4aa8-8ea8-bb0105ccb1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065032192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.1065032192
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.984416415
Short name T620
Test name
Test status
Simulation time 154008759 ps
CPU time 4.21 seconds
Started Jun 10 07:49:47 PM PDT 24
Finished Jun 10 07:49:55 PM PDT 24
Peak memory 242216 kb
Host smart-bdee8f80-33e6-42ad-b4e9-392c0d42eeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984416415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.984416415
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.4079412799
Short name T1154
Test name
Test status
Simulation time 7886320944 ps
CPU time 20.46 seconds
Started Jun 10 07:49:48 PM PDT 24
Finished Jun 10 07:50:12 PM PDT 24
Peak memory 244328 kb
Host smart-2a2c1a82-1363-4861-8d26-4dfb12d43aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079412799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.4079412799
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.3304019697
Short name T955
Test name
Test status
Simulation time 14821262205 ps
CPU time 37.46 seconds
Started Jun 10 07:49:45 PM PDT 24
Finished Jun 10 07:50:25 PM PDT 24
Peak memory 243660 kb
Host smart-ff6bf778-635a-4c33-b7fc-df7e5ec124d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304019697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.3304019697
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.3781919792
Short name T1058
Test name
Test status
Simulation time 126705635 ps
CPU time 4.11 seconds
Started Jun 10 07:49:45 PM PDT 24
Finished Jun 10 07:49:52 PM PDT 24
Peak memory 242508 kb
Host smart-048c74e6-a018-4ae5-9a21-e48efe23d923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781919792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.3781919792
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.1681134270
Short name T591
Test name
Test status
Simulation time 549619451 ps
CPU time 4.89 seconds
Started Jun 10 07:49:44 PM PDT 24
Finished Jun 10 07:49:52 PM PDT 24
Peak memory 242072 kb
Host smart-9ffba3aa-e21a-4795-a9ab-fdf6b83e1988
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1681134270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.1681134270
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.3810628081
Short name T552
Test name
Test status
Simulation time 482540225 ps
CPU time 4.48 seconds
Started Jun 10 07:49:45 PM PDT 24
Finished Jun 10 07:49:52 PM PDT 24
Peak memory 242332 kb
Host smart-2253afad-469d-44e0-9723-58bb2b6b2bb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3810628081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.3810628081
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.228254273
Short name T240
Test name
Test status
Simulation time 41505391866 ps
CPU time 204.59 seconds
Started Jun 10 07:49:54 PM PDT 24
Finished Jun 10 07:53:21 PM PDT 24
Peak memory 270872 kb
Host smart-d6426ac5-0870-45de-8ba5-0020ac6c6da6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228254273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.228254273
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.1201123886
Short name T529
Test name
Test status
Simulation time 871319235 ps
CPU time 9.91 seconds
Started Jun 10 07:49:45 PM PDT 24
Finished Jun 10 07:49:58 PM PDT 24
Peak memory 242408 kb
Host smart-424ad406-b82a-4370-beb0-3ecba544cc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201123886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.1201123886
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.1745831631
Short name T295
Test name
Test status
Simulation time 19033200903 ps
CPU time 97.14 seconds
Started Jun 10 07:49:43 PM PDT 24
Finished Jun 10 07:51:23 PM PDT 24
Peak memory 257316 kb
Host smart-ed5799b0-4c44-4150-98e8-e02846c460c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745831631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
1745831631
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.1325598945
Short name T332
Test name
Test status
Simulation time 75440744580 ps
CPU time 589.38 seconds
Started Jun 10 07:49:50 PM PDT 24
Finished Jun 10 07:59:43 PM PDT 24
Peak memory 328960 kb
Host smart-e6087ce0-850f-4a48-9123-d33628e8cb10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325598945 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.1325598945
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.2428608902
Short name T873
Test name
Test status
Simulation time 761844415 ps
CPU time 23.01 seconds
Started Jun 10 07:49:42 PM PDT 24
Finished Jun 10 07:50:08 PM PDT 24
Peak memory 242184 kb
Host smart-8b472cd1-ed2c-48e1-bb66-49a867aaa41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428608902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.2428608902
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.954354268
Short name T11
Test name
Test status
Simulation time 1643161166 ps
CPU time 19.48 seconds
Started Jun 10 07:50:15 PM PDT 24
Finished Jun 10 07:50:36 PM PDT 24
Peak memory 242728 kb
Host smart-693f04e6-24e7-47d1-bceb-dec8c985f032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954354268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.954354268
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.1422048944
Short name T1050
Test name
Test status
Simulation time 14896004092 ps
CPU time 33.03 seconds
Started Jun 10 07:50:14 PM PDT 24
Finished Jun 10 07:50:49 PM PDT 24
Peak memory 246196 kb
Host smart-47949ae5-af60-4b0e-8d0e-aaf93cea5d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422048944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.1422048944
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.1739347550
Short name T481
Test name
Test status
Simulation time 6864198783 ps
CPU time 46.52 seconds
Started Jun 10 07:50:16 PM PDT 24
Finished Jun 10 07:51:05 PM PDT 24
Peak memory 242652 kb
Host smart-1e690890-8e78-45a7-bb01-94e680339279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739347550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.1739347550
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.2194300838
Short name T485
Test name
Test status
Simulation time 365022829 ps
CPU time 5.44 seconds
Started Jun 10 07:50:17 PM PDT 24
Finished Jun 10 07:50:24 PM PDT 24
Peak memory 242480 kb
Host smart-155e143e-257d-4aa1-badf-eaf7ed98860e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194300838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.2194300838
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.4112182900
Short name T192
Test name
Test status
Simulation time 3134804631 ps
CPU time 25.43 seconds
Started Jun 10 07:50:18 PM PDT 24
Finished Jun 10 07:50:45 PM PDT 24
Peak memory 248088 kb
Host smart-7788cd52-a4e7-4433-aed3-1e581f93fd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112182900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.4112182900
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.664676126
Short name T1135
Test name
Test status
Simulation time 7016687279 ps
CPU time 17.67 seconds
Started Jun 10 07:50:15 PM PDT 24
Finished Jun 10 07:50:35 PM PDT 24
Peak memory 243464 kb
Host smart-8686f07c-b4fe-495e-aae6-2349ce955aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664676126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.664676126
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.72853044
Short name T867
Test name
Test status
Simulation time 1425780670 ps
CPU time 19.19 seconds
Started Jun 10 07:50:15 PM PDT 24
Finished Jun 10 07:50:36 PM PDT 24
Peak memory 242068 kb
Host smart-44272a1f-4ef2-4297-8a62-85ff5b472df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72853044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.72853044
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.2262085241
Short name T106
Test name
Test status
Simulation time 745533192 ps
CPU time 10.91 seconds
Started Jun 10 07:50:15 PM PDT 24
Finished Jun 10 07:50:28 PM PDT 24
Peak memory 242176 kb
Host smart-816288bb-9fa8-4d5d-9d86-0d662218f6a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2262085241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.2262085241
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.304386040
Short name T946
Test name
Test status
Simulation time 220589079 ps
CPU time 4.47 seconds
Started Jun 10 07:50:15 PM PDT 24
Finished Jun 10 07:50:21 PM PDT 24
Peak memory 242064 kb
Host smart-d42aec9a-cd9f-413b-9746-e1acfa3c34ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304386040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.304386040
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.657329263
Short name T1072
Test name
Test status
Simulation time 271384233 ps
CPU time 4.79 seconds
Started Jun 10 07:50:16 PM PDT 24
Finished Jun 10 07:50:23 PM PDT 24
Peak memory 241888 kb
Host smart-d90db3d8-2bbe-4575-ad57-50077fa2c657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657329263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.
657329263
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.2621219051
Short name T470
Test name
Test status
Simulation time 8595300622 ps
CPU time 28.27 seconds
Started Jun 10 07:50:17 PM PDT 24
Finished Jun 10 07:50:47 PM PDT 24
Peak memory 243320 kb
Host smart-5bd3686c-d964-4d1f-aa5f-571b5b6d9b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621219051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.2621219051
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.665343721
Short name T927
Test name
Test status
Simulation time 2075910479 ps
CPU time 5.78 seconds
Started Jun 10 07:52:31 PM PDT 24
Finished Jun 10 07:52:39 PM PDT 24
Peak memory 242352 kb
Host smart-561d1d38-07f1-46f0-8160-d7f70634d7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665343721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.665343721
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.3775787695
Short name T572
Test name
Test status
Simulation time 525818869 ps
CPU time 4.17 seconds
Started Jun 10 07:52:31 PM PDT 24
Finished Jun 10 07:52:38 PM PDT 24
Peak memory 242340 kb
Host smart-2888f6d5-f092-4649-80ae-8c7395b0ee7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775787695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.3775787695
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.1086290930
Short name T300
Test name
Test status
Simulation time 247804492 ps
CPU time 4.5 seconds
Started Jun 10 07:52:32 PM PDT 24
Finished Jun 10 07:52:39 PM PDT 24
Peak memory 242404 kb
Host smart-07978143-af36-4151-9ec3-f5ee48cd29fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086290930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.1086290930
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.2774514476
Short name T1011
Test name
Test status
Simulation time 778536053 ps
CPU time 6.21 seconds
Started Jun 10 07:52:31 PM PDT 24
Finished Jun 10 07:52:40 PM PDT 24
Peak memory 242608 kb
Host smart-a30834ed-64de-438e-b247-8c1e2f1407c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774514476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.2774514476
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.4226952309
Short name T1027
Test name
Test status
Simulation time 138401658 ps
CPU time 4.23 seconds
Started Jun 10 07:52:31 PM PDT 24
Finished Jun 10 07:52:38 PM PDT 24
Peak memory 242436 kb
Host smart-6d27813b-edf3-417c-977e-38a2fe96bda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226952309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.4226952309
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.2238614181
Short name T334
Test name
Test status
Simulation time 245315271 ps
CPU time 5.08 seconds
Started Jun 10 07:52:32 PM PDT 24
Finished Jun 10 07:52:40 PM PDT 24
Peak memory 242096 kb
Host smart-687e17ea-9e33-46e3-a202-c76869bfcfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238614181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.2238614181
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.2590102678
Short name T972
Test name
Test status
Simulation time 205537625 ps
CPU time 5.81 seconds
Started Jun 10 07:52:30 PM PDT 24
Finished Jun 10 07:52:39 PM PDT 24
Peak memory 242152 kb
Host smart-9bb4bd91-eaa0-43b2-aafd-d99de516478f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590102678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.2590102678
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.735238889
Short name T947
Test name
Test status
Simulation time 1878363791 ps
CPU time 5.48 seconds
Started Jun 10 07:52:32 PM PDT 24
Finished Jun 10 07:52:40 PM PDT 24
Peak memory 242436 kb
Host smart-2e650e5f-76a7-4d66-b4de-4b6c9bdf8f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735238889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.735238889
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.381606641
Short name T724
Test name
Test status
Simulation time 215731924 ps
CPU time 6.22 seconds
Started Jun 10 07:52:31 PM PDT 24
Finished Jun 10 07:52:40 PM PDT 24
Peak memory 242240 kb
Host smart-1d5b329b-2e4a-4012-bd0a-24d21fa021a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381606641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.381606641
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.1545038787
Short name T1048
Test name
Test status
Simulation time 371357051 ps
CPU time 4.68 seconds
Started Jun 10 07:52:31 PM PDT 24
Finished Jun 10 07:52:38 PM PDT 24
Peak memory 242400 kb
Host smart-33fb0b22-080d-46d0-99ee-8eca9a0a01cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545038787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.1545038787
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.4269013454
Short name T452
Test name
Test status
Simulation time 426549188 ps
CPU time 6.12 seconds
Started Jun 10 07:52:35 PM PDT 24
Finished Jun 10 07:52:44 PM PDT 24
Peak memory 242200 kb
Host smart-ccf815ff-13c6-4786-943e-899150926a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269013454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.4269013454
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.2084572667
Short name T180
Test name
Test status
Simulation time 609413838 ps
CPU time 14.19 seconds
Started Jun 10 07:52:36 PM PDT 24
Finished Jun 10 07:52:52 PM PDT 24
Peak memory 242236 kb
Host smart-ef2afc62-e5ff-42bb-a2ff-a036a4fd9eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084572667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.2084572667
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.3318391186
Short name T415
Test name
Test status
Simulation time 2056884534 ps
CPU time 5.37 seconds
Started Jun 10 07:52:33 PM PDT 24
Finished Jun 10 07:52:41 PM PDT 24
Peak memory 242408 kb
Host smart-04e6c9f2-27f1-4254-bf03-d06614ccecf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318391186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.3318391186
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.3664710342
Short name T899
Test name
Test status
Simulation time 372591724 ps
CPU time 4.82 seconds
Started Jun 10 07:52:36 PM PDT 24
Finished Jun 10 07:52:43 PM PDT 24
Peak memory 242520 kb
Host smart-42c172fa-30ef-4c95-aa78-601e26f96630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664710342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.3664710342
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.594014602
Short name T84
Test name
Test status
Simulation time 153670306 ps
CPU time 3.29 seconds
Started Jun 10 07:52:34 PM PDT 24
Finished Jun 10 07:52:40 PM PDT 24
Peak memory 242624 kb
Host smart-504a6623-76aa-4cf0-993f-5c8ae29ad0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594014602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.594014602
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.2028206586
Short name T902
Test name
Test status
Simulation time 384776158 ps
CPU time 11.04 seconds
Started Jun 10 07:52:36 PM PDT 24
Finished Jun 10 07:52:49 PM PDT 24
Peak memory 242312 kb
Host smart-1447fdc2-1f60-47ae-acfb-bd38bce9d070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028206586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.2028206586
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.2298205930
Short name T1178
Test name
Test status
Simulation time 773652134 ps
CPU time 2.52 seconds
Started Jun 10 07:50:16 PM PDT 24
Finished Jun 10 07:50:21 PM PDT 24
Peak memory 240684 kb
Host smart-206e754e-36f0-4ba5-a70d-c26df9289234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298205930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.2298205930
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.3267652118
Short name T518
Test name
Test status
Simulation time 1080125409 ps
CPU time 20.43 seconds
Started Jun 10 07:50:15 PM PDT 24
Finished Jun 10 07:50:37 PM PDT 24
Peak memory 242876 kb
Host smart-bcfb38b9-3ae8-4d89-ba94-61bd0d7035fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267652118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.3267652118
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.2652472126
Short name T1117
Test name
Test status
Simulation time 551221098 ps
CPU time 13.46 seconds
Started Jun 10 07:50:14 PM PDT 24
Finished Jun 10 07:50:29 PM PDT 24
Peak memory 242156 kb
Host smart-4f8891ff-57df-43ae-be4d-0ddb867efde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652472126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.2652472126
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.646027975
Short name T500
Test name
Test status
Simulation time 1081915895 ps
CPU time 35.56 seconds
Started Jun 10 07:50:14 PM PDT 24
Finished Jun 10 07:50:51 PM PDT 24
Peak memory 242468 kb
Host smart-0e8cb91e-a686-4831-8b90-44f0cb4028f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646027975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.646027975
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.587293031
Short name T293
Test name
Test status
Simulation time 1127598549 ps
CPU time 6.07 seconds
Started Jun 10 07:50:16 PM PDT 24
Finished Jun 10 07:50:24 PM PDT 24
Peak memory 242284 kb
Host smart-ef766430-87ef-48fb-b960-4a5bc5890ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587293031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.587293031
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.29945804
Short name T778
Test name
Test status
Simulation time 1994089426 ps
CPU time 7.1 seconds
Started Jun 10 07:50:15 PM PDT 24
Finished Jun 10 07:50:24 PM PDT 24
Peak memory 242156 kb
Host smart-5f0172d5-6a89-4d20-b94e-2aa9a825911b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29945804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.29945804
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.2497748801
Short name T469
Test name
Test status
Simulation time 1041574796 ps
CPU time 18.3 seconds
Started Jun 10 07:50:16 PM PDT 24
Finished Jun 10 07:50:37 PM PDT 24
Peak memory 242052 kb
Host smart-54f14726-00f5-4a8e-9aed-600801cc1dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497748801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.2497748801
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.421849203
Short name T531
Test name
Test status
Simulation time 315240283 ps
CPU time 5.65 seconds
Started Jun 10 07:50:15 PM PDT 24
Finished Jun 10 07:50:22 PM PDT 24
Peak memory 242188 kb
Host smart-aaa16469-5e3f-4cf2-bf55-8a6ddf16d90d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=421849203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.421849203
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.3360013251
Short name T556
Test name
Test status
Simulation time 2116680815 ps
CPU time 5.14 seconds
Started Jun 10 07:50:17 PM PDT 24
Finished Jun 10 07:50:24 PM PDT 24
Peak memory 242204 kb
Host smart-6e4e4644-6e50-4169-8fb5-65db71e1d186
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3360013251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.3360013251
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.1828300905
Short name T681
Test name
Test status
Simulation time 1180229151 ps
CPU time 11.43 seconds
Started Jun 10 07:50:15 PM PDT 24
Finished Jun 10 07:50:28 PM PDT 24
Peak memory 242472 kb
Host smart-1745b7d8-365f-4060-ab38-51954bbd6d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828300905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.1828300905
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.4248167527
Short name T697
Test name
Test status
Simulation time 35795636600 ps
CPU time 319.01 seconds
Started Jun 10 07:50:19 PM PDT 24
Finished Jun 10 07:55:39 PM PDT 24
Peak memory 248392 kb
Host smart-b165c008-542d-4127-af59-3b8bde2f497a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248167527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.4248167527
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.2358247437
Short name T26
Test name
Test status
Simulation time 319681426702 ps
CPU time 2174.21 seconds
Started Jun 10 07:50:16 PM PDT 24
Finished Jun 10 08:26:32 PM PDT 24
Peak memory 419344 kb
Host smart-4b9ea072-5f34-4367-9113-2d6e63913f35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358247437 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.2358247437
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.2730047718
Short name T960
Test name
Test status
Simulation time 340222348 ps
CPU time 5.98 seconds
Started Jun 10 07:50:12 PM PDT 24
Finished Jun 10 07:50:19 PM PDT 24
Peak memory 242200 kb
Host smart-9a0b254d-0a52-4dcc-9016-df7245e76235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730047718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.2730047718
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.3442154849
Short name T836
Test name
Test status
Simulation time 1598568178 ps
CPU time 5.55 seconds
Started Jun 10 07:52:34 PM PDT 24
Finished Jun 10 07:52:42 PM PDT 24
Peak memory 242368 kb
Host smart-a1a826b3-2082-48dc-91d7-94dbc5156591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442154849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.3442154849
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.1354786102
Short name T966
Test name
Test status
Simulation time 395393362 ps
CPU time 3.97 seconds
Started Jun 10 07:52:34 PM PDT 24
Finished Jun 10 07:52:41 PM PDT 24
Peak memory 242476 kb
Host smart-8c8d7db4-7147-4ce3-af1c-b03b651f5616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354786102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.1354786102
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.3359991064
Short name T54
Test name
Test status
Simulation time 413072152 ps
CPU time 4.61 seconds
Started Jun 10 07:52:34 PM PDT 24
Finished Jun 10 07:52:41 PM PDT 24
Peak memory 242400 kb
Host smart-a52e9c4f-ecaf-410d-b406-decd4fb631f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359991064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3359991064
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.3891375823
Short name T401
Test name
Test status
Simulation time 136293137 ps
CPU time 6.14 seconds
Started Jun 10 07:52:33 PM PDT 24
Finished Jun 10 07:52:42 PM PDT 24
Peak memory 242248 kb
Host smart-7437f49f-95a7-4533-b0b6-9d2d9b614489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891375823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.3891375823
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.2964569002
Short name T1113
Test name
Test status
Simulation time 147855297 ps
CPU time 4.46 seconds
Started Jun 10 07:52:35 PM PDT 24
Finished Jun 10 07:52:42 PM PDT 24
Peak memory 242732 kb
Host smart-3ff839b4-4a6a-409e-9e6a-ee6f2d794c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964569002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.2964569002
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.3092442535
Short name T246
Test name
Test status
Simulation time 294115951 ps
CPU time 8.02 seconds
Started Jun 10 07:52:34 PM PDT 24
Finished Jun 10 07:52:45 PM PDT 24
Peak memory 242208 kb
Host smart-1587c9f8-ca67-4b9e-ad8b-cb94cf929ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092442535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.3092442535
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.2561822236
Short name T203
Test name
Test status
Simulation time 431967310 ps
CPU time 3.04 seconds
Started Jun 10 07:52:35 PM PDT 24
Finished Jun 10 07:52:40 PM PDT 24
Peak memory 242332 kb
Host smart-45e90f54-0cbd-4dbc-a086-8d551251a4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561822236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.2561822236
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.2464902103
Short name T626
Test name
Test status
Simulation time 808219303 ps
CPU time 7.18 seconds
Started Jun 10 07:52:30 PM PDT 24
Finished Jun 10 07:52:40 PM PDT 24
Peak memory 242196 kb
Host smart-2c9a24af-6488-451d-9ac2-3e336d169301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464902103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.2464902103
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.4222560363
Short name T976
Test name
Test status
Simulation time 467363151 ps
CPU time 4.15 seconds
Started Jun 10 07:52:34 PM PDT 24
Finished Jun 10 07:52:41 PM PDT 24
Peak memory 242492 kb
Host smart-57bd4d19-5a37-44d1-86c1-784b6a69b6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222560363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.4222560363
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.833958687
Short name T1090
Test name
Test status
Simulation time 669907298 ps
CPU time 6.38 seconds
Started Jun 10 07:52:36 PM PDT 24
Finished Jun 10 07:52:45 PM PDT 24
Peak memory 242112 kb
Host smart-a19a2f1b-fbbf-44b1-b269-f6fdaa7e311d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833958687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.833958687
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.3861665378
Short name T911
Test name
Test status
Simulation time 111709972 ps
CPU time 4.58 seconds
Started Jun 10 07:52:34 PM PDT 24
Finished Jun 10 07:52:41 PM PDT 24
Peak memory 242144 kb
Host smart-78adce81-3523-4163-b71c-70846352d3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861665378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.3861665378
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.166848469
Short name T429
Test name
Test status
Simulation time 1600439350 ps
CPU time 17.74 seconds
Started Jun 10 07:52:35 PM PDT 24
Finished Jun 10 07:52:55 PM PDT 24
Peak memory 242388 kb
Host smart-85725621-b121-4d02-b713-35cc4a3d7ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166848469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.166848469
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.806314538
Short name T1162
Test name
Test status
Simulation time 213384631 ps
CPU time 5.01 seconds
Started Jun 10 07:52:36 PM PDT 24
Finished Jun 10 07:52:43 PM PDT 24
Peak memory 242464 kb
Host smart-c0d3060e-cc40-4615-ad93-96fd516a1ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806314538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.806314538
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.105990118
Short name T418
Test name
Test status
Simulation time 161589124 ps
CPU time 3.34 seconds
Started Jun 10 07:52:34 PM PDT 24
Finished Jun 10 07:52:40 PM PDT 24
Peak memory 242556 kb
Host smart-c33c0c26-6024-41b0-bcaa-016ef2334676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105990118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.105990118
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.1221736544
Short name T1081
Test name
Test status
Simulation time 155695463 ps
CPU time 4.77 seconds
Started Jun 10 07:52:32 PM PDT 24
Finished Jun 10 07:52:39 PM PDT 24
Peak memory 242324 kb
Host smart-fd97f100-e63d-4c89-97eb-50af83bfa652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221736544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.1221736544
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.3173761802
Short name T607
Test name
Test status
Simulation time 210632102 ps
CPU time 5.45 seconds
Started Jun 10 07:52:39 PM PDT 24
Finished Jun 10 07:52:47 PM PDT 24
Peak memory 242476 kb
Host smart-fa06c296-2af0-43af-a812-9817dba12e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173761802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.3173761802
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.3746944419
Short name T178
Test name
Test status
Simulation time 1620970912 ps
CPU time 4.56 seconds
Started Jun 10 07:52:34 PM PDT 24
Finished Jun 10 07:52:41 PM PDT 24
Peak memory 242340 kb
Host smart-cf2fe1f0-2dda-4212-bde4-0a42c973b6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746944419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.3746944419
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.2868450433
Short name T1042
Test name
Test status
Simulation time 212663939 ps
CPU time 5.69 seconds
Started Jun 10 07:52:32 PM PDT 24
Finished Jun 10 07:52:41 PM PDT 24
Peak memory 242508 kb
Host smart-fa6f85f7-1f77-42a8-8c54-d77ad6920d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868450433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.2868450433
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.1447614243
Short name T449
Test name
Test status
Simulation time 202915735 ps
CPU time 3.3 seconds
Started Jun 10 07:52:39 PM PDT 24
Finished Jun 10 07:52:44 PM PDT 24
Peak memory 242520 kb
Host smart-7432b44b-adf3-4e9c-8a5f-5a23438c47d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447614243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.1447614243
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.1468876240
Short name T526
Test name
Test status
Simulation time 358084255 ps
CPU time 5.46 seconds
Started Jun 10 07:52:32 PM PDT 24
Finished Jun 10 07:52:41 PM PDT 24
Peak memory 242276 kb
Host smart-b7ed9fb6-89f6-4fd6-9d8e-50a7832e2177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468876240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.1468876240
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.24096460
Short name T509
Test name
Test status
Simulation time 91301279 ps
CPU time 1.73 seconds
Started Jun 10 07:50:28 PM PDT 24
Finished Jun 10 07:50:32 PM PDT 24
Peak memory 240796 kb
Host smart-3a3dc22a-5561-4973-96cf-e4ac3403cbae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24096460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.24096460
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.1017716680
Short name T75
Test name
Test status
Simulation time 1849431892 ps
CPU time 10.77 seconds
Started Jun 10 07:50:25 PM PDT 24
Finished Jun 10 07:50:39 PM PDT 24
Peak memory 242576 kb
Host smart-c5b89132-ccb1-4018-838e-3dd1cbc90cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017716680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.1017716680
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.850699891
Short name T1186
Test name
Test status
Simulation time 187531192 ps
CPU time 9.27 seconds
Started Jun 10 07:50:23 PM PDT 24
Finished Jun 10 07:50:35 PM PDT 24
Peak memory 242280 kb
Host smart-1fecf1b6-6c7c-41cd-95e2-cddd3fcd9927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850699891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.850699891
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.3545269017
Short name T601
Test name
Test status
Simulation time 416295093 ps
CPU time 3.8 seconds
Started Jun 10 07:50:15 PM PDT 24
Finished Jun 10 07:50:21 PM PDT 24
Peak memory 242308 kb
Host smart-8bae7123-d125-4647-8643-7ded5414c5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545269017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.3545269017
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.2197384169
Short name T447
Test name
Test status
Simulation time 3813026389 ps
CPU time 7.81 seconds
Started Jun 10 07:50:24 PM PDT 24
Finished Jun 10 07:50:34 PM PDT 24
Peak memory 242416 kb
Host smart-53444153-204d-4857-819c-24d13eaf4754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197384169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.2197384169
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.693150592
Short name T1123
Test name
Test status
Simulation time 815394133 ps
CPU time 15.86 seconds
Started Jun 10 07:50:24 PM PDT 24
Finished Jun 10 07:50:42 PM PDT 24
Peak memory 242496 kb
Host smart-91ac17f6-3506-44f2-80ee-dd6f054c3775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693150592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.693150592
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.1121059344
Short name T399
Test name
Test status
Simulation time 570667930 ps
CPU time 4.97 seconds
Started Jun 10 07:50:16 PM PDT 24
Finished Jun 10 07:50:23 PM PDT 24
Peak memory 242268 kb
Host smart-38ec23ce-f1de-4c6a-aeea-a9bda5409393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121059344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.1121059344
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.3117086540
Short name T130
Test name
Test status
Simulation time 1469416156 ps
CPU time 14.09 seconds
Started Jun 10 07:50:16 PM PDT 24
Finished Jun 10 07:50:32 PM PDT 24
Peak memory 242492 kb
Host smart-ceac722b-ec40-4580-ab1f-74b328d0bc36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3117086540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.3117086540
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.1073954607
Short name T1088
Test name
Test status
Simulation time 326399365 ps
CPU time 11.94 seconds
Started Jun 10 07:50:24 PM PDT 24
Finished Jun 10 07:50:38 PM PDT 24
Peak memory 242508 kb
Host smart-d66455a5-0c59-4d74-955d-c71bed83be6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1073954607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.1073954607
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.188312556
Short name T197
Test name
Test status
Simulation time 254295583 ps
CPU time 4.44 seconds
Started Jun 10 07:50:14 PM PDT 24
Finished Jun 10 07:50:21 PM PDT 24
Peak memory 242596 kb
Host smart-5a63935d-0829-4ffc-8d60-be9526c56a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188312556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.188312556
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.3587702989
Short name T1077
Test name
Test status
Simulation time 24287208100 ps
CPU time 196.11 seconds
Started Jun 10 07:50:28 PM PDT 24
Finished Jun 10 07:53:46 PM PDT 24
Peak memory 251016 kb
Host smart-188a6a37-2656-406d-9c95-d48c6ea1d172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587702989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all
.3587702989
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.2759774486
Short name T941
Test name
Test status
Simulation time 418772066921 ps
CPU time 904.92 seconds
Started Jun 10 07:50:27 PM PDT 24
Finished Jun 10 08:05:34 PM PDT 24
Peak memory 282056 kb
Host smart-6631a0a0-48db-4aab-885d-0aca3b2d386c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759774486 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.2759774486
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.1373925898
Short name T527
Test name
Test status
Simulation time 500394050 ps
CPU time 7.95 seconds
Started Jun 10 07:50:23 PM PDT 24
Finished Jun 10 07:50:33 PM PDT 24
Peak memory 242496 kb
Host smart-dbdaf58c-c81c-422d-b1f1-3d2e9bfb3b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373925898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.1373925898
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.2258674641
Short name T878
Test name
Test status
Simulation time 168069414 ps
CPU time 4.34 seconds
Started Jun 10 07:52:34 PM PDT 24
Finished Jun 10 07:52:41 PM PDT 24
Peak memory 242576 kb
Host smart-426b636e-1534-446d-880e-845fb08b32cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258674641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.2258674641
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.2509631249
Short name T497
Test name
Test status
Simulation time 376559826 ps
CPU time 8.2 seconds
Started Jun 10 07:52:34 PM PDT 24
Finished Jun 10 07:52:45 PM PDT 24
Peak memory 242096 kb
Host smart-04f6d434-3edf-450f-b45f-11174f71fffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509631249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.2509631249
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.4244475983
Short name T149
Test name
Test status
Simulation time 109597471 ps
CPU time 3.86 seconds
Started Jun 10 07:52:39 PM PDT 24
Finished Jun 10 07:52:45 PM PDT 24
Peak memory 242580 kb
Host smart-a95c8b36-4e9a-4534-bfb1-fffe219442fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244475983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.4244475983
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.1285809887
Short name T226
Test name
Test status
Simulation time 398655752 ps
CPU time 6.56 seconds
Started Jun 10 07:52:39 PM PDT 24
Finished Jun 10 07:52:48 PM PDT 24
Peak memory 242560 kb
Host smart-29d88f54-ad38-45f9-b4d2-2c5fae26bf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285809887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.1285809887
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.1180350913
Short name T28
Test name
Test status
Simulation time 158949511 ps
CPU time 4.27 seconds
Started Jun 10 07:52:39 PM PDT 24
Finished Jun 10 07:52:46 PM PDT 24
Peak memory 242488 kb
Host smart-6c340fa4-df32-4114-a29b-60f800be9396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180350913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.1180350913
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.2264975643
Short name T804
Test name
Test status
Simulation time 450814703 ps
CPU time 11.04 seconds
Started Jun 10 07:52:34 PM PDT 24
Finished Jun 10 07:52:48 PM PDT 24
Peak memory 242560 kb
Host smart-116eda54-2c16-47f0-93cc-68a6b43de54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264975643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.2264975643
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.1756994776
Short name T1106
Test name
Test status
Simulation time 151049360 ps
CPU time 4.27 seconds
Started Jun 10 07:52:35 PM PDT 24
Finished Jun 10 07:52:41 PM PDT 24
Peak memory 242396 kb
Host smart-4de20ba5-00ed-4a21-8ddc-6616666fa1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756994776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.1756994776
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.1554594695
Short name T645
Test name
Test status
Simulation time 531499491 ps
CPU time 5.71 seconds
Started Jun 10 07:52:35 PM PDT 24
Finished Jun 10 07:52:43 PM PDT 24
Peak memory 242100 kb
Host smart-95143226-80ba-40b2-ba41-d4437d09f4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554594695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.1554594695
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.3828255784
Short name T50
Test name
Test status
Simulation time 228901692 ps
CPU time 3.83 seconds
Started Jun 10 07:52:29 PM PDT 24
Finished Jun 10 07:52:36 PM PDT 24
Peak memory 242392 kb
Host smart-3708a760-6ff6-4a0c-a544-9cef63fe9ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828255784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.3828255784
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.628364390
Short name T847
Test name
Test status
Simulation time 311347408 ps
CPU time 11.98 seconds
Started Jun 10 07:52:30 PM PDT 24
Finished Jun 10 07:52:44 PM PDT 24
Peak memory 242328 kb
Host smart-ff546bfb-56c3-41aa-b566-d6fa75eb2a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628364390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.628364390
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.1268949874
Short name T59
Test name
Test status
Simulation time 185279020 ps
CPU time 5.03 seconds
Started Jun 10 07:52:30 PM PDT 24
Finished Jun 10 07:52:38 PM PDT 24
Peak memory 242400 kb
Host smart-87b751c6-50bc-431d-94b1-463746027857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268949874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.1268949874
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.1899582384
Short name T486
Test name
Test status
Simulation time 504390958 ps
CPU time 9.26 seconds
Started Jun 10 07:52:32 PM PDT 24
Finished Jun 10 07:52:44 PM PDT 24
Peak memory 242080 kb
Host smart-deac6388-4721-4252-ad25-206ccdaf7030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899582384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.1899582384
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.1737067045
Short name T299
Test name
Test status
Simulation time 888624825 ps
CPU time 14.16 seconds
Started Jun 10 07:52:33 PM PDT 24
Finished Jun 10 07:52:50 PM PDT 24
Peak memory 242232 kb
Host smart-fa2412d9-90a9-432f-8293-60eb130c7f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737067045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.1737067045
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.2980587607
Short name T575
Test name
Test status
Simulation time 122709754 ps
CPU time 4.45 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:52:53 PM PDT 24
Peak memory 242420 kb
Host smart-3ad8c484-f726-4149-bdd3-e7f766883ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980587607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.2980587607
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.3818789652
Short name T595
Test name
Test status
Simulation time 97377303 ps
CPU time 3.37 seconds
Started Jun 10 07:52:44 PM PDT 24
Finished Jun 10 07:52:50 PM PDT 24
Peak memory 242088 kb
Host smart-f8896d83-46e9-4a4c-b239-83be3c044ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818789652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.3818789652
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.1179146746
Short name T954
Test name
Test status
Simulation time 164189102 ps
CPU time 4.55 seconds
Started Jun 10 07:52:46 PM PDT 24
Finished Jun 10 07:52:53 PM PDT 24
Peak memory 242368 kb
Host smart-d5911219-47eb-4c53-abaa-2e0d92b571e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179146746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.1179146746
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.2725364382
Short name T1094
Test name
Test status
Simulation time 364278170 ps
CPU time 8.94 seconds
Started Jun 10 07:52:46 PM PDT 24
Finished Jun 10 07:52:59 PM PDT 24
Peak memory 242108 kb
Host smart-1f461c83-287d-4953-9979-d4246c6b498e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725364382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.2725364382
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.1175522057
Short name T473
Test name
Test status
Simulation time 397807023 ps
CPU time 4.62 seconds
Started Jun 10 07:52:44 PM PDT 24
Finished Jun 10 07:52:52 PM PDT 24
Peak memory 242400 kb
Host smart-fcae9741-6ec5-4428-84b6-29d0c0f03c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175522057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.1175522057
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.2343863526
Short name T655
Test name
Test status
Simulation time 1394984243 ps
CPU time 4.81 seconds
Started Jun 10 07:52:44 PM PDT 24
Finished Jun 10 07:52:52 PM PDT 24
Peak memory 242076 kb
Host smart-6d576bdd-cc78-4912-96d3-449d1baf9649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343863526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.2343863526
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.711572808
Short name T1068
Test name
Test status
Simulation time 141062141 ps
CPU time 1.69 seconds
Started Jun 10 07:50:28 PM PDT 24
Finished Jun 10 07:50:32 PM PDT 24
Peak memory 240704 kb
Host smart-be8e4ebe-08d5-43ba-aa5b-cc9261308220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711572808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.711572808
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.3891647367
Short name T496
Test name
Test status
Simulation time 7781262019 ps
CPU time 15.47 seconds
Started Jun 10 07:50:26 PM PDT 24
Finished Jun 10 07:50:45 PM PDT 24
Peak memory 243116 kb
Host smart-893eb950-6428-461a-b02f-28248e2074fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891647367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.3891647367
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.2645335111
Short name T340
Test name
Test status
Simulation time 7112505214 ps
CPU time 16.29 seconds
Started Jun 10 07:50:24 PM PDT 24
Finished Jun 10 07:50:43 PM PDT 24
Peak memory 242560 kb
Host smart-a75af39e-082f-496b-9d02-89b593b3d247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645335111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.2645335111
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.780304948
Short name T981
Test name
Test status
Simulation time 3859053968 ps
CPU time 14.32 seconds
Started Jun 10 07:50:24 PM PDT 24
Finished Jun 10 07:50:41 PM PDT 24
Peak memory 242320 kb
Host smart-efbf185f-cbce-4bd7-bdfc-bb8434c0fd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780304948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.780304948
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.4006472214
Short name T510
Test name
Test status
Simulation time 324061333 ps
CPU time 4.32 seconds
Started Jun 10 07:50:24 PM PDT 24
Finished Jun 10 07:50:31 PM PDT 24
Peak memory 242496 kb
Host smart-b20c9193-c3e2-4f73-a08a-87c4e69c4e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006472214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.4006472214
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.3078652612
Short name T156
Test name
Test status
Simulation time 16062254856 ps
CPU time 24.05 seconds
Started Jun 10 07:50:25 PM PDT 24
Finished Jun 10 07:50:52 PM PDT 24
Peak memory 249188 kb
Host smart-9a2709e4-7a63-4236-8386-4058de7123a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078652612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.3078652612
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.3608252494
Short name T738
Test name
Test status
Simulation time 647891049 ps
CPU time 20.74 seconds
Started Jun 10 07:50:25 PM PDT 24
Finished Jun 10 07:50:48 PM PDT 24
Peak memory 242916 kb
Host smart-10350965-d7ef-41cc-bf08-5700c5435b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608252494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.3608252494
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.1111062808
Short name T617
Test name
Test status
Simulation time 173139071 ps
CPU time 3.88 seconds
Started Jun 10 07:50:25 PM PDT 24
Finished Jun 10 07:50:32 PM PDT 24
Peak memory 242152 kb
Host smart-fe716bc7-20a6-41c8-a5e0-b59d333f790b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111062808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.1111062808
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.448161940
Short name T1052
Test name
Test status
Simulation time 644924173 ps
CPU time 16.49 seconds
Started Jun 10 07:50:24 PM PDT 24
Finished Jun 10 07:50:43 PM PDT 24
Peak memory 242120 kb
Host smart-bceb7a1b-a847-4b60-8a17-a68d2917bfed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448161940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.448161940
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.4033093811
Short name T367
Test name
Test status
Simulation time 607057551 ps
CPU time 11.34 seconds
Started Jun 10 07:50:23 PM PDT 24
Finished Jun 10 07:50:35 PM PDT 24
Peak memory 242252 kb
Host smart-e33370fe-c90b-4a3a-a811-774b346b500a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4033093811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.4033093811
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.2040182538
Short name T816
Test name
Test status
Simulation time 1151696382 ps
CPU time 6.04 seconds
Started Jun 10 07:50:26 PM PDT 24
Finished Jun 10 07:50:34 PM PDT 24
Peak memory 242160 kb
Host smart-8d164215-e9db-4eb7-8f21-56b1102d675a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040182538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.2040182538
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.2013933669
Short name T1005
Test name
Test status
Simulation time 12365751653 ps
CPU time 21.83 seconds
Started Jun 10 07:50:24 PM PDT 24
Finished Jun 10 07:50:48 PM PDT 24
Peak memory 242068 kb
Host smart-3ec29697-ced8-4a92-8c2e-100a95f98c79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013933669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all
.2013933669
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.997233585
Short name T303
Test name
Test status
Simulation time 655898719178 ps
CPU time 2682.9 seconds
Started Jun 10 07:50:29 PM PDT 24
Finished Jun 10 08:35:14 PM PDT 24
Peak memory 575284 kb
Host smart-7e204cdb-428b-427a-99ae-2a1c419f04cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997233585 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.997233585
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.3706148186
Short name T1006
Test name
Test status
Simulation time 1070361980 ps
CPU time 17.74 seconds
Started Jun 10 07:50:23 PM PDT 24
Finished Jun 10 07:50:43 PM PDT 24
Peak memory 242244 kb
Host smart-26f0f5fd-24c5-41d7-b78b-b5662c7aa49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706148186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.3706148186
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.269527302
Short name T120
Test name
Test status
Simulation time 523570219 ps
CPU time 3.12 seconds
Started Jun 10 07:52:44 PM PDT 24
Finished Jun 10 07:52:51 PM PDT 24
Peak memory 242304 kb
Host smart-fadcda27-56bc-4d46-82ab-0c9fd9b8d0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269527302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.269527302
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.3059471057
Short name T114
Test name
Test status
Simulation time 481933324 ps
CPU time 7.92 seconds
Started Jun 10 07:52:43 PM PDT 24
Finished Jun 10 07:52:52 PM PDT 24
Peak memory 242296 kb
Host smart-5d0e6110-9d31-4734-9473-6264c01ffa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059471057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.3059471057
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.3406593322
Short name T70
Test name
Test status
Simulation time 1445526911 ps
CPU time 4.57 seconds
Started Jun 10 07:52:50 PM PDT 24
Finished Jun 10 07:52:58 PM PDT 24
Peak memory 242320 kb
Host smart-5c7c6859-5db4-4bf0-ae1b-62db263fd587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406593322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.3406593322
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.1067978669
Short name T230
Test name
Test status
Simulation time 188980999 ps
CPU time 5.57 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:52:53 PM PDT 24
Peak memory 242392 kb
Host smart-003b2e10-f83e-468b-9112-07d6033be59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067978669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.1067978669
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.3045369018
Short name T968
Test name
Test status
Simulation time 246150318 ps
CPU time 3.3 seconds
Started Jun 10 07:52:42 PM PDT 24
Finished Jun 10 07:52:47 PM PDT 24
Peak memory 242352 kb
Host smart-55b2bd2b-e4c4-4291-bca9-890a523c3b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045369018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.3045369018
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.2180018150
Short name T838
Test name
Test status
Simulation time 355605185 ps
CPU time 12.57 seconds
Started Jun 10 07:52:44 PM PDT 24
Finished Jun 10 07:52:59 PM PDT 24
Peak memory 242256 kb
Host smart-791a5f43-a8fe-4c85-aed8-3f35b71065e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180018150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.2180018150
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.3751486424
Short name T227
Test name
Test status
Simulation time 158577105 ps
CPU time 7.36 seconds
Started Jun 10 07:52:44 PM PDT 24
Finished Jun 10 07:52:54 PM PDT 24
Peak memory 242072 kb
Host smart-6d415dea-453f-4008-8049-7566e902f82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751486424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.3751486424
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.172766102
Short name T1049
Test name
Test status
Simulation time 160069199 ps
CPU time 3.84 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:52:52 PM PDT 24
Peak memory 242584 kb
Host smart-f4f30b91-b003-482c-8801-ad7af852bb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172766102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.172766102
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.1031136770
Short name T420
Test name
Test status
Simulation time 8843439286 ps
CPU time 14.91 seconds
Started Jun 10 07:52:49 PM PDT 24
Finished Jun 10 07:53:07 PM PDT 24
Peak memory 242536 kb
Host smart-71696ce0-1841-4b24-9e0e-1fe478457ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031136770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.1031136770
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.2004638352
Short name T948
Test name
Test status
Simulation time 177327098 ps
CPU time 4.6 seconds
Started Jun 10 07:52:48 PM PDT 24
Finished Jun 10 07:52:56 PM PDT 24
Peak memory 242596 kb
Host smart-b89c548b-ef28-46df-b428-34910c342d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004638352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.2004638352
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.1175128440
Short name T679
Test name
Test status
Simulation time 191673521 ps
CPU time 4.34 seconds
Started Jun 10 07:52:50 PM PDT 24
Finished Jun 10 07:52:59 PM PDT 24
Peak memory 242248 kb
Host smart-e2ff4061-4573-439c-b95b-4e87e57452c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175128440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.1175128440
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.2954887304
Short name T625
Test name
Test status
Simulation time 238398383 ps
CPU time 6.29 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:52:55 PM PDT 24
Peak memory 242044 kb
Host smart-6082adde-bb49-4534-8720-b45820a67e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954887304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.2954887304
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.2003922298
Short name T502
Test name
Test status
Simulation time 404743419 ps
CPU time 12.49 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:53:00 PM PDT 24
Peak memory 242176 kb
Host smart-dff966a8-7dac-40d6-8289-32052bd1fbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003922298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.2003922298
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.926049929
Short name T1172
Test name
Test status
Simulation time 115630485 ps
CPU time 3.51 seconds
Started Jun 10 07:52:42 PM PDT 24
Finished Jun 10 07:52:48 PM PDT 24
Peak memory 242268 kb
Host smart-b4d8dba5-4de6-434c-8afc-0362584c23b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926049929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.926049929
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.1050740633
Short name T1167
Test name
Test status
Simulation time 5426254485 ps
CPU time 16.98 seconds
Started Jun 10 07:52:47 PM PDT 24
Finished Jun 10 07:53:07 PM PDT 24
Peak memory 242344 kb
Host smart-f0a0fcdd-04df-42f6-8ba1-2620b4371aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050740633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.1050740633
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.2722257705
Short name T773
Test name
Test status
Simulation time 1887782961 ps
CPU time 5.78 seconds
Started Jun 10 07:52:46 PM PDT 24
Finished Jun 10 07:52:55 PM PDT 24
Peak memory 242132 kb
Host smart-da5b80b9-b927-48e6-ad08-62c0739dae09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722257705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.2722257705
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.899813221
Short name T308
Test name
Test status
Simulation time 363375421 ps
CPU time 2.35 seconds
Started Jun 10 07:50:27 PM PDT 24
Finished Jun 10 07:50:32 PM PDT 24
Peak memory 241036 kb
Host smart-ac05b125-b389-41d5-be27-32eac7456b8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899813221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.899813221
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.2768126342
Short name T109
Test name
Test status
Simulation time 9772120554 ps
CPU time 18.75 seconds
Started Jun 10 07:50:23 PM PDT 24
Finished Jun 10 07:50:44 PM PDT 24
Peak memory 243960 kb
Host smart-2d9b8977-2808-4231-a71d-c2d7f60bc3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768126342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.2768126342
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.2476950310
Short name T585
Test name
Test status
Simulation time 320560883 ps
CPU time 19.72 seconds
Started Jun 10 07:50:28 PM PDT 24
Finished Jun 10 07:50:50 PM PDT 24
Peak memory 248920 kb
Host smart-93759022-aabb-4951-b763-2e3d26d923e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476950310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.2476950310
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.606514262
Short name T904
Test name
Test status
Simulation time 1599490892 ps
CPU time 11.7 seconds
Started Jun 10 07:50:23 PM PDT 24
Finished Jun 10 07:50:37 PM PDT 24
Peak memory 242132 kb
Host smart-6ef0e24c-a00d-4164-a2d6-2d87749da789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606514262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.606514262
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.1500504111
Short name T143
Test name
Test status
Simulation time 144865907 ps
CPU time 3.52 seconds
Started Jun 10 07:50:23 PM PDT 24
Finished Jun 10 07:50:29 PM PDT 24
Peak memory 242328 kb
Host smart-20743d58-fdb8-4896-af69-8bb71fa52de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500504111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.1500504111
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.1367979613
Short name T437
Test name
Test status
Simulation time 340310086 ps
CPU time 4.48 seconds
Started Jun 10 07:50:27 PM PDT 24
Finished Jun 10 07:50:35 PM PDT 24
Peak memory 242120 kb
Host smart-cd63079d-d814-450c-9295-7da8c478a134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367979613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.1367979613
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.915012585
Short name T194
Test name
Test status
Simulation time 4922710489 ps
CPU time 13.15 seconds
Started Jun 10 07:50:29 PM PDT 24
Finished Jun 10 07:50:44 PM PDT 24
Peak memory 242836 kb
Host smart-e4cd2bfc-70e2-4dec-befa-fb40d4632ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915012585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.915012585
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.2268865746
Short name T166
Test name
Test status
Simulation time 408582177 ps
CPU time 6.01 seconds
Started Jun 10 07:50:24 PM PDT 24
Finished Jun 10 07:50:33 PM PDT 24
Peak memory 242440 kb
Host smart-53f4049a-03d3-4ae4-8fd5-912a5900cd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268865746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.2268865746
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.3110487845
Short name T378
Test name
Test status
Simulation time 1111293675 ps
CPU time 11.91 seconds
Started Jun 10 07:50:23 PM PDT 24
Finished Jun 10 07:50:37 PM PDT 24
Peak memory 242240 kb
Host smart-db23577d-f059-44c0-8dad-6f716dbb5ba0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3110487845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.3110487845
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.2419027823
Short name T1134
Test name
Test status
Simulation time 372365501 ps
CPU time 7.48 seconds
Started Jun 10 07:50:24 PM PDT 24
Finished Jun 10 07:50:34 PM PDT 24
Peak memory 242516 kb
Host smart-b2006a00-ea20-4a4c-8021-6d69b6b656f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2419027823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.2419027823
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.1534232741
Short name T608
Test name
Test status
Simulation time 290750734 ps
CPU time 6.94 seconds
Started Jun 10 07:50:27 PM PDT 24
Finished Jun 10 07:50:37 PM PDT 24
Peak memory 242000 kb
Host smart-861a0843-d470-43da-9949-e16c4af0a6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534232741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.1534232741
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.1474228255
Short name T1156
Test name
Test status
Simulation time 2016845009 ps
CPU time 38 seconds
Started Jun 10 07:50:25 PM PDT 24
Finished Jun 10 07:51:05 PM PDT 24
Peak memory 242148 kb
Host smart-fc22530b-4bb0-49ac-8e19-2651a7451a60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474228255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all
.1474228255
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.1625185666
Short name T243
Test name
Test status
Simulation time 762674116821 ps
CPU time 1279.05 seconds
Started Jun 10 07:50:25 PM PDT 24
Finished Jun 10 08:11:46 PM PDT 24
Peak memory 393928 kb
Host smart-711ab6b3-43fa-4a5c-9122-8002f6942869
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625185666 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.1625185666
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.827427779
Short name T824
Test name
Test status
Simulation time 390418786 ps
CPU time 9.21 seconds
Started Jun 10 07:50:23 PM PDT 24
Finished Jun 10 07:50:35 PM PDT 24
Peak memory 242484 kb
Host smart-0278d8c0-050b-43f8-89f5-4bb07cd840d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827427779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.827427779
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.2479889062
Short name T471
Test name
Test status
Simulation time 2701365283 ps
CPU time 5.58 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:52:54 PM PDT 24
Peak memory 242404 kb
Host smart-afed6cb9-ad6a-48d9-bb50-df0f58a60d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479889062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.2479889062
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.1100281474
Short name T121
Test name
Test status
Simulation time 228636709 ps
CPU time 12.27 seconds
Started Jun 10 07:52:44 PM PDT 24
Finished Jun 10 07:52:59 PM PDT 24
Peak memory 242060 kb
Host smart-f2c59994-ac26-4904-8823-8d94add15b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100281474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.1100281474
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.2913520337
Short name T691
Test name
Test status
Simulation time 596342360 ps
CPU time 3.97 seconds
Started Jun 10 07:52:46 PM PDT 24
Finished Jun 10 07:52:53 PM PDT 24
Peak memory 242516 kb
Host smart-acaa1920-625b-45ab-b73d-45e4af77704c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913520337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.2913520337
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.1522264699
Short name T66
Test name
Test status
Simulation time 179180009 ps
CPU time 7.5 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:52:56 PM PDT 24
Peak memory 242440 kb
Host smart-ed2d5c78-e83e-4385-9448-ad4abf41b441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522264699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.1522264699
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.2211071914
Short name T1145
Test name
Test status
Simulation time 115084922 ps
CPU time 4.19 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:52:52 PM PDT 24
Peak memory 242404 kb
Host smart-c3ab49bb-ab53-4429-af78-156da3f1a421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211071914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.2211071914
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.488066970
Short name T228
Test name
Test status
Simulation time 783644848 ps
CPU time 20.18 seconds
Started Jun 10 07:52:47 PM PDT 24
Finished Jun 10 07:53:10 PM PDT 24
Peak memory 242380 kb
Host smart-81d524f1-b253-4a64-9423-b2c276f4d5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488066970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.488066970
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.2626418585
Short name T636
Test name
Test status
Simulation time 224936133 ps
CPU time 3.83 seconds
Started Jun 10 07:52:48 PM PDT 24
Finished Jun 10 07:52:55 PM PDT 24
Peak memory 242436 kb
Host smart-0f889573-13bd-4b3e-8427-65021ca5fa1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626418585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.2626418585
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.3236532450
Short name T147
Test name
Test status
Simulation time 531668921 ps
CPU time 7.88 seconds
Started Jun 10 07:52:43 PM PDT 24
Finished Jun 10 07:52:53 PM PDT 24
Peak memory 242032 kb
Host smart-dc13d727-d70f-484e-9f46-40e65557267d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236532450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.3236532450
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.224056623
Short name T136
Test name
Test status
Simulation time 1914498060 ps
CPU time 5.22 seconds
Started Jun 10 07:52:49 PM PDT 24
Finished Jun 10 07:52:57 PM PDT 24
Peak memory 242332 kb
Host smart-1be7fa8a-609d-4224-a642-e53fd85d0ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224056623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.224056623
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.3500667450
Short name T688
Test name
Test status
Simulation time 154390087 ps
CPU time 4.62 seconds
Started Jun 10 07:52:48 PM PDT 24
Finished Jun 10 07:52:55 PM PDT 24
Peak memory 242028 kb
Host smart-1b13e113-8b61-4586-9904-c6403fa24b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500667450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.3500667450
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.1928651831
Short name T1030
Test name
Test status
Simulation time 431460675 ps
CPU time 4.37 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:52:52 PM PDT 24
Peak memory 242672 kb
Host smart-79d62d77-100c-4b2b-8245-e0aafc66454f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928651831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.1928651831
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.3556213250
Short name T638
Test name
Test status
Simulation time 419782887 ps
CPU time 3.36 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:52:51 PM PDT 24
Peak memory 242392 kb
Host smart-61a45ca0-6e8a-417f-810b-bf50637ca266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556213250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.3556213250
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.2314322850
Short name T621
Test name
Test status
Simulation time 514219399 ps
CPU time 4.16 seconds
Started Jun 10 07:52:42 PM PDT 24
Finished Jun 10 07:52:48 PM PDT 24
Peak memory 242496 kb
Host smart-64d22d20-597c-4e54-976e-af0e13df24a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314322850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.2314322850
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.2959086559
Short name T168
Test name
Test status
Simulation time 360607233 ps
CPU time 5.07 seconds
Started Jun 10 07:52:46 PM PDT 24
Finished Jun 10 07:52:54 PM PDT 24
Peak memory 242416 kb
Host smart-d0fb2973-549c-44e2-80ca-c9a1dfdfb419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959086559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.2959086559
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.441705262
Short name T770
Test name
Test status
Simulation time 317011753 ps
CPU time 7.76 seconds
Started Jun 10 07:52:44 PM PDT 24
Finished Jun 10 07:52:55 PM PDT 24
Peak memory 242516 kb
Host smart-6ad0e26f-3615-4573-8aa2-e2e2a1f83c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441705262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.441705262
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.2171642085
Short name T1161
Test name
Test status
Simulation time 172981389 ps
CPU time 4.33 seconds
Started Jun 10 07:52:44 PM PDT 24
Finished Jun 10 07:52:50 PM PDT 24
Peak memory 242328 kb
Host smart-2dafbf90-47e5-46dc-ba9b-05ad2fd73f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171642085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.2171642085
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.1014405798
Short name T519
Test name
Test status
Simulation time 245637762 ps
CPU time 7.08 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:52:56 PM PDT 24
Peak memory 242156 kb
Host smart-2befa3dc-9c9a-4830-a0d5-651768963d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014405798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.1014405798
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.3248720534
Short name T176
Test name
Test status
Simulation time 177015688 ps
CPU time 4.2 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:52:52 PM PDT 24
Peak memory 242364 kb
Host smart-eb7d1a8b-2aae-420c-8fef-c24c3ec14bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248720534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.3248720534
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.1010715216
Short name T871
Test name
Test status
Simulation time 196015120 ps
CPU time 6.36 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:52:55 PM PDT 24
Peak memory 242192 kb
Host smart-a6c750e9-c074-44bd-9654-b0443c90563b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010715216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.1010715216
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.2672924675
Short name T833
Test name
Test status
Simulation time 74434653 ps
CPU time 2.16 seconds
Started Jun 10 07:50:25 PM PDT 24
Finished Jun 10 07:50:30 PM PDT 24
Peak memory 240832 kb
Host smart-e16090ea-9954-4ef2-8faa-e773e8fb3d1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672924675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.2672924675
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.2039261741
Short name T781
Test name
Test status
Simulation time 1033392746 ps
CPU time 12.94 seconds
Started Jun 10 07:50:29 PM PDT 24
Finished Jun 10 07:50:44 PM PDT 24
Peak memory 249040 kb
Host smart-4299a760-af95-4db7-9e27-f4a76cb9d6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039261741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.2039261741
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.88206305
Short name T421
Test name
Test status
Simulation time 283714576 ps
CPU time 17.78 seconds
Started Jun 10 07:50:24 PM PDT 24
Finished Jun 10 07:50:45 PM PDT 24
Peak memory 242300 kb
Host smart-2815663a-8b7c-4dfd-86d9-882d5e53d55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88206305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.88206305
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.393134067
Short name T105
Test name
Test status
Simulation time 8835783924 ps
CPU time 19.11 seconds
Started Jun 10 07:50:24 PM PDT 24
Finished Jun 10 07:50:45 PM PDT 24
Peak memory 243712 kb
Host smart-e6d39445-90b2-4120-bfa6-b28d02bde75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393134067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.393134067
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.2908084288
Short name T931
Test name
Test status
Simulation time 134704867 ps
CPU time 3.82 seconds
Started Jun 10 07:50:24 PM PDT 24
Finished Jun 10 07:50:30 PM PDT 24
Peak memory 242264 kb
Host smart-d7f68ca8-2a21-437c-83a9-36c47f014212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908084288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.2908084288
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.958049667
Short name T461
Test name
Test status
Simulation time 4174216506 ps
CPU time 10.27 seconds
Started Jun 10 07:50:23 PM PDT 24
Finished Jun 10 07:50:36 PM PDT 24
Peak memory 242848 kb
Host smart-02a158d6-b07d-417c-adf0-e8cdae9fe984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958049667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.958049667
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.777106179
Short name T722
Test name
Test status
Simulation time 298272662 ps
CPU time 10.17 seconds
Started Jun 10 07:50:29 PM PDT 24
Finished Jun 10 07:50:41 PM PDT 24
Peak memory 242088 kb
Host smart-e6d91c69-f905-4894-aa6f-6c8bbb772fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777106179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.777106179
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.494384567
Short name T616
Test name
Test status
Simulation time 292930114 ps
CPU time 9.23 seconds
Started Jun 10 07:50:23 PM PDT 24
Finished Jun 10 07:50:34 PM PDT 24
Peak memory 242448 kb
Host smart-54175840-8db7-445b-a41b-90f715d2850a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494384567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.494384567
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.668164696
Short name T1098
Test name
Test status
Simulation time 860187931 ps
CPU time 17.3 seconds
Started Jun 10 07:50:23 PM PDT 24
Finished Jun 10 07:50:43 PM PDT 24
Peak memory 242056 kb
Host smart-eddf1235-f0e1-44c0-9aab-fd59fa77ec7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=668164696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.668164696
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.1791654825
Short name T364
Test name
Test status
Simulation time 265813244 ps
CPU time 8.76 seconds
Started Jun 10 07:50:27 PM PDT 24
Finished Jun 10 07:50:38 PM PDT 24
Peak memory 242308 kb
Host smart-de93d54e-c2c8-462f-a0de-90581538cd7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1791654825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.1791654825
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.2893514169
Short name T506
Test name
Test status
Simulation time 4381329969 ps
CPU time 10.51 seconds
Started Jun 10 07:50:25 PM PDT 24
Finished Jun 10 07:50:39 PM PDT 24
Peak memory 242420 kb
Host smart-bda858a2-2693-4072-b4ba-272c90e0f23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893514169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.2893514169
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.3397863893
Short name T91
Test name
Test status
Simulation time 13447873398 ps
CPU time 141.87 seconds
Started Jun 10 07:50:24 PM PDT 24
Finished Jun 10 07:52:49 PM PDT 24
Peak memory 257344 kb
Host smart-7e4ee80e-d2f6-49fb-86c0-30dca1431c4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397863893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all
.3397863893
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.2970612948
Short name T128
Test name
Test status
Simulation time 967159599392 ps
CPU time 2527.38 seconds
Started Jun 10 07:50:25 PM PDT 24
Finished Jun 10 08:32:36 PM PDT 24
Peak memory 371836 kb
Host smart-0dfca4e8-f810-4d6e-bb99-fc57bcda1b83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970612948 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.2970612948
Directory /workspace/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.3965596038
Short name T551
Test name
Test status
Simulation time 1614931655 ps
CPU time 12.22 seconds
Started Jun 10 07:50:24 PM PDT 24
Finished Jun 10 07:50:39 PM PDT 24
Peak memory 242584 kb
Host smart-f0b70089-2301-4016-ae04-214758adcf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965596038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.3965596038
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.3803809596
Short name T58
Test name
Test status
Simulation time 270923763 ps
CPU time 5.26 seconds
Started Jun 10 07:52:46 PM PDT 24
Finished Jun 10 07:52:54 PM PDT 24
Peak memory 242588 kb
Host smart-5ae25e42-1303-4fcb-af45-8b50cb605dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803809596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.3803809596
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.788583093
Short name T122
Test name
Test status
Simulation time 116280488 ps
CPU time 4.33 seconds
Started Jun 10 07:52:44 PM PDT 24
Finished Jun 10 07:52:50 PM PDT 24
Peak memory 242292 kb
Host smart-ccbfd9c4-5cc4-4d97-b5be-7f5a20c8ca30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788583093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.788583093
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.793116891
Short name T434
Test name
Test status
Simulation time 2040318414 ps
CPU time 3.62 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:52:52 PM PDT 24
Peak memory 242668 kb
Host smart-014a2520-6ad9-4c69-9634-2f48b74b4dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793116891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.793116891
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.1065568876
Short name T802
Test name
Test status
Simulation time 261328674 ps
CPU time 4.35 seconds
Started Jun 10 07:52:50 PM PDT 24
Finished Jun 10 07:52:59 PM PDT 24
Peak memory 242160 kb
Host smart-cc86879a-1272-4192-9892-783f161794cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065568876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.1065568876
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.2169082654
Short name T2
Test name
Test status
Simulation time 117081972 ps
CPU time 3.17 seconds
Started Jun 10 07:52:43 PM PDT 24
Finished Jun 10 07:52:49 PM PDT 24
Peak memory 242332 kb
Host smart-e72a29d2-52d2-4aee-a68e-05a612569c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169082654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.2169082654
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.4110131936
Short name T715
Test name
Test status
Simulation time 416362077 ps
CPU time 3.84 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:52:53 PM PDT 24
Peak memory 242592 kb
Host smart-a01198eb-8bbe-4fd7-af1b-8876c3278232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110131936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.4110131936
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.3289033066
Short name T536
Test name
Test status
Simulation time 145579957 ps
CPU time 3.05 seconds
Started Jun 10 07:52:47 PM PDT 24
Finished Jun 10 07:52:53 PM PDT 24
Peak memory 242248 kb
Host smart-be67a8fb-8cd0-4b2b-8ddf-2aaf4ac879ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289033066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.3289033066
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.1029783717
Short name T736
Test name
Test status
Simulation time 989581896 ps
CPU time 13.31 seconds
Started Jun 10 07:52:49 PM PDT 24
Finished Jun 10 07:53:05 PM PDT 24
Peak memory 242620 kb
Host smart-e1925bdb-cb18-4202-aec4-dcd47c350eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029783717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.1029783717
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.3484070271
Short name T113
Test name
Test status
Simulation time 132089495 ps
CPU time 4.9 seconds
Started Jun 10 07:52:45 PM PDT 24
Finished Jun 10 07:52:54 PM PDT 24
Peak memory 242492 kb
Host smart-9f7261bb-7b16-4009-b22c-3dbc1ab81f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484070271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.3484070271
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.1060043283
Short name T69
Test name
Test status
Simulation time 300664240 ps
CPU time 8.67 seconds
Started Jun 10 07:52:42 PM PDT 24
Finished Jun 10 07:52:52 PM PDT 24
Peak memory 242224 kb
Host smart-7e55ade6-f711-42fb-8918-a34c5e8a77fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060043283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.1060043283
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.1390832318
Short name T1075
Test name
Test status
Simulation time 92918991 ps
CPU time 2.95 seconds
Started Jun 10 07:52:44 PM PDT 24
Finished Jun 10 07:52:49 PM PDT 24
Peak memory 242452 kb
Host smart-8435e2ba-768f-4731-b36c-5f5f988bd64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390832318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.1390832318
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.1860548060
Short name T374
Test name
Test status
Simulation time 1022684480 ps
CPU time 15.01 seconds
Started Jun 10 07:52:49 PM PDT 24
Finished Jun 10 07:53:07 PM PDT 24
Peak memory 242128 kb
Host smart-62eb3743-3b87-4dc9-899c-db3765e8a90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860548060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.1860548060
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.1923694629
Short name T982
Test name
Test status
Simulation time 98322884 ps
CPU time 2.87 seconds
Started Jun 10 07:52:51 PM PDT 24
Finished Jun 10 07:52:58 PM PDT 24
Peak memory 242484 kb
Host smart-613cdd98-2efb-4f5b-8bfd-d3b766ac1099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923694629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.1923694629
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.4252411983
Short name T1036
Test name
Test status
Simulation time 105424892 ps
CPU time 3.9 seconds
Started Jun 10 07:52:48 PM PDT 24
Finished Jun 10 07:52:55 PM PDT 24
Peak memory 242464 kb
Host smart-4d0c9466-a641-49a9-bb99-93f71274a966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252411983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.4252411983
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.463410738
Short name T148
Test name
Test status
Simulation time 103576446 ps
CPU time 3.48 seconds
Started Jun 10 07:52:47 PM PDT 24
Finished Jun 10 07:52:54 PM PDT 24
Peak memory 242332 kb
Host smart-64b039a9-74e2-42a2-8b38-051c10fc05c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463410738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.463410738
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.2321680589
Short name T229
Test name
Test status
Simulation time 100870153 ps
CPU time 2.42 seconds
Started Jun 10 07:52:46 PM PDT 24
Finished Jun 10 07:52:52 PM PDT 24
Peak memory 242020 kb
Host smart-6174da69-4886-4fc1-bd73-6d9cf8db5889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321680589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.2321680589
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.1617952717
Short name T171
Test name
Test status
Simulation time 285101693 ps
CPU time 4.1 seconds
Started Jun 10 07:52:57 PM PDT 24
Finished Jun 10 07:53:04 PM PDT 24
Peak memory 242376 kb
Host smart-ac354ddd-41fd-4f2d-b5c8-b11a5c8d478c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617952717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.1617952717
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.2617558768
Short name T852
Test name
Test status
Simulation time 119195444 ps
CPU time 4.65 seconds
Started Jun 10 07:52:48 PM PDT 24
Finished Jun 10 07:52:56 PM PDT 24
Peak memory 242244 kb
Host smart-aba9536b-fc9c-4c2b-a361-8e58bb183cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617558768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.2617558768
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.1592322896
Short name T1047
Test name
Test status
Simulation time 269816371 ps
CPU time 4.29 seconds
Started Jun 10 07:52:56 PM PDT 24
Finished Jun 10 07:53:03 PM PDT 24
Peak memory 242564 kb
Host smart-a84f9dca-f236-4bdd-9e06-9ea512b7e192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592322896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.1592322896
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.3494532621
Short name T1008
Test name
Test status
Simulation time 3785179224 ps
CPU time 11.15 seconds
Started Jun 10 07:52:49 PM PDT 24
Finished Jun 10 07:53:04 PM PDT 24
Peak memory 242208 kb
Host smart-caa1f9a8-23a1-4799-a60d-4f5b7fc0bb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494532621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.3494532621
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.950729365
Short name T92
Test name
Test status
Simulation time 50971018 ps
CPU time 1.68 seconds
Started Jun 10 07:50:31 PM PDT 24
Finished Jun 10 07:50:35 PM PDT 24
Peak memory 240952 kb
Host smart-654ae269-d26b-4aa0-a1d7-8b14fa2cac6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950729365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.950729365
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.3690945229
Short name T423
Test name
Test status
Simulation time 340758140 ps
CPU time 3.42 seconds
Started Jun 10 07:50:25 PM PDT 24
Finished Jun 10 07:50:31 PM PDT 24
Peak memory 249104 kb
Host smart-62836cc8-887e-40ab-9d89-377280aa0063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690945229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.3690945229
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.1050095328
Short name T206
Test name
Test status
Simulation time 3230567262 ps
CPU time 32.33 seconds
Started Jun 10 07:50:26 PM PDT 24
Finished Jun 10 07:51:00 PM PDT 24
Peak memory 242520 kb
Host smart-0d222636-da24-4d24-affc-bf24451437b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050095328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.1050095328
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.1179086545
Short name T685
Test name
Test status
Simulation time 760895946 ps
CPU time 26.85 seconds
Started Jun 10 07:50:29 PM PDT 24
Finished Jun 10 07:50:58 PM PDT 24
Peak memory 242484 kb
Host smart-1ffd77cf-0c87-4eff-894e-ac9902beaa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179086545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.1179086545
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.3642874353
Short name T644
Test name
Test status
Simulation time 1941738103 ps
CPU time 4.45 seconds
Started Jun 10 07:50:24 PM PDT 24
Finished Jun 10 07:50:31 PM PDT 24
Peak memory 242612 kb
Host smart-d6af88d4-6aca-4247-b8b4-9e363d02c607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642874353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.3642874353
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.2440251322
Short name T162
Test name
Test status
Simulation time 16074751164 ps
CPU time 37.56 seconds
Started Jun 10 07:50:25 PM PDT 24
Finished Jun 10 07:51:06 PM PDT 24
Peak memory 245192 kb
Host smart-ac51729c-85b3-44bb-9d9b-d9895a0004f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440251322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.2440251322
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.2894414935
Short name T744
Test name
Test status
Simulation time 546295276 ps
CPU time 13.25 seconds
Started Jun 10 07:50:23 PM PDT 24
Finished Jun 10 07:50:38 PM PDT 24
Peak memory 248988 kb
Host smart-8595936b-a763-43da-9a66-7a7cf8daab17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894414935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.2894414935
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.642014455
Short name T345
Test name
Test status
Simulation time 3274547987 ps
CPU time 25 seconds
Started Jun 10 07:50:29 PM PDT 24
Finished Jun 10 07:50:56 PM PDT 24
Peak memory 242712 kb
Host smart-9291557c-bfe9-4a81-9661-b78f97d6bea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642014455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.642014455
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.2902242075
Short name T379
Test name
Test status
Simulation time 2011248488 ps
CPU time 24.64 seconds
Started Jun 10 07:50:26 PM PDT 24
Finished Jun 10 07:50:54 PM PDT 24
Peak memory 242248 kb
Host smart-32f216c0-a2dc-44f6-8858-57386894402d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2902242075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.2902242075
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.2601802237
Short name T989
Test name
Test status
Simulation time 126560471 ps
CPU time 4.03 seconds
Started Jun 10 07:50:34 PM PDT 24
Finished Jun 10 07:50:40 PM PDT 24
Peak memory 242508 kb
Host smart-bd1a8a67-f041-4822-a30c-86fc86bb54ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2601802237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.2601802237
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.1035127872
Short name T588
Test name
Test status
Simulation time 1142644081 ps
CPU time 13.58 seconds
Started Jun 10 07:50:29 PM PDT 24
Finished Jun 10 07:50:44 PM PDT 24
Peak memory 242468 kb
Host smart-8bb189e5-2dd0-4abc-b1e8-9e8e337d7845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035127872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.1035127872
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.1990957873
Short name T745
Test name
Test status
Simulation time 31403735563 ps
CPU time 328.42 seconds
Started Jun 10 07:50:33 PM PDT 24
Finished Jun 10 07:56:04 PM PDT 24
Peak memory 297820 kb
Host smart-d9cd4885-85dc-4b6e-86da-1b0b774f375d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990957873 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.1990957873
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.372499456
Short name T658
Test name
Test status
Simulation time 728337196 ps
CPU time 6.66 seconds
Started Jun 10 07:50:34 PM PDT 24
Finished Jun 10 07:50:42 PM PDT 24
Peak memory 242036 kb
Host smart-58e58172-bc91-4de2-b281-231303e4719c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372499456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.372499456
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.4294260474
Short name T772
Test name
Test status
Simulation time 186675599 ps
CPU time 4.72 seconds
Started Jun 10 07:52:58 PM PDT 24
Finished Jun 10 07:53:07 PM PDT 24
Peak memory 242084 kb
Host smart-e0a2363b-a7cb-49e0-9d0a-e13a2389835e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294260474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.4294260474
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.2026163461
Short name T505
Test name
Test status
Simulation time 2178346964 ps
CPU time 22.99 seconds
Started Jun 10 07:52:48 PM PDT 24
Finished Jun 10 07:53:14 PM PDT 24
Peak memory 242540 kb
Host smart-a18f5e47-9bb1-4c56-9da6-b2ef513724e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026163461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.2026163461
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.3832884542
Short name T706
Test name
Test status
Simulation time 2004272820 ps
CPU time 5.63 seconds
Started Jun 10 07:52:47 PM PDT 24
Finished Jun 10 07:52:56 PM PDT 24
Peak memory 242420 kb
Host smart-4a05493e-2a48-4705-9fdf-641f4004666c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832884542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.3832884542
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.3868571442
Short name T290
Test name
Test status
Simulation time 161656468 ps
CPU time 7.6 seconds
Started Jun 10 07:52:48 PM PDT 24
Finished Jun 10 07:52:59 PM PDT 24
Peak memory 242292 kb
Host smart-77be227f-4996-4d9c-b657-cc8f959af324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868571442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.3868571442
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.2318763099
Short name T810
Test name
Test status
Simulation time 120496282 ps
CPU time 3.52 seconds
Started Jun 10 07:52:51 PM PDT 24
Finished Jun 10 07:52:59 PM PDT 24
Peak memory 242308 kb
Host smart-2265974e-6e3e-4ce2-a0c0-0874818f2d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318763099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.2318763099
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.2911879539
Short name T460
Test name
Test status
Simulation time 1564994545 ps
CPU time 15.83 seconds
Started Jun 10 07:52:59 PM PDT 24
Finished Jun 10 07:53:18 PM PDT 24
Peak memory 241964 kb
Host smart-dab0e5d4-05fc-4f16-9553-7c282e587d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911879539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.2911879539
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.684564859
Short name T760
Test name
Test status
Simulation time 150644818 ps
CPU time 4.14 seconds
Started Jun 10 07:52:56 PM PDT 24
Finished Jun 10 07:53:03 PM PDT 24
Peak memory 242544 kb
Host smart-aa64f033-db34-401e-b67b-110de29aa21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684564859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.684564859
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.119197664
Short name T800
Test name
Test status
Simulation time 570655654 ps
CPU time 15.9 seconds
Started Jun 10 07:52:51 PM PDT 24
Finished Jun 10 07:53:12 PM PDT 24
Peak memory 242008 kb
Host smart-2abc613b-b88e-4c87-963b-d2f130ab38be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119197664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.119197664
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.4242077052
Short name T1082
Test name
Test status
Simulation time 307281051 ps
CPU time 4.89 seconds
Started Jun 10 07:52:58 PM PDT 24
Finished Jun 10 07:53:07 PM PDT 24
Peak memory 242168 kb
Host smart-f32973d9-2c6a-4557-803e-b83e687158bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242077052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.4242077052
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.1008544125
Short name T726
Test name
Test status
Simulation time 122604901 ps
CPU time 3.29 seconds
Started Jun 10 07:52:58 PM PDT 24
Finished Jun 10 07:53:05 PM PDT 24
Peak memory 242280 kb
Host smart-873f2640-e868-4b53-a108-669c32fa43f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008544125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.1008544125
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.2834003656
Short name T1179
Test name
Test status
Simulation time 1689405504 ps
CPU time 4.99 seconds
Started Jun 10 07:52:50 PM PDT 24
Finished Jun 10 07:52:59 PM PDT 24
Peak memory 242448 kb
Host smart-d2349dd6-4586-4c25-8c3a-34c3badce15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834003656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.2834003656
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.1449164018
Short name T405
Test name
Test status
Simulation time 162868627 ps
CPU time 4.55 seconds
Started Jun 10 07:52:53 PM PDT 24
Finished Jun 10 07:53:01 PM PDT 24
Peak memory 242228 kb
Host smart-b9a01ad8-87ce-4f7f-9c10-5b413e05ac27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449164018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.1449164018
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.3934597372
Short name T850
Test name
Test status
Simulation time 121860288 ps
CPU time 4.18 seconds
Started Jun 10 07:52:57 PM PDT 24
Finished Jun 10 07:53:04 PM PDT 24
Peak memory 242344 kb
Host smart-53852a41-c028-4a6b-aedc-5d2c33a91b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934597372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.3934597372
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.2995972722
Short name T784
Test name
Test status
Simulation time 266664647 ps
CPU time 3.98 seconds
Started Jun 10 07:52:50 PM PDT 24
Finished Jun 10 07:52:58 PM PDT 24
Peak memory 242568 kb
Host smart-75768779-90ac-4008-afaa-d1b67e234f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995972722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.2995972722
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.3902426103
Short name T1045
Test name
Test status
Simulation time 1595491421 ps
CPU time 5.28 seconds
Started Jun 10 07:52:57 PM PDT 24
Finished Jun 10 07:53:05 PM PDT 24
Peak memory 242312 kb
Host smart-f5cff006-9946-4420-9cba-d4e9d1f6c868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902426103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.3902426103
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.2305363434
Short name T408
Test name
Test status
Simulation time 468067645 ps
CPU time 5.69 seconds
Started Jun 10 07:52:58 PM PDT 24
Finished Jun 10 07:53:06 PM PDT 24
Peak memory 242148 kb
Host smart-aed162fd-0836-4ad3-a9b3-89d8017f2313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305363434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.2305363434
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.1237915271
Short name T507
Test name
Test status
Simulation time 555499427 ps
CPU time 4.72 seconds
Started Jun 10 07:52:52 PM PDT 24
Finished Jun 10 07:53:01 PM PDT 24
Peak memory 242472 kb
Host smart-a43c399d-1916-4a3b-a399-0a8a5ffebd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237915271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.1237915271
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.3379424344
Short name T1007
Test name
Test status
Simulation time 1018172975 ps
CPU time 16.13 seconds
Started Jun 10 07:52:49 PM PDT 24
Finished Jun 10 07:53:08 PM PDT 24
Peak memory 242028 kb
Host smart-7561c69c-b281-4b41-8078-e76a4792145d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379424344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.3379424344
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.1617216345
Short name T1109
Test name
Test status
Simulation time 205117288 ps
CPU time 5.5 seconds
Started Jun 10 07:52:47 PM PDT 24
Finished Jun 10 07:52:56 PM PDT 24
Peak memory 242292 kb
Host smart-d20272ef-f27f-49bb-8cbf-afca174da295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617216345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.1617216345
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.633747978
Short name T577
Test name
Test status
Simulation time 262566900 ps
CPU time 2.03 seconds
Started Jun 10 07:50:33 PM PDT 24
Finished Jun 10 07:50:37 PM PDT 24
Peak memory 240876 kb
Host smart-75336b03-79fa-45ce-afce-2414e94b1ca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633747978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.633747978
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.455563956
Short name T81
Test name
Test status
Simulation time 9326471344 ps
CPU time 28.72 seconds
Started Jun 10 07:50:33 PM PDT 24
Finished Jun 10 07:51:03 PM PDT 24
Peak memory 244040 kb
Host smart-52dd276d-03a9-492d-afb6-e6768d3b57af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455563956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.455563956
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.1971690652
Short name T622
Test name
Test status
Simulation time 1232535856 ps
CPU time 20.57 seconds
Started Jun 10 07:50:34 PM PDT 24
Finished Jun 10 07:50:57 PM PDT 24
Peak memory 242328 kb
Host smart-f1e68365-21ef-471d-9d0b-fd053a97a08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971690652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.1971690652
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.2054992941
Short name T377
Test name
Test status
Simulation time 710729480 ps
CPU time 15.1 seconds
Started Jun 10 07:50:36 PM PDT 24
Finished Jun 10 07:50:53 PM PDT 24
Peak memory 242452 kb
Host smart-f4b54e54-11ac-41c6-94ad-c8897799176b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054992941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.2054992941
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.2316123691
Short name T995
Test name
Test status
Simulation time 1372464334 ps
CPU time 5.01 seconds
Started Jun 10 07:50:31 PM PDT 24
Finished Jun 10 07:50:39 PM PDT 24
Peak memory 242316 kb
Host smart-7e388581-4967-4c29-8fff-9c7dbd71edb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316123691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.2316123691
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.1773493825
Short name T1192
Test name
Test status
Simulation time 527818919 ps
CPU time 11.77 seconds
Started Jun 10 07:50:32 PM PDT 24
Finished Jun 10 07:50:45 PM PDT 24
Peak memory 243852 kb
Host smart-550a6ab8-7130-40ea-8a02-31145e93985f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773493825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.1773493825
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.2674663195
Short name T918
Test name
Test status
Simulation time 3547889329 ps
CPU time 7.66 seconds
Started Jun 10 07:50:33 PM PDT 24
Finished Jun 10 07:50:42 PM PDT 24
Peak memory 242064 kb
Host smart-93811711-de81-4107-837d-eb510c13f701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674663195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.2674663195
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.1340273568
Short name T917
Test name
Test status
Simulation time 2307351122 ps
CPU time 6.64 seconds
Started Jun 10 07:50:34 PM PDT 24
Finished Jun 10 07:50:43 PM PDT 24
Peak memory 242440 kb
Host smart-2ad7d396-6685-464b-9fa0-436cee0aa3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340273568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.1340273568
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.3045866553
Short name T1137
Test name
Test status
Simulation time 244684076 ps
CPU time 6.17 seconds
Started Jun 10 07:50:40 PM PDT 24
Finished Jun 10 07:50:48 PM PDT 24
Peak memory 242200 kb
Host smart-de170b2f-8bc2-44ad-b96b-851c4dcdd74e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3045866553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.3045866553
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.892433114
Short name T1
Test name
Test status
Simulation time 441865928 ps
CPU time 6.86 seconds
Started Jun 10 07:50:33 PM PDT 24
Finished Jun 10 07:50:42 PM PDT 24
Peak memory 242580 kb
Host smart-056e714d-969d-4058-8d46-8bca11a9e719
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=892433114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.892433114
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.1165275160
Short name T963
Test name
Test status
Simulation time 2921295952 ps
CPU time 5.57 seconds
Started Jun 10 07:50:35 PM PDT 24
Finished Jun 10 07:50:43 PM PDT 24
Peak memory 242308 kb
Host smart-8e20d3b6-17c0-4b63-9133-f91d26a7ff0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165275160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.1165275160
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.2129539084
Short name T273
Test name
Test status
Simulation time 9351339200 ps
CPU time 67.19 seconds
Started Jun 10 07:50:38 PM PDT 24
Finished Jun 10 07:51:46 PM PDT 24
Peak memory 242656 kb
Host smart-4cd8ca61-2a9c-44e7-98f5-99d907aaf1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129539084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.2129539084
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.3512921170
Short name T903
Test name
Test status
Simulation time 1413331229 ps
CPU time 3.22 seconds
Started Jun 10 07:52:52 PM PDT 24
Finished Jun 10 07:53:00 PM PDT 24
Peak memory 242440 kb
Host smart-0156e83b-fcf9-4723-9b18-39658e1ff29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512921170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.3512921170
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.3676693072
Short name T657
Test name
Test status
Simulation time 1394114137 ps
CPU time 10.45 seconds
Started Jun 10 07:52:56 PM PDT 24
Finished Jun 10 07:53:10 PM PDT 24
Peak memory 242132 kb
Host smart-25300b5f-90f6-4af0-8f45-2087ea7025e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676693072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.3676693072
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.1513225559
Short name T1141
Test name
Test status
Simulation time 123481655 ps
CPU time 3.79 seconds
Started Jun 10 07:52:50 PM PDT 24
Finished Jun 10 07:52:58 PM PDT 24
Peak memory 242224 kb
Host smart-d6a2ced5-6f33-4463-bf11-7cd5fbe94ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513225559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.1513225559
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.3417285749
Short name T1148
Test name
Test status
Simulation time 641406804 ps
CPU time 11.82 seconds
Started Jun 10 07:52:57 PM PDT 24
Finished Jun 10 07:53:11 PM PDT 24
Peak memory 242128 kb
Host smart-0f7753b1-269d-4966-9be1-a068cc76423c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417285749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.3417285749
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.221692722
Short name T133
Test name
Test status
Simulation time 548701967 ps
CPU time 3.89 seconds
Started Jun 10 07:52:58 PM PDT 24
Finished Jun 10 07:53:06 PM PDT 24
Peak memory 242076 kb
Host smart-95307848-ce66-4093-bb16-2e807c4d3849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221692722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.221692722
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.202658020
Short name T223
Test name
Test status
Simulation time 1879522302 ps
CPU time 7.08 seconds
Started Jun 10 07:52:46 PM PDT 24
Finished Jun 10 07:52:56 PM PDT 24
Peak memory 242212 kb
Host smart-04bfdbdb-2eae-4af4-a3fe-2021ef0b89ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202658020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.202658020
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.1777750696
Short name T504
Test name
Test status
Simulation time 375667632 ps
CPU time 4.91 seconds
Started Jun 10 07:52:54 PM PDT 24
Finished Jun 10 07:53:03 PM PDT 24
Peak memory 242648 kb
Host smart-ff08fc6c-cf6c-4b70-8fad-ad0fdfbc4d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777750696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.1777750696
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.1550286715
Short name T426
Test name
Test status
Simulation time 217287231 ps
CPU time 5.6 seconds
Started Jun 10 07:52:50 PM PDT 24
Finished Jun 10 07:53:00 PM PDT 24
Peak memory 241992 kb
Host smart-c63fbbd2-f93c-41e4-b7eb-ae044e6fc76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550286715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.1550286715
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.626042562
Short name T973
Test name
Test status
Simulation time 157226664 ps
CPU time 3.91 seconds
Started Jun 10 07:52:50 PM PDT 24
Finished Jun 10 07:52:58 PM PDT 24
Peak memory 242224 kb
Host smart-621d9289-5672-4028-b1bf-f74f5ff03a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626042562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.626042562
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.1941385232
Short name T541
Test name
Test status
Simulation time 2444473995 ps
CPU time 17.95 seconds
Started Jun 10 07:52:58 PM PDT 24
Finished Jun 10 07:53:20 PM PDT 24
Peak memory 242400 kb
Host smart-1b101ac1-12b3-4eff-a875-b6ddcc1fcbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941385232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.1941385232
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.3309059376
Short name T766
Test name
Test status
Simulation time 382150217 ps
CPU time 3.81 seconds
Started Jun 10 07:52:58 PM PDT 24
Finished Jun 10 07:53:04 PM PDT 24
Peak memory 242448 kb
Host smart-49da587f-ed7d-471a-9bf8-72c516a8336c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309059376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.3309059376
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.293860792
Short name T723
Test name
Test status
Simulation time 296294550 ps
CPU time 4.44 seconds
Started Jun 10 07:52:52 PM PDT 24
Finished Jun 10 07:53:01 PM PDT 24
Peak memory 242556 kb
Host smart-310c45e9-3955-479c-a565-3b2f3bd7cccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293860792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.293860792
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.4013780699
Short name T854
Test name
Test status
Simulation time 490035308 ps
CPU time 5.1 seconds
Started Jun 10 07:52:56 PM PDT 24
Finished Jun 10 07:53:04 PM PDT 24
Peak memory 242476 kb
Host smart-6111f7e4-dadb-402c-8e80-46c72618d604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013780699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.4013780699
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.77052278
Short name T1126
Test name
Test status
Simulation time 605329982 ps
CPU time 4.96 seconds
Started Jun 10 07:52:47 PM PDT 24
Finished Jun 10 07:52:55 PM PDT 24
Peak memory 242196 kb
Host smart-f9413f78-b3a0-4d57-b1fe-63678ef317ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77052278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.77052278
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.480598510
Short name T811
Test name
Test status
Simulation time 226777534 ps
CPU time 3.7 seconds
Started Jun 10 07:52:56 PM PDT 24
Finished Jun 10 07:53:03 PM PDT 24
Peak memory 242460 kb
Host smart-b36cd2ea-665a-4e1e-b04d-02b61f1f1adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480598510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.480598510
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.1965192681
Short name T508
Test name
Test status
Simulation time 168327790 ps
CPU time 3.97 seconds
Started Jun 10 07:52:50 PM PDT 24
Finished Jun 10 07:52:58 PM PDT 24
Peak memory 242168 kb
Host smart-0ec30e97-f35e-4f31-95e3-3371ef4adb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965192681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.1965192681
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.387752371
Short name T788
Test name
Test status
Simulation time 247050008 ps
CPU time 4.27 seconds
Started Jun 10 07:52:48 PM PDT 24
Finished Jun 10 07:52:56 PM PDT 24
Peak memory 242448 kb
Host smart-cf13f5dd-4c3e-49d7-bc55-36f5f1cafc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387752371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.387752371
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.2877423814
Short name T1101
Test name
Test status
Simulation time 1882161560 ps
CPU time 21.81 seconds
Started Jun 10 07:52:50 PM PDT 24
Finished Jun 10 07:53:15 PM PDT 24
Peak memory 242152 kb
Host smart-c822776d-2c2f-43b3-8361-03943cd42b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877423814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.2877423814
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.3974867502
Short name T1120
Test name
Test status
Simulation time 154884543 ps
CPU time 3.67 seconds
Started Jun 10 07:52:50 PM PDT 24
Finished Jun 10 07:52:58 PM PDT 24
Peak memory 242212 kb
Host smart-84c83f8f-8d17-48e7-aaca-9b59ef8ccb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974867502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.3974867502
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.3673935913
Short name T815
Test name
Test status
Simulation time 8360398044 ps
CPU time 25.04 seconds
Started Jun 10 07:53:01 PM PDT 24
Finished Jun 10 07:53:30 PM PDT 24
Peak memory 242264 kb
Host smart-c13e3d93-23e8-4771-9526-287570642490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673935913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.3673935913
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.2523757270
Short name T410
Test name
Test status
Simulation time 120960920 ps
CPU time 2.24 seconds
Started Jun 10 07:50:40 PM PDT 24
Finished Jun 10 07:50:43 PM PDT 24
Peak memory 240800 kb
Host smart-0b183467-f052-4736-a7d2-786b46b28d2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523757270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.2523757270
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.1108155171
Short name T799
Test name
Test status
Simulation time 532786035 ps
CPU time 17.71 seconds
Started Jun 10 07:50:36 PM PDT 24
Finished Jun 10 07:50:56 PM PDT 24
Peak memory 242200 kb
Host smart-a30e26a4-b7da-4c49-ac2b-07a6c9c3943b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108155171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.1108155171
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.16471570
Short name T727
Test name
Test status
Simulation time 566079805 ps
CPU time 13.31 seconds
Started Jun 10 07:50:35 PM PDT 24
Finished Jun 10 07:50:50 PM PDT 24
Peak memory 242388 kb
Host smart-ad2eb81b-7b11-4dca-8d25-e540954b8dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16471570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.16471570
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.3481614919
Short name T663
Test name
Test status
Simulation time 146086933 ps
CPU time 3.74 seconds
Started Jun 10 07:50:34 PM PDT 24
Finished Jun 10 07:50:40 PM PDT 24
Peak memory 242604 kb
Host smart-b113c8f6-8bd1-466c-bbc7-621933a016e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481614919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.3481614919
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.1010083720
Short name T237
Test name
Test status
Simulation time 743437843 ps
CPU time 15.56 seconds
Started Jun 10 07:50:35 PM PDT 24
Finished Jun 10 07:50:52 PM PDT 24
Peak memory 245312 kb
Host smart-9bfc288c-4121-4b46-9a94-f7673237077e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010083720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.1010083720
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.1297506815
Short name T671
Test name
Test status
Simulation time 4727137399 ps
CPU time 30.14 seconds
Started Jun 10 07:50:40 PM PDT 24
Finished Jun 10 07:51:11 PM PDT 24
Peak memory 242468 kb
Host smart-44340cee-b74b-4675-9625-2debcc7f495d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297506815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.1297506815
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.2194626629
Short name T550
Test name
Test status
Simulation time 712699152 ps
CPU time 6.21 seconds
Started Jun 10 07:50:31 PM PDT 24
Finished Jun 10 07:50:39 PM PDT 24
Peak memory 242160 kb
Host smart-1d6b5b20-f33e-413b-be11-4356f12ed254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194626629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.2194626629
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.3267377539
Short name T613
Test name
Test status
Simulation time 892274713 ps
CPU time 21.92 seconds
Started Jun 10 07:50:41 PM PDT 24
Finished Jun 10 07:51:04 PM PDT 24
Peak memory 242200 kb
Host smart-0f8a7bad-384b-4806-b60f-a076f8a70ec6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3267377539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.3267377539
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.2080259053
Short name T701
Test name
Test status
Simulation time 272944237 ps
CPU time 5.72 seconds
Started Jun 10 07:50:33 PM PDT 24
Finished Jun 10 07:50:41 PM PDT 24
Peak memory 242200 kb
Host smart-b6601522-a257-4d88-8a60-9e94fab81efd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2080259053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.2080259053
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.1527108229
Short name T999
Test name
Test status
Simulation time 512041602 ps
CPU time 4.34 seconds
Started Jun 10 07:50:33 PM PDT 24
Finished Jun 10 07:50:39 PM PDT 24
Peak memory 242220 kb
Host smart-93cd627b-de0e-4981-af58-a83e441bdfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527108229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.1527108229
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.2825254724
Short name T215
Test name
Test status
Simulation time 4766393721 ps
CPU time 182.71 seconds
Started Jun 10 07:50:40 PM PDT 24
Finished Jun 10 07:53:44 PM PDT 24
Peak memory 258804 kb
Host smart-b4359545-45ae-4398-abf0-9f98498d2050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825254724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.2825254724
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.3813859441
Short name T649
Test name
Test status
Simulation time 67443585787 ps
CPU time 912.92 seconds
Started Jun 10 07:50:40 PM PDT 24
Finished Jun 10 08:05:54 PM PDT 24
Peak memory 318036 kb
Host smart-daa4ac26-6596-4a7b-8b67-196b20be88ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813859441 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.3813859441
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.4017875950
Short name T1125
Test name
Test status
Simulation time 13661840367 ps
CPU time 42.36 seconds
Started Jun 10 07:50:41 PM PDT 24
Finished Jun 10 07:51:25 PM PDT 24
Peak memory 243108 kb
Host smart-4a5f9eee-7a08-4ea8-b2a6-595e2b548001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017875950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.4017875950
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.460707735
Short name T650
Test name
Test status
Simulation time 194326629 ps
CPU time 4.78 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:09 PM PDT 24
Peak memory 242584 kb
Host smart-bffd1f23-e5f3-4d8e-829d-a9cf61fd5c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460707735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.460707735
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.3945631402
Short name T154
Test name
Test status
Simulation time 1035141781 ps
CPU time 7.2 seconds
Started Jun 10 07:52:55 PM PDT 24
Finished Jun 10 07:53:05 PM PDT 24
Peak memory 242204 kb
Host smart-6464fbe9-fa28-4fdc-8034-5f260814fc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945631402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.3945631402
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.2031562285
Short name T965
Test name
Test status
Simulation time 134186472 ps
CPU time 4.18 seconds
Started Jun 10 07:52:58 PM PDT 24
Finished Jun 10 07:53:05 PM PDT 24
Peak memory 242140 kb
Host smart-11ad544a-9fe9-4acf-945f-3aa6b33abac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031562285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.2031562285
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.3881669310
Short name T866
Test name
Test status
Simulation time 193014839 ps
CPU time 4.35 seconds
Started Jun 10 07:52:50 PM PDT 24
Finished Jun 10 07:52:59 PM PDT 24
Peak memory 241948 kb
Host smart-284d5d8a-c5cf-490f-91f7-a3488eff6886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881669310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.3881669310
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.371856793
Short name T1124
Test name
Test status
Simulation time 591113622 ps
CPU time 4.68 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:08 PM PDT 24
Peak memory 242620 kb
Host smart-86c95f47-851c-4f93-97a8-97cd22571146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371856793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.371856793
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.179219101
Short name T484
Test name
Test status
Simulation time 111506682 ps
CPU time 4.1 seconds
Started Jun 10 07:52:50 PM PDT 24
Finished Jun 10 07:52:58 PM PDT 24
Peak memory 242072 kb
Host smart-b9f3dc72-2521-43ba-b577-c7b21e0f86ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179219101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.179219101
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.4080129552
Short name T314
Test name
Test status
Simulation time 122375868 ps
CPU time 3.81 seconds
Started Jun 10 07:52:55 PM PDT 24
Finished Jun 10 07:53:02 PM PDT 24
Peak memory 242364 kb
Host smart-b6a52d58-c139-41d5-9f31-fca48f702acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080129552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.4080129552
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.2386337574
Short name T669
Test name
Test status
Simulation time 479877450 ps
CPU time 9.3 seconds
Started Jun 10 07:52:54 PM PDT 24
Finished Jun 10 07:53:07 PM PDT 24
Peak memory 242268 kb
Host smart-92ba0fe0-ed5a-48c9-8291-f439bbb980d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386337574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.2386337574
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.2815663057
Short name T889
Test name
Test status
Simulation time 131677951 ps
CPU time 3.86 seconds
Started Jun 10 07:52:51 PM PDT 24
Finished Jun 10 07:52:59 PM PDT 24
Peak memory 242380 kb
Host smart-d281517a-ae7f-400c-b276-53cfb0e006d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815663057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.2815663057
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.1283282093
Short name T1010
Test name
Test status
Simulation time 1259037086 ps
CPU time 21.15 seconds
Started Jun 10 07:52:50 PM PDT 24
Finished Jun 10 07:53:14 PM PDT 24
Peak memory 242108 kb
Host smart-bf2b70f9-3a56-4744-881b-0018d08518ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283282093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.1283282093
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.4043881725
Short name T169
Test name
Test status
Simulation time 200929536 ps
CPU time 3.94 seconds
Started Jun 10 07:52:49 PM PDT 24
Finished Jun 10 07:52:56 PM PDT 24
Peak memory 242292 kb
Host smart-c35196a2-d011-45dc-9af5-faa5fa86d52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043881725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.4043881725
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.3874570557
Short name T1190
Test name
Test status
Simulation time 736366393 ps
CPU time 23.33 seconds
Started Jun 10 07:52:51 PM PDT 24
Finished Jun 10 07:53:18 PM PDT 24
Peak memory 242108 kb
Host smart-42ea5ba9-77f3-4b8e-8f47-6bafab083965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874570557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.3874570557
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.810459450
Short name T42
Test name
Test status
Simulation time 260464122 ps
CPU time 5.6 seconds
Started Jun 10 07:53:01 PM PDT 24
Finished Jun 10 07:53:10 PM PDT 24
Peak memory 242268 kb
Host smart-abb4d6bf-af2c-45ed-b16b-13916e451486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810459450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.810459450
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.895064850
Short name T498
Test name
Test status
Simulation time 1970259753 ps
CPU time 13.02 seconds
Started Jun 10 07:52:48 PM PDT 24
Finished Jun 10 07:53:04 PM PDT 24
Peak memory 242396 kb
Host smart-df3b8ed6-04a0-4e1e-8982-c4aa28edbb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895064850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.895064850
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.1703149012
Short name T693
Test name
Test status
Simulation time 1504040220 ps
CPU time 4.49 seconds
Started Jun 10 07:52:49 PM PDT 24
Finished Jun 10 07:52:57 PM PDT 24
Peak memory 242312 kb
Host smart-9fc85daf-e1e2-4a6d-9a17-096cbba9c6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703149012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.1703149012
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.3054288878
Short name T661
Test name
Test status
Simulation time 205001289 ps
CPU time 3.65 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:08 PM PDT 24
Peak memory 242208 kb
Host smart-1c893dbc-8e0a-4141-8841-6ae4ff7772ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054288878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.3054288878
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.3402749497
Short name T571
Test name
Test status
Simulation time 2362038821 ps
CPU time 4.57 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:09 PM PDT 24
Peak memory 242500 kb
Host smart-8f3640a6-c2a9-4c76-a100-9372b29c08fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402749497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.3402749497
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.2060880162
Short name T790
Test name
Test status
Simulation time 810852134 ps
CPU time 7.11 seconds
Started Jun 10 07:52:51 PM PDT 24
Finished Jun 10 07:53:02 PM PDT 24
Peak memory 242048 kb
Host smart-715ac93b-04d8-486d-9d4c-45c3f3935482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060880162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.2060880162
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.4096365883
Short name T932
Test name
Test status
Simulation time 226354908 ps
CPU time 3.97 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:08 PM PDT 24
Peak memory 242552 kb
Host smart-8329f226-f574-465a-ae9f-ce20af9d3153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096365883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.4096365883
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.1804985512
Short name T758
Test name
Test status
Simulation time 2739310971 ps
CPU time 24.92 seconds
Started Jun 10 07:52:51 PM PDT 24
Finished Jun 10 07:53:20 PM PDT 24
Peak memory 242568 kb
Host smart-6fc35043-55a0-43fd-9d85-0919a916c9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804985512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.1804985512
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.3455810763
Short name T458
Test name
Test status
Simulation time 47742838 ps
CPU time 1.61 seconds
Started Jun 10 07:50:40 PM PDT 24
Finished Jun 10 07:50:44 PM PDT 24
Peak memory 241100 kb
Host smart-49be4087-5e9c-4c1c-b7e1-f7848484df9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455810763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.3455810763
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.1754378551
Short name T609
Test name
Test status
Simulation time 998139338 ps
CPU time 21.8 seconds
Started Jun 10 07:50:37 PM PDT 24
Finished Jun 10 07:51:01 PM PDT 24
Peak memory 242468 kb
Host smart-351a4588-3720-4a40-8d98-95e08ca78c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754378551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.1754378551
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.4114617862
Short name T698
Test name
Test status
Simulation time 703492835 ps
CPU time 13.6 seconds
Started Jun 10 07:50:35 PM PDT 24
Finished Jun 10 07:50:51 PM PDT 24
Peak memory 242276 kb
Host smart-08b2a78a-1bce-4176-8a6d-6d9c181d7deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114617862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.4114617862
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.502337998
Short name T1057
Test name
Test status
Simulation time 4087532347 ps
CPU time 25.63 seconds
Started Jun 10 07:50:34 PM PDT 24
Finished Jun 10 07:51:02 PM PDT 24
Peak memory 242528 kb
Host smart-c12b4747-efcc-4b02-8f12-c30058dc1f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502337998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.502337998
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.688776269
Short name T174
Test name
Test status
Simulation time 87198228 ps
CPU time 3.26 seconds
Started Jun 10 07:50:34 PM PDT 24
Finished Jun 10 07:50:39 PM PDT 24
Peak memory 242196 kb
Host smart-7b09aa3a-cda3-43f8-93b2-c905ad1f038e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688776269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.688776269
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.1287766780
Short name T427
Test name
Test status
Simulation time 1794128641 ps
CPU time 21.62 seconds
Started Jun 10 07:50:32 PM PDT 24
Finished Jun 10 07:50:56 PM PDT 24
Peak memory 242676 kb
Host smart-04c71ceb-0691-4ec7-8ac8-319cead1b07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287766780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.1287766780
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.64468299
Short name T1078
Test name
Test status
Simulation time 740058785 ps
CPU time 14.99 seconds
Started Jun 10 07:50:33 PM PDT 24
Finished Jun 10 07:50:50 PM PDT 24
Peak memory 242420 kb
Host smart-8e68e0a2-2529-4fdc-96a5-f95335b2cbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64468299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.64468299
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.475125727
Short name T297
Test name
Test status
Simulation time 1808437792 ps
CPU time 14.15 seconds
Started Jun 10 07:50:34 PM PDT 24
Finished Jun 10 07:50:51 PM PDT 24
Peak memory 242644 kb
Host smart-ccb724ae-9c49-44ed-9daf-18c45aa85772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475125727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.475125727
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.3971719075
Short name T983
Test name
Test status
Simulation time 4275266935 ps
CPU time 9.32 seconds
Started Jun 10 07:50:31 PM PDT 24
Finished Jun 10 07:50:43 PM PDT 24
Peak memory 249088 kb
Host smart-394565ce-4b3f-403c-93fd-e0258e63933f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3971719075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.3971719075
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.1653659869
Short name T845
Test name
Test status
Simulation time 4515266966 ps
CPU time 16.67 seconds
Started Jun 10 07:50:36 PM PDT 24
Finished Jun 10 07:50:54 PM PDT 24
Peak memory 242732 kb
Host smart-515c82dc-6cb7-403a-946f-0b5a1507dd71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653659869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.1653659869
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.3114493405
Short name T921
Test name
Test status
Simulation time 592645811 ps
CPU time 12.93 seconds
Started Jun 10 07:50:40 PM PDT 24
Finished Jun 10 07:50:54 PM PDT 24
Peak memory 242192 kb
Host smart-9f13b0ba-7a69-48a9-a108-f57e6ddffbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114493405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.3114493405
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.2502797744
Short name T1177
Test name
Test status
Simulation time 169894468881 ps
CPU time 259.69 seconds
Started Jun 10 07:50:31 PM PDT 24
Finished Jun 10 07:54:53 PM PDT 24
Peak memory 249160 kb
Host smart-60c8f6bb-eed2-4fd0-85a3-6c1e6cdb0b9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502797744 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.2502797744
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.1862136318
Short name T209
Test name
Test status
Simulation time 105391877 ps
CPU time 3.5 seconds
Started Jun 10 07:52:53 PM PDT 24
Finished Jun 10 07:53:01 PM PDT 24
Peak memory 242400 kb
Host smart-4c38014b-7e7e-4d21-b5e6-1c169d1a42e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862136318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.1862136318
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.1745921096
Short name T231
Test name
Test status
Simulation time 228679745 ps
CPU time 7.82 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:12 PM PDT 24
Peak memory 242188 kb
Host smart-9889db4b-036e-40ff-a3a8-a6d5aeb14d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745921096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.1745921096
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.2759913460
Short name T562
Test name
Test status
Simulation time 1481893105 ps
CPU time 4.61 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:08 PM PDT 24
Peak memory 242272 kb
Host smart-a4458b0f-8413-43c4-a787-ef9e910815b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759913460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.2759913460
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.227456625
Short name T615
Test name
Test status
Simulation time 13636892877 ps
CPU time 38.75 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:43 PM PDT 24
Peak memory 242288 kb
Host smart-8093489f-3781-414f-8b49-69473b13bbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227456625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.227456625
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.3918447416
Short name T157
Test name
Test status
Simulation time 207932980 ps
CPU time 4.43 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:08 PM PDT 24
Peak memory 242272 kb
Host smart-a1d06571-778e-4b86-b83a-b7cd3d6dbfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918447416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.3918447416
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.1682685617
Short name T704
Test name
Test status
Simulation time 416261603 ps
CPU time 7.58 seconds
Started Jun 10 07:52:59 PM PDT 24
Finished Jun 10 07:53:10 PM PDT 24
Peak memory 242404 kb
Host smart-4ba6f713-db49-428a-aa17-caf2a172ebfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682685617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.1682685617
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.397032732
Short name T433
Test name
Test status
Simulation time 966697929 ps
CPU time 7.42 seconds
Started Jun 10 07:52:59 PM PDT 24
Finished Jun 10 07:53:10 PM PDT 24
Peak memory 242132 kb
Host smart-5ccdf790-e8c7-4ff3-a00b-edcea0524332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397032732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.397032732
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.2333303690
Short name T453
Test name
Test status
Simulation time 287118321 ps
CPU time 4.17 seconds
Started Jun 10 07:53:02 PM PDT 24
Finished Jun 10 07:53:10 PM PDT 24
Peak memory 242568 kb
Host smart-2a87b164-2603-45ae-9588-8d7b80fe4b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333303690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.2333303690
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.2604680262
Short name T997
Test name
Test status
Simulation time 2604963401 ps
CPU time 26.22 seconds
Started Jun 10 07:52:56 PM PDT 24
Finished Jun 10 07:53:25 PM PDT 24
Peak memory 242348 kb
Host smart-c1ded46f-fbfe-469d-af92-ea1616298109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604680262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.2604680262
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.2800142891
Short name T1149
Test name
Test status
Simulation time 163425255 ps
CPU time 4.21 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:07 PM PDT 24
Peak memory 242604 kb
Host smart-17c291f9-7cf7-428e-8d78-274f6b226fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800142891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.2800142891
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.1424284569
Short name T961
Test name
Test status
Simulation time 513144317 ps
CPU time 11.79 seconds
Started Jun 10 07:52:58 PM PDT 24
Finished Jun 10 07:53:13 PM PDT 24
Peak memory 242228 kb
Host smart-708284de-ae71-4acf-afcf-6eb700249223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424284569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.1424284569
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.3253207052
Short name T786
Test name
Test status
Simulation time 466248149 ps
CPU time 4.75 seconds
Started Jun 10 07:52:59 PM PDT 24
Finished Jun 10 07:53:07 PM PDT 24
Peak memory 242296 kb
Host smart-5a508fa7-08f1-47bf-b074-7a2f59da246a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253207052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.3253207052
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.2544806279
Short name T3
Test name
Test status
Simulation time 2529370764 ps
CPU time 18.77 seconds
Started Jun 10 07:53:01 PM PDT 24
Finished Jun 10 07:53:24 PM PDT 24
Peak memory 242236 kb
Host smart-28e78b00-5ded-4afa-86ad-97e9e90ff1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544806279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.2544806279
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.3487784512
Short name T664
Test name
Test status
Simulation time 544426896 ps
CPU time 5.36 seconds
Started Jun 10 07:52:58 PM PDT 24
Finished Jun 10 07:53:06 PM PDT 24
Peak memory 242368 kb
Host smart-ce90ae60-439f-41d4-9e75-ed3a0ae4be35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487784512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.3487784512
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.3276649127
Short name T831
Test name
Test status
Simulation time 3539494602 ps
CPU time 7.74 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:11 PM PDT 24
Peak memory 242248 kb
Host smart-b9dd9645-1ccd-4e09-b641-3ef4d5efc28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276649127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.3276649127
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.2482090764
Short name T532
Test name
Test status
Simulation time 324812443 ps
CPU time 4.71 seconds
Started Jun 10 07:52:59 PM PDT 24
Finished Jun 10 07:53:07 PM PDT 24
Peak memory 242372 kb
Host smart-71b1320f-ddcb-45d0-8d9f-716714a8a36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482090764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.2482090764
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.1231247700
Short name T489
Test name
Test status
Simulation time 368134243 ps
CPU time 9 seconds
Started Jun 10 07:52:59 PM PDT 24
Finished Jun 10 07:53:11 PM PDT 24
Peak memory 242640 kb
Host smart-60d12413-c6eb-4444-9d90-8cef6ef14124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231247700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.1231247700
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.1592304377
Short name T1054
Test name
Test status
Simulation time 960054423 ps
CPU time 2.72 seconds
Started Jun 10 07:49:50 PM PDT 24
Finished Jun 10 07:49:56 PM PDT 24
Peak memory 240916 kb
Host smart-49f07739-2386-4618-8ae5-50344d147228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592304377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.1592304377
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.532218542
Short name T549
Test name
Test status
Simulation time 5732485853 ps
CPU time 36.65 seconds
Started Jun 10 07:49:44 PM PDT 24
Finished Jun 10 07:50:25 PM PDT 24
Peak memory 243096 kb
Host smart-71a793d5-c0fd-4a47-904a-4b76db1f95dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532218542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.532218542
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.1684796694
Short name T886
Test name
Test status
Simulation time 231231195 ps
CPU time 5.63 seconds
Started Jun 10 07:49:50 PM PDT 24
Finished Jun 10 07:49:59 PM PDT 24
Peak memory 248036 kb
Host smart-d476af37-6790-4f93-aedc-75543662174a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684796694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.1684796694
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.1082471295
Short name T974
Test name
Test status
Simulation time 281707329 ps
CPU time 11.67 seconds
Started Jun 10 07:49:49 PM PDT 24
Finished Jun 10 07:50:04 PM PDT 24
Peak memory 242120 kb
Host smart-ab34ea42-3a64-4e89-b54c-122c23687770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082471295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.1082471295
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.641035245
Short name T731
Test name
Test status
Simulation time 2180531983 ps
CPU time 27.09 seconds
Started Jun 10 07:49:48 PM PDT 24
Finished Jun 10 07:50:19 PM PDT 24
Peak memory 242608 kb
Host smart-152cfdeb-eb4e-4cd6-ba2a-7e385f8dcd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641035245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.641035245
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.4122143213
Short name T1133
Test name
Test status
Simulation time 1542546729 ps
CPU time 5.2 seconds
Started Jun 10 07:49:43 PM PDT 24
Finished Jun 10 07:49:52 PM PDT 24
Peak memory 242488 kb
Host smart-031db851-df0d-408d-837d-ab877ed6a23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122143213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.4122143213
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.4167308798
Short name T145
Test name
Test status
Simulation time 2161391833 ps
CPU time 32.28 seconds
Started Jun 10 07:49:50 PM PDT 24
Finished Jun 10 07:50:26 PM PDT 24
Peak memory 248384 kb
Host smart-f00012cb-b13a-4784-8f0a-21de092a1dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167308798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.4167308798
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.2919274254
Short name T1002
Test name
Test status
Simulation time 1100928843 ps
CPU time 16.7 seconds
Started Jun 10 07:49:45 PM PDT 24
Finished Jun 10 07:50:05 PM PDT 24
Peak memory 242468 kb
Host smart-293b533d-4295-4ab1-b3c7-72d8e6487ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919274254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.2919274254
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.876873675
Short name T795
Test name
Test status
Simulation time 380603976 ps
CPU time 7.65 seconds
Started Jun 10 07:49:45 PM PDT 24
Finished Jun 10 07:49:56 PM PDT 24
Peak memory 242032 kb
Host smart-0810fe9c-22f8-496f-8380-c0cdca76898e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876873675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.876873675
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.236456421
Short name T841
Test name
Test status
Simulation time 2876788526 ps
CPU time 19.77 seconds
Started Jun 10 07:49:49 PM PDT 24
Finished Jun 10 07:50:13 PM PDT 24
Peak memory 242240 kb
Host smart-9e51b430-5754-4b1d-8cbb-7b1ebca735e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=236456421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.236456421
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.456966475
Short name T241
Test name
Test status
Simulation time 21132946308 ps
CPU time 206.17 seconds
Started Jun 10 07:49:53 PM PDT 24
Finished Jun 10 07:53:23 PM PDT 24
Peak memory 279876 kb
Host smart-fff6d4a8-f20a-4c53-9bb1-64aca1e5f737
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456966475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.456966475
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.3146859095
Short name T952
Test name
Test status
Simulation time 1883858825 ps
CPU time 5.14 seconds
Started Jun 10 07:49:45 PM PDT 24
Finished Jun 10 07:49:54 PM PDT 24
Peak memory 242096 kb
Host smart-b86bd64f-5289-4cee-90a8-b018c1d85ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146859095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.3146859095
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.2712078125
Short name T654
Test name
Test status
Simulation time 17916452679 ps
CPU time 99.86 seconds
Started Jun 10 07:49:54 PM PDT 24
Finished Jun 10 07:51:37 PM PDT 24
Peak memory 247704 kb
Host smart-3f3d9833-2198-44f7-b810-51a353586935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712078125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.
2712078125
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.2105169774
Short name T646
Test name
Test status
Simulation time 806524215321 ps
CPU time 2911.24 seconds
Started Jun 10 07:49:48 PM PDT 24
Finished Jun 10 08:38:24 PM PDT 24
Peak memory 298644 kb
Host smart-cda9a6d0-11cf-48b4-8d27-608e70a9766c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105169774 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.2105169774
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.3650311992
Short name T979
Test name
Test status
Simulation time 758827137 ps
CPU time 9.38 seconds
Started Jun 10 07:49:49 PM PDT 24
Finished Jun 10 07:50:02 PM PDT 24
Peak memory 242556 kb
Host smart-9c81d2ce-2eba-4f4d-aeef-34a554abd97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650311992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.3650311992
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.1781131479
Short name T239
Test name
Test status
Simulation time 223133654 ps
CPU time 1.86 seconds
Started Jun 10 07:50:45 PM PDT 24
Finished Jun 10 07:50:49 PM PDT 24
Peak memory 240952 kb
Host smart-0036a683-fce6-45ca-b0bc-2a520465b3e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781131479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.1781131479
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.3933610626
Short name T1084
Test name
Test status
Simulation time 7246744941 ps
CPU time 14.14 seconds
Started Jun 10 07:50:48 PM PDT 24
Finished Jun 10 07:51:03 PM PDT 24
Peak memory 244504 kb
Host smart-83f0a2d9-763f-4d7b-8167-00a10d419b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933610626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.3933610626
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.4090074142
Short name T721
Test name
Test status
Simulation time 592453233 ps
CPU time 17.55 seconds
Started Jun 10 07:50:44 PM PDT 24
Finished Jun 10 07:51:04 PM PDT 24
Peak memory 242260 kb
Host smart-3b5b0d37-0ee5-4ab2-a36f-e59f4701bb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090074142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.4090074142
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.3468356079
Short name T525
Test name
Test status
Simulation time 10730191425 ps
CPU time 22.64 seconds
Started Jun 10 07:50:42 PM PDT 24
Finished Jun 10 07:51:07 PM PDT 24
Peak memory 243800 kb
Host smart-fe56e407-2ad0-43d9-826d-015adff70ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468356079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.3468356079
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.2050932859
Short name T594
Test name
Test status
Simulation time 377477690 ps
CPU time 4.54 seconds
Started Jun 10 07:50:40 PM PDT 24
Finished Jun 10 07:50:47 PM PDT 24
Peak memory 242432 kb
Host smart-6fa40ce5-d2a9-4477-8c1f-bb1e655d0ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050932859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.2050932859
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.3977622487
Short name T104
Test name
Test status
Simulation time 1201275028 ps
CPU time 24.64 seconds
Started Jun 10 07:50:43 PM PDT 24
Finished Jun 10 07:51:10 PM PDT 24
Peak memory 243084 kb
Host smart-fe441302-d422-4762-ac79-1ace6fd48c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977622487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.3977622487
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.154709720
Short name T915
Test name
Test status
Simulation time 7200552580 ps
CPU time 14.83 seconds
Started Jun 10 07:50:44 PM PDT 24
Finished Jun 10 07:51:01 PM PDT 24
Peak memory 242828 kb
Host smart-1ae6577c-6925-4563-840d-8f10c2404650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154709720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.154709720
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.1955200311
Short name T818
Test name
Test status
Simulation time 5591965246 ps
CPU time 18.31 seconds
Started Jun 10 07:50:41 PM PDT 24
Finished Jun 10 07:51:01 PM PDT 24
Peak memory 242624 kb
Host smart-f51ce072-52cc-4748-b17c-39dae5dd2e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955200311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.1955200311
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.210004951
Short name T557
Test name
Test status
Simulation time 172134577 ps
CPU time 4.6 seconds
Started Jun 10 07:50:42 PM PDT 24
Finished Jun 10 07:50:49 PM PDT 24
Peak memory 242036 kb
Host smart-7ea56469-022d-4db0-a083-bce9a245f592
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=210004951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.210004951
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.1198940040
Short name T805
Test name
Test status
Simulation time 4684686331 ps
CPU time 9.87 seconds
Started Jun 10 07:50:41 PM PDT 24
Finished Jun 10 07:50:54 PM PDT 24
Peak memory 242532 kb
Host smart-24ddccea-98ed-4b22-b576-c442c03dd833
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1198940040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.1198940040
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.2277690458
Short name T1173
Test name
Test status
Simulation time 573658107 ps
CPU time 6.23 seconds
Started Jun 10 07:50:41 PM PDT 24
Finished Jun 10 07:50:50 PM PDT 24
Peak memory 242508 kb
Host smart-b6244151-e2db-49e2-a98f-64d9fd014b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277690458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.2277690458
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.1690600020
Short name T1095
Test name
Test status
Simulation time 183142939917 ps
CPU time 931.46 seconds
Started Jun 10 07:50:44 PM PDT 24
Finished Jun 10 08:06:18 PM PDT 24
Peak memory 333408 kb
Host smart-d3d825ab-09e3-40c9-98c4-29d18f756968
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690600020 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.1690600020
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.220303229
Short name T85
Test name
Test status
Simulation time 242470056 ps
CPU time 4.53 seconds
Started Jun 10 07:53:01 PM PDT 24
Finished Jun 10 07:53:10 PM PDT 24
Peak memory 242460 kb
Host smart-b392473d-f98f-4bc4-ab36-3a9fc98b2f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220303229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.220303229
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.2054066433
Short name T1016
Test name
Test status
Simulation time 188775923 ps
CPU time 5.64 seconds
Started Jun 10 07:52:59 PM PDT 24
Finished Jun 10 07:53:08 PM PDT 24
Peak memory 242432 kb
Host smart-da8aad90-2fe5-4055-91d0-dc07349ef8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054066433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.2054066433
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.685489280
Short name T910
Test name
Test status
Simulation time 176284825 ps
CPU time 5.06 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:08 PM PDT 24
Peak memory 242320 kb
Host smart-67ed9f35-ea7e-4e4f-a1bc-0594ef02189e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685489280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.685489280
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.1199478864
Short name T158
Test name
Test status
Simulation time 504382690 ps
CPU time 4.14 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:08 PM PDT 24
Peak memory 242372 kb
Host smart-50ea7e3a-d39a-4fbb-888e-6a4e271f88da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199478864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.1199478864
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.809245378
Short name T150
Test name
Test status
Simulation time 270008422 ps
CPU time 3.81 seconds
Started Jun 10 07:53:09 PM PDT 24
Finished Jun 10 07:53:16 PM PDT 24
Peak memory 242576 kb
Host smart-5c5f1bed-6477-4e39-88a1-72020d01be3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809245378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.809245378
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.808988430
Short name T637
Test name
Test status
Simulation time 495566379 ps
CPU time 3.7 seconds
Started Jun 10 07:53:08 PM PDT 24
Finished Jun 10 07:53:15 PM PDT 24
Peak memory 242356 kb
Host smart-902271eb-b8b1-4544-ba49-9cd771192c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808988430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.808988430
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.3964631640
Short name T560
Test name
Test status
Simulation time 617705628 ps
CPU time 4.54 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:09 PM PDT 24
Peak memory 242396 kb
Host smart-d3bc1ad9-f8f7-4540-9625-50c1a9887c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964631640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.3964631640
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.1234911267
Short name T739
Test name
Test status
Simulation time 176971198 ps
CPU time 4.65 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:09 PM PDT 24
Peak memory 242296 kb
Host smart-92efa02f-559d-4465-b1b3-1003aa012bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234911267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.1234911267
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.67207455
Short name T660
Test name
Test status
Simulation time 565650478 ps
CPU time 4.46 seconds
Started Jun 10 07:53:01 PM PDT 24
Finished Jun 10 07:53:10 PM PDT 24
Peak memory 242348 kb
Host smart-a2af8b9a-51d5-46c6-8bc4-3fafe4f62cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67207455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.67207455
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.1565534044
Short name T129
Test name
Test status
Simulation time 297889098 ps
CPU time 4.01 seconds
Started Jun 10 07:52:59 PM PDT 24
Finished Jun 10 07:53:07 PM PDT 24
Peak memory 242508 kb
Host smart-89b97625-c280-466b-b8d2-0773f3293e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565534044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.1565534044
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.3210447050
Short name T762
Test name
Test status
Simulation time 47136184 ps
CPU time 1.74 seconds
Started Jun 10 07:50:41 PM PDT 24
Finished Jun 10 07:50:44 PM PDT 24
Peak memory 240732 kb
Host smart-6fc6e935-acf8-496a-864f-e0a5dda195ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210447050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.3210447050
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.2880076336
Short name T978
Test name
Test status
Simulation time 2534465292 ps
CPU time 5.83 seconds
Started Jun 10 07:50:43 PM PDT 24
Finished Jun 10 07:50:51 PM PDT 24
Peak memory 242404 kb
Host smart-7928286d-6c5d-4a0a-a8ff-251976a45f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880076336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.2880076336
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.24932582
Short name T1105
Test name
Test status
Simulation time 4462987250 ps
CPU time 18.25 seconds
Started Jun 10 07:50:43 PM PDT 24
Finished Jun 10 07:51:04 PM PDT 24
Peak memory 242436 kb
Host smart-5830013b-8d4d-4e9c-86e1-d47c0423fde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24932582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.24932582
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.3880456758
Short name T823
Test name
Test status
Simulation time 1770656324 ps
CPU time 15.66 seconds
Started Jun 10 07:50:43 PM PDT 24
Finished Jun 10 07:51:02 PM PDT 24
Peak memory 242404 kb
Host smart-9fa8fecd-66f1-46a5-8e11-6eb65e3a8ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880456758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.3880456758
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.1976848024
Short name T674
Test name
Test status
Simulation time 2781809155 ps
CPU time 6.2 seconds
Started Jun 10 07:50:42 PM PDT 24
Finished Jun 10 07:50:51 PM PDT 24
Peak memory 242516 kb
Host smart-651ea110-908a-408f-9f97-c552d39d0fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976848024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.1976848024
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.2738716168
Short name T994
Test name
Test status
Simulation time 571955767 ps
CPU time 4.85 seconds
Started Jun 10 07:50:41 PM PDT 24
Finished Jun 10 07:50:49 PM PDT 24
Peak memory 242136 kb
Host smart-e9679b2a-50d0-48ca-9013-c2ab56de5073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738716168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.2738716168
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.2723524396
Short name T395
Test name
Test status
Simulation time 3529684391 ps
CPU time 39.71 seconds
Started Jun 10 07:50:48 PM PDT 24
Finished Jun 10 07:51:29 PM PDT 24
Peak memory 243596 kb
Host smart-61a7b4d1-fcbe-4836-8f94-1a1f57e7d330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723524396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.2723524396
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.899632923
Short name T1085
Test name
Test status
Simulation time 127441568 ps
CPU time 3.73 seconds
Started Jun 10 07:50:42 PM PDT 24
Finished Jun 10 07:50:48 PM PDT 24
Peak memory 242256 kb
Host smart-8e3882c5-ff54-442c-856b-e82d443fc859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899632923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.899632923
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.1223119467
Short name T1043
Test name
Test status
Simulation time 2654584737 ps
CPU time 18.64 seconds
Started Jun 10 07:50:43 PM PDT 24
Finished Jun 10 07:51:04 PM PDT 24
Peak memory 242644 kb
Host smart-29db8769-d081-49ec-abd7-fb490d714334
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223119467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.1223119467
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.313762059
Short name T361
Test name
Test status
Simulation time 932463585 ps
CPU time 8.61 seconds
Started Jun 10 07:50:45 PM PDT 24
Finished Jun 10 07:50:55 PM PDT 24
Peak memory 242204 kb
Host smart-a32b84ab-20db-4b18-9fd6-0861cc474d46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=313762059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.313762059
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.1067899226
Short name T716
Test name
Test status
Simulation time 365969935 ps
CPU time 10.29 seconds
Started Jun 10 07:50:42 PM PDT 24
Finished Jun 10 07:50:55 PM PDT 24
Peak memory 242220 kb
Host smart-1be2b229-c8b8-4638-8f79-e98f4185f66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067899226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.1067899226
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.261374194
Short name T404
Test name
Test status
Simulation time 8000863620 ps
CPU time 21.53 seconds
Started Jun 10 07:50:43 PM PDT 24
Finished Jun 10 07:51:07 PM PDT 24
Peak memory 248996 kb
Host smart-3a166b52-81ed-4ffc-9942-ead70175b4ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261374194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.
261374194
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.340230954
Short name T600
Test name
Test status
Simulation time 659662746 ps
CPU time 9.5 seconds
Started Jun 10 07:50:42 PM PDT 24
Finished Jun 10 07:50:54 PM PDT 24
Peak memory 242348 kb
Host smart-ef1e525b-9092-4864-890d-0bbd0b9293af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340230954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.340230954
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.3550331014
Short name T940
Test name
Test status
Simulation time 2166480889 ps
CPU time 5.24 seconds
Started Jun 10 07:53:08 PM PDT 24
Finished Jun 10 07:53:16 PM PDT 24
Peak memory 242572 kb
Host smart-f87f42f2-57b9-4977-a3c8-a8f03628da2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550331014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.3550331014
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.807579405
Short name T584
Test name
Test status
Simulation time 141846311 ps
CPU time 4 seconds
Started Jun 10 07:53:09 PM PDT 24
Finished Jun 10 07:53:16 PM PDT 24
Peak memory 242360 kb
Host smart-67dd9042-e5f4-4e6a-b1f5-db1f146fbc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807579405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.807579405
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.958531122
Short name T200
Test name
Test status
Simulation time 684515044 ps
CPU time 4.81 seconds
Started Jun 10 07:53:09 PM PDT 24
Finished Jun 10 07:53:16 PM PDT 24
Peak memory 242260 kb
Host smart-cd7bf2fd-25aa-4683-8b0c-bcb74c2e1ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958531122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.958531122
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.1937150982
Short name T414
Test name
Test status
Simulation time 2702981422 ps
CPU time 5.76 seconds
Started Jun 10 07:52:59 PM PDT 24
Finished Jun 10 07:53:09 PM PDT 24
Peak memory 242520 kb
Host smart-3ac151b5-1608-4555-ba27-485ee11ff534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937150982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.1937150982
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.3870563375
Short name T699
Test name
Test status
Simulation time 132105573 ps
CPU time 3.99 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:08 PM PDT 24
Peak memory 242320 kb
Host smart-40ebd448-3dd6-478e-9751-7a9fe92d7f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870563375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.3870563375
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.3929092272
Short name T455
Test name
Test status
Simulation time 509094310 ps
CPU time 4.26 seconds
Started Jun 10 07:53:08 PM PDT 24
Finished Jun 10 07:53:15 PM PDT 24
Peak memory 242220 kb
Host smart-5d1a33da-b3a6-455d-996b-70d20b122228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929092272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.3929092272
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.2118465502
Short name T1024
Test name
Test status
Simulation time 386714862 ps
CPU time 3.49 seconds
Started Jun 10 07:52:58 PM PDT 24
Finished Jun 10 07:53:05 PM PDT 24
Peak memory 242224 kb
Host smart-704a2994-c367-4c42-8b9e-614764cb9728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118465502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.2118465502
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.3912637799
Short name T443
Test name
Test status
Simulation time 263780524 ps
CPU time 3.53 seconds
Started Jun 10 07:53:08 PM PDT 24
Finished Jun 10 07:53:14 PM PDT 24
Peak memory 242628 kb
Host smart-279ee299-ea6b-4669-b960-2111f8ae4731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912637799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.3912637799
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.1278816477
Short name T538
Test name
Test status
Simulation time 2215352293 ps
CPU time 6.21 seconds
Started Jun 10 07:52:58 PM PDT 24
Finished Jun 10 07:53:08 PM PDT 24
Peak memory 242416 kb
Host smart-e6e1fb8c-b069-4573-a6ff-addc0d176cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278816477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.1278816477
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.3487978703
Short name T438
Test name
Test status
Simulation time 94576168 ps
CPU time 2.05 seconds
Started Jun 10 07:50:41 PM PDT 24
Finished Jun 10 07:50:45 PM PDT 24
Peak memory 240776 kb
Host smart-95221a02-c75c-405b-8902-544e45f1e7fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487978703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.3487978703
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.844919640
Short name T875
Test name
Test status
Simulation time 10789151284 ps
CPU time 29.48 seconds
Started Jun 10 07:50:41 PM PDT 24
Finished Jun 10 07:51:12 PM PDT 24
Peak memory 242424 kb
Host smart-dfe4705d-bf19-45e8-95de-33e07f46169e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844919640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.844919640
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.471977249
Short name T107
Test name
Test status
Simulation time 1075565949 ps
CPU time 22.96 seconds
Started Jun 10 07:50:41 PM PDT 24
Finished Jun 10 07:51:05 PM PDT 24
Peak memory 242548 kb
Host smart-81dd6e66-c49f-42b7-8f65-3af588b98fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471977249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.471977249
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.338624842
Short name T25
Test name
Test status
Simulation time 699026825 ps
CPU time 5.12 seconds
Started Jun 10 07:50:49 PM PDT 24
Finished Jun 10 07:50:56 PM PDT 24
Peak memory 242412 kb
Host smart-def218d1-e56b-4a33-aa5d-d518f72bbbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338624842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.338624842
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.2569481180
Short name T797
Test name
Test status
Simulation time 336905348 ps
CPU time 5.63 seconds
Started Jun 10 07:50:46 PM PDT 24
Finished Jun 10 07:50:54 PM PDT 24
Peak memory 242696 kb
Host smart-390e401b-bef5-4c99-8c35-c509b660c705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569481180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.2569481180
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.1814833593
Short name T1070
Test name
Test status
Simulation time 1933661900 ps
CPU time 19.32 seconds
Started Jun 10 07:50:43 PM PDT 24
Finished Jun 10 07:51:05 PM PDT 24
Peak memory 242604 kb
Host smart-2a77c4c7-a548-4674-8ebc-54c2c6d9ed19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814833593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.1814833593
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.1699901504
Short name T539
Test name
Test status
Simulation time 180425811 ps
CPU time 8.73 seconds
Started Jun 10 07:50:41 PM PDT 24
Finished Jun 10 07:50:52 PM PDT 24
Peak memory 242524 kb
Host smart-c67305c3-3351-4d6f-b637-a239ed28e82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699901504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.1699901504
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.3970909102
Short name T925
Test name
Test status
Simulation time 538312607 ps
CPU time 16.46 seconds
Started Jun 10 07:50:43 PM PDT 24
Finished Jun 10 07:51:02 PM PDT 24
Peak memory 242260 kb
Host smart-6e19abeb-3c44-43bb-a401-05420acdb5e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3970909102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.3970909102
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.4004938364
Short name T892
Test name
Test status
Simulation time 128129556 ps
CPU time 3.39 seconds
Started Jun 10 07:50:41 PM PDT 24
Finished Jun 10 07:50:47 PM PDT 24
Peak memory 248964 kb
Host smart-e8d320be-6e5a-4776-abfb-eb138e260284
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4004938364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.4004938364
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.1153852333
Short name T957
Test name
Test status
Simulation time 151065263 ps
CPU time 4.43 seconds
Started Jun 10 07:50:44 PM PDT 24
Finished Jun 10 07:50:51 PM PDT 24
Peak memory 242108 kb
Host smart-74f3ad84-d663-46a8-b685-b024b51467b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153852333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.1153852333
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.3363695718
Short name T651
Test name
Test status
Simulation time 2746379604 ps
CPU time 50.79 seconds
Started Jun 10 07:50:45 PM PDT 24
Finished Jun 10 07:51:38 PM PDT 24
Peak memory 246224 kb
Host smart-94bde79b-9f5d-453e-86b9-891b71d122b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363695718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all
.3363695718
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.2061547360
Short name T1146
Test name
Test status
Simulation time 175953006929 ps
CPU time 1748.53 seconds
Started Jun 10 07:50:43 PM PDT 24
Finished Jun 10 08:19:55 PM PDT 24
Peak memory 334928 kb
Host smart-4f709675-c636-44cb-bc5a-4f5447f6b9af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061547360 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.2061547360
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.4112152881
Short name T381
Test name
Test status
Simulation time 577137858 ps
CPU time 13.91 seconds
Started Jun 10 07:50:44 PM PDT 24
Finished Jun 10 07:51:01 PM PDT 24
Peak memory 242604 kb
Host smart-2481c11e-5aba-4cd3-af46-ca9cee683073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112152881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.4112152881
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.921198728
Short name T201
Test name
Test status
Simulation time 1692916680 ps
CPU time 5.38 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:09 PM PDT 24
Peak memory 242272 kb
Host smart-db6a4b29-bccf-4ff6-90fd-c416a359ef9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921198728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.921198728
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.3499062642
Short name T117
Test name
Test status
Simulation time 230520348 ps
CPU time 3.53 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:08 PM PDT 24
Peak memory 242440 kb
Host smart-cd59d296-3118-4210-8595-85f90bfeca6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499062642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.3499062642
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.3390041749
Short name T891
Test name
Test status
Simulation time 410845758 ps
CPU time 5.11 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:08 PM PDT 24
Peak memory 242564 kb
Host smart-f2bea628-8659-4963-aab7-a9c012f271b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390041749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.3390041749
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.1726571808
Short name T837
Test name
Test status
Simulation time 388765633 ps
CPU time 3.82 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:08 PM PDT 24
Peak memory 242348 kb
Host smart-ca45e10a-14f7-486a-9270-94b367124996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726571808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.1726571808
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.1926393898
Short name T566
Test name
Test status
Simulation time 464913146 ps
CPU time 3.8 seconds
Started Jun 10 07:53:04 PM PDT 24
Finished Jun 10 07:53:11 PM PDT 24
Peak memory 242092 kb
Host smart-b91467a4-5070-4de8-a70c-e6ee7cb732cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926393898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.1926393898
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.2371180241
Short name T179
Test name
Test status
Simulation time 107697968 ps
CPU time 4.15 seconds
Started Jun 10 07:53:04 PM PDT 24
Finished Jun 10 07:53:11 PM PDT 24
Peak memory 242288 kb
Host smart-e395ffa5-3f23-44e1-aa10-51c34807e7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371180241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.2371180241
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.3431214372
Short name T43
Test name
Test status
Simulation time 161171117 ps
CPU time 3.87 seconds
Started Jun 10 07:53:01 PM PDT 24
Finished Jun 10 07:53:09 PM PDT 24
Peak memory 242552 kb
Host smart-84f1f9e1-e4dc-4b1b-adc3-cde00bbfdb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431214372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.3431214372
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.308768643
Short name T512
Test name
Test status
Simulation time 98641399 ps
CPU time 2.97 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:07 PM PDT 24
Peak memory 242316 kb
Host smart-654d08e4-999f-4bbd-8c75-b72520e6a9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308768643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.308768643
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.313591839
Short name T72
Test name
Test status
Simulation time 2114460977 ps
CPU time 7.04 seconds
Started Jun 10 07:52:59 PM PDT 24
Finished Jun 10 07:53:10 PM PDT 24
Peak memory 242588 kb
Host smart-f9eb934e-c47b-440b-a9b5-c7fdb6174f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313591839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.313591839
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.3327727680
Short name T869
Test name
Test status
Simulation time 298610344 ps
CPU time 4.48 seconds
Started Jun 10 07:53:01 PM PDT 24
Finished Jun 10 07:53:10 PM PDT 24
Peak memory 242416 kb
Host smart-8d75d051-312c-4166-999d-a1666d00ac22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327727680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.3327727680
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.2236424597
Short name T161
Test name
Test status
Simulation time 80519782 ps
CPU time 2.19 seconds
Started Jun 10 07:50:54 PM PDT 24
Finished Jun 10 07:50:59 PM PDT 24
Peak memory 240892 kb
Host smart-9a179b39-28e6-49e8-8a5d-fb3cc2914ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236424597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.2236424597
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.2179628611
Short name T1132
Test name
Test status
Simulation time 1225229958 ps
CPU time 9.38 seconds
Started Jun 10 07:50:51 PM PDT 24
Finished Jun 10 07:51:02 PM PDT 24
Peak memory 242348 kb
Host smart-a6f8f0cd-159a-41b5-86c2-55f22ce71e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179628611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.2179628611
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.3577284118
Short name T579
Test name
Test status
Simulation time 16416681143 ps
CPU time 41.39 seconds
Started Jun 10 07:50:52 PM PDT 24
Finished Jun 10 07:51:35 PM PDT 24
Peak memory 249628 kb
Host smart-a5ef356c-4089-47dc-9e84-27a6598d751d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577284118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.3577284118
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.252587552
Short name T199
Test name
Test status
Simulation time 7844358232 ps
CPU time 51.45 seconds
Started Jun 10 07:50:53 PM PDT 24
Finished Jun 10 07:51:47 PM PDT 24
Peak memory 243000 kb
Host smart-d627c06f-a50d-45d1-9a06-7d72dcaa2c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252587552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.252587552
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.1601203460
Short name T765
Test name
Test status
Simulation time 138978509 ps
CPU time 3.63 seconds
Started Jun 10 07:50:42 PM PDT 24
Finished Jun 10 07:50:48 PM PDT 24
Peak memory 242408 kb
Host smart-c1dc71e6-2d8d-41a4-9a11-2f8b201ed3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601203460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.1601203460
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.507069156
Short name T590
Test name
Test status
Simulation time 1224880784 ps
CPU time 7.28 seconds
Started Jun 10 07:50:53 PM PDT 24
Finished Jun 10 07:51:02 PM PDT 24
Peak memory 242280 kb
Host smart-1603d2e9-2537-4376-913b-185968c4967a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507069156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.507069156
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.38199422
Short name T1119
Test name
Test status
Simulation time 5546582280 ps
CPU time 43.61 seconds
Started Jun 10 07:50:54 PM PDT 24
Finished Jun 10 07:51:40 PM PDT 24
Peak memory 249136 kb
Host smart-fd7d0400-890f-466c-8946-26e0342a017e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38199422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.38199422
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.4139038262
Short name T1115
Test name
Test status
Simulation time 282187979 ps
CPU time 5.04 seconds
Started Jun 10 07:50:42 PM PDT 24
Finished Jun 10 07:50:50 PM PDT 24
Peak memory 242148 kb
Host smart-61e3ebf5-8daa-4d14-a428-008fdcdf6db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139038262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.4139038262
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.3422997769
Short name T783
Test name
Test status
Simulation time 3165039804 ps
CPU time 22.93 seconds
Started Jun 10 07:50:45 PM PDT 24
Finished Jun 10 07:51:10 PM PDT 24
Peak memory 242380 kb
Host smart-bc463e13-06b4-4d2d-b977-bd902523c6fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3422997769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.3422997769
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.861546144
Short name T746
Test name
Test status
Simulation time 145645897 ps
CPU time 5.91 seconds
Started Jun 10 07:50:52 PM PDT 24
Finished Jun 10 07:51:01 PM PDT 24
Peak memory 242248 kb
Host smart-d683fb25-37fa-4300-bc7a-6c55a6180719
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=861546144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.861546144
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.919108220
Short name T860
Test name
Test status
Simulation time 401080910 ps
CPU time 6.17 seconds
Started Jun 10 07:50:41 PM PDT 24
Finished Jun 10 07:50:49 PM PDT 24
Peak memory 242072 kb
Host smart-5b5ad2f8-ab4e-48a7-8e50-77ebc4bf9cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919108220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.919108220
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.3867977583
Short name T718
Test name
Test status
Simulation time 3572225238 ps
CPU time 129.72 seconds
Started Jun 10 07:50:55 PM PDT 24
Finished Jun 10 07:53:08 PM PDT 24
Peak memory 258200 kb
Host smart-9f543e0b-1a43-4507-a218-a9a1abc1f335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867977583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.3867977583
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.1290848833
Short name T748
Test name
Test status
Simulation time 279666900075 ps
CPU time 2378.19 seconds
Started Jun 10 07:50:53 PM PDT 24
Finished Jun 10 08:30:34 PM PDT 24
Peak memory 586868 kb
Host smart-7d7031ad-e6f0-4bcd-9faf-e71e0e60abc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290848833 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.1290848833
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.2088081247
Short name T428
Test name
Test status
Simulation time 2574387248 ps
CPU time 15.13 seconds
Started Jun 10 07:50:50 PM PDT 24
Finished Jun 10 07:51:06 PM PDT 24
Peak memory 249112 kb
Host smart-27091c38-2dbf-4be3-ad84-4126b09bfb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088081247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.2088081247
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.3971378511
Short name T159
Test name
Test status
Simulation time 502125804 ps
CPU time 3.88 seconds
Started Jun 10 07:53:00 PM PDT 24
Finished Jun 10 07:53:08 PM PDT 24
Peak memory 242392 kb
Host smart-da45855a-f493-4087-9567-05fdd2e7242c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971378511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.3971378511
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.2962818811
Short name T446
Test name
Test status
Simulation time 1515569220 ps
CPU time 3.95 seconds
Started Jun 10 07:53:04 PM PDT 24
Finished Jun 10 07:53:11 PM PDT 24
Peak memory 242504 kb
Host smart-bc72f1fd-397a-4842-bc95-933a174823bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962818811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.2962818811
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.2807048884
Short name T703
Test name
Test status
Simulation time 168991670 ps
CPU time 4.55 seconds
Started Jun 10 07:53:01 PM PDT 24
Finished Jun 10 07:53:10 PM PDT 24
Peak memory 242172 kb
Host smart-4a56dca7-61eb-4822-ba7e-19c427c88ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807048884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.2807048884
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.3572520322
Short name T292
Test name
Test status
Simulation time 168117801 ps
CPU time 4.56 seconds
Started Jun 10 07:53:01 PM PDT 24
Finished Jun 10 07:53:09 PM PDT 24
Peak memory 242684 kb
Host smart-8c1523d1-987d-4750-802c-759ae77f7f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572520322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.3572520322
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.2866540049
Short name T606
Test name
Test status
Simulation time 254629576 ps
CPU time 4.36 seconds
Started Jun 10 07:53:04 PM PDT 24
Finished Jun 10 07:53:11 PM PDT 24
Peak memory 242332 kb
Host smart-2642623b-7184-44d2-9ce4-999afcf1ad15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866540049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.2866540049
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.3802318670
Short name T696
Test name
Test status
Simulation time 1906908633 ps
CPU time 4.67 seconds
Started Jun 10 07:53:12 PM PDT 24
Finished Jun 10 07:53:19 PM PDT 24
Peak memory 242364 kb
Host smart-112491b6-ec92-429e-8a71-d65c5f0723f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802318670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.3802318670
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.3473123828
Short name T1035
Test name
Test status
Simulation time 298861209 ps
CPU time 5.35 seconds
Started Jun 10 07:53:10 PM PDT 24
Finished Jun 10 07:53:18 PM PDT 24
Peak memory 242496 kb
Host smart-dec73e84-9c3d-48bb-bbbb-f9df1c3778b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473123828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.3473123828
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.213513266
Short name T1014
Test name
Test status
Simulation time 1605986661 ps
CPU time 4.89 seconds
Started Jun 10 07:53:16 PM PDT 24
Finished Jun 10 07:53:24 PM PDT 24
Peak memory 242200 kb
Host smart-19e11abe-13a3-44a9-abe8-f5272968fe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213513266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.213513266
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.2159075707
Short name T29
Test name
Test status
Simulation time 177307439 ps
CPU time 4.81 seconds
Started Jun 10 07:53:05 PM PDT 24
Finished Jun 10 07:53:13 PM PDT 24
Peak memory 242304 kb
Host smart-523d25da-399c-4439-9618-7494648851cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159075707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.2159075707
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.1271326897
Short name T872
Test name
Test status
Simulation time 464720315 ps
CPU time 5.16 seconds
Started Jun 10 07:53:11 PM PDT 24
Finished Jun 10 07:53:18 PM PDT 24
Peak memory 242440 kb
Host smart-e93d60f1-3fca-476a-8d1f-21e12c033607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271326897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.1271326897
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.457655123
Short name T1037
Test name
Test status
Simulation time 76589382 ps
CPU time 1.94 seconds
Started Jun 10 07:50:52 PM PDT 24
Finished Jun 10 07:50:56 PM PDT 24
Peak memory 241152 kb
Host smart-dbecb4de-44bb-43c9-8ee4-bd21b7804dd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457655123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.457655123
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.1076952128
Short name T34
Test name
Test status
Simulation time 374191329 ps
CPU time 7.6 seconds
Started Jun 10 07:50:53 PM PDT 24
Finished Jun 10 07:51:03 PM PDT 24
Peak memory 242316 kb
Host smart-b37b5d4a-f4a7-471a-8943-0a03a089af78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076952128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.1076952128
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.2152088607
Short name T956
Test name
Test status
Simulation time 597132079 ps
CPU time 19.74 seconds
Started Jun 10 07:50:53 PM PDT 24
Finished Jun 10 07:51:16 PM PDT 24
Peak memory 242216 kb
Host smart-f8c48d17-8fe1-4553-bc0b-a7721621c53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152088607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.2152088607
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.4115216582
Short name T1004
Test name
Test status
Simulation time 1573622505 ps
CPU time 15.63 seconds
Started Jun 10 07:50:53 PM PDT 24
Finished Jun 10 07:51:11 PM PDT 24
Peak memory 242496 kb
Host smart-1afd5373-8e67-4c96-b926-021066cce16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115216582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.4115216582
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.3664876943
Short name T61
Test name
Test status
Simulation time 162911956 ps
CPU time 4.2 seconds
Started Jun 10 07:50:51 PM PDT 24
Finished Jun 10 07:50:57 PM PDT 24
Peak memory 242352 kb
Host smart-fcdbcc1a-c198-47ce-bf99-eef74636182d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664876943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.3664876943
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.1130923324
Short name T829
Test name
Test status
Simulation time 8734533617 ps
CPU time 47.57 seconds
Started Jun 10 07:50:53 PM PDT 24
Finished Jun 10 07:51:43 PM PDT 24
Peak memory 243332 kb
Host smart-d0dd90fa-d1e8-437c-9d58-88750868196e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130923324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.1130923324
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.1858946073
Short name T742
Test name
Test status
Simulation time 1644889044 ps
CPU time 18.49 seconds
Started Jun 10 07:50:54 PM PDT 24
Finished Jun 10 07:51:15 PM PDT 24
Peak memory 242256 kb
Host smart-1898410e-bf2b-4e15-a181-8565440685ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858946073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.1858946073
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.103071240
Short name T468
Test name
Test status
Simulation time 310970765 ps
CPU time 9.28 seconds
Started Jun 10 07:50:56 PM PDT 24
Finished Jun 10 07:51:08 PM PDT 24
Peak memory 241812 kb
Host smart-6a587385-3c30-4c47-a5b4-fa78711cd126
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=103071240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.103071240
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.2737240830
Short name T992
Test name
Test status
Simulation time 308931572 ps
CPU time 10.19 seconds
Started Jun 10 07:50:55 PM PDT 24
Finished Jun 10 07:51:08 PM PDT 24
Peak memory 242572 kb
Host smart-85cc5e76-bab0-4c5e-a0bd-90137deb5577
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2737240830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.2737240830
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.2003429396
Short name T624
Test name
Test status
Simulation time 588045707 ps
CPU time 3.89 seconds
Started Jun 10 07:50:54 PM PDT 24
Finished Jun 10 07:51:00 PM PDT 24
Peak memory 242096 kb
Host smart-db736a65-41ca-4b4e-a264-3d85a5b4cc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003429396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.2003429396
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.2224831604
Short name T942
Test name
Test status
Simulation time 10727657451 ps
CPU time 65.1 seconds
Started Jun 10 07:50:53 PM PDT 24
Finished Jun 10 07:52:00 PM PDT 24
Peak memory 257384 kb
Host smart-16b93510-cdfa-40e5-8bd9-26f45bb060fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224831604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.2224831604
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.926450734
Short name T279
Test name
Test status
Simulation time 21785680976 ps
CPU time 418.46 seconds
Started Jun 10 07:50:54 PM PDT 24
Finished Jun 10 07:57:55 PM PDT 24
Peak memory 257484 kb
Host smart-02eb83eb-036f-4da5-b728-99c951f83abc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926450734 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.926450734
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.1218093522
Short name T589
Test name
Test status
Simulation time 871930336 ps
CPU time 15.4 seconds
Started Jun 10 07:50:57 PM PDT 24
Finished Jun 10 07:51:15 PM PDT 24
Peak memory 242736 kb
Host smart-61318a33-1f6d-42d4-8afb-ced431420a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218093522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.1218093522
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.2770301991
Short name T1079
Test name
Test status
Simulation time 254411501 ps
CPU time 3.88 seconds
Started Jun 10 07:53:15 PM PDT 24
Finished Jun 10 07:53:22 PM PDT 24
Peak memory 242448 kb
Host smart-4a742d78-0f2c-455c-81d6-d8f912fbb6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770301991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.2770301991
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.3743404920
Short name T1166
Test name
Test status
Simulation time 166385218 ps
CPU time 4.62 seconds
Started Jun 10 07:53:10 PM PDT 24
Finished Jun 10 07:53:17 PM PDT 24
Peak memory 242240 kb
Host smart-5bd50f64-e6ca-434b-9599-d425c1f1c621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743404920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.3743404920
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.1551135679
Short name T737
Test name
Test status
Simulation time 190238346 ps
CPU time 4.05 seconds
Started Jun 10 07:53:07 PM PDT 24
Finished Jun 10 07:53:14 PM PDT 24
Peak memory 242352 kb
Host smart-d2faea26-d2e0-40c6-85b5-45f0b87f76c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551135679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.1551135679
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.2814180079
Short name T492
Test name
Test status
Simulation time 125776113 ps
CPU time 3.48 seconds
Started Jun 10 07:53:16 PM PDT 24
Finished Jun 10 07:53:22 PM PDT 24
Peak memory 242224 kb
Host smart-c7cf7eab-af6f-4717-84ff-d9668890f33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814180079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.2814180079
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.3217190298
Short name T757
Test name
Test status
Simulation time 311643697 ps
CPU time 4.93 seconds
Started Jun 10 07:53:09 PM PDT 24
Finished Jun 10 07:53:17 PM PDT 24
Peak memory 242316 kb
Host smart-74407980-86fa-4830-80fa-59f7c465b952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217190298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.3217190298
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.1126963841
Short name T950
Test name
Test status
Simulation time 283442909 ps
CPU time 4.23 seconds
Started Jun 10 07:53:15 PM PDT 24
Finished Jun 10 07:53:22 PM PDT 24
Peak memory 242456 kb
Host smart-89ff6629-ec18-40de-9a20-75c5bac875d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126963841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.1126963841
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.309874808
Short name T289
Test name
Test status
Simulation time 345033022 ps
CPU time 4.03 seconds
Started Jun 10 07:53:10 PM PDT 24
Finished Jun 10 07:53:16 PM PDT 24
Peak memory 242520 kb
Host smart-85610fe8-0ae9-4fa4-9aad-980b2c2cbac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309874808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.309874808
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.2376883115
Short name T542
Test name
Test status
Simulation time 1482789610 ps
CPU time 4.57 seconds
Started Jun 10 07:53:08 PM PDT 24
Finished Jun 10 07:53:16 PM PDT 24
Peak memory 242352 kb
Host smart-11b6a277-e9ab-4610-b825-1e0ee21708a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376883115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.2376883115
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.1200694632
Short name T1017
Test name
Test status
Simulation time 1501444374 ps
CPU time 4.28 seconds
Started Jun 10 07:53:06 PM PDT 24
Finished Jun 10 07:53:13 PM PDT 24
Peak memory 242452 kb
Host smart-0ceddff8-cf2b-4ee2-8ed8-6ef5814a73ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200694632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.1200694632
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.981260084
Short name T71
Test name
Test status
Simulation time 354473772 ps
CPU time 4.66 seconds
Started Jun 10 07:53:08 PM PDT 24
Finished Jun 10 07:53:16 PM PDT 24
Peak memory 242520 kb
Host smart-385f2d7a-dd7f-4778-8a2e-ad6875215a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981260084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.981260084
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.2893046574
Short name T627
Test name
Test status
Simulation time 118102304 ps
CPU time 2.19 seconds
Started Jun 10 07:50:54 PM PDT 24
Finished Jun 10 07:50:59 PM PDT 24
Peak memory 240864 kb
Host smart-6cfe656f-7073-4805-9a79-10549e2673a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893046574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.2893046574
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.1076540273
Short name T689
Test name
Test status
Simulation time 13648836124 ps
CPU time 43.92 seconds
Started Jun 10 07:50:55 PM PDT 24
Finished Jun 10 07:51:41 PM PDT 24
Peak memory 249168 kb
Host smart-31523206-9cb3-4449-9e4a-756ad9e0aa2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076540273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.1076540273
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.2846858722
Short name T346
Test name
Test status
Simulation time 4273822075 ps
CPU time 22.11 seconds
Started Jun 10 07:50:55 PM PDT 24
Finished Jun 10 07:51:20 PM PDT 24
Peak memory 242484 kb
Host smart-6f013ea3-68bf-47b0-acda-c686dae747d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846858722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.2846858722
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.2206305170
Short name T185
Test name
Test status
Simulation time 984731453 ps
CPU time 26.12 seconds
Started Jun 10 07:50:51 PM PDT 24
Finished Jun 10 07:51:19 PM PDT 24
Peak memory 242356 kb
Host smart-ca8ed189-787e-4db8-a317-f14f6a9fbe60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206305170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.2206305170
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.3865249458
Short name T848
Test name
Test status
Simulation time 225835949 ps
CPU time 3.4 seconds
Started Jun 10 07:50:53 PM PDT 24
Finished Jun 10 07:51:00 PM PDT 24
Peak memory 242396 kb
Host smart-a432f46e-6e6a-4992-b716-85824d717c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865249458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.3865249458
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.3501499918
Short name T935
Test name
Test status
Simulation time 2954733703 ps
CPU time 20.49 seconds
Started Jun 10 07:50:55 PM PDT 24
Finished Jun 10 07:51:18 PM PDT 24
Peak memory 249120 kb
Host smart-4b4fab4d-5210-43de-b882-bdd0fe44acda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501499918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.3501499918
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.1997797476
Short name T759
Test name
Test status
Simulation time 166286930 ps
CPU time 4.21 seconds
Started Jun 10 07:50:54 PM PDT 24
Finished Jun 10 07:51:01 PM PDT 24
Peak memory 242068 kb
Host smart-29828dbe-37af-46f1-9015-dabb8a5dbfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997797476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.1997797476
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.2820846129
Short name T97
Test name
Test status
Simulation time 638866613 ps
CPU time 16.24 seconds
Started Jun 10 07:50:52 PM PDT 24
Finished Jun 10 07:51:11 PM PDT 24
Peak memory 242180 kb
Host smart-da49e537-c625-42f2-b3d9-4e278c314c62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2820846129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.2820846129
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.3044919080
Short name T422
Test name
Test status
Simulation time 602598208 ps
CPU time 6.17 seconds
Started Jun 10 07:50:56 PM PDT 24
Finished Jun 10 07:51:05 PM PDT 24
Peak memory 242472 kb
Host smart-d5b872be-28dd-41ff-b42a-dcb1e7cc1ce8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3044919080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.3044919080
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.2583844101
Short name T412
Test name
Test status
Simulation time 226151740 ps
CPU time 4.92 seconds
Started Jun 10 07:50:51 PM PDT 24
Finished Jun 10 07:50:57 PM PDT 24
Peak memory 248680 kb
Host smart-e0071a2f-0eb3-4489-8c6e-5517d2fbb82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583844101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.2583844101
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.2266840846
Short name T282
Test name
Test status
Simulation time 285916849471 ps
CPU time 828.35 seconds
Started Jun 10 07:50:52 PM PDT 24
Finished Jun 10 08:04:42 PM PDT 24
Peak memory 296488 kb
Host smart-2bfd7488-1ff7-414b-9b5c-f6cb3193f22d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266840846 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.2266840846
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.4085250801
Short name T767
Test name
Test status
Simulation time 1954547477 ps
CPU time 40.83 seconds
Started Jun 10 07:50:53 PM PDT 24
Finished Jun 10 07:51:37 PM PDT 24
Peak memory 243360 kb
Host smart-0f27e163-2b11-4b29-a4de-e600f3c35a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085250801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.4085250801
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.2403604141
Short name T36
Test name
Test status
Simulation time 147218353 ps
CPU time 4.91 seconds
Started Jun 10 07:53:06 PM PDT 24
Finished Jun 10 07:53:14 PM PDT 24
Peak memory 242276 kb
Host smart-717fdffc-0c63-4c6f-8667-0a62bd307970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403604141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.2403604141
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.3745617783
Short name T1174
Test name
Test status
Simulation time 2798857201 ps
CPU time 5.81 seconds
Started Jun 10 07:53:09 PM PDT 24
Finished Jun 10 07:53:18 PM PDT 24
Peak memory 242788 kb
Host smart-517de626-f730-4105-a378-49fb91228f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745617783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.3745617783
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.1694019218
Short name T172
Test name
Test status
Simulation time 132219243 ps
CPU time 4.74 seconds
Started Jun 10 07:53:08 PM PDT 24
Finished Jun 10 07:53:16 PM PDT 24
Peak memory 242496 kb
Host smart-8c668e2c-509c-421c-b833-0b88a2464f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694019218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.1694019218
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.4040149431
Short name T792
Test name
Test status
Simulation time 2388977455 ps
CPU time 5.14 seconds
Started Jun 10 07:53:12 PM PDT 24
Finished Jun 10 07:53:19 PM PDT 24
Peak memory 242432 kb
Host smart-5101d9d6-0685-4729-9258-ac5d8ad16cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040149431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.4040149431
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.3814853461
Short name T747
Test name
Test status
Simulation time 619621611 ps
CPU time 5.15 seconds
Started Jun 10 07:53:09 PM PDT 24
Finished Jun 10 07:53:17 PM PDT 24
Peak memory 242444 kb
Host smart-7b73090e-c3c1-41f6-8e3c-a7e8d938ce38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814853461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.3814853461
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.1375075339
Short name T628
Test name
Test status
Simulation time 100937488 ps
CPU time 3.88 seconds
Started Jun 10 07:53:11 PM PDT 24
Finished Jun 10 07:53:17 PM PDT 24
Peak memory 242336 kb
Host smart-dcc624fe-9133-4b83-a6da-3bd55a1ef0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375075339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.1375075339
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.1136426523
Short name T1091
Test name
Test status
Simulation time 145936663 ps
CPU time 4.32 seconds
Started Jun 10 07:53:13 PM PDT 24
Finished Jun 10 07:53:19 PM PDT 24
Peak memory 242404 kb
Host smart-2be6836d-8675-4986-96cc-c57f0d6584c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136426523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.1136426523
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.840989564
Short name T545
Test name
Test status
Simulation time 2426976542 ps
CPU time 5.39 seconds
Started Jun 10 07:53:09 PM PDT 24
Finished Jun 10 07:53:17 PM PDT 24
Peak memory 242648 kb
Host smart-ba78af41-bdba-4a03-b977-f98ace0bafc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840989564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.840989564
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.1039506399
Short name T202
Test name
Test status
Simulation time 527549375 ps
CPU time 4.37 seconds
Started Jun 10 07:53:09 PM PDT 24
Finished Jun 10 07:53:16 PM PDT 24
Peak memory 242304 kb
Host smart-7e3df368-21f6-428e-a484-bb3b49431e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039506399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.1039506399
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.3903520886
Short name T207
Test name
Test status
Simulation time 106809972 ps
CPU time 3.56 seconds
Started Jun 10 07:53:13 PM PDT 24
Finished Jun 10 07:53:18 PM PDT 24
Peak memory 242692 kb
Host smart-0446559a-3b06-4206-9d0c-037cfdd69a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903520886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.3903520886
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.3546160173
Short name T1086
Test name
Test status
Simulation time 492011813 ps
CPU time 2.98 seconds
Started Jun 10 07:50:55 PM PDT 24
Finished Jun 10 07:51:01 PM PDT 24
Peak memory 241112 kb
Host smart-35cf86bc-c1f6-458c-8945-2228da463a87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546160173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.3546160173
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.3168940361
Short name T115
Test name
Test status
Simulation time 514876765 ps
CPU time 16.32 seconds
Started Jun 10 07:50:55 PM PDT 24
Finished Jun 10 07:51:15 PM PDT 24
Peak memory 243004 kb
Host smart-b99007fc-f1cd-49d7-ba32-6a41af591485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168940361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.3168940361
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.3248250905
Short name T491
Test name
Test status
Simulation time 8337488052 ps
CPU time 18.64 seconds
Started Jun 10 07:50:53 PM PDT 24
Finished Jun 10 07:51:14 PM PDT 24
Peak memory 242336 kb
Host smart-99e982a2-e284-4560-af65-d21ac3b5e78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248250905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.3248250905
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.289988158
Short name T883
Test name
Test status
Simulation time 8627169239 ps
CPU time 52.46 seconds
Started Jun 10 07:50:52 PM PDT 24
Finished Jun 10 07:51:46 PM PDT 24
Peak memory 242288 kb
Host smart-f99ef6fb-b3bf-4282-9cee-efffa55d018e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289988158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.289988158
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.149981720
Short name T820
Test name
Test status
Simulation time 654667965 ps
CPU time 5.4 seconds
Started Jun 10 07:50:54 PM PDT 24
Finished Jun 10 07:51:02 PM PDT 24
Peak memory 242240 kb
Host smart-7ace1c88-37cc-4b9e-bb48-be2869beb695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149981720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.149981720
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.3469297901
Short name T825
Test name
Test status
Simulation time 453740542 ps
CPU time 10.49 seconds
Started Jun 10 07:50:57 PM PDT 24
Finished Jun 10 07:51:10 PM PDT 24
Peak memory 242764 kb
Host smart-b880e8fe-d822-4981-92b0-34fd5789594f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469297901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.3469297901
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.2426851529
Short name T676
Test name
Test status
Simulation time 8802611793 ps
CPU time 25.98 seconds
Started Jun 10 07:50:54 PM PDT 24
Finished Jun 10 07:51:23 PM PDT 24
Peak memory 242500 kb
Host smart-c54e1a52-e533-468f-b084-e9873559f847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426851529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.2426851529
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.2547150686
Short name T603
Test name
Test status
Simulation time 232912564 ps
CPU time 3.84 seconds
Started Jun 10 07:50:55 PM PDT 24
Finished Jun 10 07:51:02 PM PDT 24
Peak memory 242188 kb
Host smart-65900dae-c83f-4db1-9d1a-e68b462074f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547150686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.2547150686
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.453203837
Short name T533
Test name
Test status
Simulation time 1015910553 ps
CPU time 10.3 seconds
Started Jun 10 07:50:57 PM PDT 24
Finished Jun 10 07:51:10 PM PDT 24
Peak memory 242144 kb
Host smart-d2776cd3-4773-4952-bf40-1a5b4a222f01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=453203837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.453203837
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.370721633
Short name T368
Test name
Test status
Simulation time 144849396 ps
CPU time 4.96 seconds
Started Jun 10 07:50:55 PM PDT 24
Finished Jun 10 07:51:03 PM PDT 24
Peak memory 242296 kb
Host smart-493f7ed0-0a07-4bc2-95d0-8df43206e087
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370721633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.370721633
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.1764842702
Short name T431
Test name
Test status
Simulation time 10139384373 ps
CPU time 14.45 seconds
Started Jun 10 07:50:55 PM PDT 24
Finished Jun 10 07:51:13 PM PDT 24
Peak memory 242636 kb
Host smart-65157281-3e07-40ac-8b37-e63363f4d180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764842702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.1764842702
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.2049418931
Short name T247
Test name
Test status
Simulation time 63601357636 ps
CPU time 133.7 seconds
Started Jun 10 07:50:53 PM PDT 24
Finished Jun 10 07:53:09 PM PDT 24
Peak memory 259576 kb
Host smart-bd86888c-39c2-4aad-a86d-0de910aefe88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049418931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all
.2049418931
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.61681392
Short name T217
Test name
Test status
Simulation time 20927555952 ps
CPU time 463.23 seconds
Started Jun 10 07:50:54 PM PDT 24
Finished Jun 10 07:58:40 PM PDT 24
Peak memory 257468 kb
Host smart-84aa0456-7590-4b9f-b18b-6424b49a5a6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61681392 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.61681392
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.3740735798
Short name T390
Test name
Test status
Simulation time 454502085 ps
CPU time 8.54 seconds
Started Jun 10 07:50:52 PM PDT 24
Finished Jun 10 07:51:02 PM PDT 24
Peak memory 242492 kb
Host smart-4221e825-27c5-4749-8c29-2c732a62e056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740735798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.3740735798
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.918121363
Short name T451
Test name
Test status
Simulation time 512964758 ps
CPU time 4.8 seconds
Started Jun 10 07:53:08 PM PDT 24
Finished Jun 10 07:53:16 PM PDT 24
Peak memory 242308 kb
Host smart-7ba76ce9-8eaa-4504-b01e-775169270ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918121363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.918121363
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.1512788618
Short name T719
Test name
Test status
Simulation time 576606442 ps
CPU time 4.63 seconds
Started Jun 10 07:53:08 PM PDT 24
Finished Jun 10 07:53:16 PM PDT 24
Peak memory 242712 kb
Host smart-92e31161-3373-47a1-bfea-df9df8981193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512788618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.1512788618
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.841818658
Short name T208
Test name
Test status
Simulation time 375070900 ps
CPU time 3.81 seconds
Started Jun 10 07:53:10 PM PDT 24
Finished Jun 10 07:53:16 PM PDT 24
Peak memory 242508 kb
Host smart-0c7fcb3a-38a3-46ec-b4dd-c157283f6e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841818658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.841818658
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.3781423958
Short name T499
Test name
Test status
Simulation time 163270214 ps
CPU time 4.06 seconds
Started Jun 10 07:53:11 PM PDT 24
Finished Jun 10 07:53:17 PM PDT 24
Peak memory 242632 kb
Host smart-9acecb7d-9750-46dc-aa3d-0b192b21dd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781423958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.3781423958
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.2151438918
Short name T198
Test name
Test status
Simulation time 513979730 ps
CPU time 4.64 seconds
Started Jun 10 07:53:11 PM PDT 24
Finished Jun 10 07:53:18 PM PDT 24
Peak memory 242340 kb
Host smart-700fe0bb-120c-4b11-b809-1fab396333e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151438918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.2151438918
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.553287661
Short name T567
Test name
Test status
Simulation time 1860508986 ps
CPU time 4.26 seconds
Started Jun 10 07:53:08 PM PDT 24
Finished Jun 10 07:53:15 PM PDT 24
Peak memory 242312 kb
Host smart-3fdc8c5d-6fc0-488e-b6f0-cfad060d0a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553287661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.553287661
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.2608438297
Short name T23
Test name
Test status
Simulation time 174259766 ps
CPU time 4.38 seconds
Started Jun 10 07:53:15 PM PDT 24
Finished Jun 10 07:53:22 PM PDT 24
Peak memory 242536 kb
Host smart-244936cd-e4c4-4dd6-b956-82a5bb676d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608438297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.2608438297
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.2129571652
Short name T479
Test name
Test status
Simulation time 188331798 ps
CPU time 3.65 seconds
Started Jun 10 07:53:17 PM PDT 24
Finished Jun 10 07:53:23 PM PDT 24
Peak memory 242224 kb
Host smart-264b1bf4-37fd-4866-8900-107f63cccc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129571652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.2129571652
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.4214584253
Short name T126
Test name
Test status
Simulation time 181196923 ps
CPU time 4.18 seconds
Started Jun 10 07:53:17 PM PDT 24
Finished Jun 10 07:53:23 PM PDT 24
Peak memory 242364 kb
Host smart-121ec4c7-b842-4fb3-8516-d2d79e0f74dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214584253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.4214584253
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.2229424168
Short name T1031
Test name
Test status
Simulation time 422092861 ps
CPU time 4.1 seconds
Started Jun 10 07:53:16 PM PDT 24
Finished Jun 10 07:53:23 PM PDT 24
Peak memory 242580 kb
Host smart-ffd69bc0-6a3f-4349-b5ab-0d2ab4c1e365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229424168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.2229424168
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.2009792523
Short name T791
Test name
Test status
Simulation time 906333674 ps
CPU time 2.78 seconds
Started Jun 10 07:51:09 PM PDT 24
Finished Jun 10 07:51:13 PM PDT 24
Peak memory 241184 kb
Host smart-4b7f9afb-6f85-43e5-b4ca-c75c434633b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009792523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.2009792523
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.3179564722
Short name T898
Test name
Test status
Simulation time 531264644 ps
CPU time 17.94 seconds
Started Jun 10 07:50:54 PM PDT 24
Finished Jun 10 07:51:15 PM PDT 24
Peak memory 243104 kb
Host smart-3189ec8b-f2a2-468e-89cd-261723e95ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179564722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.3179564722
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.3208349515
Short name T1061
Test name
Test status
Simulation time 11616378802 ps
CPU time 23.95 seconds
Started Jun 10 07:50:57 PM PDT 24
Finished Jun 10 07:51:24 PM PDT 24
Peak memory 242404 kb
Host smart-3d89ac8c-ab51-409a-a0e6-d26caa0bf2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208349515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.3208349515
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.1916094973
Short name T31
Test name
Test status
Simulation time 1189819265 ps
CPU time 22.3 seconds
Started Jun 10 07:50:53 PM PDT 24
Finished Jun 10 07:51:19 PM PDT 24
Peak memory 242116 kb
Host smart-19ad4845-f53f-4023-ac5a-49a3d2cfeec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916094973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.1916094973
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.1911579628
Short name T516
Test name
Test status
Simulation time 131844194 ps
CPU time 3.17 seconds
Started Jun 10 07:50:56 PM PDT 24
Finished Jun 10 07:51:02 PM PDT 24
Peak memory 242344 kb
Host smart-2f8328a0-3e17-45c9-abed-3f3454f24012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911579628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.1911579628
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.4189328422
Short name T236
Test name
Test status
Simulation time 1035851416 ps
CPU time 17.1 seconds
Started Jun 10 07:50:52 PM PDT 24
Finished Jun 10 07:51:11 PM PDT 24
Peak memory 243816 kb
Host smart-45b4bfc9-1e22-437a-b002-d082300edaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189328422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.4189328422
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.2296397394
Short name T611
Test name
Test status
Simulation time 13698590146 ps
CPU time 33.6 seconds
Started Jun 10 07:50:56 PM PDT 24
Finished Jun 10 07:51:33 PM PDT 24
Peak memory 243772 kb
Host smart-3ac9a2ad-592d-4503-87dc-c22ba749416f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296397394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.2296397394
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.1006267632
Short name T411
Test name
Test status
Simulation time 220177515 ps
CPU time 10.47 seconds
Started Jun 10 07:50:55 PM PDT 24
Finished Jun 10 07:51:08 PM PDT 24
Peak memory 242172 kb
Host smart-556bb96e-724d-4eb7-8179-524974fca253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006267632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.1006267632
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.2056426182
Short name T419
Test name
Test status
Simulation time 956335284 ps
CPU time 8.82 seconds
Started Jun 10 07:50:56 PM PDT 24
Finished Jun 10 07:51:08 PM PDT 24
Peak memory 241760 kb
Host smart-7dcf3f10-136c-493c-a425-512b7d4cd26a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2056426182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.2056426182
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.783631582
Short name T803
Test name
Test status
Simulation time 231934309 ps
CPU time 4.35 seconds
Started Jun 10 07:50:55 PM PDT 24
Finished Jun 10 07:51:02 PM PDT 24
Peak memory 242264 kb
Host smart-51ba3faa-0b2b-4afc-8f47-6ccad5d9cef2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=783631582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.783631582
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.2508895687
Short name T639
Test name
Test status
Simulation time 220797686 ps
CPU time 3.97 seconds
Started Jun 10 07:50:53 PM PDT 24
Finished Jun 10 07:51:00 PM PDT 24
Peak memory 242296 kb
Host smart-fa3f6428-3d1c-4ccf-825a-465025bc0bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508895687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.2508895687
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.2948758755
Short name T251
Test name
Test status
Simulation time 6249787785 ps
CPU time 90.33 seconds
Started Jun 10 07:51:04 PM PDT 24
Finished Jun 10 07:52:37 PM PDT 24
Peak memory 249248 kb
Host smart-71fbe999-70fb-424c-831c-ef856cc1c8a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948758755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.2948758755
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.1810940470
Short name T951
Test name
Test status
Simulation time 644047886 ps
CPU time 15.81 seconds
Started Jun 10 07:51:09 PM PDT 24
Finished Jun 10 07:51:26 PM PDT 24
Peak memory 242744 kb
Host smart-899bc428-d208-43fe-a443-89fc7b583cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810940470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.1810940470
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.344940944
Short name T1191
Test name
Test status
Simulation time 201019682 ps
CPU time 3.67 seconds
Started Jun 10 07:53:20 PM PDT 24
Finished Jun 10 07:53:26 PM PDT 24
Peak memory 242492 kb
Host smart-8d82051c-b452-4a9c-8cb5-00139b0f9aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344940944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.344940944
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.78222632
Short name T582
Test name
Test status
Simulation time 217614862 ps
CPU time 3.49 seconds
Started Jun 10 07:53:19 PM PDT 24
Finished Jun 10 07:53:24 PM PDT 24
Peak memory 242604 kb
Host smart-487bc504-e7e3-42e1-94b1-ca7248b692f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78222632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.78222632
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.2493953847
Short name T463
Test name
Test status
Simulation time 247304498 ps
CPU time 3.31 seconds
Started Jun 10 07:53:16 PM PDT 24
Finished Jun 10 07:53:21 PM PDT 24
Peak memory 242348 kb
Host smart-510e1ac0-3de6-4a3e-9735-a147e029f394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493953847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.2493953847
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.4007580686
Short name T432
Test name
Test status
Simulation time 236000040 ps
CPU time 3.95 seconds
Started Jun 10 07:53:15 PM PDT 24
Finished Jun 10 07:53:21 PM PDT 24
Peak memory 242352 kb
Host smart-04b45c86-61c1-4c5b-9f8e-19a588c9d290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007580686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.4007580686
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.3788484416
Short name T47
Test name
Test status
Simulation time 480924389 ps
CPU time 4.55 seconds
Started Jun 10 07:53:18 PM PDT 24
Finished Jun 10 07:53:25 PM PDT 24
Peak memory 242372 kb
Host smart-abd02d07-0cc4-462a-95a1-c080c9722a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788484416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.3788484416
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.1466438969
Short name T643
Test name
Test status
Simulation time 191740029 ps
CPU time 4.03 seconds
Started Jun 10 07:53:21 PM PDT 24
Finished Jun 10 07:53:27 PM PDT 24
Peak memory 242300 kb
Host smart-51733bd3-9118-4fcd-bad1-7e84fb131202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466438969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.1466438969
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.2706080997
Short name T870
Test name
Test status
Simulation time 321563378 ps
CPU time 3.6 seconds
Started Jun 10 07:53:16 PM PDT 24
Finished Jun 10 07:53:22 PM PDT 24
Peak memory 242252 kb
Host smart-205d50e0-6548-4a8c-be50-c428b114dac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706080997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.2706080997
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.1019164222
Short name T920
Test name
Test status
Simulation time 1074405689 ps
CPU time 2.46 seconds
Started Jun 10 07:51:03 PM PDT 24
Finished Jun 10 07:51:08 PM PDT 24
Peak memory 240708 kb
Host smart-273774a3-735f-4084-925e-3aeecc37db6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019164222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.1019164222
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.3267797553
Short name T112
Test name
Test status
Simulation time 1531492368 ps
CPU time 13.69 seconds
Started Jun 10 07:51:04 PM PDT 24
Finished Jun 10 07:51:20 PM PDT 24
Peak memory 242852 kb
Host smart-bd76d4de-8c66-44ae-8935-67b45f47000b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267797553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.3267797553
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.763078841
Short name T980
Test name
Test status
Simulation time 829189853 ps
CPU time 24.28 seconds
Started Jun 10 07:51:11 PM PDT 24
Finished Jun 10 07:51:37 PM PDT 24
Peak memory 242284 kb
Host smart-8474d591-0964-4d6f-a752-268fe9474822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763078841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.763078841
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.916947859
Short name T1136
Test name
Test status
Simulation time 10953660156 ps
CPU time 18.34 seconds
Started Jun 10 07:51:05 PM PDT 24
Finished Jun 10 07:51:26 PM PDT 24
Peak memory 243232 kb
Host smart-fc7ed8b0-a3b3-4a70-a94b-383debf96a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916947859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.916947859
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.3783783031
Short name T962
Test name
Test status
Simulation time 264944938 ps
CPU time 4.99 seconds
Started Jun 10 07:51:03 PM PDT 24
Finished Jun 10 07:51:11 PM PDT 24
Peak memory 242472 kb
Host smart-2f515590-6edf-407d-8ba8-dec0ed6d82cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783783031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.3783783031
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.1878289272
Short name T1110
Test name
Test status
Simulation time 226024876 ps
CPU time 5.44 seconds
Started Jun 10 07:51:05 PM PDT 24
Finished Jun 10 07:51:14 PM PDT 24
Peak memory 242536 kb
Host smart-39ab4c70-0460-4dd8-ab42-837ca374e1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878289272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.1878289272
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.3437764409
Short name T587
Test name
Test status
Simulation time 10223649195 ps
CPU time 19 seconds
Started Jun 10 07:51:05 PM PDT 24
Finished Jun 10 07:51:26 PM PDT 24
Peak memory 243684 kb
Host smart-4821dec8-438d-459f-a8e0-ae90f37e80b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437764409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.3437764409
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.3906379318
Short name T605
Test name
Test status
Simulation time 2227880870 ps
CPU time 9.94 seconds
Started Jun 10 07:51:04 PM PDT 24
Finished Jun 10 07:51:16 PM PDT 24
Peak memory 242284 kb
Host smart-644bd9e1-7d01-4cd1-a293-ffc1ae508da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906379318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.3906379318
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.3519129740
Short name T798
Test name
Test status
Simulation time 812142799 ps
CPU time 12.97 seconds
Started Jun 10 07:51:05 PM PDT 24
Finished Jun 10 07:51:21 PM PDT 24
Peak memory 248968 kb
Host smart-3c5990b1-8bc9-4c45-bb7a-c1e512c01725
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3519129740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.3519129740
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.2924592509
Short name T373
Test name
Test status
Simulation time 236061119 ps
CPU time 6.39 seconds
Started Jun 10 07:51:05 PM PDT 24
Finished Jun 10 07:51:14 PM PDT 24
Peak memory 242504 kb
Host smart-de63be86-f9e4-4f24-8569-dbfa6fd4666f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2924592509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.2924592509
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.730901174
Short name T8
Test name
Test status
Simulation time 545439006 ps
CPU time 6.81 seconds
Started Jun 10 07:51:03 PM PDT 24
Finished Jun 10 07:51:12 PM PDT 24
Peak memory 242208 kb
Host smart-64f01cfd-9edf-4817-9b97-910fc9504724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730901174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.730901174
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.1014528090
Short name T98
Test name
Test status
Simulation time 12752960148 ps
CPU time 82.19 seconds
Started Jun 10 07:51:03 PM PDT 24
Finished Jun 10 07:52:28 PM PDT 24
Peak memory 257328 kb
Host smart-5a7d5e15-0bff-464a-95e5-ecb16345f63c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014528090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all
.1014528090
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.250042343
Short name T863
Test name
Test status
Simulation time 147581599915 ps
CPU time 1089.87 seconds
Started Jun 10 07:51:05 PM PDT 24
Finished Jun 10 08:09:18 PM PDT 24
Peak memory 340188 kb
Host smart-34654991-a673-49c9-ae22-d0d03a64e9b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250042343 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.250042343
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.3388312215
Short name T659
Test name
Test status
Simulation time 6009960265 ps
CPU time 38.74 seconds
Started Jun 10 07:51:03 PM PDT 24
Finished Jun 10 07:51:44 PM PDT 24
Peak memory 242496 kb
Host smart-4fdab4dd-269d-420c-8830-1ad312138270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388312215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.3388312215
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.3914535158
Short name T851
Test name
Test status
Simulation time 105122997 ps
CPU time 3.7 seconds
Started Jun 10 07:53:21 PM PDT 24
Finished Jun 10 07:53:27 PM PDT 24
Peak memory 242220 kb
Host smart-9c23dd11-c55b-4a15-b25e-20304c4b6d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914535158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.3914535158
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.1354016403
Short name T175
Test name
Test status
Simulation time 121018494 ps
CPU time 3.13 seconds
Started Jun 10 07:53:16 PM PDT 24
Finished Jun 10 07:53:22 PM PDT 24
Peak memory 242584 kb
Host smart-209695e5-ae86-4a26-8a08-4c572ac7668c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354016403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.1354016403
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.1157157335
Short name T1021
Test name
Test status
Simulation time 709462419 ps
CPU time 5.53 seconds
Started Jun 10 07:53:18 PM PDT 24
Finished Jun 10 07:53:26 PM PDT 24
Peak memory 242376 kb
Host smart-9fddc6b6-bf95-4930-b02e-23a864a84241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157157335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.1157157335
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.410702288
Short name T79
Test name
Test status
Simulation time 170228246 ps
CPU time 4.49 seconds
Started Jun 10 07:53:17 PM PDT 24
Finished Jun 10 07:53:24 PM PDT 24
Peak memory 242560 kb
Host smart-ef4aa62e-5f67-4435-a167-944d5032c030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410702288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.410702288
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.1947540071
Short name T514
Test name
Test status
Simulation time 126524707 ps
CPU time 4.11 seconds
Started Jun 10 07:53:18 PM PDT 24
Finished Jun 10 07:53:25 PM PDT 24
Peak memory 242376 kb
Host smart-1b14b349-be04-4b59-a7c8-dd9a970b1662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947540071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.1947540071
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.1933290766
Short name T478
Test name
Test status
Simulation time 312850496 ps
CPU time 5.65 seconds
Started Jun 10 07:53:16 PM PDT 24
Finished Jun 10 07:53:24 PM PDT 24
Peak memory 242316 kb
Host smart-2e53a529-cbf7-48d1-950c-0bf40d7d81af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933290766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.1933290766
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.1059180959
Short name T78
Test name
Test status
Simulation time 2684645131 ps
CPU time 6.33 seconds
Started Jun 10 07:53:20 PM PDT 24
Finished Jun 10 07:53:29 PM PDT 24
Peak memory 242680 kb
Host smart-8c1c9888-9d3a-4ca4-9c57-909011d356c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059180959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.1059180959
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.3436187886
Short name T821
Test name
Test status
Simulation time 275770682 ps
CPU time 3.92 seconds
Started Jun 10 07:53:18 PM PDT 24
Finished Jun 10 07:53:24 PM PDT 24
Peak memory 242360 kb
Host smart-7b06a45c-0353-4333-9525-4ecbf22c943b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436187886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.3436187886
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.121478666
Short name T211
Test name
Test status
Simulation time 103652667 ps
CPU time 3.85 seconds
Started Jun 10 07:53:19 PM PDT 24
Finished Jun 10 07:53:26 PM PDT 24
Peak memory 242580 kb
Host smart-f2227342-7d57-4d04-8d0a-dcd5bcf3fc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121478666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.121478666
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.1425066958
Short name T48
Test name
Test status
Simulation time 320365862 ps
CPU time 4.36 seconds
Started Jun 10 07:53:19 PM PDT 24
Finished Jun 10 07:53:25 PM PDT 24
Peak memory 242264 kb
Host smart-d25301d3-e79d-4656-aecf-4180d4ddddcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425066958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.1425066958
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.2608603190
Short name T534
Test name
Test status
Simulation time 274562726 ps
CPU time 1.92 seconds
Started Jun 10 07:51:04 PM PDT 24
Finished Jun 10 07:51:08 PM PDT 24
Peak memory 240764 kb
Host smart-c7d27e21-d9db-48d0-b80c-042d114c131d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608603190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.2608603190
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.1255796834
Short name T907
Test name
Test status
Simulation time 350921786 ps
CPU time 8.02 seconds
Started Jun 10 07:51:03 PM PDT 24
Finished Jun 10 07:51:14 PM PDT 24
Peak memory 242132 kb
Host smart-3aff62be-55d8-4a19-a6b0-27018873cfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255796834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.1255796834
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.1424554733
Short name T490
Test name
Test status
Simulation time 4413775828 ps
CPU time 38.15 seconds
Started Jun 10 07:51:09 PM PDT 24
Finished Jun 10 07:51:48 PM PDT 24
Peak memory 248052 kb
Host smart-ea321b85-1e7b-42c2-b5b6-628e64b219fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424554733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.1424554733
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.3613991994
Short name T686
Test name
Test status
Simulation time 389507700 ps
CPU time 9.95 seconds
Started Jun 10 07:51:05 PM PDT 24
Finished Jun 10 07:51:17 PM PDT 24
Peak memory 242084 kb
Host smart-a39507c1-eed0-41c5-939c-b5245e54b8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613991994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.3613991994
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.1603885281
Short name T86
Test name
Test status
Simulation time 625223516 ps
CPU time 4.79 seconds
Started Jun 10 07:51:03 PM PDT 24
Finished Jun 10 07:51:10 PM PDT 24
Peak memory 242356 kb
Host smart-7450cec8-78df-4a59-83ce-31c38b3a4dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603885281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.1603885281
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.759206893
Short name T880
Test name
Test status
Simulation time 413149273 ps
CPU time 5.85 seconds
Started Jun 10 07:51:03 PM PDT 24
Finished Jun 10 07:51:11 PM PDT 24
Peak memory 242168 kb
Host smart-1c11b335-e9bc-437d-9775-e4493ef3ae80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759206893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.759206893
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.1090393792
Short name T926
Test name
Test status
Simulation time 785404550 ps
CPU time 30.88 seconds
Started Jun 10 07:51:03 PM PDT 24
Finished Jun 10 07:51:36 PM PDT 24
Peak memory 242912 kb
Host smart-8a579d76-0890-4933-bd0e-6e7f9a0da6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090393792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.1090393792
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.238527891
Short name T407
Test name
Test status
Simulation time 1326450325 ps
CPU time 5.35 seconds
Started Jun 10 07:51:06 PM PDT 24
Finished Jun 10 07:51:14 PM PDT 24
Peak memory 241956 kb
Host smart-b107c61b-58db-484e-8802-f3850646edf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238527891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.238527891
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.812560000
Short name T1171
Test name
Test status
Simulation time 1188065997 ps
CPU time 9.8 seconds
Started Jun 10 07:51:03 PM PDT 24
Finished Jun 10 07:51:15 PM PDT 24
Peak memory 242160 kb
Host smart-247fd863-3012-4650-8514-8355b313f707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=812560000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.812560000
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.762496398
Short name T901
Test name
Test status
Simulation time 1133540643 ps
CPU time 11.49 seconds
Started Jun 10 07:51:04 PM PDT 24
Finished Jun 10 07:51:19 PM PDT 24
Peak memory 242344 kb
Host smart-63d35c10-87a5-47d2-adbc-7804b53488f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=762496398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.762496398
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.455035001
Short name T1103
Test name
Test status
Simulation time 2481587342 ps
CPU time 7.07 seconds
Started Jun 10 07:51:03 PM PDT 24
Finished Jun 10 07:51:12 PM PDT 24
Peak memory 242168 kb
Host smart-337e42cd-701d-4b73-be16-012fced10d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455035001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.455035001
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.2362181847
Short name T1020
Test name
Test status
Simulation time 4014651010 ps
CPU time 53.88 seconds
Started Jun 10 07:51:03 PM PDT 24
Finished Jun 10 07:51:59 PM PDT 24
Peak memory 244704 kb
Host smart-2ee59ff5-26e6-4e63-a5a6-af1c986330ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362181847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.2362181847
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.3078850829
Short name T853
Test name
Test status
Simulation time 101799330302 ps
CPU time 730.99 seconds
Started Jun 10 07:51:08 PM PDT 24
Finished Jun 10 08:03:21 PM PDT 24
Peak memory 305052 kb
Host smart-1cd4480b-ad72-4fbc-bcf2-61728aad5506
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078850829 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.3078850829
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.900979622
Short name T436
Test name
Test status
Simulation time 11571494222 ps
CPU time 40.69 seconds
Started Jun 10 07:51:05 PM PDT 24
Finished Jun 10 07:51:49 PM PDT 24
Peak memory 242340 kb
Host smart-861c58cb-a5d7-4bad-8d73-a651706e75ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900979622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.900979622
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.1185679768
Short name T528
Test name
Test status
Simulation time 227752413 ps
CPU time 3.46 seconds
Started Jun 10 07:53:18 PM PDT 24
Finished Jun 10 07:53:24 PM PDT 24
Peak memory 242180 kb
Host smart-1260f4f2-38f3-4272-a86c-0c171370d701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185679768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.1185679768
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.1106380310
Short name T998
Test name
Test status
Simulation time 127345321 ps
CPU time 4.1 seconds
Started Jun 10 07:53:19 PM PDT 24
Finished Jun 10 07:53:25 PM PDT 24
Peak memory 242252 kb
Host smart-8c85413c-4a1c-4239-8384-1f680ed029e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106380310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.1106380310
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.3106458080
Short name T135
Test name
Test status
Simulation time 122704493 ps
CPU time 3.29 seconds
Started Jun 10 07:53:16 PM PDT 24
Finished Jun 10 07:53:22 PM PDT 24
Peak memory 242540 kb
Host smart-0c49b6ea-beab-488e-91bd-8c99876191cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106458080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.3106458080
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.2519236658
Short name T457
Test name
Test status
Simulation time 338671367 ps
CPU time 4.52 seconds
Started Jun 10 07:53:18 PM PDT 24
Finished Jun 10 07:53:24 PM PDT 24
Peak memory 242396 kb
Host smart-360f8283-4ac3-4cd6-84c6-fcdc3c902098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519236658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.2519236658
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.1602858709
Short name T144
Test name
Test status
Simulation time 228266671 ps
CPU time 4.37 seconds
Started Jun 10 07:53:16 PM PDT 24
Finished Jun 10 07:53:23 PM PDT 24
Peak memory 242608 kb
Host smart-1dad4dc6-7bc7-4571-8b81-a833b4f08924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602858709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.1602858709
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.389835852
Short name T569
Test name
Test status
Simulation time 1808122516 ps
CPU time 4.36 seconds
Started Jun 10 07:53:17 PM PDT 24
Finished Jun 10 07:53:24 PM PDT 24
Peak memory 242540 kb
Host smart-4da19299-ea56-4c79-8018-eee11b463c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389835852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.389835852
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.4070470649
Short name T842
Test name
Test status
Simulation time 195039858 ps
CPU time 4.03 seconds
Started Jun 10 07:53:27 PM PDT 24
Finished Jun 10 07:53:33 PM PDT 24
Peak memory 242604 kb
Host smart-f7586060-2bae-4bcf-9296-743b3e6fd59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070470649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.4070470649
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.2273489565
Short name T993
Test name
Test status
Simulation time 122761797 ps
CPU time 5.25 seconds
Started Jun 10 07:53:27 PM PDT 24
Finished Jun 10 07:53:34 PM PDT 24
Peak memory 242500 kb
Host smart-16d60515-6dcc-4d08-8f34-d69853488fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273489565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.2273489565
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.879473767
Short name T1000
Test name
Test status
Simulation time 156587257 ps
CPU time 1.76 seconds
Started Jun 10 07:49:51 PM PDT 24
Finished Jun 10 07:49:56 PM PDT 24
Peak memory 241184 kb
Host smart-b5946371-3392-4062-9bc1-f336f3d937bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879473767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.879473767
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.89448926
Short name T480
Test name
Test status
Simulation time 239961299 ps
CPU time 8.35 seconds
Started Jun 10 07:49:53 PM PDT 24
Finished Jun 10 07:50:05 PM PDT 24
Peak memory 242244 kb
Host smart-0b4ccce3-1073-4045-8371-8d780e5f23c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89448926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.89448926
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.3620864939
Short name T1129
Test name
Test status
Simulation time 1830573712 ps
CPU time 13.69 seconds
Started Jun 10 07:49:52 PM PDT 24
Finished Jun 10 07:50:10 PM PDT 24
Peak memory 242972 kb
Host smart-2ed0b3df-5c57-453e-976c-ea723f59b78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620864939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.3620864939
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.219987290
Short name T740
Test name
Test status
Simulation time 14254045198 ps
CPU time 36.51 seconds
Started Jun 10 07:49:53 PM PDT 24
Finished Jun 10 07:50:33 PM PDT 24
Peak memory 245796 kb
Host smart-449eb559-e6cd-437f-ba5a-7dc4bd18e8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219987290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.219987290
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.1119271780
Short name T1092
Test name
Test status
Simulation time 12604400083 ps
CPU time 36.92 seconds
Started Jun 10 07:49:52 PM PDT 24
Finished Jun 10 07:50:33 PM PDT 24
Peak memory 243796 kb
Host smart-4369212d-ebb9-4773-b6ba-360a1504b0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119271780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.1119271780
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.1567517309
Short name T568
Test name
Test status
Simulation time 745479328 ps
CPU time 4.2 seconds
Started Jun 10 07:49:50 PM PDT 24
Finished Jun 10 07:49:58 PM PDT 24
Peak memory 241612 kb
Host smart-9f97279c-4134-4399-b9ce-dbe0f99645f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567517309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.1567517309
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.1168799840
Short name T929
Test name
Test status
Simulation time 1335322910 ps
CPU time 25.41 seconds
Started Jun 10 07:49:52 PM PDT 24
Finished Jun 10 07:50:21 PM PDT 24
Peak memory 246160 kb
Host smart-0f4b1ee3-534f-4137-8cae-e5da33088b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168799840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.1168799840
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.2719357944
Short name T466
Test name
Test status
Simulation time 409216841 ps
CPU time 6.52 seconds
Started Jun 10 07:49:53 PM PDT 24
Finished Jun 10 07:50:03 PM PDT 24
Peak memory 242148 kb
Host smart-4821f1b7-2197-4cef-b708-187384e1e5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719357944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.2719357944
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.4075991958
Short name T1055
Test name
Test status
Simulation time 1477609224 ps
CPU time 4.9 seconds
Started Jun 10 07:49:54 PM PDT 24
Finished Jun 10 07:50:02 PM PDT 24
Peak memory 242548 kb
Host smart-dfb4d128-fb07-4365-bb41-94181d3177ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075991958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.4075991958
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.1180851824
Short name T814
Test name
Test status
Simulation time 409493397 ps
CPU time 11.77 seconds
Started Jun 10 07:49:46 PM PDT 24
Finished Jun 10 07:50:01 PM PDT 24
Peak memory 242076 kb
Host smart-9f89cc92-d9bd-4a38-89f9-d986fd0e840f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180851824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.1180851824
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.4158053065
Short name T882
Test name
Test status
Simulation time 3445102245 ps
CPU time 9.04 seconds
Started Jun 10 07:49:52 PM PDT 24
Finished Jun 10 07:50:05 PM PDT 24
Peak memory 249160 kb
Host smart-54d4aa76-dc35-4a33-b42e-84276ff1f3e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4158053065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.4158053065
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.1213320746
Short name T884
Test name
Test status
Simulation time 1044795287 ps
CPU time 7.53 seconds
Started Jun 10 07:49:53 PM PDT 24
Finished Jun 10 07:50:04 PM PDT 24
Peak memory 242152 kb
Host smart-bf1e3bcf-cec8-45f2-9803-47b6d4b1dfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213320746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.1213320746
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.55653512
Short name T398
Test name
Test status
Simulation time 4991915449 ps
CPU time 48.82 seconds
Started Jun 10 07:49:52 PM PDT 24
Finished Jun 10 07:50:45 PM PDT 24
Peak memory 250552 kb
Host smart-c913c471-c233-4510-aafb-0470d18a74a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55653512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.55653512
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.3264938739
Short name T131
Test name
Test status
Simulation time 8880586631 ps
CPU time 45.1 seconds
Started Jun 10 07:49:53 PM PDT 24
Finished Jun 10 07:50:42 PM PDT 24
Peak memory 243508 kb
Host smart-ab045023-c61d-4fd1-a7a5-618faa43005b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264938739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.3264938739
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.2291422598
Short name T311
Test name
Test status
Simulation time 634924435 ps
CPU time 2.11 seconds
Started Jun 10 07:51:09 PM PDT 24
Finished Jun 10 07:51:12 PM PDT 24
Peak memory 240652 kb
Host smart-9ea447ac-01f6-4a51-8acd-e8c9dd75ba3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291422598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.2291422598
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.1518527510
Short name T111
Test name
Test status
Simulation time 4473937922 ps
CPU time 10.93 seconds
Started Jun 10 07:51:07 PM PDT 24
Finished Jun 10 07:51:20 PM PDT 24
Peak memory 243680 kb
Host smart-e15356eb-03cb-4f33-8fdb-d3185160b235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518527510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.1518527510
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.2328794469
Short name T213
Test name
Test status
Simulation time 2512163274 ps
CPU time 30.22 seconds
Started Jun 10 07:51:05 PM PDT 24
Finished Jun 10 07:51:38 PM PDT 24
Peak memory 244888 kb
Host smart-cd70edd9-d263-4e7e-af0a-ac5d4b241c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328794469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.2328794469
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.3287358705
Short name T1076
Test name
Test status
Simulation time 390939653 ps
CPU time 3.41 seconds
Started Jun 10 07:51:04 PM PDT 24
Finished Jun 10 07:51:10 PM PDT 24
Peak memory 242256 kb
Host smart-a578b7c0-984f-4c34-b96d-fe5809b95091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287358705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.3287358705
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.2739891056
Short name T754
Test name
Test status
Simulation time 217368978 ps
CPU time 5.02 seconds
Started Jun 10 07:51:05 PM PDT 24
Finished Jun 10 07:51:13 PM PDT 24
Peak memory 242312 kb
Host smart-157552d7-9519-4fc5-ad20-ca6ed9b77bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739891056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.2739891056
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.2494838080
Short name T776
Test name
Test status
Simulation time 1593909210 ps
CPU time 21.59 seconds
Started Jun 10 07:51:06 PM PDT 24
Finished Jun 10 07:51:30 PM PDT 24
Peak memory 242572 kb
Host smart-3b5f73c5-fc4a-45db-be7f-4f7433f9bf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494838080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.2494838080
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.3388118763
Short name T188
Test name
Test status
Simulation time 477229207 ps
CPU time 6.67 seconds
Started Jun 10 07:51:02 PM PDT 24
Finished Jun 10 07:51:12 PM PDT 24
Peak memory 242520 kb
Host smart-b1a28eab-3a9d-4b7b-b393-f1bbaa0522b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388118763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.3388118763
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.3569812055
Short name T692
Test name
Test status
Simulation time 1338189705 ps
CPU time 21.82 seconds
Started Jun 10 07:51:06 PM PDT 24
Finished Jun 10 07:51:30 PM PDT 24
Peak memory 242224 kb
Host smart-3c2f7728-cef9-43e7-bee6-b37ff8db8b9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3569812055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.3569812055
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.3549200494
Short name T1026
Test name
Test status
Simulation time 641074715 ps
CPU time 7.96 seconds
Started Jun 10 07:51:03 PM PDT 24
Finished Jun 10 07:51:14 PM PDT 24
Peak memory 242496 kb
Host smart-6bf2ce9e-1179-4d25-8f92-244d9f836771
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3549200494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.3549200494
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.1493483641
Short name T1033
Test name
Test status
Simulation time 155167379 ps
CPU time 4.63 seconds
Started Jun 10 07:51:04 PM PDT 24
Finished Jun 10 07:51:11 PM PDT 24
Peak memory 242000 kb
Host smart-614d811b-b45a-4013-ae26-f575364fe12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493483641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.1493483641
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.4131664251
Short name T249
Test name
Test status
Simulation time 34233896409 ps
CPU time 139.85 seconds
Started Jun 10 07:51:09 PM PDT 24
Finished Jun 10 07:53:30 PM PDT 24
Peak memory 273668 kb
Host smart-798dd229-1d2b-4cf0-b2a3-7ff29577320c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131664251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all
.4131664251
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.2965660986
Short name T132
Test name
Test status
Simulation time 11195047690 ps
CPU time 29.15 seconds
Started Jun 10 07:51:05 PM PDT 24
Finished Jun 10 07:51:37 PM PDT 24
Peak memory 243728 kb
Host smart-f26637c3-3c60-4f62-90c4-d45d531fbdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965660986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.2965660986
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.1227655381
Short name T475
Test name
Test status
Simulation time 192417818 ps
CPU time 2.23 seconds
Started Jun 10 07:51:14 PM PDT 24
Finished Jun 10 07:51:18 PM PDT 24
Peak memory 240856 kb
Host smart-559703a1-a44f-4167-8647-c7c93aeb6b93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227655381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.1227655381
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.184232025
Short name T80
Test name
Test status
Simulation time 1574754092 ps
CPU time 24.29 seconds
Started Jun 10 07:51:17 PM PDT 24
Finished Jun 10 07:51:44 PM PDT 24
Peak memory 249040 kb
Host smart-855912f1-8dbd-4bbf-9744-4461af6ee8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184232025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.184232025
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.2582605250
Short name T1071
Test name
Test status
Simulation time 1623532975 ps
CPU time 18.81 seconds
Started Jun 10 07:51:16 PM PDT 24
Finished Jun 10 07:51:37 PM PDT 24
Peak memory 242380 kb
Host smart-72f7e094-c264-46ed-baf7-44b74c1c1438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582605250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.2582605250
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.3197149644
Short name T4
Test name
Test status
Simulation time 209275366 ps
CPU time 3.3 seconds
Started Jun 10 07:51:09 PM PDT 24
Finished Jun 10 07:51:14 PM PDT 24
Peak memory 242436 kb
Host smart-e2fa7a9b-d72d-4fd7-9aad-7afa4dee8f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197149644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.3197149644
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.2065786328
Short name T170
Test name
Test status
Simulation time 331787036 ps
CPU time 4.92 seconds
Started Jun 10 07:51:05 PM PDT 24
Finished Jun 10 07:51:13 PM PDT 24
Peak memory 242524 kb
Host smart-2c3df129-6a74-4eb3-9a12-090d9d6bfe7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065786328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.2065786328
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.2355238150
Short name T1046
Test name
Test status
Simulation time 678088644 ps
CPU time 24.55 seconds
Started Jun 10 07:51:15 PM PDT 24
Finished Jun 10 07:51:42 PM PDT 24
Peak memory 242328 kb
Host smart-46a991ff-ff9e-421d-bc21-5d55cfdf5712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355238150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.2355238150
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.2466543194
Short name T1001
Test name
Test status
Simulation time 205525253 ps
CPU time 3.18 seconds
Started Jun 10 07:51:11 PM PDT 24
Finished Jun 10 07:51:16 PM PDT 24
Peak memory 242176 kb
Host smart-05bc863d-ced2-497d-841a-2236b911e854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466543194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.2466543194
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.1980707618
Short name T779
Test name
Test status
Simulation time 1992680347 ps
CPU time 17.42 seconds
Started Jun 10 07:51:05 PM PDT 24
Finished Jun 10 07:51:26 PM PDT 24
Peak memory 248704 kb
Host smart-d50892ad-4557-48c1-91b8-9ef908d981a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1980707618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.1980707618
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.13456184
Short name T647
Test name
Test status
Simulation time 525003243 ps
CPU time 12.91 seconds
Started Jun 10 07:51:16 PM PDT 24
Finished Jun 10 07:51:31 PM PDT 24
Peak memory 242320 kb
Host smart-8e10fa85-4f6e-4145-a9be-2a62b18f7c94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=13456184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.13456184
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.3056347255
Short name T465
Test name
Test status
Simulation time 354319509 ps
CPU time 5.17 seconds
Started Jun 10 07:51:05 PM PDT 24
Finished Jun 10 07:51:13 PM PDT 24
Peak memory 242244 kb
Host smart-d7af4608-041a-4cf7-9d51-213717088c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056347255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.3056347255
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.1908012598
Short name T1164
Test name
Test status
Simulation time 11186780105 ps
CPU time 205.04 seconds
Started Jun 10 07:51:14 PM PDT 24
Finished Jun 10 07:54:41 PM PDT 24
Peak memory 259292 kb
Host smart-ac0e8269-635c-421b-af5a-f13fbcbcf0c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908012598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.1908012598
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.2062966466
Short name T245
Test name
Test status
Simulation time 299822664185 ps
CPU time 2134.05 seconds
Started Jun 10 07:51:16 PM PDT 24
Finished Jun 10 08:26:53 PM PDT 24
Peak memory 313388 kb
Host smart-61f66a4d-52d1-45fa-8985-fb0ce47df515
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062966466 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.2062966466
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.1520858994
Short name T183
Test name
Test status
Simulation time 4101207889 ps
CPU time 40.02 seconds
Started Jun 10 07:51:14 PM PDT 24
Finished Jun 10 07:51:56 PM PDT 24
Peak memory 242228 kb
Host smart-5664d6c3-53cb-4a92-a73c-fd58e86fdbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520858994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.1520858994
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.2170893187
Short name T1160
Test name
Test status
Simulation time 60961096 ps
CPU time 1.88 seconds
Started Jun 10 07:51:14 PM PDT 24
Finished Jun 10 07:51:18 PM PDT 24
Peak memory 241216 kb
Host smart-38acfa98-9c24-4bb5-99a7-3a502feb234f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170893187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.2170893187
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.1682171328
Short name T877
Test name
Test status
Simulation time 244664125 ps
CPU time 3.59 seconds
Started Jun 10 07:51:16 PM PDT 24
Finished Jun 10 07:51:22 PM PDT 24
Peak memory 242184 kb
Host smart-4bf2ec8b-76b4-4a83-918f-04707c85b687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682171328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.1682171328
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.2703165220
Short name T945
Test name
Test status
Simulation time 187500991 ps
CPU time 8.82 seconds
Started Jun 10 07:51:15 PM PDT 24
Finished Jun 10 07:51:26 PM PDT 24
Peak memory 242360 kb
Host smart-4a78de5d-c2a4-4a49-b4f6-2eff62890d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703165220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.2703165220
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.3051193323
Short name T735
Test name
Test status
Simulation time 1005159234 ps
CPU time 37.26 seconds
Started Jun 10 07:51:17 PM PDT 24
Finished Jun 10 07:51:56 PM PDT 24
Peak memory 242620 kb
Host smart-c526f096-bce7-4c61-803d-3ecc81a31a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051193323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.3051193323
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.570894074
Short name T554
Test name
Test status
Simulation time 210327685 ps
CPU time 3.75 seconds
Started Jun 10 07:51:15 PM PDT 24
Finished Jun 10 07:51:21 PM PDT 24
Peak memory 242160 kb
Host smart-fdc428a2-bab8-45e2-b748-6e70c1be6ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570894074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.570894074
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.1275941810
Short name T454
Test name
Test status
Simulation time 5182732866 ps
CPU time 9.96 seconds
Started Jun 10 07:51:15 PM PDT 24
Finished Jun 10 07:51:27 PM PDT 24
Peak memory 249076 kb
Host smart-d8250036-8531-4e81-8b68-8c17e6a4840e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275941810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.1275941810
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.1388659544
Short name T856
Test name
Test status
Simulation time 6316829101 ps
CPU time 21.02 seconds
Started Jun 10 07:51:14 PM PDT 24
Finished Jun 10 07:51:37 PM PDT 24
Peak memory 243316 kb
Host smart-f8504e8b-14c2-472d-af4f-c8eb0d938355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388659544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.1388659544
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.1722395443
Short name T690
Test name
Test status
Simulation time 695727397 ps
CPU time 16.13 seconds
Started Jun 10 07:51:16 PM PDT 24
Finished Jun 10 07:51:34 PM PDT 24
Peak memory 242508 kb
Host smart-5886e4a1-906e-4a92-9437-6b4a1247ff59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722395443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.1722395443
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.3640795778
Short name T675
Test name
Test status
Simulation time 2732352191 ps
CPU time 17.45 seconds
Started Jun 10 07:51:15 PM PDT 24
Finished Jun 10 07:51:34 PM PDT 24
Peak memory 242264 kb
Host smart-8a7e5a47-8ca6-43e9-ace1-06256e23e735
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640795778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.3640795778
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.1861147483
Short name T312
Test name
Test status
Simulation time 112534042 ps
CPU time 4.33 seconds
Started Jun 10 07:51:15 PM PDT 24
Finished Jun 10 07:51:22 PM PDT 24
Peak memory 242148 kb
Host smart-1ce63da3-14c9-43f1-b8ff-8c1150b14b96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1861147483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.1861147483
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.3269579383
Short name T768
Test name
Test status
Simulation time 202347462 ps
CPU time 6.77 seconds
Started Jun 10 07:51:15 PM PDT 24
Finished Jun 10 07:51:24 PM PDT 24
Peak memory 242500 kb
Host smart-419c7e58-1b3f-41f9-960a-c5b5ea305b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269579383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.3269579383
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.14781924
Short name T665
Test name
Test status
Simulation time 4360176356 ps
CPU time 26.51 seconds
Started Jun 10 07:51:16 PM PDT 24
Finished Jun 10 07:51:45 PM PDT 24
Peak memory 249044 kb
Host smart-d1027a8c-be14-4669-b66c-980b384bfa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14781924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.14781924
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.2567894573
Short name T913
Test name
Test status
Simulation time 85243645 ps
CPU time 1.73 seconds
Started Jun 10 07:51:18 PM PDT 24
Finished Jun 10 07:51:22 PM PDT 24
Peak memory 241160 kb
Host smart-eb54f0b8-79ce-4661-a857-428f00088982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567894573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.2567894573
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.3574204062
Short name T750
Test name
Test status
Simulation time 578443695 ps
CPU time 18.1 seconds
Started Jun 10 07:51:14 PM PDT 24
Finished Jun 10 07:51:34 PM PDT 24
Peak memory 242108 kb
Host smart-76b91db6-bf7b-4ed0-8d93-4a311f18b234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574204062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.3574204062
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.2209038252
Short name T653
Test name
Test status
Simulation time 4990320630 ps
CPU time 10.28 seconds
Started Jun 10 07:51:16 PM PDT 24
Finished Jun 10 07:51:29 PM PDT 24
Peak memory 242176 kb
Host smart-209c9866-d8cb-400c-8eeb-9f014247a6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209038252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.2209038252
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.2821520454
Short name T41
Test name
Test status
Simulation time 195581344 ps
CPU time 4.51 seconds
Started Jun 10 07:51:16 PM PDT 24
Finished Jun 10 07:51:23 PM PDT 24
Peak memory 242412 kb
Host smart-7cdefee5-bba9-4880-b381-fcad3c02515f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821520454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.2821520454
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.1960491134
Short name T732
Test name
Test status
Simulation time 6628454578 ps
CPU time 17.24 seconds
Started Jun 10 07:51:17 PM PDT 24
Finished Jun 10 07:51:37 PM PDT 24
Peak memory 242864 kb
Host smart-cb947c0e-fc8b-4fcf-a316-66e6bf57df49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960491134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.1960491134
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.3113233961
Short name T391
Test name
Test status
Simulation time 628634880 ps
CPU time 13.98 seconds
Started Jun 10 07:51:16 PM PDT 24
Finished Jun 10 07:51:33 PM PDT 24
Peak memory 242616 kb
Host smart-2140e574-2c28-4719-8202-434c958aa098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113233961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.3113233961
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.2141955836
Short name T835
Test name
Test status
Simulation time 523778215 ps
CPU time 7.1 seconds
Started Jun 10 07:51:16 PM PDT 24
Finished Jun 10 07:51:25 PM PDT 24
Peak memory 242312 kb
Host smart-1aa8b5c4-0cc6-4f5b-ae90-88654ab5d9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141955836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.2141955836
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.2454902924
Short name T633
Test name
Test status
Simulation time 181584497 ps
CPU time 5.19 seconds
Started Jun 10 07:51:16 PM PDT 24
Finished Jun 10 07:51:24 PM PDT 24
Peak memory 242108 kb
Host smart-46b3b9a0-5fd6-463d-8f82-e18091d68200
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2454902924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.2454902924
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.2063537017
Short name T964
Test name
Test status
Simulation time 171050928 ps
CPU time 6.22 seconds
Started Jun 10 07:51:17 PM PDT 24
Finished Jun 10 07:51:26 PM PDT 24
Peak memory 242196 kb
Host smart-d4f669e9-9d20-4c25-b98b-d03fa6e3dcca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2063537017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.2063537017
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.4156497800
Short name T417
Test name
Test status
Simulation time 394743863 ps
CPU time 5.13 seconds
Started Jun 10 07:51:17 PM PDT 24
Finished Jun 10 07:51:25 PM PDT 24
Peak memory 248044 kb
Host smart-6e706159-a890-4e5f-bf77-d87c069b8bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156497800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.4156497800
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.1647465971
Short name T1034
Test name
Test status
Simulation time 21723955561 ps
CPU time 77.29 seconds
Started Jun 10 07:51:19 PM PDT 24
Finished Jun 10 07:52:38 PM PDT 24
Peak memory 247520 kb
Host smart-97e74231-0e7e-4a6a-8245-5afa41ec641e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647465971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.1647465971
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.1388313296
Short name T291
Test name
Test status
Simulation time 3048023614 ps
CPU time 34.97 seconds
Started Jun 10 07:51:16 PM PDT 24
Finished Jun 10 07:51:53 PM PDT 24
Peak memory 242316 kb
Host smart-e3f9c51b-d3e2-4e85-b740-c0d284614848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388313296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.1388313296
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.3963666619
Short name T535
Test name
Test status
Simulation time 65510683 ps
CPU time 1.9 seconds
Started Jun 10 07:51:17 PM PDT 24
Finished Jun 10 07:51:22 PM PDT 24
Peak memory 240836 kb
Host smart-950c21a0-2b10-44c5-b45a-e64502b41f26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963666619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.3963666619
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.1333179169
Short name T73
Test name
Test status
Simulation time 11160601846 ps
CPU time 27.18 seconds
Started Jun 10 07:51:19 PM PDT 24
Finished Jun 10 07:51:48 PM PDT 24
Peak memory 242332 kb
Host smart-b6c8f5c7-9b36-4077-8bef-2d0951218d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333179169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.1333179169
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.3419857625
Short name T1102
Test name
Test status
Simulation time 171538485 ps
CPU time 9.74 seconds
Started Jun 10 07:51:19 PM PDT 24
Finished Jun 10 07:51:31 PM PDT 24
Peak memory 242380 kb
Host smart-682a07db-1494-4f6d-b2ab-f4d005ae7a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419857625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.3419857625
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.2788872132
Short name T813
Test name
Test status
Simulation time 2546791153 ps
CPU time 21.74 seconds
Started Jun 10 07:51:12 PM PDT 24
Finished Jun 10 07:51:35 PM PDT 24
Peak memory 243324 kb
Host smart-c064c5ac-74d4-4e6c-9b3e-bfea3a01708c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788872132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.2788872132
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.627364176
Short name T563
Test name
Test status
Simulation time 171798627 ps
CPU time 4.7 seconds
Started Jun 10 07:51:18 PM PDT 24
Finished Jun 10 07:51:25 PM PDT 24
Peak memory 241692 kb
Host smart-55f8cc96-16de-45a7-a9e6-1c01a1ebe4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627364176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.627364176
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.1338810072
Short name T922
Test name
Test status
Simulation time 2831004711 ps
CPU time 35.06 seconds
Started Jun 10 07:51:16 PM PDT 24
Finished Jun 10 07:51:54 PM PDT 24
Peak memory 249164 kb
Host smart-5d84ed33-a1e1-4c8d-8abc-745678082620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338810072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.1338810072
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.3108071282
Short name T1029
Test name
Test status
Simulation time 1612874589 ps
CPU time 37.14 seconds
Started Jun 10 07:51:14 PM PDT 24
Finished Jun 10 07:51:53 PM PDT 24
Peak memory 242828 kb
Host smart-6d8225be-f82e-46a4-8486-735f9d28314c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108071282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.3108071282
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.125064987
Short name T578
Test name
Test status
Simulation time 2245496259 ps
CPU time 5.12 seconds
Started Jun 10 07:51:18 PM PDT 24
Finished Jun 10 07:51:25 PM PDT 24
Peak memory 241600 kb
Host smart-dbf63229-d7a7-43d0-8ee0-3d8d6b9067af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125064987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.125064987
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.3831259415
Short name T634
Test name
Test status
Simulation time 1430872183 ps
CPU time 23.57 seconds
Started Jun 10 07:51:17 PM PDT 24
Finished Jun 10 07:51:43 PM PDT 24
Peak memory 242508 kb
Host smart-13178d61-41b1-41b5-a7a8-7be744c0b86b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3831259415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.3831259415
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.3491332093
Short name T362
Test name
Test status
Simulation time 261841105 ps
CPU time 4.97 seconds
Started Jun 10 07:51:17 PM PDT 24
Finished Jun 10 07:51:25 PM PDT 24
Peak memory 242440 kb
Host smart-922278b8-399e-42a4-a2b0-882398f13fd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3491332093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.3491332093
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.64789732
Short name T761
Test name
Test status
Simulation time 409413320 ps
CPU time 9.62 seconds
Started Jun 10 07:51:16 PM PDT 24
Finished Jun 10 07:51:28 PM PDT 24
Peak memory 242312 kb
Host smart-a95b1551-3210-45fd-b273-edb02245e4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64789732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.64789732
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.2098012841
Short name T787
Test name
Test status
Simulation time 6616991068 ps
CPU time 41.91 seconds
Started Jun 10 07:51:19 PM PDT 24
Finished Jun 10 07:52:03 PM PDT 24
Peak memory 244152 kb
Host smart-85776836-4f6a-4280-8220-e7157afab812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098012841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.2098012841
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.1301444719
Short name T95
Test name
Test status
Simulation time 112938532003 ps
CPU time 2609.72 seconds
Started Jun 10 07:51:19 PM PDT 24
Finished Jun 10 08:34:51 PM PDT 24
Peak memory 280320 kb
Host smart-18f81d89-5792-41a0-8789-2dc63a87fa5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301444719 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.1301444719
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.2357181066
Short name T879
Test name
Test status
Simulation time 750706408 ps
CPU time 12.86 seconds
Started Jun 10 07:51:19 PM PDT 24
Finished Jun 10 07:51:34 PM PDT 24
Peak memory 242224 kb
Host smart-2bc65dd2-36b6-424b-8480-89708cbc1145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357181066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.2357181066
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.1665260257
Short name T694
Test name
Test status
Simulation time 561013103 ps
CPU time 1.98 seconds
Started Jun 10 07:51:30 PM PDT 24
Finished Jun 10 07:51:36 PM PDT 24
Peak memory 240796 kb
Host smart-ed6f994a-8383-444a-a64a-402f372086e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665260257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.1665260257
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.584612230
Short name T896
Test name
Test status
Simulation time 5250318995 ps
CPU time 25.69 seconds
Started Jun 10 07:51:31 PM PDT 24
Finished Jun 10 07:52:00 PM PDT 24
Peak memory 245144 kb
Host smart-5acce1c0-4edf-44ff-827f-8dd4d19c85d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584612230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.584612230
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.3180204759
Short name T888
Test name
Test status
Simulation time 5063767037 ps
CPU time 23.3 seconds
Started Jun 10 07:51:30 PM PDT 24
Finished Jun 10 07:51:56 PM PDT 24
Peak memory 242844 kb
Host smart-69bacff8-dc66-457b-ab02-f21b27131704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180204759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.3180204759
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.219509697
Short name T574
Test name
Test status
Simulation time 1050998769 ps
CPU time 17.59 seconds
Started Jun 10 07:51:22 PM PDT 24
Finished Jun 10 07:51:41 PM PDT 24
Peak memory 242652 kb
Host smart-70b1e72e-8223-4df6-80ab-684de2e99faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219509697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.219509697
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.692566596
Short name T1099
Test name
Test status
Simulation time 178471366 ps
CPU time 4.11 seconds
Started Jun 10 07:51:18 PM PDT 24
Finished Jun 10 07:51:25 PM PDT 24
Peak memory 242276 kb
Host smart-e1d28f7a-adf1-4eb2-8fb2-f00979ad90ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692566596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.692566596
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.106739281
Short name T482
Test name
Test status
Simulation time 8681610194 ps
CPU time 33.26 seconds
Started Jun 10 07:51:30 PM PDT 24
Finished Jun 10 07:52:06 PM PDT 24
Peak memory 245896 kb
Host smart-81c3e8be-6ccc-439b-8c39-f16accd98a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106739281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.106739281
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.104474978
Short name T923
Test name
Test status
Simulation time 4771748506 ps
CPU time 31.83 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:52:04 PM PDT 24
Peak memory 242720 kb
Host smart-de9f9ba9-f8c2-4cee-956e-51f96a167a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104474978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.104474978
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.4266491279
Short name T780
Test name
Test status
Simulation time 4666153451 ps
CPU time 15.26 seconds
Started Jun 10 07:51:16 PM PDT 24
Finished Jun 10 07:51:34 PM PDT 24
Peak memory 242384 kb
Host smart-9758e57a-779c-4b81-8998-cdc0b735a4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266491279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.4266491279
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.443759776
Short name T96
Test name
Test status
Simulation time 1753997394 ps
CPU time 25.26 seconds
Started Jun 10 07:51:18 PM PDT 24
Finished Jun 10 07:51:45 PM PDT 24
Peak memory 242476 kb
Host smart-261020e2-2d02-4052-8885-ef1d23457ecb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=443759776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.443759776
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.2763643308
Short name T464
Test name
Test status
Simulation time 588218641 ps
CPU time 7.46 seconds
Started Jun 10 07:51:17 PM PDT 24
Finished Jun 10 07:51:27 PM PDT 24
Peak memory 242148 kb
Host smart-6b5124e1-01ca-4528-bc22-eefa09604597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763643308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.2763643308
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.2978973266
Short name T1100
Test name
Test status
Simulation time 155096511446 ps
CPU time 2602.83 seconds
Started Jun 10 07:51:32 PM PDT 24
Finished Jun 10 08:34:58 PM PDT 24
Peak memory 545948 kb
Host smart-939c0113-dc7b-468a-b8cd-53b7ba7d642e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978973266 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.2978973266
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.1147658160
Short name T402
Test name
Test status
Simulation time 250471462 ps
CPU time 4.75 seconds
Started Jun 10 07:51:28 PM PDT 24
Finished Jun 10 07:51:34 PM PDT 24
Peak memory 242132 kb
Host smart-86843130-628f-4fb1-bd70-f4adcd2ef3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147658160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.1147658160
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.1331731330
Short name T93
Test name
Test status
Simulation time 200886900 ps
CPU time 2 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:51:33 PM PDT 24
Peak memory 241164 kb
Host smart-85b4af84-69b7-4896-b127-836990cdebbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331731330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.1331731330
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.2935250638
Short name T444
Test name
Test status
Simulation time 804183918 ps
CPU time 24.71 seconds
Started Jun 10 07:51:30 PM PDT 24
Finished Jun 10 07:51:58 PM PDT 24
Peak memory 242656 kb
Host smart-df3aae66-35a3-44f9-86b2-0c27f21d6dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935250638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.2935250638
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.1454654907
Short name T864
Test name
Test status
Simulation time 6159432424 ps
CPU time 19.92 seconds
Started Jun 10 07:51:30 PM PDT 24
Finished Jun 10 07:51:53 PM PDT 24
Peak memory 243572 kb
Host smart-e1efe26a-f63b-4447-9ac9-f644fb50d1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454654907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.1454654907
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.60625164
Short name T193
Test name
Test status
Simulation time 504657183 ps
CPU time 3.25 seconds
Started Jun 10 07:51:30 PM PDT 24
Finished Jun 10 07:51:36 PM PDT 24
Peak memory 242280 kb
Host smart-03990233-95a3-48dc-9cb8-8f93461e26fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60625164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.60625164
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.244975487
Short name T558
Test name
Test status
Simulation time 1813994186 ps
CPU time 18.26 seconds
Started Jun 10 07:51:31 PM PDT 24
Finished Jun 10 07:51:52 PM PDT 24
Peak memory 244568 kb
Host smart-bc3c3197-511d-4b9a-9651-a9fe5993f421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244975487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.244975487
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.429921239
Short name T547
Test name
Test status
Simulation time 1393124358 ps
CPU time 31.93 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:52:04 PM PDT 24
Peak memory 242308 kb
Host smart-537cf23e-3744-404b-9353-be88b96d756e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429921239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.429921239
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.2074365008
Short name T459
Test name
Test status
Simulation time 465116766 ps
CPU time 6.79 seconds
Started Jun 10 07:51:33 PM PDT 24
Finished Jun 10 07:51:43 PM PDT 24
Peak memory 242272 kb
Host smart-54f886df-9a48-4a0d-8c2c-ef04549490f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074365008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.2074365008
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.2145518007
Short name T165
Test name
Test status
Simulation time 197378622 ps
CPU time 5.86 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:51:37 PM PDT 24
Peak memory 242052 kb
Host smart-d3cfa31f-f975-4ae8-8c68-f78b99a05567
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2145518007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.2145518007
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.3023360281
Short name T294
Test name
Test status
Simulation time 4169397571 ps
CPU time 9.01 seconds
Started Jun 10 07:51:31 PM PDT 24
Finished Jun 10 07:51:43 PM PDT 24
Peak memory 242264 kb
Host smart-e76624df-c8af-4689-acd2-4cd72ce802f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3023360281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.3023360281
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.2789650549
Short name T991
Test name
Test status
Simulation time 129546931 ps
CPU time 4.58 seconds
Started Jun 10 07:51:28 PM PDT 24
Finished Jun 10 07:51:34 PM PDT 24
Peak memory 242200 kb
Host smart-b7c71618-43d0-4c56-aefe-16758258a2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789650549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.2789650549
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.598434990
Short name T546
Test name
Test status
Simulation time 33854393288 ps
CPU time 185.6 seconds
Started Jun 10 07:51:33 PM PDT 24
Finished Jun 10 07:54:41 PM PDT 24
Peak memory 259572 kb
Host smart-68651486-c316-4414-965e-3373fc0dec14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598434990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.
598434990
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.3624299080
Short name T1080
Test name
Test status
Simulation time 69698999370 ps
CPU time 434.57 seconds
Started Jun 10 07:51:28 PM PDT 24
Finished Jun 10 07:58:45 PM PDT 24
Peak memory 263888 kb
Host smart-f34541e7-0c7c-4a0f-9ebd-73c9f3887831
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624299080 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.3624299080
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.434556159
Short name T642
Test name
Test status
Simulation time 10605058609 ps
CPU time 28.83 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:52:00 PM PDT 24
Peak memory 242252 kb
Host smart-b536ee70-7d35-4d15-a8f1-37c9f547e74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434556159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.434556159
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.995353945
Short name T785
Test name
Test status
Simulation time 59444484 ps
CPU time 1.77 seconds
Started Jun 10 07:51:28 PM PDT 24
Finished Jun 10 07:51:32 PM PDT 24
Peak memory 240704 kb
Host smart-82f56cd4-3772-4eb5-a12a-14e752f955b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995353945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.995353945
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.2489322821
Short name T832
Test name
Test status
Simulation time 552381192 ps
CPU time 13.77 seconds
Started Jun 10 07:51:31 PM PDT 24
Finished Jun 10 07:51:48 PM PDT 24
Peak memory 242260 kb
Host smart-506aba9d-f463-44eb-a251-159f173b0f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489322821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.2489322821
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.1159256630
Short name T100
Test name
Test status
Simulation time 1461503180 ps
CPU time 24.36 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:51:56 PM PDT 24
Peak memory 242844 kb
Host smart-8690d8fb-0203-4009-bea2-938c231e53f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159256630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.1159256630
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.2718697350
Short name T970
Test name
Test status
Simulation time 206922703 ps
CPU time 4.77 seconds
Started Jun 10 07:51:31 PM PDT 24
Finished Jun 10 07:51:39 PM PDT 24
Peak memory 242352 kb
Host smart-46e169b3-9ddb-48bd-bd73-78c30404f6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718697350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.2718697350
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.1010301427
Short name T186
Test name
Test status
Simulation time 156759847 ps
CPU time 3.17 seconds
Started Jun 10 07:51:31 PM PDT 24
Finished Jun 10 07:51:38 PM PDT 24
Peak memory 242304 kb
Host smart-e0892cd2-0897-440b-91ef-487ebeecf62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010301427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.1010301427
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.2371998541
Short name T930
Test name
Test status
Simulation time 1010818712 ps
CPU time 32.36 seconds
Started Jun 10 07:51:31 PM PDT 24
Finished Jun 10 07:52:07 PM PDT 24
Peak memory 242444 kb
Host smart-f7a1c653-f22c-4eaf-a215-58a6998cbe58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371998541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.2371998541
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.969374915
Short name T806
Test name
Test status
Simulation time 402240140 ps
CPU time 4.62 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:51:36 PM PDT 24
Peak memory 242496 kb
Host smart-f110df96-772c-40f4-8948-6627c61853f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969374915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.969374915
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.1871461063
Short name T1163
Test name
Test status
Simulation time 1026499843 ps
CPU time 19.42 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:51:50 PM PDT 24
Peak memory 242112 kb
Host smart-c987ded5-9658-4494-9228-7f0dcb59e63b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1871461063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.1871461063
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.1991724624
Short name T702
Test name
Test status
Simulation time 599603303 ps
CPU time 5.82 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:51:38 PM PDT 24
Peak memory 242248 kb
Host smart-a9d95a4a-c29e-45a8-a2a9-ec97e5d9cee8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1991724624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.1991724624
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.2430630838
Short name T103
Test name
Test status
Simulation time 258726122 ps
CPU time 6.21 seconds
Started Jun 10 07:51:30 PM PDT 24
Finished Jun 10 07:51:39 PM PDT 24
Peak memory 242140 kb
Host smart-c54786fa-8863-49e6-abdf-e7688c40cf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430630838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.2430630838
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.226631146
Short name T1028
Test name
Test status
Simulation time 12251237448 ps
CPU time 137.7 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:53:49 PM PDT 24
Peak memory 260748 kb
Host smart-9a787f13-aa0d-4bfb-9166-77e998596442
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226631146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.
226631146
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.1396743949
Short name T20
Test name
Test status
Simulation time 619651331176 ps
CPU time 1944.79 seconds
Started Jun 10 07:51:30 PM PDT 24
Finished Jun 10 08:23:59 PM PDT 24
Peak memory 278700 kb
Host smart-d86b0ee8-8659-41b2-beb0-e431c3c7dd19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396743949 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.1396743949
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.2965789332
Short name T855
Test name
Test status
Simulation time 1351499425 ps
CPU time 17.89 seconds
Started Jun 10 07:51:27 PM PDT 24
Finished Jun 10 07:51:46 PM PDT 24
Peak memory 242628 kb
Host smart-24fe4f30-bca8-4d80-8b37-b12d3f7064ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965789332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.2965789332
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.1301458910
Short name T710
Test name
Test status
Simulation time 196308445 ps
CPU time 1.91 seconds
Started Jun 10 07:51:30 PM PDT 24
Finished Jun 10 07:51:35 PM PDT 24
Peak memory 240744 kb
Host smart-6bb50434-8e63-46bb-9812-769630f629e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301458910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.1301458910
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.2276304464
Short name T1157
Test name
Test status
Simulation time 1607197135 ps
CPU time 13.13 seconds
Started Jun 10 07:51:32 PM PDT 24
Finished Jun 10 07:51:48 PM PDT 24
Peak memory 242600 kb
Host smart-a52d5c94-b30f-4d22-ade4-ee96918a50da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276304464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.2276304464
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.2917515413
Short name T912
Test name
Test status
Simulation time 356549994 ps
CPU time 19.93 seconds
Started Jun 10 07:51:31 PM PDT 24
Finished Jun 10 07:51:54 PM PDT 24
Peak memory 242160 kb
Host smart-dbdff5f6-7f0e-4409-90a5-a7c9f8f63e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917515413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.2917515413
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.1161293264
Short name T720
Test name
Test status
Simulation time 826074305 ps
CPU time 18.67 seconds
Started Jun 10 07:51:33 PM PDT 24
Finished Jun 10 07:51:54 PM PDT 24
Peak memory 242460 kb
Host smart-70dbb80e-68c5-4cf2-af58-ae7d0c766b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161293264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.1161293264
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.1474810121
Short name T89
Test name
Test status
Simulation time 294802495 ps
CPU time 3.37 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:51:36 PM PDT 24
Peak memory 242356 kb
Host smart-b78e42e3-c425-4b35-8256-a6ad30e0321e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474810121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.1474810121
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.2601310466
Short name T987
Test name
Test status
Simulation time 7547202569 ps
CPU time 28.01 seconds
Started Jun 10 07:51:30 PM PDT 24
Finished Jun 10 07:52:02 PM PDT 24
Peak memory 243384 kb
Host smart-24b9ef1a-2483-4f97-a4c6-1a56492e2d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601310466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.2601310466
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.4028525737
Short name T540
Test name
Test status
Simulation time 499670419 ps
CPU time 8.31 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:51:41 PM PDT 24
Peak memory 242448 kb
Host smart-f732e52f-147c-47c9-a834-b4d527963643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028525737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.4028525737
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.2427601291
Short name T583
Test name
Test status
Simulation time 411276099 ps
CPU time 9.63 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:51:41 PM PDT 24
Peak memory 242120 kb
Host smart-f5fc7d0f-778a-45b5-a690-78a901a12c80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2427601291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.2427601291
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.3907395703
Short name T775
Test name
Test status
Simulation time 875699862 ps
CPU time 8.77 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:51:40 PM PDT 24
Peak memory 242132 kb
Host smart-bd42f1fc-251a-4950-8cd2-4540593d3ae1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3907395703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.3907395703
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.377896250
Short name T807
Test name
Test status
Simulation time 4294018418 ps
CPU time 11.96 seconds
Started Jun 10 07:51:30 PM PDT 24
Finished Jun 10 07:51:44 PM PDT 24
Peak memory 242720 kb
Host smart-581a4b3e-07c0-4e38-a391-32703c89bd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377896250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.377896250
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.955817988
Short name T7
Test name
Test status
Simulation time 27355887751 ps
CPU time 100.02 seconds
Started Jun 10 07:51:28 PM PDT 24
Finished Jun 10 07:53:10 PM PDT 24
Peak memory 263352 kb
Host smart-e2a6cb20-5c95-42d0-9775-c5fc4cb57bb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955817988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.
955817988
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.436095985
Short name T337
Test name
Test status
Simulation time 132230975828 ps
CPU time 729 seconds
Started Jun 10 07:51:28 PM PDT 24
Finished Jun 10 08:03:39 PM PDT 24
Peak memory 301796 kb
Host smart-18eeb888-3442-4e7d-9dd3-32a8d9ee7ea8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436095985 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.436095985
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.443614975
Short name T830
Test name
Test status
Simulation time 924054664 ps
CPU time 30.27 seconds
Started Jun 10 07:51:31 PM PDT 24
Finished Jun 10 07:52:04 PM PDT 24
Peak memory 242352 kb
Host smart-07e02500-0521-4974-9af4-b79455fca019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443614975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.443614975
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.2022687868
Short name T1015
Test name
Test status
Simulation time 227751962 ps
CPU time 2.06 seconds
Started Jun 10 07:51:31 PM PDT 24
Finished Jun 10 07:51:36 PM PDT 24
Peak memory 240752 kb
Host smart-a6114877-6965-4b94-bc94-2af8f28f74f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022687868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.2022687868
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.4252024273
Short name T827
Test name
Test status
Simulation time 607108325 ps
CPU time 20.11 seconds
Started Jun 10 07:51:33 PM PDT 24
Finished Jun 10 07:51:56 PM PDT 24
Peak memory 242612 kb
Host smart-e7d2362a-722f-4a93-894a-2220680bece3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252024273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.4252024273
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.3332145375
Short name T741
Test name
Test status
Simulation time 5927262157 ps
CPU time 52.7 seconds
Started Jun 10 07:51:30 PM PDT 24
Finished Jun 10 07:52:26 PM PDT 24
Peak memory 255768 kb
Host smart-f17091af-3af4-441a-8a17-d6f78985eb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332145375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.3332145375
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.2639210006
Short name T677
Test name
Test status
Simulation time 238542541 ps
CPU time 5.34 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:51:36 PM PDT 24
Peak memory 242352 kb
Host smart-06709911-91c7-49cd-8d0b-780cd6dba6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639210006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.2639210006
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.1642202565
Short name T629
Test name
Test status
Simulation time 549585411 ps
CPU time 3.9 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:51:35 PM PDT 24
Peak memory 242536 kb
Host smart-7df5a0a5-4ccd-49c4-8771-c0d6d1db201a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642202565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.1642202565
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.2807730058
Short name T599
Test name
Test status
Simulation time 141583235 ps
CPU time 3.63 seconds
Started Jun 10 07:51:38 PM PDT 24
Finished Jun 10 07:51:44 PM PDT 24
Peak memory 242124 kb
Host smart-1ecdb344-b1a2-4242-92a1-f29ab0f6ced1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807730058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.2807730058
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.795558085
Short name T1083
Test name
Test status
Simulation time 369377988 ps
CPU time 12.96 seconds
Started Jun 10 07:51:33 PM PDT 24
Finished Jun 10 07:51:49 PM PDT 24
Peak memory 242200 kb
Host smart-6437e2d8-2674-4ca2-a644-9995dd00584d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795558085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.795558085
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.2362728372
Short name T834
Test name
Test status
Simulation time 208208071 ps
CPU time 6.09 seconds
Started Jun 10 07:51:33 PM PDT 24
Finished Jun 10 07:51:42 PM PDT 24
Peak memory 242052 kb
Host smart-19c0122d-b94e-4206-8a9f-ec321b57fa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362728372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.2362728372
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.1804391072
Short name T844
Test name
Test status
Simulation time 2069942850 ps
CPU time 24.23 seconds
Started Jun 10 07:51:30 PM PDT 24
Finished Jun 10 07:51:57 PM PDT 24
Peak memory 242428 kb
Host smart-2612c534-61bb-47a8-9eae-7414372a1975
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1804391072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.1804391072
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.1179563265
Short name T944
Test name
Test status
Simulation time 226469922 ps
CPU time 5.6 seconds
Started Jun 10 07:51:34 PM PDT 24
Finished Jun 10 07:51:42 PM PDT 24
Peak memory 242496 kb
Host smart-e8c1d1ef-83eb-4aa1-b78d-be508ed5bd28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1179563265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.1179563265
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.845837197
Short name T445
Test name
Test status
Simulation time 171658455 ps
CPU time 4.18 seconds
Started Jun 10 07:51:31 PM PDT 24
Finished Jun 10 07:51:38 PM PDT 24
Peak memory 242076 kb
Host smart-0778d062-84c0-4216-bd62-ccc23f77b4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845837197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.845837197
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.2916448813
Short name T769
Test name
Test status
Simulation time 57558104217 ps
CPU time 181.38 seconds
Started Jun 10 07:51:38 PM PDT 24
Finished Jun 10 07:54:41 PM PDT 24
Peak memory 249156 kb
Host smart-632a8839-8239-4842-9f70-2ffa19e76edf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916448813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.2916448813
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.3354149487
Short name T271
Test name
Test status
Simulation time 373524806637 ps
CPU time 1007.9 seconds
Started Jun 10 07:51:38 PM PDT 24
Finished Jun 10 08:08:28 PM PDT 24
Peak memory 282812 kb
Host smart-a4787ed0-949a-421a-a3c7-52055ab570c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354149487 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.3354149487
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.2825295747
Short name T278
Test name
Test status
Simulation time 1185817912 ps
CPU time 20.01 seconds
Started Jun 10 07:51:31 PM PDT 24
Finished Jun 10 07:51:54 PM PDT 24
Peak memory 242872 kb
Host smart-49ea6127-d700-4d78-bd3b-45e29445a736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825295747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.2825295747
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.215546044
Short name T88
Test name
Test status
Simulation time 206446623 ps
CPU time 1.58 seconds
Started Jun 10 07:49:54 PM PDT 24
Finished Jun 10 07:49:59 PM PDT 24
Peak memory 240680 kb
Host smart-f64e9ae4-3531-4d14-ab63-750f18f4ae6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215546044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.215546044
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.656890082
Short name T521
Test name
Test status
Simulation time 2602330711 ps
CPU time 18.77 seconds
Started Jun 10 07:49:57 PM PDT 24
Finished Jun 10 07:50:18 PM PDT 24
Peak memory 242876 kb
Host smart-fb1a6416-02ef-441e-a2a7-92ac1616b8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656890082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.656890082
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.2657601251
Short name T774
Test name
Test status
Simulation time 1376090469 ps
CPU time 4.48 seconds
Started Jun 10 07:49:54 PM PDT 24
Finished Jun 10 07:50:02 PM PDT 24
Peak memory 246524 kb
Host smart-03c69ae2-dc7a-4e34-b0cd-c3ca35e7ae4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657601251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.2657601251
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.1322713113
Short name T881
Test name
Test status
Simulation time 11343712207 ps
CPU time 27.36 seconds
Started Jun 10 07:49:57 PM PDT 24
Finished Jun 10 07:50:26 PM PDT 24
Peak memory 242720 kb
Host smart-6d444eec-79b2-44e4-b9b2-0d72a58d7370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322713113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.1322713113
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.2197583453
Short name T828
Test name
Test status
Simulation time 10333225623 ps
CPU time 19.76 seconds
Started Jun 10 07:49:54 PM PDT 24
Finished Jun 10 07:50:17 PM PDT 24
Peak memory 242884 kb
Host smart-58076ede-0344-49ba-9d1f-41424e341e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197583453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.2197583453
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.3670699008
Short name T672
Test name
Test status
Simulation time 320860514 ps
CPU time 3.94 seconds
Started Jun 10 07:49:53 PM PDT 24
Finished Jun 10 07:50:01 PM PDT 24
Peak memory 242148 kb
Host smart-fdc95efa-a9a1-40f8-92d5-c9d2fb20a7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670699008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.3670699008
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.3050784959
Short name T573
Test name
Test status
Simulation time 1990951219 ps
CPU time 12.18 seconds
Started Jun 10 07:49:55 PM PDT 24
Finished Jun 10 07:50:10 PM PDT 24
Peak memory 243232 kb
Host smart-4116a20f-9b84-46c0-8928-3c942f0fac5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050784959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.3050784959
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.3806249441
Short name T822
Test name
Test status
Simulation time 121312019 ps
CPU time 4.17 seconds
Started Jun 10 07:49:54 PM PDT 24
Finished Jun 10 07:50:01 PM PDT 24
Peak memory 248908 kb
Host smart-2c91dd36-9d9b-4e15-9279-82702eb242d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806249441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.3806249441
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.1196494089
Short name T1139
Test name
Test status
Simulation time 141321352 ps
CPU time 3.91 seconds
Started Jun 10 07:49:53 PM PDT 24
Finished Jun 10 07:50:01 PM PDT 24
Peak memory 242136 kb
Host smart-fc5dba62-40f4-4668-a05f-ed9accf17b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196494089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.1196494089
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.2181858277
Short name T733
Test name
Test status
Simulation time 407969265 ps
CPU time 13.22 seconds
Started Jun 10 07:49:56 PM PDT 24
Finished Jun 10 07:50:12 PM PDT 24
Peak memory 242088 kb
Host smart-2171bc54-da59-4427-8634-a0abdf1a688e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2181858277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.2181858277
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.2901391354
Short name T369
Test name
Test status
Simulation time 392354732 ps
CPU time 6.18 seconds
Started Jun 10 07:49:53 PM PDT 24
Finished Jun 10 07:50:03 PM PDT 24
Peak memory 242136 kb
Host smart-41a11e0f-8038-45ac-a1e4-1c91bd2b6376
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2901391354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.2901391354
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.4228552749
Short name T435
Test name
Test status
Simulation time 2182713710 ps
CPU time 7.52 seconds
Started Jun 10 07:49:55 PM PDT 24
Finished Jun 10 07:50:05 PM PDT 24
Peak memory 242588 kb
Host smart-0ce12179-82ea-44c6-9352-211c89e288fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228552749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.4228552749
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.3769080943
Short name T936
Test name
Test status
Simulation time 67971595187 ps
CPU time 301.26 seconds
Started Jun 10 07:49:55 PM PDT 24
Finished Jun 10 07:54:59 PM PDT 24
Peak memory 303420 kb
Host smart-671b8870-964a-4995-a5ae-fccafa002363
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769080943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.
3769080943
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.1455333918
Short name T1188
Test name
Test status
Simulation time 54166444540 ps
CPU time 1223.04 seconds
Started Jun 10 07:49:51 PM PDT 24
Finished Jun 10 08:10:18 PM PDT 24
Peak memory 298476 kb
Host smart-8e6886ab-f8d5-458d-a7c6-e68de7b4a21a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455333918 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.1455333918
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.402513560
Short name T522
Test name
Test status
Simulation time 697426464 ps
CPU time 13.64 seconds
Started Jun 10 07:49:51 PM PDT 24
Finished Jun 10 07:50:08 PM PDT 24
Peak memory 242548 kb
Host smart-fa642c05-1f64-4be9-9118-c3ccb4358701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402513560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.402513560
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.209238768
Short name T1018
Test name
Test status
Simulation time 191781793 ps
CPU time 2.26 seconds
Started Jun 10 07:51:41 PM PDT 24
Finished Jun 10 07:51:46 PM PDT 24
Peak memory 241052 kb
Host smart-a967eb19-1314-4751-86cf-e7ef5e743044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209238768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.209238768
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.1329448541
Short name T32
Test name
Test status
Simulation time 1003911706 ps
CPU time 15.27 seconds
Started Jun 10 07:51:37 PM PDT 24
Finished Jun 10 07:51:55 PM PDT 24
Peak memory 242212 kb
Host smart-e7f19043-2a83-4c7b-8f01-703211a51d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329448541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.1329448541
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.1270022558
Short name T1181
Test name
Test status
Simulation time 330743975 ps
CPU time 20.2 seconds
Started Jun 10 07:51:30 PM PDT 24
Finished Jun 10 07:51:53 PM PDT 24
Peak memory 242596 kb
Host smart-2ed288c9-a300-4abb-9f82-c7421c278e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270022558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.1270022558
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.1998766997
Short name T99
Test name
Test status
Simulation time 1371894409 ps
CPU time 14.03 seconds
Started Jun 10 07:51:37 PM PDT 24
Finished Jun 10 07:51:54 PM PDT 24
Peak memory 242112 kb
Host smart-3282d63a-e301-45d0-9f4e-c8fc213bc343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998766997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.1998766997
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.3700464555
Short name T503
Test name
Test status
Simulation time 110123818 ps
CPU time 4.35 seconds
Started Jun 10 07:51:30 PM PDT 24
Finished Jun 10 07:51:37 PM PDT 24
Peak memory 242300 kb
Host smart-656d343d-0556-4353-a853-11c4d44ea459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700464555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.3700464555
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.3401682535
Short name T604
Test name
Test status
Simulation time 18017808544 ps
CPU time 42.3 seconds
Started Jun 10 07:51:34 PM PDT 24
Finished Jun 10 07:52:20 PM PDT 24
Peak memory 245756 kb
Host smart-44fa0d82-e05d-4204-ac31-55d39f6ca660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401682535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.3401682535
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.2976201018
Short name T394
Test name
Test status
Simulation time 1001640961 ps
CPU time 9.76 seconds
Started Jun 10 07:51:33 PM PDT 24
Finished Jun 10 07:51:45 PM PDT 24
Peak memory 242492 kb
Host smart-0ca01711-72f6-41a2-aba1-556610c756eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976201018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.2976201018
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.1487105262
Short name T286
Test name
Test status
Simulation time 7911988146 ps
CPU time 26.17 seconds
Started Jun 10 07:51:38 PM PDT 24
Finished Jun 10 07:52:06 PM PDT 24
Peak memory 242300 kb
Host smart-4fc9bbf9-fd94-4d8c-83be-8c18d8c1a53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487105262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.1487105262
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.1792425454
Short name T861
Test name
Test status
Simulation time 1057524369 ps
CPU time 31.99 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:52:03 PM PDT 24
Peak memory 242156 kb
Host smart-b581c8e5-4db1-42fa-be69-6941ed52d851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1792425454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.1792425454
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.4053517316
Short name T370
Test name
Test status
Simulation time 231942938 ps
CPU time 5.59 seconds
Started Jun 10 07:51:34 PM PDT 24
Finished Jun 10 07:51:43 PM PDT 24
Peak memory 242128 kb
Host smart-d34e625e-b0a7-4e62-abad-370e582b36d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4053517316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.4053517316
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.2547611598
Short name T1122
Test name
Test status
Simulation time 1259388243 ps
CPU time 14.47 seconds
Started Jun 10 07:51:29 PM PDT 24
Finished Jun 10 07:51:46 PM PDT 24
Peak memory 242228 kb
Host smart-e8166099-7ad0-459d-9fe3-fd307a20534c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547611598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.2547611598
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.2536935045
Short name T667
Test name
Test status
Simulation time 13262424425 ps
CPU time 314.25 seconds
Started Jun 10 07:51:30 PM PDT 24
Finished Jun 10 07:56:47 PM PDT 24
Peak memory 277096 kb
Host smart-23dc1c02-7705-4598-8255-6a963dad3d0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536935045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all
.2536935045
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.2668542244
Short name T1121
Test name
Test status
Simulation time 680097201 ps
CPU time 11.83 seconds
Started Jun 10 07:51:34 PM PDT 24
Finished Jun 10 07:51:49 PM PDT 24
Peak memory 242164 kb
Host smart-5e6acb82-7691-48dd-ac20-79fc3c8b2a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668542244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.2668542244
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.3050575992
Short name T309
Test name
Test status
Simulation time 120382563 ps
CPU time 2 seconds
Started Jun 10 07:51:42 PM PDT 24
Finished Jun 10 07:51:48 PM PDT 24
Peak memory 240884 kb
Host smart-5017a7e0-8e27-48e9-a3aa-281f20f4f998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050575992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.3050575992
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.4272329089
Short name T1038
Test name
Test status
Simulation time 8123735096 ps
CPU time 11.6 seconds
Started Jun 10 07:51:41 PM PDT 24
Finished Jun 10 07:51:55 PM PDT 24
Peak memory 249172 kb
Host smart-51e5430a-611b-4fe8-86d7-52d309467f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272329089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.4272329089
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.2158321972
Short name T347
Test name
Test status
Simulation time 3781147758 ps
CPU time 13.79 seconds
Started Jun 10 07:51:41 PM PDT 24
Finished Jun 10 07:51:58 PM PDT 24
Peak memory 242728 kb
Host smart-f3faa5aa-2146-4b9b-b694-3be061f64001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158321972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.2158321972
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.4262606881
Short name T376
Test name
Test status
Simulation time 2417153196 ps
CPU time 13.63 seconds
Started Jun 10 07:51:42 PM PDT 24
Finished Jun 10 07:51:59 PM PDT 24
Peak memory 242256 kb
Host smart-d71cf5f4-e40e-4070-b981-1bfaee6b72bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262606881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.4262606881
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.2847146673
Short name T134
Test name
Test status
Simulation time 1730756240 ps
CPU time 5.67 seconds
Started Jun 10 07:51:41 PM PDT 24
Finished Jun 10 07:51:50 PM PDT 24
Peak memory 242704 kb
Host smart-15abdb55-a40a-49b8-9f91-903940be21b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847146673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.2847146673
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.1050271482
Short name T191
Test name
Test status
Simulation time 464487579 ps
CPU time 12.23 seconds
Started Jun 10 07:51:38 PM PDT 24
Finished Jun 10 07:51:52 PM PDT 24
Peak memory 242680 kb
Host smart-f262ac41-d00a-4da7-be8d-43d81ae5a457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050271482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.1050271482
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.1851851102
Short name T580
Test name
Test status
Simulation time 6490865884 ps
CPU time 19.01 seconds
Started Jun 10 07:51:40 PM PDT 24
Finished Jun 10 07:52:01 PM PDT 24
Peak memory 243764 kb
Host smart-984c5c82-5874-4d67-8fac-8dcf77d94d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851851102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.1851851102
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.4049475517
Short name T868
Test name
Test status
Simulation time 966236886 ps
CPU time 15.63 seconds
Started Jun 10 07:51:41 PM PDT 24
Finished Jun 10 07:52:00 PM PDT 24
Peak memory 242364 kb
Host smart-13b1e7ce-f34e-457e-881b-0c5785b09ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049475517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.4049475517
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.4102742274
Short name T859
Test name
Test status
Simulation time 13644161440 ps
CPU time 34.95 seconds
Started Jun 10 07:51:42 PM PDT 24
Finished Jun 10 07:52:21 PM PDT 24
Peak memory 242228 kb
Host smart-344f0af6-69e0-48b6-9bbc-1d1ed787aabd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4102742274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.4102742274
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.3038272000
Short name T1150
Test name
Test status
Simulation time 572529264 ps
CPU time 11.59 seconds
Started Jun 10 07:51:50 PM PDT 24
Finished Jun 10 07:52:04 PM PDT 24
Peak memory 242280 kb
Host smart-607e2685-3a67-4e2c-9af6-4d2c508552a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3038272000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.3038272000
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.1772659492
Short name T1066
Test name
Test status
Simulation time 575032726 ps
CPU time 6.22 seconds
Started Jun 10 07:51:38 PM PDT 24
Finished Jun 10 07:51:46 PM PDT 24
Peak memory 248944 kb
Host smart-2c558196-5f64-475f-884d-6299f3f3784e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772659492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.1772659492
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.2827442975
Short name T678
Test name
Test status
Simulation time 8709477333 ps
CPU time 26.57 seconds
Started Jun 10 07:51:42 PM PDT 24
Finished Jun 10 07:52:12 PM PDT 24
Peak memory 243692 kb
Host smart-6fdfd0c1-ad6a-495b-85f5-efe257ea31ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827442975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.2827442975
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.1052379456
Short name T596
Test name
Test status
Simulation time 2221783340 ps
CPU time 30.97 seconds
Started Jun 10 07:51:41 PM PDT 24
Finished Jun 10 07:52:16 PM PDT 24
Peak memory 242232 kb
Host smart-71807a74-5b7b-48aa-804f-bfeeab564fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052379456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.1052379456
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.1319128823
Short name T160
Test name
Test status
Simulation time 178353859 ps
CPU time 1.66 seconds
Started Jun 10 07:51:46 PM PDT 24
Finished Jun 10 07:51:51 PM PDT 24
Peak memory 241116 kb
Host smart-9873190b-fd3d-4b10-8e5a-8f19f2bd5bf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319128823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.1319128823
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.1245511416
Short name T33
Test name
Test status
Simulation time 7315497514 ps
CPU time 14.72 seconds
Started Jun 10 07:51:41 PM PDT 24
Finished Jun 10 07:51:58 PM PDT 24
Peak memory 243944 kb
Host smart-91d8c547-c135-49e0-b2d5-8204c8d11c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245511416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.1245511416
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.415022460
Short name T1184
Test name
Test status
Simulation time 306602647 ps
CPU time 16.14 seconds
Started Jun 10 07:51:41 PM PDT 24
Finished Jun 10 07:52:00 PM PDT 24
Peak memory 242332 kb
Host smart-fcdbcb62-09cc-4097-8bc9-1034ed67e620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415022460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.415022460
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.2204782680
Short name T1116
Test name
Test status
Simulation time 1773649772 ps
CPU time 28.05 seconds
Started Jun 10 07:51:43 PM PDT 24
Finished Jun 10 07:52:15 PM PDT 24
Peak memory 242236 kb
Host smart-1e4daad2-becf-4923-8ac7-e1fc1ddeb27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204782680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.2204782680
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.170356808
Short name T1140
Test name
Test status
Simulation time 119215549 ps
CPU time 3.13 seconds
Started Jun 10 07:51:43 PM PDT 24
Finished Jun 10 07:51:50 PM PDT 24
Peak memory 242356 kb
Host smart-c7f88113-eed3-4746-b882-3c79d4723826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170356808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.170356808
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.1698982341
Short name T298
Test name
Test status
Simulation time 415319896 ps
CPU time 7.66 seconds
Started Jun 10 07:51:43 PM PDT 24
Finished Jun 10 07:51:54 PM PDT 24
Peak memory 242396 kb
Host smart-35190e40-48ea-4a12-99df-658b13186a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698982341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.1698982341
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.3970695611
Short name T386
Test name
Test status
Simulation time 991360300 ps
CPU time 23.9 seconds
Started Jun 10 07:51:43 PM PDT 24
Finished Jun 10 07:52:10 PM PDT 24
Peak memory 242716 kb
Host smart-977cac44-69c8-4538-aa63-f876eb358687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970695611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.3970695611
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.2345345443
Short name T163
Test name
Test status
Simulation time 3914668258 ps
CPU time 12.26 seconds
Started Jun 10 07:51:41 PM PDT 24
Finished Jun 10 07:51:56 PM PDT 24
Peak memory 242300 kb
Host smart-a6eee247-957a-4407-89a0-ca13fa889185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345345443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.2345345443
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.838315146
Short name T90
Test name
Test status
Simulation time 3293436925 ps
CPU time 9.62 seconds
Started Jun 10 07:51:41 PM PDT 24
Finished Jun 10 07:51:54 PM PDT 24
Peak memory 242556 kb
Host smart-9e5cb40b-525a-49c2-95b9-27c0bf4b0841
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=838315146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.838315146
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.3071067942
Short name T668
Test name
Test status
Simulation time 139286492 ps
CPU time 4.56 seconds
Started Jun 10 07:51:43 PM PDT 24
Finished Jun 10 07:51:52 PM PDT 24
Peak memory 242216 kb
Host smart-e8e23df3-bed9-4751-aba4-bc0180af5a6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3071067942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.3071067942
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.3932618213
Short name T809
Test name
Test status
Simulation time 1117733849 ps
CPU time 10.84 seconds
Started Jun 10 07:51:44 PM PDT 24
Finished Jun 10 07:51:59 PM PDT 24
Peak memory 242556 kb
Host smart-e6507fc6-e320-489f-86ca-3a8ffcdf00a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932618213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.3932618213
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.2921403679
Short name T874
Test name
Test status
Simulation time 70113873600 ps
CPU time 1110.09 seconds
Started Jun 10 07:51:40 PM PDT 24
Finished Jun 10 08:10:13 PM PDT 24
Peak memory 282136 kb
Host smart-bbe6c654-0634-48a6-880e-45a40bb0719e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921403679 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.2921403679
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.2269997279
Short name T734
Test name
Test status
Simulation time 2204377257 ps
CPU time 14.54 seconds
Started Jun 10 07:51:42 PM PDT 24
Finished Jun 10 07:52:00 PM PDT 24
Peak memory 242672 kb
Host smart-7f7e83e8-fc60-4e91-be40-c3b9ae8df681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269997279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.2269997279
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.3806397263
Short name T472
Test name
Test status
Simulation time 73409058 ps
CPU time 1.54 seconds
Started Jun 10 07:51:44 PM PDT 24
Finished Jun 10 07:51:49 PM PDT 24
Peak memory 240716 kb
Host smart-06903da3-cc2b-45d1-a8aa-cb71c13d7d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806397263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.3806397263
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.978493575
Short name T68
Test name
Test status
Simulation time 9978846930 ps
CPU time 26.46 seconds
Started Jun 10 07:51:40 PM PDT 24
Finished Jun 10 07:52:09 PM PDT 24
Peak memory 243568 kb
Host smart-b2b18a72-6a46-4e30-adb7-036b09e1d5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978493575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.978493575
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.4053305576
Short name T640
Test name
Test status
Simulation time 5437036574 ps
CPU time 42.91 seconds
Started Jun 10 07:51:41 PM PDT 24
Finished Jun 10 07:52:28 PM PDT 24
Peak memory 249204 kb
Host smart-048e0eca-6da8-4122-8233-932831345517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053305576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.4053305576
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.803254018
Short name T1025
Test name
Test status
Simulation time 1959531724 ps
CPU time 21.24 seconds
Started Jun 10 07:51:43 PM PDT 24
Finished Jun 10 07:52:08 PM PDT 24
Peak memory 242232 kb
Host smart-b47f05fc-f1e8-4789-bdbe-f251567006e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803254018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.803254018
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.1790607214
Short name T561
Test name
Test status
Simulation time 153275668 ps
CPU time 4.26 seconds
Started Jun 10 07:51:43 PM PDT 24
Finished Jun 10 07:51:51 PM PDT 24
Peak memory 242388 kb
Host smart-742dda3d-b411-47ae-a520-4ac107f023bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790607214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.1790607214
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.4116635753
Short name T1074
Test name
Test status
Simulation time 894696608 ps
CPU time 5.01 seconds
Started Jun 10 07:51:45 PM PDT 24
Finished Jun 10 07:51:54 PM PDT 24
Peak memory 242600 kb
Host smart-365680f1-97b5-4d35-b0f7-e3105d0bfccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116635753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.4116635753
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.3586599578
Short name T728
Test name
Test status
Simulation time 14210820124 ps
CPU time 32.77 seconds
Started Jun 10 07:51:41 PM PDT 24
Finished Jun 10 07:52:18 PM PDT 24
Peak memory 242628 kb
Host smart-e0680c07-2b0d-47a8-9d48-052033679fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586599578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.3586599578
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.1581903216
Short name T234
Test name
Test status
Simulation time 155635726 ps
CPU time 3.21 seconds
Started Jun 10 07:51:44 PM PDT 24
Finished Jun 10 07:51:51 PM PDT 24
Peak memory 242068 kb
Host smart-5ac98cbb-022f-4887-a096-064059acf9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581903216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.1581903216
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.3948996410
Short name T495
Test name
Test status
Simulation time 745160206 ps
CPU time 20.1 seconds
Started Jun 10 07:51:44 PM PDT 24
Finished Jun 10 07:52:07 PM PDT 24
Peak memory 242640 kb
Host smart-3439b113-cbfa-4008-a9bd-9464b2606739
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3948996410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.3948996410
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.2682942843
Short name T1142
Test name
Test status
Simulation time 1791360101 ps
CPU time 4.85 seconds
Started Jun 10 07:51:45 PM PDT 24
Finished Jun 10 07:51:53 PM PDT 24
Peak memory 242084 kb
Host smart-37b0f007-ee17-4538-9bed-dc257a0ca6df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2682942843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.2682942843
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.3414222536
Short name T635
Test name
Test status
Simulation time 262525186 ps
CPU time 6.14 seconds
Started Jun 10 07:51:39 PM PDT 24
Finished Jun 10 07:51:48 PM PDT 24
Peak memory 242104 kb
Host smart-42c9fc21-c3e1-4f9e-b65e-0aadd41b6a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414222536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.3414222536
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.5315120
Short name T384
Test name
Test status
Simulation time 1364406362 ps
CPU time 25.2 seconds
Started Jun 10 07:51:44 PM PDT 24
Finished Jun 10 07:52:13 PM PDT 24
Peak memory 242588 kb
Host smart-fdaade9e-5ad4-4106-9be8-62ef991ff4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5315120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.5315120
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.3890399530
Short name T971
Test name
Test status
Simulation time 175032136 ps
CPU time 1.74 seconds
Started Jun 10 07:51:40 PM PDT 24
Finished Jun 10 07:51:44 PM PDT 24
Peak memory 241072 kb
Host smart-dc865c61-6ba9-4e3e-935d-3c414b147b0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890399530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.3890399530
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.3268679484
Short name T559
Test name
Test status
Simulation time 763141126 ps
CPU time 8.11 seconds
Started Jun 10 07:51:42 PM PDT 24
Finished Jun 10 07:51:54 PM PDT 24
Peak memory 242648 kb
Host smart-af44a2f8-cbcb-4d15-915e-55451b94fe45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268679484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.3268679484
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.3231785015
Short name T1089
Test name
Test status
Simulation time 3439749619 ps
CPU time 16.41 seconds
Started Jun 10 07:51:45 PM PDT 24
Finished Jun 10 07:52:05 PM PDT 24
Peak memory 242476 kb
Host smart-b5797a7d-17d2-4018-a61d-4197a95b535c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231785015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.3231785015
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.1326329215
Short name T1022
Test name
Test status
Simulation time 324591224 ps
CPU time 4.02 seconds
Started Jun 10 07:51:44 PM PDT 24
Finished Jun 10 07:51:52 PM PDT 24
Peak memory 242112 kb
Host smart-ac932e20-ca6f-4d94-b6fe-06da70345119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326329215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.1326329215
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.2906713772
Short name T975
Test name
Test status
Simulation time 564210603 ps
CPU time 3.69 seconds
Started Jun 10 07:51:45 PM PDT 24
Finished Jun 10 07:51:52 PM PDT 24
Peak memory 242388 kb
Host smart-55dc4cfc-2bcb-4d4d-a19e-07778c5012f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906713772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.2906713772
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.2699387929
Short name T1013
Test name
Test status
Simulation time 4278175131 ps
CPU time 27.85 seconds
Started Jun 10 07:51:44 PM PDT 24
Finished Jun 10 07:52:16 PM PDT 24
Peak memory 246388 kb
Host smart-61272beb-bfee-4c66-bd4f-0d0e255618d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699387929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.2699387929
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.2852239699
Short name T967
Test name
Test status
Simulation time 1145597571 ps
CPU time 17.49 seconds
Started Jun 10 07:51:45 PM PDT 24
Finished Jun 10 07:52:06 PM PDT 24
Peak memory 242864 kb
Host smart-e9bd3934-9636-4f6d-ac82-68db290b3c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852239699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.2852239699
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.1787156454
Short name T708
Test name
Test status
Simulation time 254500206 ps
CPU time 6.3 seconds
Started Jun 10 07:51:44 PM PDT 24
Finished Jun 10 07:51:54 PM PDT 24
Peak memory 242216 kb
Host smart-ea932f7f-14f9-42c9-b3a5-6553333930ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787156454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.1787156454
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.1376914806
Short name T537
Test name
Test status
Simulation time 332254495 ps
CPU time 10.83 seconds
Started Jun 10 07:51:42 PM PDT 24
Finished Jun 10 07:51:57 PM PDT 24
Peak memory 248924 kb
Host smart-9c4c6224-2a4e-448c-b331-cfee6cbb65b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1376914806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.1376914806
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.1495493011
Short name T363
Test name
Test status
Simulation time 891769933 ps
CPU time 6.01 seconds
Started Jun 10 07:51:44 PM PDT 24
Finished Jun 10 07:51:53 PM PDT 24
Peak memory 248624 kb
Host smart-bc904b7e-b13d-4506-b019-d3dc0d4f280d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1495493011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.1495493011
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.134528288
Short name T570
Test name
Test status
Simulation time 613036002 ps
CPU time 4.75 seconds
Started Jun 10 07:51:44 PM PDT 24
Finished Jun 10 07:51:52 PM PDT 24
Peak memory 242068 kb
Host smart-64d83056-fdb9-425e-846a-d549d3f415eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134528288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.134528288
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.772097937
Short name T984
Test name
Test status
Simulation time 126933474466 ps
CPU time 3538.66 seconds
Started Jun 10 07:51:44 PM PDT 24
Finished Jun 10 08:50:47 PM PDT 24
Peak memory 835032 kb
Host smart-41367e15-76b3-4a0f-bc87-aed14974cd6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772097937 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.772097937
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.1323144561
Short name T632
Test name
Test status
Simulation time 436745967 ps
CPU time 14.92 seconds
Started Jun 10 07:51:42 PM PDT 24
Finished Jun 10 07:52:00 PM PDT 24
Peak memory 242376 kb
Host smart-0843695f-a0e5-4db3-a2cc-90af1d686ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323144561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.1323144561
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.2937171922
Short name T817
Test name
Test status
Simulation time 62812141 ps
CPU time 1.88 seconds
Started Jun 10 07:51:50 PM PDT 24
Finished Jun 10 07:51:55 PM PDT 24
Peak memory 240776 kb
Host smart-6d603a94-a88a-4c12-b2b9-fb335c89ff2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937171922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.2937171922
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.1828562213
Short name T857
Test name
Test status
Simulation time 1761660901 ps
CPU time 9.59 seconds
Started Jun 10 07:51:40 PM PDT 24
Finished Jun 10 07:51:52 PM PDT 24
Peak memory 242564 kb
Host smart-718c27db-ddb5-4c39-a928-ea74be0ce81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828562213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.1828562213
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.721682403
Short name T819
Test name
Test status
Simulation time 1803419740 ps
CPU time 27.49 seconds
Started Jun 10 07:51:43 PM PDT 24
Finished Jun 10 07:52:14 PM PDT 24
Peak memory 242220 kb
Host smart-89578322-ff76-44bd-a929-6f47a302b92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721682403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.721682403
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.509415205
Short name T548
Test name
Test status
Simulation time 4164377811 ps
CPU time 32.68 seconds
Started Jun 10 07:51:41 PM PDT 24
Finished Jun 10 07:52:16 PM PDT 24
Peak memory 242432 kb
Host smart-19e7f7a3-98d2-4d10-b34f-c7f281d8e42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509415205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.509415205
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.2507295945
Short name T1104
Test name
Test status
Simulation time 290949866 ps
CPU time 4.22 seconds
Started Jun 10 07:51:42 PM PDT 24
Finished Jun 10 07:51:50 PM PDT 24
Peak memory 242340 kb
Host smart-7c21a09d-de3f-4fc8-beb0-e436f5a71bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507295945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.2507295945
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.2851887302
Short name T462
Test name
Test status
Simulation time 237180160 ps
CPU time 4.58 seconds
Started Jun 10 07:51:39 PM PDT 24
Finished Jun 10 07:51:46 PM PDT 24
Peak memory 242748 kb
Host smart-bd6db7bc-d04f-44e0-9fd4-20cb947a670c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851887302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.2851887302
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.1742348871
Short name T1170
Test name
Test status
Simulation time 22106948249 ps
CPU time 42.22 seconds
Started Jun 10 07:51:40 PM PDT 24
Finished Jun 10 07:52:25 PM PDT 24
Peak memory 243372 kb
Host smart-c4169dee-2ce5-4087-becd-c6d23b000091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742348871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.1742348871
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.1052039639
Short name T219
Test name
Test status
Simulation time 128076603 ps
CPU time 3.55 seconds
Started Jun 10 07:51:42 PM PDT 24
Finished Jun 10 07:51:49 PM PDT 24
Peak memory 242256 kb
Host smart-d0dd7a30-868a-4991-afaf-4aac40a5e1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052039639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.1052039639
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.2463766144
Short name T887
Test name
Test status
Simulation time 2113842197 ps
CPU time 7.25 seconds
Started Jun 10 07:51:39 PM PDT 24
Finished Jun 10 07:51:48 PM PDT 24
Peak memory 242476 kb
Host smart-d9ccb5ce-0103-47a3-8dec-ab1f24b514db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2463766144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.2463766144
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.510355048
Short name T360
Test name
Test status
Simulation time 763656190 ps
CPU time 7.21 seconds
Started Jun 10 07:51:42 PM PDT 24
Finished Jun 10 07:51:53 PM PDT 24
Peak memory 242292 kb
Host smart-28f529b6-d2d8-41d2-a2f4-de5a413d059e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=510355048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.510355048
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.2360366440
Short name T1128
Test name
Test status
Simulation time 648159450 ps
CPU time 6.79 seconds
Started Jun 10 07:51:39 PM PDT 24
Finished Jun 10 07:51:48 PM PDT 24
Peak memory 242312 kb
Host smart-84b4cb4e-3089-4095-96ed-acaa88b6a951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360366440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.2360366440
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.4067320382
Short name T1107
Test name
Test status
Simulation time 10626332773 ps
CPU time 74.33 seconds
Started Jun 10 07:52:03 PM PDT 24
Finished Jun 10 07:53:20 PM PDT 24
Peak memory 245652 kb
Host smart-e57cc1e1-e56f-4d47-a31a-3da2af35b9c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067320382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all
.4067320382
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.126921384
Short name T338
Test name
Test status
Simulation time 798082863940 ps
CPU time 1651.93 seconds
Started Jun 10 07:51:49 PM PDT 24
Finished Jun 10 08:19:24 PM PDT 24
Peak memory 370480 kb
Host smart-5915f7e6-3515-41ff-b847-1ca007cbb116
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126921384 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.126921384
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.3385797428
Short name T450
Test name
Test status
Simulation time 448857185 ps
CPU time 9.16 seconds
Started Jun 10 07:51:52 PM PDT 24
Finished Jun 10 07:52:04 PM PDT 24
Peak memory 242216 kb
Host smart-e3b9f2cd-9832-48c9-a5fe-43e85db47f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385797428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.3385797428
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.1804612049
Short name T937
Test name
Test status
Simulation time 47565538 ps
CPU time 1.79 seconds
Started Jun 10 07:51:53 PM PDT 24
Finished Jun 10 07:51:57 PM PDT 24
Peak memory 240768 kb
Host smart-dc2e43bc-0647-401a-b42e-b0abddacd9d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804612049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.1804612049
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.4099572382
Short name T82
Test name
Test status
Simulation time 1019073502 ps
CPU time 19.56 seconds
Started Jun 10 07:51:47 PM PDT 24
Finished Jun 10 07:52:10 PM PDT 24
Peak memory 249064 kb
Host smart-579c7bb8-45f4-4498-ae44-546b44f69d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099572382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.4099572382
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.2109815068
Short name T181
Test name
Test status
Simulation time 1077942095 ps
CPU time 17.29 seconds
Started Jun 10 07:51:57 PM PDT 24
Finished Jun 10 07:52:17 PM PDT 24
Peak memory 242248 kb
Host smart-c701653f-7540-429e-af84-0522a7b44317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109815068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.2109815068
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.1519547583
Short name T513
Test name
Test status
Simulation time 778179787 ps
CPU time 6.96 seconds
Started Jun 10 07:51:58 PM PDT 24
Finished Jun 10 07:52:07 PM PDT 24
Peak memory 242528 kb
Host smart-8f4591b2-17fe-4f69-99f3-03217bfb86c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519547583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.1519547583
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.3964076426
Short name T905
Test name
Test status
Simulation time 1946550246 ps
CPU time 6.25 seconds
Started Jun 10 07:51:49 PM PDT 24
Finished Jun 10 07:51:58 PM PDT 24
Peak memory 242544 kb
Host smart-2fd8a8b6-6bea-44e7-ae27-c4dc4529f98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964076426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.3964076426
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.3228516441
Short name T1039
Test name
Test status
Simulation time 2021465833 ps
CPU time 33.75 seconds
Started Jun 10 07:51:49 PM PDT 24
Finished Jun 10 07:52:25 PM PDT 24
Peak memory 247164 kb
Host smart-ada11930-7b70-4300-a760-062be1fcb1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228516441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.3228516441
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.3122163592
Short name T406
Test name
Test status
Simulation time 215573922 ps
CPU time 4.4 seconds
Started Jun 10 07:51:54 PM PDT 24
Finished Jun 10 07:52:00 PM PDT 24
Peak memory 242100 kb
Host smart-34372733-32e2-4f84-a668-404b007cd4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122163592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.3122163592
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.1296542968
Short name T597
Test name
Test status
Simulation time 594262367 ps
CPU time 9 seconds
Started Jun 10 07:51:50 PM PDT 24
Finished Jun 10 07:52:02 PM PDT 24
Peak memory 242128 kb
Host smart-8dc6cfb3-5359-4600-b0f1-4a1b039e076f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296542968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.1296542968
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.3360108096
Short name T476
Test name
Test status
Simulation time 1027248589 ps
CPU time 17.24 seconds
Started Jun 10 07:51:51 PM PDT 24
Finished Jun 10 07:52:11 PM PDT 24
Peak memory 242156 kb
Host smart-fe03c5f8-6695-4396-a08e-c4e6286cf1f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3360108096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.3360108096
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.489748276
Short name T564
Test name
Test status
Simulation time 1316096968 ps
CPU time 12.51 seconds
Started Jun 10 07:52:02 PM PDT 24
Finished Jun 10 07:52:17 PM PDT 24
Peak memory 242500 kb
Host smart-59b4baac-8c65-422e-9692-c7d21c7c2268
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=489748276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.489748276
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.3542440503
Short name T1044
Test name
Test status
Simulation time 879678507 ps
CPU time 6.59 seconds
Started Jun 10 07:51:48 PM PDT 24
Finished Jun 10 07:51:58 PM PDT 24
Peak memory 241984 kb
Host smart-d722ad91-504b-4caa-9cd1-1c04427bcafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542440503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.3542440503
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.3014955148
Short name T1185
Test name
Test status
Simulation time 29177571848 ps
CPU time 329.74 seconds
Started Jun 10 07:51:48 PM PDT 24
Finished Jun 10 07:57:21 PM PDT 24
Peak memory 289636 kb
Host smart-5ea77cde-214e-408b-95db-e02f09f87c0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014955148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all
.3014955148
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.2602826867
Short name T895
Test name
Test status
Simulation time 11229929101 ps
CPU time 25.5 seconds
Started Jun 10 07:51:50 PM PDT 24
Finished Jun 10 07:52:18 PM PDT 24
Peak memory 242772 kb
Host smart-2c3bf63c-2a3c-487a-821b-c61f90a93e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602826867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.2602826867
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.2526312693
Short name T652
Test name
Test status
Simulation time 112734434 ps
CPU time 1.8 seconds
Started Jun 10 07:51:51 PM PDT 24
Finished Jun 10 07:51:55 PM PDT 24
Peak memory 240756 kb
Host smart-e992d7cd-81b3-421e-a6b6-d8be97f89cb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526312693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.2526312693
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.2186774552
Short name T56
Test name
Test status
Simulation time 1419700837 ps
CPU time 19.55 seconds
Started Jun 10 07:51:50 PM PDT 24
Finished Jun 10 07:52:12 PM PDT 24
Peak memory 244248 kb
Host smart-a4b23020-821c-47ca-814a-bbd8a4013a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186774552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.2186774552
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.2903919168
Short name T439
Test name
Test status
Simulation time 948249646 ps
CPU time 17.65 seconds
Started Jun 10 07:51:54 PM PDT 24
Finished Jun 10 07:52:14 PM PDT 24
Peak memory 242484 kb
Host smart-12982f4a-eefb-4b1d-92ed-7c2f0c92cc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903919168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.2903919168
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.3922164726
Short name T826
Test name
Test status
Simulation time 179970384 ps
CPU time 5.32 seconds
Started Jun 10 07:51:50 PM PDT 24
Finished Jun 10 07:51:58 PM PDT 24
Peak memory 242188 kb
Host smart-3877448e-710e-4e6f-b47b-4902a479dbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922164726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.3922164726
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.424709104
Short name T544
Test name
Test status
Simulation time 428495294 ps
CPU time 4.55 seconds
Started Jun 10 07:51:50 PM PDT 24
Finished Jun 10 07:51:57 PM PDT 24
Peak memory 242360 kb
Host smart-a1cb5a6c-8ef0-4c62-ac93-79a3433cc8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424709104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.424709104
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.4240632008
Short name T146
Test name
Test status
Simulation time 7760445690 ps
CPU time 22.26 seconds
Started Jun 10 07:51:57 PM PDT 24
Finished Jun 10 07:52:21 PM PDT 24
Peak memory 243272 kb
Host smart-10239c11-e981-44c7-b271-d4d505f83231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240632008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.4240632008
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.534814964
Short name T375
Test name
Test status
Simulation time 240114668 ps
CPU time 10.66 seconds
Started Jun 10 07:51:51 PM PDT 24
Finished Jun 10 07:52:04 PM PDT 24
Peak memory 242480 kb
Host smart-934799cc-d930-4810-8693-2bcb97a6b48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534814964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.534814964
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.335906770
Short name T619
Test name
Test status
Simulation time 680646037 ps
CPU time 10.19 seconds
Started Jun 10 07:51:50 PM PDT 24
Finished Jun 10 07:52:03 PM PDT 24
Peak memory 242124 kb
Host smart-41e6cb0d-b11c-4ca3-aabe-0a7976b0bb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335906770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.335906770
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.1317680481
Short name T167
Test name
Test status
Simulation time 718240820 ps
CPU time 13.96 seconds
Started Jun 10 07:51:56 PM PDT 24
Finished Jun 10 07:52:13 PM PDT 24
Peak memory 242152 kb
Host smart-eb6a9ec4-bb86-4f01-83c4-fca30ff01157
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1317680481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.1317680481
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.2473131057
Short name T808
Test name
Test status
Simulation time 1442729457 ps
CPU time 6.02 seconds
Started Jun 10 07:51:53 PM PDT 24
Finished Jun 10 07:52:01 PM PDT 24
Peak memory 242224 kb
Host smart-fc1f9761-34ba-4cd7-8787-ad548992c23d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2473131057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.2473131057
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.1449123632
Short name T934
Test name
Test status
Simulation time 358838674 ps
CPU time 4.44 seconds
Started Jun 10 07:51:48 PM PDT 24
Finished Jun 10 07:51:55 PM PDT 24
Peak memory 242268 kb
Host smart-64bb60e3-0717-4c8a-8119-2ecb08f2d9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449123632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.1449123632
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.1951867817
Short name T713
Test name
Test status
Simulation time 1847718980 ps
CPU time 54.77 seconds
Started Jun 10 07:52:11 PM PDT 24
Finished Jun 10 07:53:07 PM PDT 24
Peak memory 245220 kb
Host smart-d761c252-85ac-4cac-a71b-0870dd7077cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951867817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all
.1951867817
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.1235362942
Short name T729
Test name
Test status
Simulation time 41653366828 ps
CPU time 897.67 seconds
Started Jun 10 07:51:50 PM PDT 24
Finished Jun 10 08:06:50 PM PDT 24
Peak memory 264448 kb
Host smart-d881452a-9ce5-4127-81ef-aa0be2155024
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235362942 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.1235362942
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.3876732909
Short name T184
Test name
Test status
Simulation time 18424227967 ps
CPU time 37.03 seconds
Started Jun 10 07:51:51 PM PDT 24
Finished Jun 10 07:52:30 PM PDT 24
Peak memory 242588 kb
Host smart-1ad4d142-67e4-44bd-86a1-2e5acb90999b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876732909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.3876732909
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.2453162990
Short name T630
Test name
Test status
Simulation time 62759415 ps
CPU time 1.87 seconds
Started Jun 10 07:51:57 PM PDT 24
Finished Jun 10 07:52:02 PM PDT 24
Peak memory 241108 kb
Host smart-f17dea54-2e84-4598-99f9-3ca9cb7b58ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453162990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.2453162990
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.431277050
Short name T1019
Test name
Test status
Simulation time 1082560210 ps
CPU time 11.29 seconds
Started Jun 10 07:51:51 PM PDT 24
Finished Jun 10 07:52:05 PM PDT 24
Peak memory 242304 kb
Host smart-1e5b0f98-e595-4ef5-8474-24641293802a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431277050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.431277050
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.2712610449
Short name T641
Test name
Test status
Simulation time 628716375 ps
CPU time 19.09 seconds
Started Jun 10 07:51:49 PM PDT 24
Finished Jun 10 07:52:11 PM PDT 24
Peak memory 242224 kb
Host smart-51624f80-54bb-41b0-b109-4886707cf196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712610449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.2712610449
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.1259096847
Short name T777
Test name
Test status
Simulation time 108607070 ps
CPU time 3.18 seconds
Started Jun 10 07:51:49 PM PDT 24
Finished Jun 10 07:51:55 PM PDT 24
Peak memory 242160 kb
Host smart-277017c9-7b9b-4034-a1bb-3fc07b0156f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259096847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.1259096847
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.7656938
Short name T487
Test name
Test status
Simulation time 1993343784 ps
CPU time 5.95 seconds
Started Jun 10 07:51:48 PM PDT 24
Finished Jun 10 07:51:57 PM PDT 24
Peak memory 242312 kb
Host smart-cd65108f-272d-4a73-8bed-d3d30827d78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7656938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.7656938
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.367287068
Short name T413
Test name
Test status
Simulation time 1140164617 ps
CPU time 8.43 seconds
Started Jun 10 07:51:57 PM PDT 24
Finished Jun 10 07:52:08 PM PDT 24
Peak memory 242232 kb
Host smart-ce068dc0-1736-435d-ae0a-638e0c300318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367287068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.367287068
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.3178496654
Short name T756
Test name
Test status
Simulation time 2197170178 ps
CPU time 48.34 seconds
Started Jun 10 07:51:48 PM PDT 24
Finished Jun 10 07:52:39 PM PDT 24
Peak memory 242892 kb
Host smart-ecd357c1-4152-441c-9121-295869fe4279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178496654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.3178496654
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.1116159562
Short name T749
Test name
Test status
Simulation time 264194012 ps
CPU time 6.53 seconds
Started Jun 10 07:52:02 PM PDT 24
Finished Jun 10 07:52:11 PM PDT 24
Peak memory 242444 kb
Host smart-b4545e60-a314-447f-8968-c50490bc9a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116159562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.1116159562
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.1435714785
Short name T393
Test name
Test status
Simulation time 1955206533 ps
CPU time 21.95 seconds
Started Jun 10 07:51:49 PM PDT 24
Finished Jun 10 07:52:14 PM PDT 24
Peak memory 242448 kb
Host smart-494514c6-184d-40a6-978d-daa2041ffa0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1435714785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.1435714785
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.701263477
Short name T371
Test name
Test status
Simulation time 114149010 ps
CPU time 3.41 seconds
Started Jun 10 07:51:48 PM PDT 24
Finished Jun 10 07:51:55 PM PDT 24
Peak memory 242132 kb
Host smart-c4999e38-a345-432c-8133-6e5a33424777
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=701263477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.701263477
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.4167608770
Short name T959
Test name
Test status
Simulation time 958441325 ps
CPU time 7.21 seconds
Started Jun 10 07:51:47 PM PDT 24
Finished Jun 10 07:51:58 PM PDT 24
Peak memory 242160 kb
Host smart-6795740f-2206-40f8-8ba7-8da97fba8715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167608770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.4167608770
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.2382209312
Short name T119
Test name
Test status
Simulation time 589729968 ps
CPU time 6.65 seconds
Started Jun 10 07:51:52 PM PDT 24
Finished Jun 10 07:52:01 PM PDT 24
Peak memory 241724 kb
Host smart-767bfb90-bcef-4351-b285-5e8dc7c532d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382209312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all
.2382209312
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.3612365245
Short name T908
Test name
Test status
Simulation time 37934686660 ps
CPU time 307.83 seconds
Started Jun 10 07:51:47 PM PDT 24
Finished Jun 10 07:56:58 PM PDT 24
Peak memory 294240 kb
Host smart-b93f1cdf-695a-4631-87ef-94f1fbe719c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612365245 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.3612365245
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.499233593
Short name T683
Test name
Test status
Simulation time 245519401 ps
CPU time 5.9 seconds
Started Jun 10 07:51:58 PM PDT 24
Finished Jun 10 07:52:06 PM PDT 24
Peak memory 242148 kb
Host smart-2f2daeb1-d526-46d8-9a50-4c0263c450fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499233593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.499233593
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.463599478
Short name T1180
Test name
Test status
Simulation time 50653084 ps
CPU time 1.71 seconds
Started Jun 10 07:51:57 PM PDT 24
Finished Jun 10 07:52:01 PM PDT 24
Peak memory 240892 kb
Host smart-1c9f35d6-bb74-43d8-a589-a6479aca4d57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463599478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.463599478
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.1688728188
Short name T52
Test name
Test status
Simulation time 298003666 ps
CPU time 6.41 seconds
Started Jun 10 07:52:03 PM PDT 24
Finished Jun 10 07:52:12 PM PDT 24
Peak memory 242448 kb
Host smart-94e3569b-ff0f-4f75-8a54-bbad26e450a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688728188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.1688728188
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.4293225787
Short name T662
Test name
Test status
Simulation time 797641471 ps
CPU time 15.5 seconds
Started Jun 10 07:51:49 PM PDT 24
Finished Jun 10 07:52:07 PM PDT 24
Peak memory 242592 kb
Host smart-a4edbbe3-1901-4261-9d84-cd9ea066b050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293225787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.4293225787
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.3245848618
Short name T196
Test name
Test status
Simulation time 3740400624 ps
CPU time 39.48 seconds
Started Jun 10 07:51:57 PM PDT 24
Finished Jun 10 07:52:39 PM PDT 24
Peak memory 242816 kb
Host smart-684f362e-4c5f-4b88-a557-58c34327e093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245848618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.3245848618
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.2442676907
Short name T1165
Test name
Test status
Simulation time 583343249 ps
CPU time 5.07 seconds
Started Jun 10 07:51:51 PM PDT 24
Finished Jun 10 07:51:58 PM PDT 24
Peak memory 242556 kb
Host smart-a22ae523-2d75-4eee-8e15-8e205cb11eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442676907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.2442676907
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.2710295713
Short name T771
Test name
Test status
Simulation time 529313828 ps
CPU time 8.48 seconds
Started Jun 10 07:51:50 PM PDT 24
Finished Jun 10 07:52:01 PM PDT 24
Peak memory 242792 kb
Host smart-cf7c7792-9fc9-4d34-b1c1-595190b1a8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710295713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.2710295713
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.3354285564
Short name T392
Test name
Test status
Simulation time 7352673799 ps
CPU time 24.91 seconds
Started Jun 10 07:51:51 PM PDT 24
Finished Jun 10 07:52:18 PM PDT 24
Peak memory 242728 kb
Host smart-cd35bef1-d4f0-4d39-9664-7001939e0d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354285564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.3354285564
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.3851280476
Short name T1009
Test name
Test status
Simulation time 593628748 ps
CPU time 15.33 seconds
Started Jun 10 07:51:54 PM PDT 24
Finished Jun 10 07:52:11 PM PDT 24
Peak memory 242260 kb
Host smart-8088d234-4452-49ed-8129-4d6dc693372e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851280476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.3851280476
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.553478845
Short name T442
Test name
Test status
Simulation time 420171063 ps
CPU time 5.38 seconds
Started Jun 10 07:51:58 PM PDT 24
Finished Jun 10 07:52:06 PM PDT 24
Peak memory 248604 kb
Host smart-6f574640-4afc-47fd-a2c8-07562c00749d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=553478845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.553478845
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.4026268999
Short name T1023
Test name
Test status
Simulation time 198909650 ps
CPU time 5.52 seconds
Started Jun 10 07:52:02 PM PDT 24
Finished Jun 10 07:52:10 PM PDT 24
Peak memory 242412 kb
Host smart-d8b5a78b-b4b4-4cb6-a715-1d5071669abc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4026268999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.4026268999
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.4273773281
Short name T1012
Test name
Test status
Simulation time 7603324168 ps
CPU time 13.93 seconds
Started Jun 10 07:52:03 PM PDT 24
Finished Jun 10 07:52:19 PM PDT 24
Peak memory 242504 kb
Host smart-8c7c6075-c801-44e1-bca1-a61d18610f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273773281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.4273773281
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.176676263
Short name T1151
Test name
Test status
Simulation time 12069441487 ps
CPU time 122.56 seconds
Started Jun 10 07:52:02 PM PDT 24
Finished Jun 10 07:54:07 PM PDT 24
Peak memory 246880 kb
Host smart-c03926ed-64a7-48a6-a700-7aa00b88d6f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176676263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.
176676263
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.151900287
Short name T277
Test name
Test status
Simulation time 222152868532 ps
CPU time 363.65 seconds
Started Jun 10 07:52:02 PM PDT 24
Finished Jun 10 07:58:09 PM PDT 24
Peak memory 254584 kb
Host smart-3d15486b-bfad-4cb5-9349-7e41f70aa328
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151900287 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.151900287
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.1282948807
Short name T839
Test name
Test status
Simulation time 366041402 ps
CPU time 7.08 seconds
Started Jun 10 07:52:03 PM PDT 24
Finished Jun 10 07:52:13 PM PDT 24
Peak memory 242004 kb
Host smart-8f12285f-29e4-4514-9db0-4fcd4abf6757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282948807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.1282948807
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.3372988381
Short name T501
Test name
Test status
Simulation time 235428946 ps
CPU time 3.16 seconds
Started Jun 10 07:49:56 PM PDT 24
Finished Jun 10 07:50:02 PM PDT 24
Peak memory 240760 kb
Host smart-7a62f679-e21c-43ca-a9f6-8c0455d77581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372988381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.3372988381
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.824810838
Short name T380
Test name
Test status
Simulation time 2250850295 ps
CPU time 33.56 seconds
Started Jun 10 07:49:54 PM PDT 24
Finished Jun 10 07:50:31 PM PDT 24
Peak memory 242464 kb
Host smart-d1b108b8-1699-4fca-9684-232e44fd4658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824810838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.824810838
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.4164613311
Short name T46
Test name
Test status
Simulation time 3181416489 ps
CPU time 32.37 seconds
Started Jun 10 07:49:53 PM PDT 24
Finished Jun 10 07:50:29 PM PDT 24
Peak memory 242380 kb
Host smart-e2f46964-a7fe-4f50-92f0-79dd47be1284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164613311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.4164613311
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.3512480073
Short name T348
Test name
Test status
Simulation time 5384031263 ps
CPU time 23.38 seconds
Started Jun 10 07:49:56 PM PDT 24
Finished Jun 10 07:50:22 PM PDT 24
Peak memory 242192 kb
Host smart-c7b117c2-7c27-4a02-a079-e7ec3ac7d028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512480073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.3512480073
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.1985186273
Short name T794
Test name
Test status
Simulation time 1583267730 ps
CPU time 15.58 seconds
Started Jun 10 07:49:55 PM PDT 24
Finished Jun 10 07:50:13 PM PDT 24
Peak memory 242780 kb
Host smart-44784897-a766-4f31-8816-fde64b5b48fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985186273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.1985186273
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.104968481
Short name T173
Test name
Test status
Simulation time 1663511973 ps
CPU time 7.01 seconds
Started Jun 10 07:49:53 PM PDT 24
Finished Jun 10 07:50:03 PM PDT 24
Peak memory 242324 kb
Host smart-3999bb21-e0f7-4a08-b946-76ab1b87ce4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104968481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.104968481
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.2796662953
Short name T140
Test name
Test status
Simulation time 3137078141 ps
CPU time 27.65 seconds
Started Jun 10 07:49:56 PM PDT 24
Finished Jun 10 07:50:26 PM PDT 24
Peak memory 242456 kb
Host smart-c52f462c-cc9b-45b4-98f7-80729a990847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796662953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.2796662953
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.1871974669
Short name T893
Test name
Test status
Simulation time 1243519934 ps
CPU time 29.45 seconds
Started Jun 10 07:49:57 PM PDT 24
Finished Jun 10 07:50:28 PM PDT 24
Peak memory 242832 kb
Host smart-81a48777-eb34-460b-9859-db8fa1e17c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871974669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.1871974669
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.1496799540
Short name T1108
Test name
Test status
Simulation time 470237163 ps
CPU time 6.1 seconds
Started Jun 10 07:49:52 PM PDT 24
Finished Jun 10 07:50:02 PM PDT 24
Peak memory 242064 kb
Host smart-f54a3040-2214-45d9-94d4-b9de44a8076a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496799540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.1496799540
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.1141697382
Short name T730
Test name
Test status
Simulation time 877160336 ps
CPU time 24.94 seconds
Started Jun 10 07:49:54 PM PDT 24
Finished Jun 10 07:50:22 PM PDT 24
Peak memory 242148 kb
Host smart-3c05a656-4637-4bab-af7d-eebbb6befa53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1141697382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.1141697382
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.4171333388
Short name T366
Test name
Test status
Simulation time 345056498 ps
CPU time 10.49 seconds
Started Jun 10 07:49:54 PM PDT 24
Finished Jun 10 07:50:08 PM PDT 24
Peak memory 242168 kb
Host smart-bc2f3268-daa6-47c7-b9bb-8b17d8cf593d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4171333388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.4171333388
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.3864266978
Short name T1069
Test name
Test status
Simulation time 573032572 ps
CPU time 8.24 seconds
Started Jun 10 07:49:54 PM PDT 24
Finished Jun 10 07:50:05 PM PDT 24
Peak memory 242308 kb
Host smart-6198eca7-9ec1-41eb-949a-9f365886bbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864266978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.3864266978
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.1119678677
Short name T16
Test name
Test status
Simulation time 92098294399 ps
CPU time 1751.37 seconds
Started Jun 10 07:49:55 PM PDT 24
Finished Jun 10 08:19:10 PM PDT 24
Peak memory 300364 kb
Host smart-3c6ab4e9-204d-4451-86b3-a8a735c57afb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119678677 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.1119678677
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.2355910944
Short name T182
Test name
Test status
Simulation time 1446586835 ps
CPU time 11.3 seconds
Started Jun 10 07:49:53 PM PDT 24
Finished Jun 10 07:50:08 PM PDT 24
Peak memory 242552 kb
Host smart-a27af5fd-8383-4c5c-8c3e-f4532e155b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355910944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.2355910944
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.941383511
Short name T288
Test name
Test status
Simulation time 130404749 ps
CPU time 3.3 seconds
Started Jun 10 07:51:59 PM PDT 24
Finished Jun 10 07:52:05 PM PDT 24
Peak memory 242496 kb
Host smart-9fb9a409-01e9-494e-af7a-b91a5bcf19cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941383511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.941383511
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.3858046295
Short name T862
Test name
Test status
Simulation time 106567658 ps
CPU time 2.72 seconds
Started Jun 10 07:51:58 PM PDT 24
Finished Jun 10 07:52:04 PM PDT 24
Peak memory 242232 kb
Host smart-6733dc3a-c482-498b-ab67-6f7f716f1855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858046295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.3858046295
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.1822676529
Short name T204
Test name
Test status
Simulation time 175639142 ps
CPU time 4.25 seconds
Started Jun 10 07:51:59 PM PDT 24
Finished Jun 10 07:52:06 PM PDT 24
Peak memory 242320 kb
Host smart-03eba2dc-9d26-42c5-8845-b3cdbf4e9fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822676529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.1822676529
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.4168329461
Short name T943
Test name
Test status
Simulation time 1715246543 ps
CPU time 6.87 seconds
Started Jun 10 07:51:56 PM PDT 24
Finished Jun 10 07:52:05 PM PDT 24
Peak memory 242228 kb
Host smart-b178689c-f09d-40a7-b9e3-5b982db49603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168329461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.4168329461
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.3067668537
Short name T336
Test name
Test status
Simulation time 30408635585 ps
CPU time 763.07 seconds
Started Jun 10 07:51:57 PM PDT 24
Finished Jun 10 08:04:42 PM PDT 24
Peak memory 342304 kb
Host smart-591df57a-440b-4923-995c-c4baf6ca69da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067668537 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.3067668537
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.4224058280
Short name T530
Test name
Test status
Simulation time 1676491544 ps
CPU time 4.27 seconds
Started Jun 10 07:52:01 PM PDT 24
Finished Jun 10 07:52:08 PM PDT 24
Peak memory 242412 kb
Host smart-489e4c6e-819e-43f1-9ec6-9932c1679c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224058280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.4224058280
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.1357455187
Short name T623
Test name
Test status
Simulation time 7028822163 ps
CPU time 23.38 seconds
Started Jun 10 07:52:00 PM PDT 24
Finished Jun 10 07:52:27 PM PDT 24
Peak memory 242276 kb
Host smart-cea6b45d-8a93-4277-b53f-e1df9c60614a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357455187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.1357455187
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.975339451
Short name T914
Test name
Test status
Simulation time 1138132899 ps
CPU time 8.82 seconds
Started Jun 10 07:51:58 PM PDT 24
Finished Jun 10 07:52:10 PM PDT 24
Peak memory 242048 kb
Host smart-5d9276b9-3871-4e67-9fde-c3a954b1f448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975339451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.975339451
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.3791959000
Short name T933
Test name
Test status
Simulation time 519367277631 ps
CPU time 4177.19 seconds
Started Jun 10 07:51:58 PM PDT 24
Finished Jun 10 09:01:38 PM PDT 24
Peak memory 664052 kb
Host smart-ea421714-0219-49f1-8cb8-01da42c13906
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791959000 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.3791959000
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.2047972559
Short name T1097
Test name
Test status
Simulation time 592426457 ps
CPU time 5.2 seconds
Started Jun 10 07:52:00 PM PDT 24
Finished Jun 10 07:52:08 PM PDT 24
Peak memory 242364 kb
Host smart-64e0e8f3-f016-47f4-9619-81f4c91f2048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047972559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.2047972559
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.4193638041
Short name T342
Test name
Test status
Simulation time 371508067 ps
CPU time 8.63 seconds
Started Jun 10 07:51:57 PM PDT 24
Finished Jun 10 07:52:08 PM PDT 24
Peak memory 242256 kb
Host smart-c43574c8-a3c0-427a-a20e-0721566cb2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193638041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.4193638041
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.1456655263
Short name T687
Test name
Test status
Simulation time 262419147 ps
CPU time 4.23 seconds
Started Jun 10 07:51:59 PM PDT 24
Finished Jun 10 07:52:06 PM PDT 24
Peak memory 242632 kb
Host smart-a091c407-602e-4b69-9cae-3c7fd3fecba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456655263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.1456655263
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.1104498123
Short name T553
Test name
Test status
Simulation time 3992470321 ps
CPU time 12.52 seconds
Started Jun 10 07:51:59 PM PDT 24
Finished Jun 10 07:52:15 PM PDT 24
Peak memory 242340 kb
Host smart-1804535a-0a52-43bc-95a4-c26c24c0fd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104498123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.1104498123
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.4222619711
Short name T494
Test name
Test status
Simulation time 210875998190 ps
CPU time 1425.84 seconds
Started Jun 10 07:51:56 PM PDT 24
Finished Jun 10 08:15:45 PM PDT 24
Peak memory 282036 kb
Host smart-d229c244-3c52-4499-9b70-2860bc7acc7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222619711 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.4222619711
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.1986713872
Short name T1003
Test name
Test status
Simulation time 2660848839 ps
CPU time 6.4 seconds
Started Jun 10 07:51:58 PM PDT 24
Finished Jun 10 07:52:08 PM PDT 24
Peak memory 242508 kb
Host smart-6c1af1df-3000-40ec-a616-8c0022699f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986713872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.1986713872
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.243860502
Short name T252
Test name
Test status
Simulation time 1434223534 ps
CPU time 28.98 seconds
Started Jun 10 07:51:58 PM PDT 24
Finished Jun 10 07:52:30 PM PDT 24
Peak memory 242552 kb
Host smart-256ea133-5578-4730-bb71-19d525c29b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243860502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.243860502
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.3014673229
Short name T310
Test name
Test status
Simulation time 237479468649 ps
CPU time 1046.02 seconds
Started Jun 10 07:51:59 PM PDT 24
Finished Jun 10 08:09:29 PM PDT 24
Peak memory 281464 kb
Host smart-20751e40-6246-4659-8396-40005c246110
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014673229 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.3014673229
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.509598645
Short name T977
Test name
Test status
Simulation time 438310065 ps
CPU time 4.37 seconds
Started Jun 10 07:51:57 PM PDT 24
Finished Jun 10 07:52:03 PM PDT 24
Peak memory 242360 kb
Host smart-037eb59b-c90e-4a4a-a449-b632585d33b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509598645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.509598645
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.1992626309
Short name T717
Test name
Test status
Simulation time 111931688 ps
CPU time 4.2 seconds
Started Jun 10 07:51:59 PM PDT 24
Finished Jun 10 07:52:07 PM PDT 24
Peak memory 242632 kb
Host smart-892a6c12-8152-4522-8b46-6f5e49f6b61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992626309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.1992626309
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.3923288787
Short name T40
Test name
Test status
Simulation time 228533255 ps
CPU time 3.45 seconds
Started Jun 10 07:51:57 PM PDT 24
Finished Jun 10 07:52:03 PM PDT 24
Peak memory 242380 kb
Host smart-c088ab67-d7a3-41dc-bf13-d757977ab891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923288787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.3923288787
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.1573872298
Short name T242
Test name
Test status
Simulation time 638198768 ps
CPU time 9.93 seconds
Started Jun 10 07:51:59 PM PDT 24
Finished Jun 10 07:52:13 PM PDT 24
Peak memory 242476 kb
Host smart-3317a7b3-300f-44e2-a22f-187b5799dfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573872298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.1573872298
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.3436937508
Short name T17
Test name
Test status
Simulation time 16867887714 ps
CPU time 532.27 seconds
Started Jun 10 07:51:58 PM PDT 24
Finished Jun 10 08:00:52 PM PDT 24
Peak memory 273024 kb
Host smart-9dde3486-f084-4546-94b5-1772bb7ce709
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436937508 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.3436937508
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.2208427602
Short name T138
Test name
Test status
Simulation time 167539585 ps
CPU time 4.33 seconds
Started Jun 10 07:51:59 PM PDT 24
Finished Jun 10 07:52:07 PM PDT 24
Peak memory 242620 kb
Host smart-1efaa920-93dd-44be-a47d-abe7cf7b7d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208427602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.2208427602
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.3321371674
Short name T224
Test name
Test status
Simulation time 4119808627 ps
CPU time 18.59 seconds
Started Jun 10 07:52:00 PM PDT 24
Finished Jun 10 07:52:22 PM PDT 24
Peak memory 242244 kb
Host smart-c0c49d1a-21dc-40cc-8f85-68d17bb8d3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321371674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.3321371674
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.104048091
Short name T707
Test name
Test status
Simulation time 93068140 ps
CPU time 1.81 seconds
Started Jun 10 07:50:02 PM PDT 24
Finished Jun 10 07:50:06 PM PDT 24
Peak memory 240652 kb
Host smart-5bb8d4c2-35d2-4194-82c8-a1eabb69e7af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104048091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.104048091
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.694732373
Short name T1063
Test name
Test status
Simulation time 1542361669 ps
CPU time 24.72 seconds
Started Jun 10 07:49:57 PM PDT 24
Finished Jun 10 07:50:24 PM PDT 24
Peak memory 243196 kb
Host smart-0a2f63d0-a34b-463b-8f71-5367fbe3864a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694732373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.694732373
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.1993382418
Short name T789
Test name
Test status
Simulation time 1681501713 ps
CPU time 10.29 seconds
Started Jun 10 07:49:58 PM PDT 24
Finished Jun 10 07:50:10 PM PDT 24
Peak memory 242256 kb
Host smart-0195e694-66c7-4a3e-8a2b-32884621076c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993382418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.1993382418
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.522904191
Short name T801
Test name
Test status
Simulation time 4252388871 ps
CPU time 38.48 seconds
Started Jun 10 07:49:56 PM PDT 24
Finished Jun 10 07:50:37 PM PDT 24
Peak memory 250768 kb
Host smart-19da7d6c-f283-4979-ae36-67cea9695174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522904191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.522904191
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.352129210
Short name T285
Test name
Test status
Simulation time 28477243355 ps
CPU time 51.68 seconds
Started Jun 10 07:50:01 PM PDT 24
Finished Jun 10 07:50:54 PM PDT 24
Peak memory 242820 kb
Host smart-1f0abfd2-95b2-48d8-9dfc-ff4e92a2eb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352129210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.352129210
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.72461903
Short name T195
Test name
Test status
Simulation time 153184423 ps
CPU time 3.66 seconds
Started Jun 10 07:49:57 PM PDT 24
Finished Jun 10 07:50:03 PM PDT 24
Peak memory 242228 kb
Host smart-124646fc-d779-41d7-b06b-1242dd6d5e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72461903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.72461903
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.2952920873
Short name T712
Test name
Test status
Simulation time 3423460663 ps
CPU time 33.4 seconds
Started Jun 10 07:49:58 PM PDT 24
Finished Jun 10 07:50:33 PM PDT 24
Peak memory 242468 kb
Host smart-9d7b80bc-baef-4f8d-b59f-617a2b66e7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952920873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.2952920873
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.2302575395
Short name T382
Test name
Test status
Simulation time 773956180 ps
CPU time 10.16 seconds
Started Jun 10 07:49:54 PM PDT 24
Finished Jun 10 07:50:07 PM PDT 24
Peak memory 248988 kb
Host smart-d90704e5-f508-418e-b5e5-3b0a369fa822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302575395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.2302575395
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.1200522491
Short name T648
Test name
Test status
Simulation time 1853213852 ps
CPU time 5.02 seconds
Started Jun 10 07:50:01 PM PDT 24
Finished Jun 10 07:50:07 PM PDT 24
Peak memory 242236 kb
Host smart-30e97c1d-2de2-4790-bbfe-cbd1042467f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200522491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.1200522491
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.3081927328
Short name T985
Test name
Test status
Simulation time 1121008436 ps
CPU time 19.84 seconds
Started Jun 10 07:50:00 PM PDT 24
Finished Jun 10 07:50:22 PM PDT 24
Peak memory 242560 kb
Host smart-694dd6bb-9e1d-4e46-8404-77bf5a281ddd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3081927328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.3081927328
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.1963127393
Short name T796
Test name
Test status
Simulation time 212722078 ps
CPU time 4.79 seconds
Started Jun 10 07:49:59 PM PDT 24
Finished Jun 10 07:50:05 PM PDT 24
Peak memory 242076 kb
Host smart-9c50ef39-d987-452a-9edf-f646fdb25851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1963127393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.1963127393
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.113604977
Short name T1187
Test name
Test status
Simulation time 516523228 ps
CPU time 12.15 seconds
Started Jun 10 07:49:55 PM PDT 24
Finished Jun 10 07:50:10 PM PDT 24
Peak memory 242272 kb
Host smart-bf1d74fc-c344-4e7d-9004-ca4b19fdfc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113604977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.113604977
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.2844061316
Short name T764
Test name
Test status
Simulation time 17067567415 ps
CPU time 152.2 seconds
Started Jun 10 07:50:03 PM PDT 24
Finished Jun 10 07:52:37 PM PDT 24
Peak memory 263284 kb
Host smart-2395725d-5cb8-4307-bd17-cc7420f905dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844061316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.
2844061316
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.1974333013
Short name T846
Test name
Test status
Simulation time 212112320991 ps
CPU time 2283.78 seconds
Started Jun 10 07:50:05 PM PDT 24
Finished Jun 10 08:28:11 PM PDT 24
Peak memory 305952 kb
Host smart-e4660c65-278e-481d-b481-d01b211b5555
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974333013 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.1974333013
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.3943352079
Short name T695
Test name
Test status
Simulation time 20604260247 ps
CPU time 31.59 seconds
Started Jun 10 07:50:04 PM PDT 24
Finished Jun 10 07:50:38 PM PDT 24
Peak memory 242800 kb
Host smart-aa6bcc23-f98f-4c39-a9bb-ef6cf20bbf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943352079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.3943352079
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.2655495356
Short name T555
Test name
Test status
Simulation time 334175888 ps
CPU time 4.32 seconds
Started Jun 10 07:52:00 PM PDT 24
Finished Jun 10 07:52:08 PM PDT 24
Peak memory 242372 kb
Host smart-ef87412a-d939-4ce8-a1ca-8ab3ef0a0217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655495356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.2655495356
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.1872697003
Short name T424
Test name
Test status
Simulation time 435764641 ps
CPU time 5.44 seconds
Started Jun 10 07:51:59 PM PDT 24
Finished Jun 10 07:52:07 PM PDT 24
Peak memory 242084 kb
Host smart-c2e55fd5-326f-4323-ae73-4477420301f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872697003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1872697003
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.3403329623
Short name T110
Test name
Test status
Simulation time 1680533397 ps
CPU time 5.83 seconds
Started Jun 10 07:51:59 PM PDT 24
Finished Jun 10 07:52:07 PM PDT 24
Peak memory 242300 kb
Host smart-8e8a1e96-35bd-43a5-95a1-14570433b307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403329623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.3403329623
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.3582226126
Short name T1059
Test name
Test status
Simulation time 319703068 ps
CPU time 7.45 seconds
Started Jun 10 07:52:01 PM PDT 24
Finished Jun 10 07:52:12 PM PDT 24
Peak memory 242504 kb
Host smart-6c9eecb9-5b15-44d3-a9df-4e18e7cc8f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582226126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.3582226126
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.3394588006
Short name T287
Test name
Test status
Simulation time 565279076120 ps
CPU time 3683.58 seconds
Started Jun 10 07:52:02 PM PDT 24
Finished Jun 10 08:53:29 PM PDT 24
Peak memory 531976 kb
Host smart-546bc6da-4b54-4d68-bbbf-07ad0c0d96f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394588006 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.3394588006
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.4044562098
Short name T581
Test name
Test status
Simulation time 140475247 ps
CPU time 5.48 seconds
Started Jun 10 07:51:59 PM PDT 24
Finished Jun 10 07:52:07 PM PDT 24
Peak memory 242176 kb
Host smart-c8b26a9a-70d0-4a83-b529-1a5105495922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044562098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.4044562098
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.178041703
Short name T916
Test name
Test status
Simulation time 599424246992 ps
CPU time 1390.29 seconds
Started Jun 10 07:51:58 PM PDT 24
Finished Jun 10 08:15:12 PM PDT 24
Peak memory 465288 kb
Host smart-dcfda25f-e2b7-4b4d-b6d7-f87580e7d5a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178041703 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.178041703
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.2663338732
Short name T152
Test name
Test status
Simulation time 294351433 ps
CPU time 4.02 seconds
Started Jun 10 07:52:02 PM PDT 24
Finished Jun 10 07:52:09 PM PDT 24
Peak memory 242504 kb
Host smart-1f5952b3-fb0e-4887-8c15-da0c38c32653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663338732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.2663338732
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.1752596396
Short name T900
Test name
Test status
Simulation time 697783917 ps
CPU time 10.01 seconds
Started Jun 10 07:51:59 PM PDT 24
Finished Jun 10 07:52:12 PM PDT 24
Peak memory 242572 kb
Host smart-26766958-8b01-4aa5-b7a6-0bcce5baae30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752596396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.1752596396
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.914346065
Short name T1153
Test name
Test status
Simulation time 38033250391 ps
CPU time 527.62 seconds
Started Jun 10 07:52:00 PM PDT 24
Finished Jun 10 08:00:51 PM PDT 24
Peak memory 249284 kb
Host smart-19d4953d-3f1d-4a69-89de-d9544e32f6cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914346065 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.914346065
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.460492046
Short name T1056
Test name
Test status
Simulation time 1839821143 ps
CPU time 3.26 seconds
Started Jun 10 07:51:59 PM PDT 24
Finished Jun 10 07:52:06 PM PDT 24
Peak memory 242616 kb
Host smart-1c8f3e48-4d3b-429b-bb93-6edf8e8183b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460492046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.460492046
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.4217013316
Short name T1073
Test name
Test status
Simulation time 6606466331 ps
CPU time 23.58 seconds
Started Jun 10 07:52:06 PM PDT 24
Finished Jun 10 07:52:32 PM PDT 24
Peak memory 242396 kb
Host smart-a81fe68e-84db-49c7-869c-4a146ceafaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217013316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.4217013316
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.58966820
Short name T272
Test name
Test status
Simulation time 60805493503 ps
CPU time 859.12 seconds
Started Jun 10 07:52:06 PM PDT 24
Finished Jun 10 08:06:27 PM PDT 24
Peak memory 328744 kb
Host smart-9760b9b1-b017-4c9e-ae97-5c5a44aa5104
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58966820 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.58966820
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.3912344609
Short name T543
Test name
Test status
Simulation time 153604127 ps
CPU time 4.7 seconds
Started Jun 10 07:52:01 PM PDT 24
Finished Jun 10 07:52:09 PM PDT 24
Peak memory 242184 kb
Host smart-8bbeeb3e-5b75-47dd-92d1-3d6975276aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912344609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.3912344609
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.604611016
Short name T709
Test name
Test status
Simulation time 900749162 ps
CPU time 13.76 seconds
Started Jun 10 07:51:59 PM PDT 24
Finished Jun 10 07:52:16 PM PDT 24
Peak memory 242244 kb
Host smart-ad1acd08-1294-4138-9e90-94c225fe1f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604611016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.604611016
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.697178449
Short name T137
Test name
Test status
Simulation time 2932867903 ps
CPU time 5.96 seconds
Started Jun 10 07:52:06 PM PDT 24
Finished Jun 10 07:52:14 PM PDT 24
Peak memory 242440 kb
Host smart-293fb27f-2adf-455f-be0b-ba1bd559edee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697178449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.697178449
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.1345572167
Short name T631
Test name
Test status
Simulation time 141477518 ps
CPU time 6.77 seconds
Started Jun 10 07:52:01 PM PDT 24
Finished Jun 10 07:52:11 PM PDT 24
Peak memory 242020 kb
Host smart-7d19624b-4a25-41f8-a58d-25768fb92eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345572167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.1345572167
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.3510995588
Short name T15
Test name
Test status
Simulation time 749995732267 ps
CPU time 3007.02 seconds
Started Jun 10 07:52:06 PM PDT 24
Finished Jun 10 08:42:16 PM PDT 24
Peak memory 273892 kb
Host smart-eaf7cbb8-5249-4ee7-b59e-be369c116be1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510995588 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.3510995588
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.3279631314
Short name T909
Test name
Test status
Simulation time 1867102972 ps
CPU time 6.19 seconds
Started Jun 10 07:51:57 PM PDT 24
Finished Jun 10 07:52:05 PM PDT 24
Peak memory 242448 kb
Host smart-49829b71-82e7-4d2d-9a49-84cf0f4de875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279631314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.3279631314
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.402157233
Short name T343
Test name
Test status
Simulation time 259187418 ps
CPU time 7.52 seconds
Started Jun 10 07:52:05 PM PDT 24
Finished Jun 10 07:52:14 PM PDT 24
Peak memory 242112 kb
Host smart-7f45a0a5-4395-4a82-bcae-d9b7aef69fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402157233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.402157233
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.1410593586
Short name T592
Test name
Test status
Simulation time 113683621 ps
CPU time 3.99 seconds
Started Jun 10 07:52:10 PM PDT 24
Finished Jun 10 07:52:16 PM PDT 24
Peak memory 242584 kb
Host smart-71095556-2011-4069-8815-dbbad87bb7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410593586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.1410593586
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.854179678
Short name T255
Test name
Test status
Simulation time 216871011 ps
CPU time 8.92 seconds
Started Jun 10 07:52:08 PM PDT 24
Finished Jun 10 07:52:19 PM PDT 24
Peak memory 242216 kb
Host smart-2083a748-709c-49cd-9adf-aa534bd5a6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854179678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.854179678
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.612490448
Short name T13
Test name
Test status
Simulation time 777969305257 ps
CPU time 1416.59 seconds
Started Jun 10 07:52:13 PM PDT 24
Finished Jun 10 08:15:51 PM PDT 24
Peak memory 279880 kb
Host smart-287e9247-444c-4423-9d6e-f35ee5cdc4bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612490448 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.612490448
Directory /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.3765431362
Short name T586
Test name
Test status
Simulation time 239358314 ps
CPU time 4.49 seconds
Started Jun 10 07:52:15 PM PDT 24
Finished Jun 10 07:52:20 PM PDT 24
Peak memory 242564 kb
Host smart-f34a3a1a-3330-45d0-9d4e-2cf849e92e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765431362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.3765431362
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.1720431203
Short name T755
Test name
Test status
Simulation time 901796947 ps
CPU time 24.14 seconds
Started Jun 10 07:52:12 PM PDT 24
Finished Jun 10 07:52:38 PM PDT 24
Peak memory 242152 kb
Host smart-7d5fbeb8-e8e2-4863-aab7-e6a0754b4629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720431203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.1720431203
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.2143605650
Short name T18
Test name
Test status
Simulation time 68525538898 ps
CPU time 1662.07 seconds
Started Jun 10 07:52:09 PM PDT 24
Finished Jun 10 08:19:53 PM PDT 24
Peak memory 335188 kb
Host smart-26b05ae2-a8d8-4c2b-950f-93db7b4850e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143605650 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.2143605650
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.568499492
Short name T493
Test name
Test status
Simulation time 102315590 ps
CPU time 1.86 seconds
Started Jun 10 07:50:02 PM PDT 24
Finished Jun 10 07:50:06 PM PDT 24
Peak memory 240768 kb
Host smart-0dcdac13-48e9-4bb9-a5fa-d548327c33ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568499492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.568499492
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.1581478950
Short name T387
Test name
Test status
Simulation time 2798265327 ps
CPU time 16.24 seconds
Started Jun 10 07:50:05 PM PDT 24
Finished Jun 10 07:50:23 PM PDT 24
Peak memory 242556 kb
Host smart-e112d248-f519-447f-bf8d-dcb0022f2b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581478950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.1581478950
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.1104654204
Short name T1060
Test name
Test status
Simulation time 338733006 ps
CPU time 3.97 seconds
Started Jun 10 07:50:04 PM PDT 24
Finished Jun 10 07:50:10 PM PDT 24
Peak memory 242484 kb
Host smart-10cbf7e4-f2a1-4287-aec5-f6706b74d9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104654204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.1104654204
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.2303538761
Short name T313
Test name
Test status
Simulation time 1246112374 ps
CPU time 17.31 seconds
Started Jun 10 07:50:02 PM PDT 24
Finished Jun 10 07:50:21 PM PDT 24
Peak memory 242316 kb
Host smart-5d183d78-646d-4b04-8d51-ee71896460e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303538761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.2303538761
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.2100117559
Short name T1114
Test name
Test status
Simulation time 584481247 ps
CPU time 8.1 seconds
Started Jun 10 07:50:03 PM PDT 24
Finished Jun 10 07:50:13 PM PDT 24
Peak memory 242184 kb
Host smart-377d1f81-8a4c-4230-965c-6ff6cc332dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100117559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.2100117559
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.3552027108
Short name T474
Test name
Test status
Simulation time 112168846 ps
CPU time 3.87 seconds
Started Jun 10 07:50:01 PM PDT 24
Finished Jun 10 07:50:06 PM PDT 24
Peak memory 242288 kb
Host smart-73427be7-f26c-4f5e-88ac-8b804558ddb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552027108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.3552027108
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.3626100707
Short name T488
Test name
Test status
Simulation time 1717980042 ps
CPU time 20.49 seconds
Started Jun 10 07:50:03 PM PDT 24
Finished Jun 10 07:50:25 PM PDT 24
Peak memory 246168 kb
Host smart-294bd2ce-65e1-4437-a4f3-cbf8e077aac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626100707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.3626100707
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.361193305
Short name T517
Test name
Test status
Simulation time 1188508302 ps
CPU time 11.89 seconds
Started Jun 10 07:50:03 PM PDT 24
Finished Jun 10 07:50:17 PM PDT 24
Peak memory 242428 kb
Host smart-70889216-91c4-4fb9-b258-215abfc2fbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361193305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.361193305
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.1473138525
Short name T743
Test name
Test status
Simulation time 176532154 ps
CPU time 5.14 seconds
Started Jun 10 07:50:03 PM PDT 24
Finished Jun 10 07:50:10 PM PDT 24
Peak memory 242412 kb
Host smart-41ff9505-289e-441c-a9ac-5a29bf6782ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473138525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.1473138525
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.3848869087
Short name T396
Test name
Test status
Simulation time 7101224127 ps
CPU time 17.43 seconds
Started Jun 10 07:50:07 PM PDT 24
Finished Jun 10 07:50:26 PM PDT 24
Peak memory 242196 kb
Host smart-cebb7545-1748-42a3-8369-c8be36f9fa93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3848869087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.3848869087
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.3035807030
Short name T680
Test name
Test status
Simulation time 1122911022 ps
CPU time 9.77 seconds
Started Jun 10 07:50:06 PM PDT 24
Finished Jun 10 07:50:18 PM PDT 24
Peak memory 242200 kb
Host smart-9ded849b-d5a4-4b56-bad5-bb3d4c8cabc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3035807030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.3035807030
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.160331309
Short name T840
Test name
Test status
Simulation time 1095703326 ps
CPU time 7.87 seconds
Started Jun 10 07:50:06 PM PDT 24
Finished Jun 10 07:50:16 PM PDT 24
Peak memory 242080 kb
Host smart-afd167ec-1a20-46cb-8786-81bf06fcf25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160331309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.160331309
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.876833677
Short name T938
Test name
Test status
Simulation time 11233349431 ps
CPU time 60.15 seconds
Started Jun 10 07:50:03 PM PDT 24
Finished Jun 10 07:51:06 PM PDT 24
Peak memory 249136 kb
Host smart-69ebc502-d249-4c02-a5bb-96bcbec7fe0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876833677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.876833677
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.430962510
Short name T705
Test name
Test status
Simulation time 52262127216 ps
CPU time 712.51 seconds
Started Jun 10 07:50:04 PM PDT 24
Finished Jun 10 08:01:58 PM PDT 24
Peak memory 268864 kb
Host smart-2bac4de0-df8b-48ae-9b46-099fc54dc335
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430962510 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.430962510
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.188715697
Short name T440
Test name
Test status
Simulation time 1488439963 ps
CPU time 7.82 seconds
Started Jun 10 07:50:07 PM PDT 24
Finished Jun 10 07:50:17 PM PDT 24
Peak memory 242176 kb
Host smart-f4953f3b-24f3-45c5-be36-a12c3ed33d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188715697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.188715697
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.2697785322
Short name T614
Test name
Test status
Simulation time 1921249658 ps
CPU time 7.57 seconds
Started Jun 10 07:52:10 PM PDT 24
Finished Jun 10 07:52:20 PM PDT 24
Peak memory 242280 kb
Host smart-538639a7-ec81-4e7d-a096-9f1e1cdfbed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697785322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.2697785322
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.4154325490
Short name T1155
Test name
Test status
Simulation time 1645905364 ps
CPU time 26.83 seconds
Started Jun 10 07:52:11 PM PDT 24
Finished Jun 10 07:52:39 PM PDT 24
Peak memory 242236 kb
Host smart-9a075ff0-4287-4feb-9777-0ce7ff263bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154325490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.4154325490
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.4255908215
Short name T281
Test name
Test status
Simulation time 137384918939 ps
CPU time 1507.73 seconds
Started Jun 10 07:52:09 PM PDT 24
Finished Jun 10 08:17:18 PM PDT 24
Peak memory 297932 kb
Host smart-f04406d7-3158-430b-916f-2832555b1dc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255908215 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.4255908215
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.3019390234
Short name T1067
Test name
Test status
Simulation time 273052491 ps
CPU time 4.02 seconds
Started Jun 10 07:52:10 PM PDT 24
Finished Jun 10 07:52:15 PM PDT 24
Peak memory 242248 kb
Host smart-4b5f2b2b-5124-4421-981b-5cba6aaf4450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019390234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.3019390234
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.2005292903
Short name T441
Test name
Test status
Simulation time 336074878 ps
CPU time 8.69 seconds
Started Jun 10 07:52:11 PM PDT 24
Finished Jun 10 07:52:21 PM PDT 24
Peak memory 242680 kb
Host smart-e66d36b7-1e32-44f5-8860-5379e26494c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005292903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.2005292903
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.1346338950
Short name T906
Test name
Test status
Simulation time 74752231703 ps
CPU time 1260.13 seconds
Started Jun 10 07:52:10 PM PDT 24
Finished Jun 10 08:13:12 PM PDT 24
Peak memory 366136 kb
Host smart-8a889323-aca6-4226-a78f-cc91b2d985de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346338950 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.1346338950
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.4075533561
Short name T1051
Test name
Test status
Simulation time 208906472 ps
CPU time 3.92 seconds
Started Jun 10 07:52:13 PM PDT 24
Finished Jun 10 07:52:18 PM PDT 24
Peak memory 242340 kb
Host smart-6aa8a8ca-aa14-46c6-b7b1-fac2c6222454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075533561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.4075533561
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.3397103661
Short name T1182
Test name
Test status
Simulation time 1253414559 ps
CPU time 8.32 seconds
Started Jun 10 07:52:12 PM PDT 24
Finished Jun 10 07:52:22 PM PDT 24
Peak memory 242220 kb
Host smart-d480fd70-eee7-4fdc-a0cd-198359f52142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397103661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.3397103661
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.445699161
Short name T388
Test name
Test status
Simulation time 135888288384 ps
CPU time 1157.19 seconds
Started Jun 10 07:52:15 PM PDT 24
Finished Jun 10 08:11:33 PM PDT 24
Peak memory 392952 kb
Host smart-c57db40d-6aaf-4743-a4dc-7f30e09c85f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445699161 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.445699161
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.162979879
Short name T1032
Test name
Test status
Simulation time 211701556 ps
CPU time 4.16 seconds
Started Jun 10 07:52:08 PM PDT 24
Finished Jun 10 07:52:13 PM PDT 24
Peak memory 242232 kb
Host smart-da78a8ad-8e3c-41a6-ab2d-d1e5299b0a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162979879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.162979879
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.1479526288
Short name T919
Test name
Test status
Simulation time 550265006 ps
CPU time 5.05 seconds
Started Jun 10 07:52:13 PM PDT 24
Finished Jun 10 07:52:19 PM PDT 24
Peak memory 242128 kb
Host smart-f8f5d0ca-4147-4b92-8bbb-3f68fae762d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479526288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.1479526288
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.298520902
Short name T1062
Test name
Test status
Simulation time 2072920127 ps
CPU time 5.16 seconds
Started Jun 10 07:52:12 PM PDT 24
Finished Jun 10 07:52:18 PM PDT 24
Peak memory 242240 kb
Host smart-62d0aa89-e056-4d96-8a08-41cdf27e99a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298520902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.298520902
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.1651412610
Short name T988
Test name
Test status
Simulation time 1030826765 ps
CPU time 6.77 seconds
Started Jun 10 07:52:10 PM PDT 24
Finished Jun 10 07:52:19 PM PDT 24
Peak memory 242212 kb
Host smart-dbdf6b66-4183-4b2b-b049-6341ad61bcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651412610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.1651412610
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.2061473484
Short name T990
Test name
Test status
Simulation time 313621624248 ps
CPU time 686.57 seconds
Started Jun 10 07:52:11 PM PDT 24
Finished Jun 10 08:03:39 PM PDT 24
Peak memory 293676 kb
Host smart-26e6b63c-9de7-4215-a61e-fa0474f7a939
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061473484 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.2061473484
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.3743321174
Short name T74
Test name
Test status
Simulation time 392191216 ps
CPU time 4.42 seconds
Started Jun 10 07:52:12 PM PDT 24
Finished Jun 10 07:52:18 PM PDT 24
Peak memory 242640 kb
Host smart-6fa03e6d-076b-4897-83a4-46594d716ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743321174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.3743321174
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.439833838
Short name T885
Test name
Test status
Simulation time 229312063 ps
CPU time 5.97 seconds
Started Jun 10 07:52:09 PM PDT 24
Finished Jun 10 07:52:17 PM PDT 24
Peak memory 242072 kb
Host smart-4cf4d524-73dc-49ac-b8e0-0d2a4fd20ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439833838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.439833838
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.2017459481
Short name T123
Test name
Test status
Simulation time 357574076020 ps
CPU time 897.26 seconds
Started Jun 10 07:52:10 PM PDT 24
Finished Jun 10 08:07:09 PM PDT 24
Peak memory 314608 kb
Host smart-fae63a05-62c3-484a-9c48-fee9d4c07269
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017459481 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.2017459481
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.2946308087
Short name T949
Test name
Test status
Simulation time 2479776162 ps
CPU time 5.27 seconds
Started Jun 10 07:52:14 PM PDT 24
Finished Jun 10 07:52:20 PM PDT 24
Peak memory 242684 kb
Host smart-b270a35b-b79c-42fd-a822-d1852c576a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946308087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.2946308087
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.2802663407
Short name T1087
Test name
Test status
Simulation time 639139962 ps
CPU time 10.43 seconds
Started Jun 10 07:52:13 PM PDT 24
Finished Jun 10 07:52:24 PM PDT 24
Peak memory 242176 kb
Host smart-497ea855-54bb-4b11-a033-9b75cdc296be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802663407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.2802663407
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.3086254193
Short name T520
Test name
Test status
Simulation time 416722623 ps
CPU time 3.48 seconds
Started Jun 10 07:52:15 PM PDT 24
Finished Jun 10 07:52:19 PM PDT 24
Peak memory 242508 kb
Host smart-fb8249c3-e0ac-41fa-95e3-d8bfd3e1c6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086254193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.3086254193
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.904583509
Short name T280
Test name
Test status
Simulation time 138278490290 ps
CPU time 773.25 seconds
Started Jun 10 07:52:09 PM PDT 24
Finished Jun 10 08:05:03 PM PDT 24
Peak memory 300792 kb
Host smart-73d26fef-44ca-44ba-846c-40b524da73a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904583509 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.904583509
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.12304162
Short name T94
Test name
Test status
Simulation time 511503049 ps
CPU time 6.53 seconds
Started Jun 10 07:52:12 PM PDT 24
Finished Jun 10 07:52:20 PM PDT 24
Peak memory 242060 kb
Host smart-f9c2ce0d-ae7d-481c-9ca3-63e6aacb8bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12304162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.12304162
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.298420787
Short name T858
Test name
Test status
Simulation time 341262394052 ps
CPU time 631.12 seconds
Started Jun 10 07:52:13 PM PDT 24
Finished Jun 10 08:02:45 PM PDT 24
Peak memory 325424 kb
Host smart-505fe7ed-a58b-45ea-9f9e-5a98c7490843
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298420787 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.298420787
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.1877985669
Short name T897
Test name
Test status
Simulation time 150015365 ps
CPU time 4.04 seconds
Started Jun 10 07:52:13 PM PDT 24
Finished Jun 10 07:52:18 PM PDT 24
Peak memory 242272 kb
Host smart-70d8ee90-3ce1-4e4c-860e-9a2be4dd02b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877985669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.1877985669
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.3457537321
Short name T344
Test name
Test status
Simulation time 219089434 ps
CPU time 11.13 seconds
Started Jun 10 07:52:13 PM PDT 24
Finished Jun 10 07:52:26 PM PDT 24
Peak memory 242484 kb
Host smart-0be9ab6f-6da0-4262-8a1c-26d4ef90870d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457537321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.3457537321
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.632729492
Short name T456
Test name
Test status
Simulation time 179530641 ps
CPU time 1.77 seconds
Started Jun 10 07:50:04 PM PDT 24
Finished Jun 10 07:50:08 PM PDT 24
Peak memory 240816 kb
Host smart-20c06593-e2f1-4ae4-ba36-c6cd94528ffc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632729492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.632729492
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.3530223070
Short name T1189
Test name
Test status
Simulation time 668600197 ps
CPU time 14.28 seconds
Started Jun 10 07:50:03 PM PDT 24
Finished Jun 10 07:50:20 PM PDT 24
Peak memory 242624 kb
Host smart-720583c3-97bd-45a8-ba1b-aae1c43ff65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530223070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.3530223070
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.2289196107
Short name T1169
Test name
Test status
Simulation time 738242895 ps
CPU time 9.7 seconds
Started Jun 10 07:50:03 PM PDT 24
Finished Jun 10 07:50:15 PM PDT 24
Peak memory 242276 kb
Host smart-16994f4c-614e-4425-9b09-6e54513c5508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289196107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.2289196107
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.896162195
Short name T752
Test name
Test status
Simulation time 11965827182 ps
CPU time 21.4 seconds
Started Jun 10 07:50:03 PM PDT 24
Finished Jun 10 07:50:27 PM PDT 24
Peak memory 243928 kb
Host smart-c4afedcd-b0e2-4472-80f6-39daf29dfe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896162195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.896162195
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.1761991469
Short name T1093
Test name
Test status
Simulation time 2039641016 ps
CPU time 7.34 seconds
Started Jun 10 07:50:02 PM PDT 24
Finished Jun 10 07:50:11 PM PDT 24
Peak memory 242136 kb
Host smart-c37269bc-4a6b-4dfe-9af9-a8485554f16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761991469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.1761991469
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.2782679199
Short name T141
Test name
Test status
Simulation time 15148968062 ps
CPU time 50.49 seconds
Started Jun 10 07:50:05 PM PDT 24
Finished Jun 10 07:50:58 PM PDT 24
Peak memory 246252 kb
Host smart-dbdf200b-bb96-422d-afef-f5725d8be674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782679199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.2782679199
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.1227425350
Short name T1159
Test name
Test status
Simulation time 1465755157 ps
CPU time 19.88 seconds
Started Jun 10 07:50:06 PM PDT 24
Finished Jun 10 07:50:27 PM PDT 24
Peak memory 242912 kb
Host smart-b56c138e-236a-4572-908d-0064a0e305c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227425350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.1227425350
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.1862235821
Short name T682
Test name
Test status
Simulation time 2241742576 ps
CPU time 17 seconds
Started Jun 10 07:50:02 PM PDT 24
Finished Jun 10 07:50:21 PM PDT 24
Peak memory 242268 kb
Host smart-fc94b08b-5189-47ce-a4e4-a9444c428bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862235821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.1862235821
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.738783689
Short name T576
Test name
Test status
Simulation time 2900239733 ps
CPU time 27.48 seconds
Started Jun 10 07:50:01 PM PDT 24
Finished Jun 10 07:50:30 PM PDT 24
Peak memory 242324 kb
Host smart-5b7b1321-594a-4e1e-a9db-e45d9a28775b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=738783689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.738783689
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.649869107
Short name T610
Test name
Test status
Simulation time 3942108785 ps
CPU time 9.68 seconds
Started Jun 10 07:50:02 PM PDT 24
Finished Jun 10 07:50:14 PM PDT 24
Peak memory 242408 kb
Host smart-d98c74c4-5209-4a14-bf26-edc3f03e193a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=649869107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.649869107
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.2867546944
Short name T843
Test name
Test status
Simulation time 389436793 ps
CPU time 7.45 seconds
Started Jun 10 07:50:01 PM PDT 24
Finished Jun 10 07:50:10 PM PDT 24
Peak memory 242148 kb
Host smart-bb14b887-de9c-4730-abf6-02f113359460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867546944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.2867546944
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.2056696143
Short name T1065
Test name
Test status
Simulation time 881241254106 ps
CPU time 1299.65 seconds
Started Jun 10 07:50:04 PM PDT 24
Finished Jun 10 08:11:46 PM PDT 24
Peak memory 298440 kb
Host smart-f39220a8-9927-4eac-8395-40c0a7724fa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056696143 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.2056696143
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.3859316732
Short name T1064
Test name
Test status
Simulation time 7663791710 ps
CPU time 27.64 seconds
Started Jun 10 07:50:04 PM PDT 24
Finished Jun 10 07:50:34 PM PDT 24
Peak memory 242772 kb
Host smart-ed406d20-1dea-4667-92ef-8f399b3e455d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859316732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.3859316732
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.3722217199
Short name T511
Test name
Test status
Simulation time 122067337 ps
CPU time 3.41 seconds
Started Jun 10 07:52:13 PM PDT 24
Finished Jun 10 07:52:17 PM PDT 24
Peak memory 242632 kb
Host smart-c01b01c3-a2ce-457b-8669-2233ba8bae95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722217199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.3722217199
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.3884223849
Short name T711
Test name
Test status
Simulation time 123932726 ps
CPU time 4.97 seconds
Started Jun 10 07:52:10 PM PDT 24
Finished Jun 10 07:52:17 PM PDT 24
Peak memory 242004 kb
Host smart-9caadb09-000b-4d0b-88ea-17af0325c1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884223849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.3884223849
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.1419903076
Short name T876
Test name
Test status
Simulation time 57815531053 ps
CPU time 1346.22 seconds
Started Jun 10 07:52:15 PM PDT 24
Finished Jun 10 08:14:43 PM PDT 24
Peak memory 287508 kb
Host smart-ceff9c03-e6cb-4b17-8ae0-4a0636de8fb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419903076 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.1419903076
Directory /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.4007495573
Short name T753
Test name
Test status
Simulation time 2424650202 ps
CPU time 17.21 seconds
Started Jun 10 07:52:19 PM PDT 24
Finished Jun 10 07:52:38 PM PDT 24
Peak memory 242276 kb
Host smart-5062c6be-3804-4792-a08e-f1fdf911b6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007495573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.4007495573
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.3175256181
Short name T283
Test name
Test status
Simulation time 71031431221 ps
CPU time 575.17 seconds
Started Jun 10 07:52:20 PM PDT 24
Finished Jun 10 08:01:57 PM PDT 24
Peak memory 264304 kb
Host smart-c60247e8-6083-438b-92c0-57aef4b46702
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175256181 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.3175256181
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.186625674
Short name T177
Test name
Test status
Simulation time 2135077817 ps
CPU time 4.77 seconds
Started Jun 10 07:52:22 PM PDT 24
Finished Jun 10 07:52:30 PM PDT 24
Peak memory 242284 kb
Host smart-40ee11f7-5aa2-492a-a69c-81079feeaa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186625674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.186625674
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.1369437669
Short name T335
Test name
Test status
Simulation time 1476875212 ps
CPU time 12.67 seconds
Started Jun 10 07:52:21 PM PDT 24
Finished Jun 10 07:52:37 PM PDT 24
Peak memory 242664 kb
Host smart-2ad9ba3e-96e1-45ff-bbfb-49e3c0abc153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369437669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.1369437669
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.940271682
Short name T1112
Test name
Test status
Simulation time 60815337543 ps
CPU time 1454.96 seconds
Started Jun 10 07:52:21 PM PDT 24
Finished Jun 10 08:16:40 PM PDT 24
Peak memory 290680 kb
Host smart-08938f86-a019-4d25-b2cb-dd498d5da5d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940271682 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.940271682
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.3585693504
Short name T523
Test name
Test status
Simulation time 2048684022 ps
CPU time 7.24 seconds
Started Jun 10 07:52:22 PM PDT 24
Finished Jun 10 07:52:33 PM PDT 24
Peak memory 242148 kb
Host smart-f1616e03-3d5e-4626-85e4-733c6069291f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585693504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.3585693504
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.964068740
Short name T1131
Test name
Test status
Simulation time 1277079037 ps
CPU time 17.86 seconds
Started Jun 10 07:52:21 PM PDT 24
Finished Jun 10 07:52:42 PM PDT 24
Peak memory 242468 kb
Host smart-82754544-ce8b-4a64-8fd0-b8a678d3976f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964068740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.964068740
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.1632688028
Short name T467
Test name
Test status
Simulation time 448681560 ps
CPU time 4.11 seconds
Started Jun 10 07:52:22 PM PDT 24
Finished Jun 10 07:52:29 PM PDT 24
Peak memory 242580 kb
Host smart-30a607f4-f816-4e49-9809-efafa43a1355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632688028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.1632688028
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.1235075985
Short name T763
Test name
Test status
Simulation time 9696936241 ps
CPU time 34.46 seconds
Started Jun 10 07:52:21 PM PDT 24
Finished Jun 10 07:52:59 PM PDT 24
Peak memory 242312 kb
Host smart-e905ff51-10c3-4cc7-abd7-de8176834b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235075985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.1235075985
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.403673358
Short name T1118
Test name
Test status
Simulation time 112801008 ps
CPU time 3.33 seconds
Started Jun 10 07:52:21 PM PDT 24
Finished Jun 10 07:52:28 PM PDT 24
Peak memory 242328 kb
Host smart-59d9185e-8c05-4de2-9fb7-5f2a511a7bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403673358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.403673358
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.2894239774
Short name T339
Test name
Test status
Simulation time 99650541804 ps
CPU time 1235.75 seconds
Started Jun 10 07:52:22 PM PDT 24
Finished Jun 10 08:13:01 PM PDT 24
Peak memory 310788 kb
Host smart-1cb181df-179c-4d12-9099-701650e710fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894239774 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.2894239774
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.1325259784
Short name T1143
Test name
Test status
Simulation time 146753095 ps
CPU time 4.23 seconds
Started Jun 10 07:52:19 PM PDT 24
Finished Jun 10 07:52:25 PM PDT 24
Peak memory 242348 kb
Host smart-33e89fbf-4f10-4a54-a5b2-83eef8bb4bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325259784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.1325259784
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.3324239935
Short name T1158
Test name
Test status
Simulation time 164504104 ps
CPU time 4.19 seconds
Started Jun 10 07:52:21 PM PDT 24
Finished Jun 10 07:52:28 PM PDT 24
Peak memory 242228 kb
Host smart-6b7d3c68-fae6-45b4-a07d-9622a939019f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324239935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.3324239935
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.1724184282
Short name T1040
Test name
Test status
Simulation time 901530239 ps
CPU time 6.64 seconds
Started Jun 10 07:52:25 PM PDT 24
Finished Jun 10 07:52:34 PM PDT 24
Peak memory 242288 kb
Host smart-9d7e790f-6778-4d38-a867-c5cee8fbb785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724184282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.1724184282
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.1091405266
Short name T385
Test name
Test status
Simulation time 98895628106 ps
CPU time 851.83 seconds
Started Jun 10 07:52:22 PM PDT 24
Finished Jun 10 08:06:37 PM PDT 24
Peak memory 342872 kb
Host smart-e0f6bbb1-3d4f-4326-9968-c0feb28998d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091405266 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.1091405266
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.2668599780
Short name T296
Test name
Test status
Simulation time 413933048 ps
CPU time 4.49 seconds
Started Jun 10 07:52:22 PM PDT 24
Finished Jun 10 07:52:30 PM PDT 24
Peak memory 242080 kb
Host smart-2a6d63b4-296f-48f1-9b9c-a02f8d023f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668599780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.2668599780
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.2754927404
Short name T1147
Test name
Test status
Simulation time 221506503 ps
CPU time 3.42 seconds
Started Jun 10 07:52:21 PM PDT 24
Finished Jun 10 07:52:28 PM PDT 24
Peak memory 242436 kb
Host smart-8a96f59b-cc75-4600-bdbf-ffd3e688c7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754927404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.2754927404
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.1866796813
Short name T1183
Test name
Test status
Simulation time 313846850 ps
CPU time 4.5 seconds
Started Jun 10 07:52:21 PM PDT 24
Finished Jun 10 07:52:29 PM PDT 24
Peak memory 242432 kb
Host smart-134dfdce-f6d4-451b-a796-3ebd8cb5c9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866796813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.1866796813
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.1923105201
Short name T284
Test name
Test status
Simulation time 1002556939869 ps
CPU time 2406.55 seconds
Started Jun 10 07:52:21 PM PDT 24
Finished Jun 10 08:32:31 PM PDT 24
Peak memory 614092 kb
Host smart-1ee91e52-a333-451e-85ad-85cb71dd3216
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923105201 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.1923105201
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.2165389285
Short name T409
Test name
Test status
Simulation time 152282650 ps
CPU time 2.08 seconds
Started Jun 10 07:50:14 PM PDT 24
Finished Jun 10 07:50:18 PM PDT 24
Peak memory 240848 kb
Host smart-7d5f0ddf-f32b-40f7-9649-1a0379ee95d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165389285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.2165389285
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.912132461
Short name T1127
Test name
Test status
Simulation time 23796663431 ps
CPU time 42.79 seconds
Started Jun 10 07:50:03 PM PDT 24
Finished Jun 10 07:50:48 PM PDT 24
Peak memory 243004 kb
Host smart-cd200556-c145-475e-9984-411fa5106ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912132461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.912132461
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.1489406341
Short name T751
Test name
Test status
Simulation time 3309746596 ps
CPU time 30.98 seconds
Started Jun 10 07:50:15 PM PDT 24
Finished Jun 10 07:50:48 PM PDT 24
Peak memory 245460 kb
Host smart-83d4044f-f53a-4027-b66b-5ff72242eae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489406341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.1489406341
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.2522378603
Short name T524
Test name
Test status
Simulation time 10400217174 ps
CPU time 19.82 seconds
Started Jun 10 07:50:14 PM PDT 24
Finished Jun 10 07:50:35 PM PDT 24
Peak memory 242996 kb
Host smart-54c50d45-e239-49fa-a1b1-7e230723244d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522378603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.2522378603
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.2263285113
Short name T782
Test name
Test status
Simulation time 299122546 ps
CPU time 3.97 seconds
Started Jun 10 07:50:03 PM PDT 24
Finished Jun 10 07:50:09 PM PDT 24
Peak memory 242532 kb
Host smart-59deb6ff-4aee-48c8-a8b6-2934098fedbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263285113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.2263285113
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.1359997118
Short name T190
Test name
Test status
Simulation time 13320762524 ps
CPU time 37.11 seconds
Started Jun 10 07:50:15 PM PDT 24
Finished Jun 10 07:50:54 PM PDT 24
Peak memory 248364 kb
Host smart-b8ca0d88-8f47-4620-939d-613e3c5204a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359997118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.1359997118
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.2908637329
Short name T1111
Test name
Test status
Simulation time 1270825006 ps
CPU time 27.07 seconds
Started Jun 10 07:50:15 PM PDT 24
Finished Jun 10 07:50:44 PM PDT 24
Peak memory 248992 kb
Host smart-cd3c7534-bf02-4373-aef6-14b1a3c64c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908637329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.2908637329
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.1450987368
Short name T221
Test name
Test status
Simulation time 205097796 ps
CPU time 6.15 seconds
Started Jun 10 07:50:17 PM PDT 24
Finished Jun 10 07:50:25 PM PDT 24
Peak memory 242612 kb
Host smart-4bad8af7-73f2-4eb6-8b43-e694e65bdd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450987368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.1450987368
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.458398369
Short name T953
Test name
Test status
Simulation time 1621805982 ps
CPU time 11.01 seconds
Started Jun 10 07:50:02 PM PDT 24
Finished Jun 10 07:50:15 PM PDT 24
Peak memory 242116 kb
Host smart-4f41a2f0-b6d5-446d-97c0-153a9b83e1da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=458398369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.458398369
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.3715666461
Short name T684
Test name
Test status
Simulation time 334506396 ps
CPU time 3.08 seconds
Started Jun 10 07:50:15 PM PDT 24
Finished Jun 10 07:50:21 PM PDT 24
Peak memory 242228 kb
Host smart-c01b1101-c4c8-4f98-8113-614507397a9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3715666461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.3715666461
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.3855566290
Short name T425
Test name
Test status
Simulation time 4157688012 ps
CPU time 12 seconds
Started Jun 10 07:50:02 PM PDT 24
Finished Jun 10 07:50:16 PM PDT 24
Peak memory 243000 kb
Host smart-17431527-7839-4223-a251-8edd74c6fb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855566290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.3855566290
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.254451504
Short name T1130
Test name
Test status
Simulation time 27242030044 ps
CPU time 82.74 seconds
Started Jun 10 07:50:17 PM PDT 24
Finished Jun 10 07:51:42 PM PDT 24
Peak memory 247676 kb
Host smart-02c66977-db80-46bc-b0fc-801568196356
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254451504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.254451504
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.1659043768
Short name T673
Test name
Test status
Simulation time 40046317433 ps
CPU time 566.76 seconds
Started Jun 10 07:50:14 PM PDT 24
Finished Jun 10 07:59:43 PM PDT 24
Peak memory 295592 kb
Host smart-77306a08-4655-41f2-b2c1-0b0a0f475859
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659043768 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.1659043768
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.2670678003
Short name T274
Test name
Test status
Simulation time 685753161 ps
CPU time 18.28 seconds
Started Jun 10 07:50:15 PM PDT 24
Finished Jun 10 07:50:36 PM PDT 24
Peak memory 242500 kb
Host smart-3fb6878d-d710-48f8-8275-eeb8e5d6676a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670678003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.2670678003
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.2420236815
Short name T430
Test name
Test status
Simulation time 289922511 ps
CPU time 4.31 seconds
Started Jun 10 07:52:20 PM PDT 24
Finished Jun 10 07:52:26 PM PDT 24
Peak memory 242436 kb
Host smart-49b48469-5868-4f26-9558-1210e00c4eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420236815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.2420236815
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.2789452847
Short name T618
Test name
Test status
Simulation time 2124884913 ps
CPU time 5.93 seconds
Started Jun 10 07:52:26 PM PDT 24
Finished Jun 10 07:52:34 PM PDT 24
Peak memory 242608 kb
Host smart-dd12cc5f-f211-4470-bca3-be8f437cc6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789452847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.2789452847
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.2100493512
Short name T270
Test name
Test status
Simulation time 335900344686 ps
CPU time 954.01 seconds
Started Jun 10 07:52:25 PM PDT 24
Finished Jun 10 08:08:22 PM PDT 24
Peak memory 260444 kb
Host smart-ebd6301b-d5ef-4ea8-8fff-232bf7ed36a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100493512 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.2100493512
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.790722606
Short name T64
Test name
Test status
Simulation time 127616311 ps
CPU time 4.41 seconds
Started Jun 10 07:52:29 PM PDT 24
Finished Jun 10 07:52:35 PM PDT 24
Peak memory 242452 kb
Host smart-e03373e4-c7f6-42f5-9db2-7bc307a3c776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790722606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.790722606
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.4133056218
Short name T958
Test name
Test status
Simulation time 305556525 ps
CPU time 7.41 seconds
Started Jun 10 07:52:24 PM PDT 24
Finished Jun 10 07:52:34 PM PDT 24
Peak memory 242152 kb
Host smart-5a92848b-4858-4b53-b5d7-472d1b797315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133056218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.4133056218
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.856436740
Short name T1144
Test name
Test status
Simulation time 477829582 ps
CPU time 4.29 seconds
Started Jun 10 07:52:21 PM PDT 24
Finished Jun 10 07:52:28 PM PDT 24
Peak memory 242488 kb
Host smart-433841b2-d47b-45fe-ae09-c9188ee7e2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856436740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.856436740
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.3730817109
Short name T1168
Test name
Test status
Simulation time 1071472404 ps
CPU time 12.77 seconds
Started Jun 10 07:52:22 PM PDT 24
Finished Jun 10 07:52:38 PM PDT 24
Peak memory 242224 kb
Host smart-f6c902c9-fb31-4cb7-a739-0ae8ff1588fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730817109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.3730817109
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.4025747090
Short name T205
Test name
Test status
Simulation time 232631334 ps
CPU time 4.29 seconds
Started Jun 10 07:52:22 PM PDT 24
Finished Jun 10 07:52:30 PM PDT 24
Peak memory 242324 kb
Host smart-1ae4eca7-9913-4124-987b-13d7d4a1793b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025747090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.4025747090
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.2882221156
Short name T235
Test name
Test status
Simulation time 841733071 ps
CPU time 8.73 seconds
Started Jun 10 07:52:22 PM PDT 24
Finished Jun 10 07:52:34 PM PDT 24
Peak memory 242320 kb
Host smart-361ccf7b-beaa-46b9-b0f3-e1cda961bad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882221156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.2882221156
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.3780137037
Short name T1053
Test name
Test status
Simulation time 32276655879 ps
CPU time 298.16 seconds
Started Jun 10 07:52:20 PM PDT 24
Finished Jun 10 07:57:20 PM PDT 24
Peak memory 264784 kb
Host smart-3a46c232-d574-49ab-84e3-8ef497eedecd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780137037 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.3780137037
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.1047564066
Short name T996
Test name
Test status
Simulation time 445818983 ps
CPU time 4.54 seconds
Started Jun 10 07:52:26 PM PDT 24
Finished Jun 10 07:52:33 PM PDT 24
Peak memory 242604 kb
Host smart-1f205bdb-91ca-4749-9b16-baf77affb16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047564066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.1047564066
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.1352385922
Short name T225
Test name
Test status
Simulation time 462884254 ps
CPU time 13.36 seconds
Started Jun 10 07:52:25 PM PDT 24
Finished Jun 10 07:52:41 PM PDT 24
Peak memory 242148 kb
Host smart-ea7b097e-ca97-4c81-87c0-1090a100c87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352385922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.1352385922
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.4052050780
Short name T301
Test name
Test status
Simulation time 865113874043 ps
CPU time 2752.86 seconds
Started Jun 10 07:52:20 PM PDT 24
Finished Jun 10 08:38:17 PM PDT 24
Peak memory 387468 kb
Host smart-20318aa4-6767-4dca-8aff-d3082fb13897
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052050780 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.4052050780
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.3552138380
Short name T894
Test name
Test status
Simulation time 128696955 ps
CPU time 3.87 seconds
Started Jun 10 07:52:27 PM PDT 24
Finished Jun 10 07:52:33 PM PDT 24
Peak memory 242312 kb
Host smart-d601511d-bc7c-4566-ba9a-629563fdc757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552138380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.3552138380
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.2581538557
Short name T341
Test name
Test status
Simulation time 9410039421 ps
CPU time 18.39 seconds
Started Jun 10 07:52:21 PM PDT 24
Finished Jun 10 07:52:42 PM PDT 24
Peak memory 242656 kb
Host smart-1acd5ba2-7647-4f50-84b8-b76d637dae89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581538557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.2581538557
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.148930696
Short name T890
Test name
Test status
Simulation time 102862033 ps
CPU time 4.29 seconds
Started Jun 10 07:52:32 PM PDT 24
Finished Jun 10 07:52:39 PM PDT 24
Peak memory 242476 kb
Host smart-ce68f90d-9910-4f2d-86e1-808cc6a7148b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148930696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.148930696
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.2739371276
Short name T232
Test name
Test status
Simulation time 464022252 ps
CPU time 3.59 seconds
Started Jun 10 07:52:28 PM PDT 24
Finished Jun 10 07:52:33 PM PDT 24
Peak memory 242200 kb
Host smart-4b2542db-a1da-45b2-b60e-0dd3b7cac319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739371276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.2739371276
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.1497872484
Short name T331
Test name
Test status
Simulation time 237018721455 ps
CPU time 3260.91 seconds
Started Jun 10 07:52:31 PM PDT 24
Finished Jun 10 08:46:55 PM PDT 24
Peak memory 330340 kb
Host smart-f3926017-5865-4d40-827e-761f04f25115
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497872484 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.1497872484
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.2584356562
Short name T1041
Test name
Test status
Simulation time 282444755 ps
CPU time 4.46 seconds
Started Jun 10 07:52:30 PM PDT 24
Finished Jun 10 07:52:37 PM PDT 24
Peak memory 242388 kb
Host smart-42a12dd7-f9c9-4efc-aeaf-25da570e3a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584356562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.2584356562
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.2367252960
Short name T483
Test name
Test status
Simulation time 452658086 ps
CPU time 9.66 seconds
Started Jun 10 07:52:29 PM PDT 24
Finished Jun 10 07:52:41 PM PDT 24
Peak memory 242456 kb
Host smart-d48e29bd-2cca-4990-9cb2-d1e868cebb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367252960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.2367252960
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.4244857813
Short name T928
Test name
Test status
Simulation time 109324360793 ps
CPU time 717.99 seconds
Started Jun 10 07:52:29 PM PDT 24
Finished Jun 10 08:04:29 PM PDT 24
Peak memory 276856 kb
Host smart-7c70405e-d271-4dec-941c-9eec1b56e9df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244857813 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.4244857813
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.2305479130
Short name T1096
Test name
Test status
Simulation time 1657479638 ps
CPU time 5.04 seconds
Started Jun 10 07:52:30 PM PDT 24
Finished Jun 10 07:52:37 PM PDT 24
Peak memory 242328 kb
Host smart-58468649-3da8-48d4-9e9a-91c9b45e0c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305479130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.2305479130
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.3823121884
Short name T448
Test name
Test status
Simulation time 299805550 ps
CPU time 17.2 seconds
Started Jun 10 07:52:29 PM PDT 24
Finished Jun 10 07:52:49 PM PDT 24
Peak memory 242052 kb
Host smart-2678bc54-9f10-47ec-829c-420e98178188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823121884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.3823121884
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.1693829815
Short name T302
Test name
Test status
Simulation time 1408088162082 ps
CPU time 2333.13 seconds
Started Jun 10 07:52:29 PM PDT 24
Finished Jun 10 08:31:24 PM PDT 24
Peak memory 333604 kb
Host smart-cf182804-7c79-40ba-afe7-3af5866ad3e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693829815 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.1693829815
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.1096969810
Short name T986
Test name
Test status
Simulation time 174377000 ps
CPU time 4.67 seconds
Started Jun 10 07:52:30 PM PDT 24
Finished Jun 10 07:52:37 PM PDT 24
Peak memory 242368 kb
Host smart-006ca7c4-0680-40bd-a404-484a66f99a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096969810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.1096969810
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.3592951884
Short name T598
Test name
Test status
Simulation time 394659454 ps
CPU time 4.3 seconds
Started Jun 10 07:52:29 PM PDT 24
Finished Jun 10 07:52:36 PM PDT 24
Peak memory 242220 kb
Host smart-1683a62c-96c6-4a56-87e8-10bf06938fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592951884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.3592951884
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest
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