Group : tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
flash_addr_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
flash_addr_req_during_lc_esc 2 0 2 100.00 100 1 1 0
flash_addr_req_during_otbn_req 2 0 2 100.00 100 1 1 2
flash_addr_req_during_otp_idle 2 0 2 100.00 100 1 1 2
flash_addr_req_during_sram_0_req 2 0 2 100.00 100 1 1 2
flash_addr_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable flash_addr_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11578 1 T2 15 T3 22 T4 24
auto[1] 1844 1 T2 15 T4 24 T6 6



Summary for Variable flash_addr_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for flash_addr_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 13389 1 T2 30 T3 22 T4 48
lc_esc_on 33 1 T10 1 T376 1 T377 1



Summary for Variable flash_addr_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12493 1 T2 30 T3 22 T4 48
auto[1] 929 1 T6 16 T12 12 T13 6



Summary for Variable flash_addr_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1870 1 T2 12 T4 9 T6 6
auto[1] 11552 1 T2 18 T3 22 T4 39



Summary for Variable flash_addr_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12599 1 T2 30 T3 22 T4 48
auto[1] 823 1 T6 20 T12 19 T13 10



Summary for Variable flash_addr_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12890 1 T2 30 T3 22 T4 48
auto[1] 532 1 T12 16 T13 12 T102 1

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