Group : tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg
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Group : tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv


Summary for Group tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 0 14 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
lc_prog_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
lc_prog_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
lc_prog_req_during_lc_esc 2 0 2 100.00 100 1 1 0
lc_prog_req_during_otbn_req 2 0 2 100.00 100 1 1 2
lc_prog_req_during_otp_idle 2 0 2 100.00 100 1 1 2
lc_prog_req_during_sram_0_req 2 0 2 100.00 100 1 1 2
lc_prog_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable lc_prog_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_prog_req_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29891 1 T2 1487 T3 20 T4 371
auto[1] 883 1 T2 39 T4 5 T6 6


Summary for Variable lc_prog_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_prog_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29659 1 T2 1437 T3 20 T4 367
auto[1] 1115 1 T2 89 T4 9 T6 6


Summary for Variable lc_prog_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for lc_prog_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 30737 1 T2 1526 T3 20 T4 376
lc_esc_on 37 1 T6 1 T144 1 T237 1


Summary for Variable lc_prog_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_prog_req_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28752 1 T2 1337 T3 20 T4 359
auto[1] 2022 1 T2 189 T4 17 T6 7


Summary for Variable lc_prog_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_prog_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 16327 1 T2 764 T3 10 T4 188
auto[1] 14447 1 T2 762 T3 10 T4 188


Summary for Variable lc_prog_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_prog_req_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28640 1 T2 1269 T3 20 T4 356
auto[1] 2134 1 T2 257 T4 20 T6 7


Summary for Variable lc_prog_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_prog_req_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28767 1 T2 1297 T3 20 T4 351
auto[1] 2007 1 T2 229 T4 25 T6 8

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