Group : tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
sram_1_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
sram_1_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
sram_1_req_during_lc_esc 2 0 2 100.00 100 1 1 0
sram_1_req_during_otbn_req 2 0 2 100.00 100 1 1 2
sram_1_req_during_otp_idle 2 0 2 100.00 100 1 1 2
sram_1_req_during_sram_0_req 2 0 2 100.00 100 1 1 2


Summary for Variable sram_1_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13098 1 T2 28 T3 22 T4 48
auto[1] 732 1 T6 30 T12 16 T13 12



Summary for Variable sram_1_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13044 1 T2 28 T3 22 T4 48
auto[1] 786 1 T6 48 T12 18 T13 15



Summary for Variable sram_1_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for sram_1_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 13794 1 T2 28 T3 22 T4 48
lc_esc_on 36 1 T242 1 T149 1 T99 1



Summary for Variable sram_1_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13244 1 T2 28 T3 22 T4 48
auto[1] 586 1 T6 18 T12 18 T13 7



Summary for Variable sram_1_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2069 1 T2 5 T4 7 T6 6
auto[1] 11761 1 T2 23 T3 22 T4 41



Summary for Variable sram_1_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13717 1 T2 28 T3 22 T4 48
auto[1] 113 1 T242 1 T99 1 T156 1

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