SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 48892 | 1 | T10 | 339 | T100 | 358 | T242 | 207 | ||||
access_err | 64483 | 1 | T2 | 109 | T3 | 394 | T4 | 195 | ||||
write_blank_err | 479 | 1 | T4 | 1 | T6 | 1 | T10 | 4 | ||||
ecc_uncorr_err | 66611 | 1 | T4 | 127 | T6 | 490 | T10 | 1295 | ||||
ecc_corr_err | 1583 | 1 | T135 | 2 | T136 | 1 | T137 | 1 | ||||
no_err | 94409 | 1 | T2 | 140 | T3 | 372 | T4 | 420 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 773 | 1 | T4 | 11 | T6 | 2 | T10 | 16 | ||||
secret2 | 23295 | 1 | T2 | 28 | T3 | 88 | T4 | 48 | ||||
secret1 | 29017 | 1 | T2 | 19 | T3 | 84 | T4 | 44 | ||||
secret0 | 41273 | 1 | T2 | 15 | T3 | 85 | T4 | 58 | ||||
hw_cfg1 | 37023 | 1 | T2 | 11 | T3 | 80 | T4 | 164 | ||||
hw_cfg0 | 26040 | 1 | T2 | 22 | T3 | 66 | T4 | 71 | ||||
rot_creator_auth_state | 22985 | 1 | T2 | 33 | T3 | 68 | T4 | 63 | ||||
rot_creator_auth_codesign | 21400 | 1 | T2 | 24 | T3 | 84 | T4 | 96 | ||||
owner_sw_cfg | 20399 | 1 | T2 | 37 | T3 | 65 | T4 | 85 | ||||
creator_sw_cfg | 21714 | 1 | T2 | 34 | T3 | 73 | T4 | 40 | ||||
vendor_test | 32538 | 1 | T2 | 26 | T3 | 73 | T4 | 63 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 1090 | 1 | T280 | 10 | T372 | 17 | T247 | 3 | ||||
fsm_err | secret1 | 3291 | 1 | T145 | 27 | T146 | 59 | T238 | 132 | ||||
fsm_err | secret0 | 9524 | 1 | T100 | 358 | T149 | 112 | T261 | 414 | ||||
fsm_err | hw_cfg1 | 2156 | 1 | T177 | 109 | T373 | 74 | T374 | 12 | ||||
fsm_err | hw_cfg0 | 5449 | 1 | T236 | 71 | T178 | 196 | T252 | 86 | ||||
fsm_err | rot_creator_auth_state | 4495 | 1 | T10 | 177 | T162 | 617 | T68 | 132 | ||||
fsm_err | rot_creator_auth_codesign | 2782 | 1 | T242 | 207 | T175 | 35 | T375 | 68 | ||||
fsm_err | owner_sw_cfg | 2800 | 1 | T10 | 118 | T376 | 141 | T136 | 13 | ||||
fsm_err | creator_sw_cfg | 3135 | 1 | T10 | 44 | T171 | 11 | T329 | 272 | ||||
fsm_err | vendor_test | 14170 | 1 | T204 | 64 | T377 | 29 | T62 | 75 | ||||
access_err | life_cycle | 773 | 1 | T4 | 11 | T6 | 2 | T10 | 16 | ||||
access_err | secret2 | 11052 | 1 | T2 | 17 | T3 | 21 | T4 | 41 | ||||
access_err | secret1 | 6238 | 1 | T3 | 63 | T10 | 46 | T31 | 1 | ||||
access_err | secret0 | 4693 | 1 | T3 | 61 | T4 | 3 | T10 | 50 | ||||
access_err | hw_cfg1 | 1328 | 1 | T3 | 2 | T4 | 2 | T6 | 1 | ||||
access_err | hw_cfg0 | 2116 | 1 | T3 | 12 | T10 | 22 | T11 | 2 | ||||
access_err | rot_creator_auth_state | 6352 | 1 | T2 | 21 | T3 | 33 | T4 | 29 | ||||
access_err | rot_creator_auth_codesign | 8354 | 1 | T2 | 17 | T3 | 66 | T4 | 44 | ||||
access_err | owner_sw_cfg | 7355 | 1 | T2 | 19 | T3 | 49 | T4 | 19 | ||||
access_err | creator_sw_cfg | 8316 | 1 | T2 | 22 | T3 | 52 | T4 | 15 | ||||
access_err | vendor_test | 7906 | 1 | T2 | 13 | T3 | 35 | T4 | 31 | ||||
write_blank_err | secret2 | 13 | 1 | T125 | 1 | T378 | 1 | T372 | 1 | ||||
write_blank_err | secret1 | 25 | 1 | T10 | 1 | T58 | 1 | T99 | 1 | ||||
write_blank_err | secret0 | 46 | 1 | T10 | 1 | T161 | 1 | T162 | 1 | ||||
write_blank_err | hw_cfg1 | 76 | 1 | T4 | 1 | T6 | 1 | T137 | 2 | ||||
write_blank_err | hw_cfg0 | 12 | 1 | T125 | 1 | T174 | 1 | T308 | 1 | ||||
write_blank_err | rot_creator_auth_state | 163 | 1 | T10 | 2 | T161 | 1 | T162 | 3 | ||||
write_blank_err | rot_creator_auth_codesign | 51 | 1 | T161 | 2 | T162 | 3 | T98 | 3 | ||||
write_blank_err | owner_sw_cfg | 44 | 1 | T98 | 1 | T99 | 1 | T280 | 1 | ||||
write_blank_err | creator_sw_cfg | 14 | 1 | T98 | 1 | T71 | 1 | T379 | 2 | ||||
write_blank_err | vendor_test | 35 | 1 | T98 | 1 | T99 | 2 | T125 | 1 | ||||
ecc_uncorr_err | secret2 | 5412 | 1 | T169 | 66 | T125 | 370 | T378 | 161 | ||||
ecc_uncorr_err | secret1 | 9712 | 1 | T10 | 528 | T135 | 10 | T58 | 140 | ||||
ecc_uncorr_err | secret0 | 18059 | 1 | T10 | 436 | T161 | 185 | T136 | 9 | ||||
ecc_uncorr_err | hw_cfg1 | 22060 | 1 | T4 | 127 | T6 | 490 | T137 | 663 | ||||
ecc_uncorr_err | hw_cfg0 | 5318 | 1 | T125 | 504 | T174 | 431 | T380 | 47 | ||||
ecc_uncorr_err | rot_creator_auth_state | 2991 | 1 | T10 | 331 | T163 | 82 | T285 | 712 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 909 | 1 | T163 | 46 | T169 | 203 | T381 | 19 | ||||
ecc_uncorr_err | owner_sw_cfg | 980 | 1 | T209 | 134 | T382 | 81 | T211 | 17 | ||||
ecc_uncorr_err | creator_sw_cfg | 1170 | 1 | T98 | 204 | T169 | 67 | T219 | 65 | ||||
ecc_corr_err | secret2 | 97 | 1 | T32 | 5 | T72 | 5 | T381 | 2 | ||||
ecc_corr_err | secret1 | 141 | 1 | T163 | 1 | T62 | 8 | T32 | 1 | ||||
ecc_corr_err | secret0 | 180 | 1 | T62 | 9 | T99 | 4 | T169 | 7 | ||||
ecc_corr_err | hw_cfg1 | 315 | 1 | T137 | 1 | T62 | 12 | T99 | 5 | ||||
ecc_corr_err | hw_cfg0 | 281 | 1 | T62 | 2 | T32 | 9 | T380 | 1 | ||||
ecc_corr_err | rot_creator_auth_state | 112 | 1 | T163 | 1 | T62 | 3 | T32 | 5 | ||||
ecc_corr_err | rot_creator_auth_codesign | 161 | 1 | T62 | 1 | T32 | 10 | T23 | 2 | ||||
ecc_corr_err | owner_sw_cfg | 166 | 1 | T135 | 2 | T136 | 1 | T163 | 1 | ||||
ecc_corr_err | creator_sw_cfg | 130 | 1 | T62 | 10 | T32 | 5 | T169 | 1 | ||||
no_err | secret2 | 5631 | 1 | T2 | 11 | T3 | 67 | T4 | 7 | ||||
no_err | secret1 | 9610 | 1 | T2 | 19 | T3 | 21 | T4 | 44 | ||||
no_err | secret0 | 8771 | 1 | T2 | 15 | T3 | 24 | T4 | 55 | ||||
no_err | hw_cfg1 | 11088 | 1 | T2 | 11 | T3 | 78 | T4 | 34 | ||||
no_err | hw_cfg0 | 12864 | 1 | T2 | 22 | T3 | 54 | T4 | 71 | ||||
no_err | rot_creator_auth_state | 8872 | 1 | T2 | 12 | T3 | 35 | T4 | 34 | ||||
no_err | rot_creator_auth_codesign | 9143 | 1 | T2 | 7 | T3 | 18 | T4 | 52 | ||||
no_err | owner_sw_cfg | 9054 | 1 | T2 | 18 | T3 | 16 | T4 | 66 | ||||
no_err | creator_sw_cfg | 8949 | 1 | T2 | 12 | T3 | 21 | T4 | 25 | ||||
no_err | vendor_test | 10427 | 1 | T2 | 13 | T3 | 38 | T4 | 32 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |